Elijah Orr / mbed-renbed

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TARGET_SAMD21G18A/comp_pm.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

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Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for PM
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_PM_COMPONENT_
Kojto 111:4336505e4b1c 48 #define _SAMD21_PM_COMPONENT_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========================================================================== */
Kojto 111:4336505e4b1c 51 /** SOFTWARE API DEFINITION FOR PM */
Kojto 111:4336505e4b1c 52 /* ========================================================================== */
Kojto 111:4336505e4b1c 53 /** \addtogroup SAMD21_PM Power Manager */
Kojto 111:4336505e4b1c 54 /*@{*/
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 #define PM_U2206
Kojto 111:4336505e4b1c 57 #define REV_PM 0x211
Kojto 111:4336505e4b1c 58
Kojto 111:4336505e4b1c 59 /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
Kojto 111:4336505e4b1c 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 61 typedef union {
Kojto 111:4336505e4b1c 62 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 63 } PM_CTRL_Type;
Kojto 111:4336505e4b1c 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 65
Kojto 111:4336505e4b1c 66 #define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
Kojto 111:4336505e4b1c 67 #define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */
Kojto 111:4336505e4b1c 68
Kojto 111:4336505e4b1c 69 #define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */
Kojto 111:4336505e4b1c 70
Kojto 111:4336505e4b1c 71 /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
Kojto 111:4336505e4b1c 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 73 typedef union {
Kojto 111:4336505e4b1c 74 struct {
Kojto 111:4336505e4b1c 75 uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
Kojto 111:4336505e4b1c 76 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 77 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 78 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 79 } PM_SLEEP_Type;
Kojto 111:4336505e4b1c 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 81
Kojto 111:4336505e4b1c 82 #define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
Kojto 111:4336505e4b1c 83 #define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */
Kojto 111:4336505e4b1c 84
Kojto 111:4336505e4b1c 85 #define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
Kojto 111:4336505e4b1c 86 #define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
Kojto 111:4336505e4b1c 87 #define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
Kojto 111:4336505e4b1c 88 #define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
Kojto 111:4336505e4b1c 89 #define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
Kojto 111:4336505e4b1c 90 #define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
Kojto 111:4336505e4b1c 91 #define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
Kojto 111:4336505e4b1c 92 #define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
Kojto 111:4336505e4b1c 93 #define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
Kojto 111:4336505e4b1c 94 #define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */
Kojto 111:4336505e4b1c 95
Kojto 111:4336505e4b1c 96 /* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */
Kojto 111:4336505e4b1c 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 98 typedef union {
Kojto 111:4336505e4b1c 99 struct {
Kojto 111:4336505e4b1c 100 uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
Kojto 111:4336505e4b1c 101 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 102 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 103 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 104 } PM_EXTCTRL_Type;
Kojto 111:4336505e4b1c 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 106
Kojto 111:4336505e4b1c 107 #define PM_EXTCTRL_OFFSET 0x02 /**< \brief (PM_EXTCTRL offset) External Reset Controller */
Kojto 111:4336505e4b1c 108 #define PM_EXTCTRL_RESETVALUE 0x00ul /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
Kojto 111:4336505e4b1c 109
Kojto 111:4336505e4b1c 110 #define PM_EXTCTRL_SETDIS_Pos 0 /**< \brief (PM_EXTCTRL) External Reset Disable */
Kojto 111:4336505e4b1c 111 #define PM_EXTCTRL_SETDIS (0x1ul << PM_EXTCTRL_SETDIS_Pos)
Kojto 111:4336505e4b1c 112 #define PM_EXTCTRL_MASK 0x01ul /**< \brief (PM_EXTCTRL) MASK Register */
Kojto 111:4336505e4b1c 113
Kojto 111:4336505e4b1c 114 /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
Kojto 111:4336505e4b1c 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 116 typedef union {
Kojto 111:4336505e4b1c 117 struct {
Kojto 111:4336505e4b1c 118 uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
Kojto 111:4336505e4b1c 119 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 120 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 121 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 122 } PM_CPUSEL_Type;
Kojto 111:4336505e4b1c 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 124
Kojto 111:4336505e4b1c 125 #define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
Kojto 111:4336505e4b1c 126 #define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
Kojto 111:4336505e4b1c 127
Kojto 111:4336505e4b1c 128 #define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
Kojto 111:4336505e4b1c 129 #define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 130 #define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
Kojto 111:4336505e4b1c 131 #define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
Kojto 111:4336505e4b1c 132 #define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
Kojto 111:4336505e4b1c 133 #define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
Kojto 111:4336505e4b1c 134 #define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */
Kojto 111:4336505e4b1c 135 #define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */
Kojto 111:4336505e4b1c 136 #define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */
Kojto 111:4336505e4b1c 137 #define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */
Kojto 111:4336505e4b1c 138 #define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */
Kojto 111:4336505e4b1c 139 #define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 140 #define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 141 #define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 142 #define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 143 #define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 144 #define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 145 #define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 146 #define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
Kojto 111:4336505e4b1c 147 #define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */
Kojto 111:4336505e4b1c 148
Kojto 111:4336505e4b1c 149 /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
Kojto 111:4336505e4b1c 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 151 typedef union {
Kojto 111:4336505e4b1c 152 struct {
Kojto 111:4336505e4b1c 153 uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
Kojto 111:4336505e4b1c 154 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 155 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 156 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 157 } PM_APBASEL_Type;
Kojto 111:4336505e4b1c 158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 159
Kojto 111:4336505e4b1c 160 #define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
Kojto 111:4336505e4b1c 161 #define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
Kojto 111:4336505e4b1c 162
Kojto 111:4336505e4b1c 163 #define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
Kojto 111:4336505e4b1c 164 #define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 165 #define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
Kojto 111:4336505e4b1c 166 #define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
Kojto 111:4336505e4b1c 167 #define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
Kojto 111:4336505e4b1c 168 #define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
Kojto 111:4336505e4b1c 169 #define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */
Kojto 111:4336505e4b1c 170 #define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */
Kojto 111:4336505e4b1c 171 #define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */
Kojto 111:4336505e4b1c 172 #define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */
Kojto 111:4336505e4b1c 173 #define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */
Kojto 111:4336505e4b1c 174 #define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 175 #define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 176 #define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 177 #define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 178 #define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 179 #define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 180 #define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 181 #define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
Kojto 111:4336505e4b1c 182 #define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */
Kojto 111:4336505e4b1c 183
Kojto 111:4336505e4b1c 184 /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
Kojto 111:4336505e4b1c 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 186 typedef union {
Kojto 111:4336505e4b1c 187 struct {
Kojto 111:4336505e4b1c 188 uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
Kojto 111:4336505e4b1c 189 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 190 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 191 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 192 } PM_APBBSEL_Type;
Kojto 111:4336505e4b1c 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 194
Kojto 111:4336505e4b1c 195 #define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
Kojto 111:4336505e4b1c 196 #define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
Kojto 111:4336505e4b1c 197
Kojto 111:4336505e4b1c 198 #define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
Kojto 111:4336505e4b1c 199 #define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 200 #define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
Kojto 111:4336505e4b1c 201 #define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
Kojto 111:4336505e4b1c 202 #define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
Kojto 111:4336505e4b1c 203 #define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
Kojto 111:4336505e4b1c 204 #define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */
Kojto 111:4336505e4b1c 205 #define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */
Kojto 111:4336505e4b1c 206 #define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */
Kojto 111:4336505e4b1c 207 #define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */
Kojto 111:4336505e4b1c 208 #define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */
Kojto 111:4336505e4b1c 209 #define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 210 #define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 211 #define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 212 #define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 213 #define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 214 #define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 215 #define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 216 #define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
Kojto 111:4336505e4b1c 217 #define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */
Kojto 111:4336505e4b1c 218
Kojto 111:4336505e4b1c 219 /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
Kojto 111:4336505e4b1c 220 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 221 typedef union {
Kojto 111:4336505e4b1c 222 struct {
Kojto 111:4336505e4b1c 223 uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
Kojto 111:4336505e4b1c 224 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 225 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 226 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 227 } PM_APBCSEL_Type;
Kojto 111:4336505e4b1c 228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 229
Kojto 111:4336505e4b1c 230 #define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
Kojto 111:4336505e4b1c 231 #define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
Kojto 111:4336505e4b1c 232
Kojto 111:4336505e4b1c 233 #define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
Kojto 111:4336505e4b1c 234 #define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 235 #define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
Kojto 111:4336505e4b1c 236 #define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
Kojto 111:4336505e4b1c 237 #define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
Kojto 111:4336505e4b1c 238 #define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
Kojto 111:4336505e4b1c 239 #define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */
Kojto 111:4336505e4b1c 240 #define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */
Kojto 111:4336505e4b1c 241 #define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */
Kojto 111:4336505e4b1c 242 #define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */
Kojto 111:4336505e4b1c 243 #define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */
Kojto 111:4336505e4b1c 244 #define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 245 #define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 246 #define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 247 #define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 248 #define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 249 #define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 250 #define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 251 #define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
Kojto 111:4336505e4b1c 252 #define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */
Kojto 111:4336505e4b1c 253
Kojto 111:4336505e4b1c 254 /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
Kojto 111:4336505e4b1c 255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 256 typedef union {
Kojto 111:4336505e4b1c 257 struct {
Kojto 111:4336505e4b1c 258 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
Kojto 111:4336505e4b1c 259 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
Kojto 111:4336505e4b1c 260 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
Kojto 111:4336505e4b1c 261 uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
Kojto 111:4336505e4b1c 262 uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
Kojto 111:4336505e4b1c 263 uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
Kojto 111:4336505e4b1c 264 uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
Kojto 111:4336505e4b1c 265 uint32_t :25; /*!< bit: 7..31 Reserved */
Kojto 111:4336505e4b1c 266 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 267 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 268 } PM_AHBMASK_Type;
Kojto 111:4336505e4b1c 269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 270
Kojto 111:4336505e4b1c 271 #define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
Kojto 111:4336505e4b1c 272 #define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
Kojto 111:4336505e4b1c 273
Kojto 111:4336505e4b1c 274 #define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
Kojto 111:4336505e4b1c 275 #define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos)
Kojto 111:4336505e4b1c 276 #define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
Kojto 111:4336505e4b1c 277 #define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos)
Kojto 111:4336505e4b1c 278 #define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
Kojto 111:4336505e4b1c 279 #define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos)
Kojto 111:4336505e4b1c 280 #define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
Kojto 111:4336505e4b1c 281 #define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos)
Kojto 111:4336505e4b1c 282 #define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
Kojto 111:4336505e4b1c 283 #define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
Kojto 111:4336505e4b1c 284 #define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
Kojto 111:4336505e4b1c 285 #define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos)
Kojto 111:4336505e4b1c 286 #define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
Kojto 111:4336505e4b1c 287 #define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos)
Kojto 111:4336505e4b1c 288 #define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
Kojto 111:4336505e4b1c 289
Kojto 111:4336505e4b1c 290 /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
Kojto 111:4336505e4b1c 291 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 292 typedef union {
Kojto 111:4336505e4b1c 293 struct {
Kojto 111:4336505e4b1c 294 uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
Kojto 111:4336505e4b1c 295 uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
Kojto 111:4336505e4b1c 296 uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
Kojto 111:4336505e4b1c 297 uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
Kojto 111:4336505e4b1c 298 uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
Kojto 111:4336505e4b1c 299 uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
Kojto 111:4336505e4b1c 300 uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
Kojto 111:4336505e4b1c 301 uint32_t :25; /*!< bit: 7..31 Reserved */
Kojto 111:4336505e4b1c 302 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 303 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 304 } PM_APBAMASK_Type;
Kojto 111:4336505e4b1c 305 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 306
Kojto 111:4336505e4b1c 307 #define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
Kojto 111:4336505e4b1c 308 #define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
Kojto 111:4336505e4b1c 309
Kojto 111:4336505e4b1c 310 #define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
Kojto 111:4336505e4b1c 311 #define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos)
Kojto 111:4336505e4b1c 312 #define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
Kojto 111:4336505e4b1c 313 #define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos)
Kojto 111:4336505e4b1c 314 #define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
Kojto 111:4336505e4b1c 315 #define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
Kojto 111:4336505e4b1c 316 #define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
Kojto 111:4336505e4b1c 317 #define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos)
Kojto 111:4336505e4b1c 318 #define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
Kojto 111:4336505e4b1c 319 #define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos)
Kojto 111:4336505e4b1c 320 #define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
Kojto 111:4336505e4b1c 321 #define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos)
Kojto 111:4336505e4b1c 322 #define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
Kojto 111:4336505e4b1c 323 #define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos)
Kojto 111:4336505e4b1c 324 #define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
Kojto 111:4336505e4b1c 325
Kojto 111:4336505e4b1c 326 /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
Kojto 111:4336505e4b1c 327 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 328 typedef union {
Kojto 111:4336505e4b1c 329 struct {
Kojto 111:4336505e4b1c 330 uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
Kojto 111:4336505e4b1c 331 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
Kojto 111:4336505e4b1c 332 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
Kojto 111:4336505e4b1c 333 uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
Kojto 111:4336505e4b1c 334 uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
Kojto 111:4336505e4b1c 335 uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
Kojto 111:4336505e4b1c 336 uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
Kojto 111:4336505e4b1c 337 uint32_t :25; /*!< bit: 7..31 Reserved */
Kojto 111:4336505e4b1c 338 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 339 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 340 } PM_APBBMASK_Type;
Kojto 111:4336505e4b1c 341 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 342
Kojto 111:4336505e4b1c 343 #define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
Kojto 111:4336505e4b1c 344 #define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
Kojto 111:4336505e4b1c 345
Kojto 111:4336505e4b1c 346 #define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
Kojto 111:4336505e4b1c 347 #define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos)
Kojto 111:4336505e4b1c 348 #define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
Kojto 111:4336505e4b1c 349 #define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos)
Kojto 111:4336505e4b1c 350 #define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
Kojto 111:4336505e4b1c 351 #define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
Kojto 111:4336505e4b1c 352 #define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
Kojto 111:4336505e4b1c 353 #define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos)
Kojto 111:4336505e4b1c 354 #define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
Kojto 111:4336505e4b1c 355 #define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos)
Kojto 111:4336505e4b1c 356 #define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
Kojto 111:4336505e4b1c 357 #define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos)
Kojto 111:4336505e4b1c 358 #define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
Kojto 111:4336505e4b1c 359 #define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos)
Kojto 111:4336505e4b1c 360 #define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
Kojto 111:4336505e4b1c 361
Kojto 111:4336505e4b1c 362 /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
Kojto 111:4336505e4b1c 363 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 364 typedef union {
Kojto 111:4336505e4b1c 365 struct {
Kojto 111:4336505e4b1c 366 uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
Kojto 111:4336505e4b1c 367 uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
Kojto 111:4336505e4b1c 368 uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
Kojto 111:4336505e4b1c 369 uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
Kojto 111:4336505e4b1c 370 uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
Kojto 111:4336505e4b1c 371 uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
Kojto 111:4336505e4b1c 372 uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
Kojto 111:4336505e4b1c 373 uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
Kojto 111:4336505e4b1c 374 uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
Kojto 111:4336505e4b1c 375 uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
Kojto 111:4336505e4b1c 376 uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
Kojto 111:4336505e4b1c 377 uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
Kojto 111:4336505e4b1c 378 uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
Kojto 111:4336505e4b1c 379 uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
Kojto 111:4336505e4b1c 380 uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
Kojto 111:4336505e4b1c 381 uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
Kojto 111:4336505e4b1c 382 uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
Kojto 111:4336505e4b1c 383 uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
Kojto 111:4336505e4b1c 384 uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
Kojto 111:4336505e4b1c 385 uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
Kojto 111:4336505e4b1c 386 uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
Kojto 111:4336505e4b1c 387 uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
Kojto 111:4336505e4b1c 388 uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
Kojto 111:4336505e4b1c 389 uint32_t :9; /*!< bit: 23..31 Reserved */
Kojto 111:4336505e4b1c 390 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 391 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 392 } PM_APBCMASK_Type;
Kojto 111:4336505e4b1c 393 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 394
Kojto 111:4336505e4b1c 395 #define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
Kojto 111:4336505e4b1c 396 #define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
Kojto 111:4336505e4b1c 397
Kojto 111:4336505e4b1c 398 #define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
Kojto 111:4336505e4b1c 399 #define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos)
Kojto 111:4336505e4b1c 400 #define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
Kojto 111:4336505e4b1c 401 #define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos)
Kojto 111:4336505e4b1c 402 #define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
Kojto 111:4336505e4b1c 403 #define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos)
Kojto 111:4336505e4b1c 404 #define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
Kojto 111:4336505e4b1c 405 #define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos)
Kojto 111:4336505e4b1c 406 #define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
Kojto 111:4336505e4b1c 407 #define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos)
Kojto 111:4336505e4b1c 408 #define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
Kojto 111:4336505e4b1c 409 #define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos)
Kojto 111:4336505e4b1c 410 #define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
Kojto 111:4336505e4b1c 411 #define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos)
Kojto 111:4336505e4b1c 412 #define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
Kojto 111:4336505e4b1c 413 #define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos)
Kojto 111:4336505e4b1c 414 #define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
Kojto 111:4336505e4b1c 415 #define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos)
Kojto 111:4336505e4b1c 416 #define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
Kojto 111:4336505e4b1c 417 #define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos)
Kojto 111:4336505e4b1c 418 #define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
Kojto 111:4336505e4b1c 419 #define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos)
Kojto 111:4336505e4b1c 420 #define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
Kojto 111:4336505e4b1c 421 #define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos)
Kojto 111:4336505e4b1c 422 #define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
Kojto 111:4336505e4b1c 423 #define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos)
Kojto 111:4336505e4b1c 424 #define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
Kojto 111:4336505e4b1c 425 #define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos)
Kojto 111:4336505e4b1c 426 #define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
Kojto 111:4336505e4b1c 427 #define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos)
Kojto 111:4336505e4b1c 428 #define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
Kojto 111:4336505e4b1c 429 #define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos)
Kojto 111:4336505e4b1c 430 #define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
Kojto 111:4336505e4b1c 431 #define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos)
Kojto 111:4336505e4b1c 432 #define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
Kojto 111:4336505e4b1c 433 #define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos)
Kojto 111:4336505e4b1c 434 #define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
Kojto 111:4336505e4b1c 435 #define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos)
Kojto 111:4336505e4b1c 436 #define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
Kojto 111:4336505e4b1c 437 #define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos)
Kojto 111:4336505e4b1c 438 #define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
Kojto 111:4336505e4b1c 439 #define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos)
Kojto 111:4336505e4b1c 440 #define PM_APBCMASK_AC1_Pos 21 /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
Kojto 111:4336505e4b1c 441 #define PM_APBCMASK_AC1 (0x1ul << PM_APBCMASK_AC1_Pos)
Kojto 111:4336505e4b1c 442 #define PM_APBCMASK_LINCTRL_Pos 22 /**< \brief (PM_APBCMASK) LINCTRL APB Clock Enable */
Kojto 111:4336505e4b1c 443 #define PM_APBCMASK_LINCTRL (0x1ul << PM_APBCMASK_LINCTRL_Pos)
Kojto 111:4336505e4b1c 444 #define PM_APBCMASK_MASK 0x007FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
Kojto 111:4336505e4b1c 445
Kojto 111:4336505e4b1c 446 /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 447 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 448 typedef union {
Kojto 111:4336505e4b1c 449 struct {
Kojto 111:4336505e4b1c 450 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
Kojto 111:4336505e4b1c 451 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 452 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 453 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 454 } PM_INTENCLR_Type;
Kojto 111:4336505e4b1c 455 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 456
Kojto 111:4336505e4b1c 457 #define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 458 #define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 459
Kojto 111:4336505e4b1c 460 #define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
Kojto 111:4336505e4b1c 461 #define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos)
Kojto 111:4336505e4b1c 462 #define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 463
Kojto 111:4336505e4b1c 464 /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 465 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 466 typedef union {
Kojto 111:4336505e4b1c 467 struct {
Kojto 111:4336505e4b1c 468 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
Kojto 111:4336505e4b1c 469 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 470 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 471 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 472 } PM_INTENSET_Type;
Kojto 111:4336505e4b1c 473 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 474
Kojto 111:4336505e4b1c 475 #define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 476 #define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 477
Kojto 111:4336505e4b1c 478 #define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
Kojto 111:4336505e4b1c 479 #define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos)
Kojto 111:4336505e4b1c 480 #define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 481
Kojto 111:4336505e4b1c 482 /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 484 typedef union {
Kojto 111:4336505e4b1c 485 struct {
Kojto 111:4336505e4b1c 486 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
Kojto 111:4336505e4b1c 487 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 488 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 489 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 490 } PM_INTFLAG_Type;
Kojto 111:4336505e4b1c 491 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 492
Kojto 111:4336505e4b1c 493 #define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 494 #define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 495
Kojto 111:4336505e4b1c 496 #define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
Kojto 111:4336505e4b1c 497 #define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos)
Kojto 111:4336505e4b1c 498 #define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 499
Kojto 111:4336505e4b1c 500 /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
Kojto 111:4336505e4b1c 501 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 502 typedef union {
Kojto 111:4336505e4b1c 503 struct {
Kojto 111:4336505e4b1c 504 uint8_t POR:1; /*!< bit: 0 Power On Reset */
Kojto 111:4336505e4b1c 505 uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
Kojto 111:4336505e4b1c 506 uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
Kojto 111:4336505e4b1c 507 uint8_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 508 uint8_t EXT:1; /*!< bit: 4 External Reset */
Kojto 111:4336505e4b1c 509 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
Kojto 111:4336505e4b1c 510 uint8_t SYST:1; /*!< bit: 6 System Reset Request */
Kojto 111:4336505e4b1c 511 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 512 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 513 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 514 } PM_RCAUSE_Type;
Kojto 111:4336505e4b1c 515 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 516
Kojto 111:4336505e4b1c 517 #define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
Kojto 111:4336505e4b1c 518 #define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */
Kojto 111:4336505e4b1c 519
Kojto 111:4336505e4b1c 520 #define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
Kojto 111:4336505e4b1c 521 #define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos)
Kojto 111:4336505e4b1c 522 #define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
Kojto 111:4336505e4b1c 523 #define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos)
Kojto 111:4336505e4b1c 524 #define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
Kojto 111:4336505e4b1c 525 #define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos)
Kojto 111:4336505e4b1c 526 #define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
Kojto 111:4336505e4b1c 527 #define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos)
Kojto 111:4336505e4b1c 528 #define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
Kojto 111:4336505e4b1c 529 #define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos)
Kojto 111:4336505e4b1c 530 #define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
Kojto 111:4336505e4b1c 531 #define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos)
Kojto 111:4336505e4b1c 532 #define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */
Kojto 111:4336505e4b1c 533
Kojto 111:4336505e4b1c 534 /** \brief PM hardware registers */
Kojto 111:4336505e4b1c 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 536 typedef struct {
Kojto 111:4336505e4b1c 537 __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
Kojto 111:4336505e4b1c 538 __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
Kojto 111:4336505e4b1c 539 __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
Kojto 111:4336505e4b1c 540 RoReg8 Reserved1[0x5];
Kojto 111:4336505e4b1c 541 __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
Kojto 111:4336505e4b1c 542 __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
Kojto 111:4336505e4b1c 543 __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
Kojto 111:4336505e4b1c 544 __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
Kojto 111:4336505e4b1c 545 RoReg8 Reserved2[0x8];
Kojto 111:4336505e4b1c 546 __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
Kojto 111:4336505e4b1c 547 __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
Kojto 111:4336505e4b1c 548 __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
Kojto 111:4336505e4b1c 549 __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
Kojto 111:4336505e4b1c 550 RoReg8 Reserved3[0x10];
Kojto 111:4336505e4b1c 551 __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 552 __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
Kojto 111:4336505e4b1c 553 __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 554 RoReg8 Reserved4[0x1];
Kojto 111:4336505e4b1c 555 __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
Kojto 111:4336505e4b1c 556 } Pm;
Kojto 111:4336505e4b1c 557 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 558
Kojto 111:4336505e4b1c 559 /*@}*/
Kojto 111:4336505e4b1c 560
Kojto 111:4336505e4b1c 561 #endif /* _SAMD21_PM_COMPONENT_ */