Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
110:165afa46840b 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_sdram.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
emilmont 77:869cf507173a 7 * @brief Header file of SDRAM HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_SDRAM_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_SDRAM_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
Kojto 110:165afa46840b 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 47 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 50 #include "stm32f4xx_ll_fmc.h"
emilmont 77:869cf507173a 51
emilmont 77:869cf507173a 52 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 53 * @{
emilmont 77:869cf507173a 54 */
emilmont 77:869cf507173a 55
emilmont 77:869cf507173a 56 /** @addtogroup SDRAM
emilmont 77:869cf507173a 57 * @{
emilmont 77:869cf507173a 58 */
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 /* Exported typedef ----------------------------------------------------------*/
Kojto 99:dbbf35b96557 61 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
Kojto 99:dbbf35b96557 62 * @{
Kojto 99:dbbf35b96557 63 */
emilmont 77:869cf507173a 64
emilmont 77:869cf507173a 65 /**
emilmont 77:869cf507173a 66 * @brief HAL SDRAM State structure definition
emilmont 77:869cf507173a 67 */
emilmont 77:869cf507173a 68 typedef enum
emilmont 77:869cf507173a 69 {
emilmont 77:869cf507173a 70 HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */
emilmont 77:869cf507173a 71 HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */
emilmont 77:869cf507173a 72 HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */
emilmont 77:869cf507173a 73 HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */
emilmont 77:869cf507173a 74 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */
emilmont 77:869cf507173a 75 HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 }HAL_SDRAM_StateTypeDef;
emilmont 77:869cf507173a 78
emilmont 77:869cf507173a 79 /**
emilmont 77:869cf507173a 80 * @brief SDRAM handle Structure definition
emilmont 77:869cf507173a 81 */
emilmont 77:869cf507173a 82 typedef struct
emilmont 77:869cf507173a 83 {
emilmont 77:869cf507173a 84 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
emilmont 77:869cf507173a 89
emilmont 77:869cf507173a 90 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94 }SDRAM_HandleTypeDef;
Kojto 99:dbbf35b96557 95 /**
Kojto 99:dbbf35b96557 96 * @}
Kojto 99:dbbf35b96557 97 */
Kojto 99:dbbf35b96557 98
Kojto 99:dbbf35b96557 99 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 100 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 101 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
Kojto 99:dbbf35b96557 102 * @{
Kojto 99:dbbf35b96557 103 */
bogdanm 85:024bf7f99721 104
bogdanm 85:024bf7f99721 105 /** @brief Reset SDRAM handle state
bogdanm 85:024bf7f99721 106 * @param __HANDLE__: specifies the SDRAM handle.
bogdanm 85:024bf7f99721 107 * @retval None
bogdanm 85:024bf7f99721 108 */
bogdanm 85:024bf7f99721 109 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
Kojto 99:dbbf35b96557 110 /**
Kojto 99:dbbf35b96557 111 * @}
Kojto 99:dbbf35b96557 112 */
bogdanm 85:024bf7f99721 113
emilmont 77:869cf507173a 114 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 115 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
Kojto 99:dbbf35b96557 116 * @{
Kojto 99:dbbf35b96557 117 */
emilmont 77:869cf507173a 118
Kojto 99:dbbf35b96557 119 /** @addtogroup SDRAM_Exported_Functions_Group1
Kojto 99:dbbf35b96557 120 * @{
Kojto 99:dbbf35b96557 121 */
Kojto 99:dbbf35b96557 122
Kojto 99:dbbf35b96557 123 /* Initialization/de-initialization functions *********************************/
emilmont 77:869cf507173a 124 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
emilmont 77:869cf507173a 125 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 126 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 127 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 128
emilmont 77:869cf507173a 129 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 130 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 131 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
bogdanm 81:7d30d6019079 132 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 133 /**
Kojto 99:dbbf35b96557 134 * @}
Kojto 99:dbbf35b96557 135 */
emilmont 77:869cf507173a 136
Kojto 99:dbbf35b96557 137 /** @addtogroup SDRAM_Exported_Functions_Group2
Kojto 99:dbbf35b96557 138 * @{
Kojto 99:dbbf35b96557 139 */
Kojto 99:dbbf35b96557 140 /* I/O operation functions ****************************************************/
emilmont 77:869cf507173a 141 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 142 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 143 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 144 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 145 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 146 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 147
emilmont 77:869cf507173a 148 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 149 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
Kojto 99:dbbf35b96557 150 /**
Kojto 99:dbbf35b96557 151 * @}
Kojto 99:dbbf35b96557 152 */
Kojto 99:dbbf35b96557 153
Kojto 99:dbbf35b96557 154 /** @addtogroup SDRAM_Exported_Functions_Group3
Kojto 99:dbbf35b96557 155 * @{
Kojto 99:dbbf35b96557 156 */
emilmont 77:869cf507173a 157 /* SDRAM Control functions *****************************************************/
emilmont 77:869cf507173a 158 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 159 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 160 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
emilmont 77:869cf507173a 161 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
emilmont 77:869cf507173a 162 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
emilmont 77:869cf507173a 163 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
Kojto 99:dbbf35b96557 164 /**
Kojto 99:dbbf35b96557 165 * @}
Kojto 99:dbbf35b96557 166 */
emilmont 77:869cf507173a 167
Kojto 99:dbbf35b96557 168 /** @addtogroup SDRAM_Exported_Functions_Group4
Kojto 99:dbbf35b96557 169 * @{
Kojto 99:dbbf35b96557 170 */
emilmont 77:869cf507173a 171 /* SDRAM State functions ********************************************************/
emilmont 77:869cf507173a 172 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
Kojto 99:dbbf35b96557 173 /**
Kojto 99:dbbf35b96557 174 * @}
Kojto 99:dbbf35b96557 175 */
emilmont 77:869cf507173a 176
emilmont 77:869cf507173a 177 /**
emilmont 77:869cf507173a 178 * @}
Kojto 99:dbbf35b96557 179 */
Kojto 99:dbbf35b96557 180
Kojto 99:dbbf35b96557 181 /**
Kojto 99:dbbf35b96557 182 * @}
Kojto 99:dbbf35b96557 183 */
Kojto 99:dbbf35b96557 184
Kojto 110:165afa46840b 185 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
emilmont 77:869cf507173a 186
emilmont 77:869cf507173a 187 /**
emilmont 77:869cf507173a 188 * @}
emilmont 77:869cf507173a 189 */
emilmont 77:869cf507173a 190
emilmont 77:869cf507173a 191 #ifdef __cplusplus
emilmont 77:869cf507173a 192 }
emilmont 77:869cf507173a 193 #endif
emilmont 77:869cf507173a 194
emilmont 77:869cf507173a 195 #endif /* __STM32F4xx_HAL_SDRAM_H */
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/