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TARGET_NUCLEO_F042K6/stm32f0xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
109:9296ab0bfc11 
.

Who changed what in which revision?

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Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f0xx_hal_rcc.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version V1.3.0
Kojto 109:9296ab0bfc11 6 * @date 26-June-2015
Kojto 109:9296ab0bfc11 7 * @brief Header file of RCC HAL module.
Kojto 109:9296ab0bfc11 8 ******************************************************************************
Kojto 109:9296ab0bfc11 9 * @attention
Kojto 109:9296ab0bfc11 10 *
Kojto 109:9296ab0bfc11 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 12 *
Kojto 109:9296ab0bfc11 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 14 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 16 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 18 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 19 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 21 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 22 * without specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 34 *
Kojto 109:9296ab0bfc11 35 ******************************************************************************
Kojto 109:9296ab0bfc11 36 */
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 109:9296ab0bfc11 39 #ifndef __STM32F0xx_HAL_RCC_H
Kojto 109:9296ab0bfc11 40 #define __STM32F0xx_HAL_RCC_H
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 43 extern "C" {
Kojto 109:9296ab0bfc11 44 #endif
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 /* Includes ------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 47 #include "stm32f0xx_hal_def.h"
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 109:9296ab0bfc11 50 * @{
Kojto 109:9296ab0bfc11 51 */
Kojto 109:9296ab0bfc11 52
Kojto 109:9296ab0bfc11 53 /** @addtogroup RCC
Kojto 109:9296ab0bfc11 54 * @{
Kojto 109:9296ab0bfc11 55 */
Kojto 109:9296ab0bfc11 56
Kojto 109:9296ab0bfc11 57 /** @addtogroup RCC_Private_Constants
Kojto 109:9296ab0bfc11 58 * @{
Kojto 109:9296ab0bfc11 59 */
Kojto 109:9296ab0bfc11 60
Kojto 109:9296ab0bfc11 61 /** @defgroup RCC_Timeout RCC Timeout
Kojto 109:9296ab0bfc11 62 * @{
Kojto 109:9296ab0bfc11 63 */
Kojto 109:9296ab0bfc11 64
Kojto 109:9296ab0bfc11 65 /* Disable Backup domain write protection state change timeout */
Kojto 109:9296ab0bfc11 66 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 67 /* LSE state change timeout */
Kojto 109:9296ab0bfc11 68 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 109:9296ab0bfc11 69 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto 109:9296ab0bfc11 70 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 109:9296ab0bfc11 71 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 72 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 73 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 74 #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 75 #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 76
Kojto 109:9296ab0bfc11 77 /**
Kojto 109:9296ab0bfc11 78 * @}
Kojto 109:9296ab0bfc11 79 */
Kojto 109:9296ab0bfc11 80
Kojto 109:9296ab0bfc11 81 /** @defgroup RCC_Register_Offset Register offsets
Kojto 109:9296ab0bfc11 82 * @{
Kojto 109:9296ab0bfc11 83 */
Kojto 109:9296ab0bfc11 84 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 109:9296ab0bfc11 85 #define RCC_CR_OFFSET 0x00
Kojto 109:9296ab0bfc11 86 #define RCC_CFGR_OFFSET 0x04
Kojto 109:9296ab0bfc11 87 #define RCC_CIR_OFFSET 0x08
Kojto 109:9296ab0bfc11 88 #define RCC_BDCR_OFFSET 0x20
Kojto 109:9296ab0bfc11 89 #define RCC_CSR_OFFSET 0x24
Kojto 109:9296ab0bfc11 90
Kojto 109:9296ab0bfc11 91 /**
Kojto 109:9296ab0bfc11 92 * @}
Kojto 109:9296ab0bfc11 93 */
Kojto 109:9296ab0bfc11 94
Kojto 109:9296ab0bfc11 95
Kojto 109:9296ab0bfc11 96 /* CR register byte 2 (Bits[23:16]) base address */
Kojto 109:9296ab0bfc11 97 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
Kojto 109:9296ab0bfc11 98
Kojto 109:9296ab0bfc11 99 /* CIR register byte 1 (Bits[15:8]) base address */
Kojto 109:9296ab0bfc11 100 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
Kojto 109:9296ab0bfc11 101
Kojto 109:9296ab0bfc11 102 /* CIR register byte 2 (Bits[23:16]) base address */
Kojto 109:9296ab0bfc11 103 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
Kojto 109:9296ab0bfc11 104
Kojto 109:9296ab0bfc11 105 /* Defines used for Flags */
Kojto 109:9296ab0bfc11 106 #define CR_REG_INDEX ((uint8_t)1)
Kojto 109:9296ab0bfc11 107 #define CR2_REG_INDEX 2
Kojto 109:9296ab0bfc11 108 #define BDCR_REG_INDEX 3
Kojto 109:9296ab0bfc11 109 #define CSR_REG_INDEX 4
Kojto 109:9296ab0bfc11 110
Kojto 109:9296ab0bfc11 111 /* Flags in the CFGR register */
Kojto 109:9296ab0bfc11 112 #define RCC_CFGR_PLLMUL_BITNUMBER 18
Kojto 109:9296ab0bfc11 113 #define RCC_CFGR_HPRE_BITNUMBER 4
Kojto 109:9296ab0bfc11 114 #define RCC_CFGR_PPRE_BITNUMBER 8
Kojto 109:9296ab0bfc11 115 /* Flags in the CFGR2 register */
Kojto 109:9296ab0bfc11 116 #define RCC_CFGR2_PREDIV_BITNUMBER 0
Kojto 109:9296ab0bfc11 117 /* Flags in the CR register */
Kojto 109:9296ab0bfc11 118 #define RCC_CR_HSIRDY_BitNumber 1
Kojto 109:9296ab0bfc11 119 #define RCC_CR_HSERDY_BitNumber 17
Kojto 109:9296ab0bfc11 120 #define RCC_CR_PLLRDY_BitNumber 25
Kojto 109:9296ab0bfc11 121 /* Flags in the CR2 register */
Kojto 109:9296ab0bfc11 122 #define RCC_CR2_HSI14RDY_BitNumber 1
Kojto 109:9296ab0bfc11 123 #define RCC_CR2_HSI48RDY_BitNumber 16
Kojto 109:9296ab0bfc11 124 /* Flags in the BDCR register */
Kojto 109:9296ab0bfc11 125 #define RCC_BDCR_LSERDY_BitNumber 1
Kojto 109:9296ab0bfc11 126 /* Flags in the CSR register */
Kojto 109:9296ab0bfc11 127 #define RCC_CSR_LSIRDY_BitNumber 1
Kojto 109:9296ab0bfc11 128 #define RCC_CSR_V18PWRRSTF_BitNumber 23
Kojto 109:9296ab0bfc11 129 #define RCC_CSR_RMVF_BitNumber 24
Kojto 109:9296ab0bfc11 130 #define RCC_CSR_OBLRSTF_BitNumber 25
Kojto 109:9296ab0bfc11 131 #define RCC_CSR_PINRSTF_BitNumber 26
Kojto 109:9296ab0bfc11 132 #define RCC_CSR_PORRSTF_BitNumber 27
Kojto 109:9296ab0bfc11 133 #define RCC_CSR_SFTRSTF_BitNumber 28
Kojto 109:9296ab0bfc11 134 #define RCC_CSR_IWDGRSTF_BitNumber 29
Kojto 109:9296ab0bfc11 135 #define RCC_CSR_WWDGRSTF_BitNumber 30
Kojto 109:9296ab0bfc11 136 #define RCC_CSR_LPWRRSTF_BitNumber 31
Kojto 109:9296ab0bfc11 137 /* Flags in the HSITRIM register */
Kojto 109:9296ab0bfc11 138 #define RCC_CR_HSITRIM_BitNumber 3
Kojto 109:9296ab0bfc11 139 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 109:9296ab0bfc11 140
Kojto 109:9296ab0bfc11 141 /**
Kojto 109:9296ab0bfc11 142 * @}
Kojto 109:9296ab0bfc11 143 */
Kojto 109:9296ab0bfc11 144
Kojto 109:9296ab0bfc11 145 /** @addtogroup RCC_Private_Macros
Kojto 109:9296ab0bfc11 146 * @{
Kojto 109:9296ab0bfc11 147 */
Kojto 109:9296ab0bfc11 148
Kojto 109:9296ab0bfc11 149 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
Kojto 109:9296ab0bfc11 150 ((__HSE__) == RCC_HSE_BYPASS))
Kojto 109:9296ab0bfc11 151 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
Kojto 109:9296ab0bfc11 152 ((__LSE__) == RCC_LSE_BYPASS))
Kojto 109:9296ab0bfc11 153 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
Kojto 109:9296ab0bfc11 154 #define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
Kojto 109:9296ab0bfc11 155 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto 109:9296ab0bfc11 156 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
Kojto 109:9296ab0bfc11 157 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
Kojto 109:9296ab0bfc11 158 ((__PLL__) == RCC_PLL_ON))
Kojto 109:9296ab0bfc11 159 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
Kojto 109:9296ab0bfc11 160 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
Kojto 109:9296ab0bfc11 161 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
Kojto 109:9296ab0bfc11 162 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
Kojto 109:9296ab0bfc11 163 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
Kojto 109:9296ab0bfc11 164 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
Kojto 109:9296ab0bfc11 165 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
Kojto 109:9296ab0bfc11 166 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
Kojto 109:9296ab0bfc11 167 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
Kojto 109:9296ab0bfc11 168 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
Kojto 109:9296ab0bfc11 169 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
Kojto 109:9296ab0bfc11 170 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
Kojto 109:9296ab0bfc11 171 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
Kojto 109:9296ab0bfc11 172 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
Kojto 109:9296ab0bfc11 173 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
Kojto 109:9296ab0bfc11 174 ((__MUL__) == RCC_PLL_MUL16))
Kojto 109:9296ab0bfc11 175 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
Kojto 109:9296ab0bfc11 176 (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
Kojto 109:9296ab0bfc11 177 (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
Kojto 109:9296ab0bfc11 178 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
Kojto 109:9296ab0bfc11 179 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
Kojto 109:9296ab0bfc11 180 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
Kojto 109:9296ab0bfc11 181 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
Kojto 109:9296ab0bfc11 182 ((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto 109:9296ab0bfc11 183 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
Kojto 109:9296ab0bfc11 184 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
Kojto 109:9296ab0bfc11 185 ((__PCLK__) == RCC_HCLK_DIV16))
Kojto 109:9296ab0bfc11 186 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
Kojto 109:9296ab0bfc11 187 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
Kojto 109:9296ab0bfc11 188 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 189 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 109:9296ab0bfc11 190 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto 109:9296ab0bfc11 191 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 192 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 193 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 194 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 195 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 196 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 197
Kojto 109:9296ab0bfc11 198 /**
Kojto 109:9296ab0bfc11 199 * @}
Kojto 109:9296ab0bfc11 200 */
Kojto 109:9296ab0bfc11 201
Kojto 109:9296ab0bfc11 202 /* Exported types ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 203
Kojto 109:9296ab0bfc11 204 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 109:9296ab0bfc11 205 * @{
Kojto 109:9296ab0bfc11 206 */
Kojto 109:9296ab0bfc11 207
Kojto 109:9296ab0bfc11 208 /**
Kojto 109:9296ab0bfc11 209 * @brief RCC PLL configuration structure definition
Kojto 109:9296ab0bfc11 210 */
Kojto 109:9296ab0bfc11 211 typedef struct
Kojto 109:9296ab0bfc11 212 {
Kojto 109:9296ab0bfc11 213 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 109:9296ab0bfc11 214 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 109:9296ab0bfc11 215
Kojto 109:9296ab0bfc11 216 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto 109:9296ab0bfc11 217 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 109:9296ab0bfc11 218
Kojto 109:9296ab0bfc11 219 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 220 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto 109:9296ab0bfc11 221
Kojto 109:9296ab0bfc11 222 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 223 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
Kojto 109:9296ab0bfc11 224
Kojto 109:9296ab0bfc11 225 } RCC_PLLInitTypeDef;
Kojto 109:9296ab0bfc11 226
Kojto 109:9296ab0bfc11 227 /**
Kojto 109:9296ab0bfc11 228 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 109:9296ab0bfc11 229 */
Kojto 109:9296ab0bfc11 230 typedef struct
Kojto 109:9296ab0bfc11 231 {
Kojto 109:9296ab0bfc11 232 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 109:9296ab0bfc11 233 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 109:9296ab0bfc11 234
Kojto 109:9296ab0bfc11 235 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 109:9296ab0bfc11 236 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 109:9296ab0bfc11 237
Kojto 109:9296ab0bfc11 238 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 109:9296ab0bfc11 239 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 109:9296ab0bfc11 240
Kojto 109:9296ab0bfc11 241 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 109:9296ab0bfc11 242 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 109:9296ab0bfc11 243
Kojto 109:9296ab0bfc11 244 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 109:9296ab0bfc11 245 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 109:9296ab0bfc11 246
Kojto 109:9296ab0bfc11 247 uint32_t HSI14State; /*!< The new state of the HSI14.
Kojto 109:9296ab0bfc11 248 This parameter can be a value of @ref RCC_HSI14_Config */
Kojto 109:9296ab0bfc11 249
Kojto 109:9296ab0bfc11 250 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
Kojto 109:9296ab0bfc11 251 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 109:9296ab0bfc11 252
Kojto 109:9296ab0bfc11 253 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
Kojto 109:9296ab0bfc11 254 This parameter can be a value of @ref RCCEx_HSI48_Config */
Kojto 109:9296ab0bfc11 255
Kojto 109:9296ab0bfc11 256 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 109:9296ab0bfc11 257 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 109:9296ab0bfc11 258
Kojto 109:9296ab0bfc11 259 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 109:9296ab0bfc11 260
Kojto 109:9296ab0bfc11 261 } RCC_OscInitTypeDef;
Kojto 109:9296ab0bfc11 262
Kojto 109:9296ab0bfc11 263
Kojto 109:9296ab0bfc11 264 /**
Kojto 109:9296ab0bfc11 265 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 109:9296ab0bfc11 266 */
Kojto 109:9296ab0bfc11 267 typedef struct
Kojto 109:9296ab0bfc11 268 {
Kojto 109:9296ab0bfc11 269 uint32_t ClockType; /*!< The clock to be configured.
Kojto 109:9296ab0bfc11 270 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 109:9296ab0bfc11 271
Kojto 109:9296ab0bfc11 272 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 109:9296ab0bfc11 273 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 109:9296ab0bfc11 274
Kojto 109:9296ab0bfc11 275 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 109:9296ab0bfc11 276 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 109:9296ab0bfc11 277
Kojto 109:9296ab0bfc11 278 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 109:9296ab0bfc11 279 This parameter can be a value of @ref RCC_APB1_Clock_Source */
Kojto 109:9296ab0bfc11 280
Kojto 109:9296ab0bfc11 281 } RCC_ClkInitTypeDef;
Kojto 109:9296ab0bfc11 282
Kojto 109:9296ab0bfc11 283 /**
Kojto 109:9296ab0bfc11 284 * @}
Kojto 109:9296ab0bfc11 285 */
Kojto 109:9296ab0bfc11 286
Kojto 109:9296ab0bfc11 287 /* Exported constants --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 288 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 109:9296ab0bfc11 289 * @{
Kojto 109:9296ab0bfc11 290 */
Kojto 109:9296ab0bfc11 291
Kojto 109:9296ab0bfc11 292 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 109:9296ab0bfc11 293 * @{
Kojto 109:9296ab0bfc11 294 */
Kojto 109:9296ab0bfc11 295
Kojto 109:9296ab0bfc11 296 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 297
Kojto 109:9296ab0bfc11 298 /**
Kojto 109:9296ab0bfc11 299 * @}
Kojto 109:9296ab0bfc11 300 */
Kojto 109:9296ab0bfc11 301
Kojto 109:9296ab0bfc11 302 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 109:9296ab0bfc11 303 * @{
Kojto 109:9296ab0bfc11 304 */
Kojto 109:9296ab0bfc11 305 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 306 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 307 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 308 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 309 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 310 #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 311 /**
Kojto 109:9296ab0bfc11 312 * @}
Kojto 109:9296ab0bfc11 313 */
Kojto 109:9296ab0bfc11 314
Kojto 109:9296ab0bfc11 315 /** @defgroup RCC_HSE_Config HSE Config
Kojto 109:9296ab0bfc11 316 * @{
Kojto 109:9296ab0bfc11 317 */
Kojto 109:9296ab0bfc11 318 #define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
Kojto 109:9296ab0bfc11 319 #define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */
Kojto 109:9296ab0bfc11 320 #define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
Kojto 109:9296ab0bfc11 321 /**
Kojto 109:9296ab0bfc11 322 * @}
Kojto 109:9296ab0bfc11 323 */
Kojto 109:9296ab0bfc11 324
Kojto 109:9296ab0bfc11 325 /** @defgroup RCC_LSE_Config LSE Config
Kojto 109:9296ab0bfc11 326 * @{
Kojto 109:9296ab0bfc11 327 */
Kojto 109:9296ab0bfc11 328 #define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
Kojto 109:9296ab0bfc11 329 #define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */
Kojto 109:9296ab0bfc11 330 #define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
Kojto 109:9296ab0bfc11 331
Kojto 109:9296ab0bfc11 332 /**
Kojto 109:9296ab0bfc11 333 * @}
Kojto 109:9296ab0bfc11 334 */
Kojto 109:9296ab0bfc11 335
Kojto 109:9296ab0bfc11 336 /** @defgroup RCC_HSI_Config HSI Config
Kojto 109:9296ab0bfc11 337 * @{
Kojto 109:9296ab0bfc11 338 */
Kojto 109:9296ab0bfc11 339 #define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
Kojto 109:9296ab0bfc11 340 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
Kojto 109:9296ab0bfc11 341
Kojto 109:9296ab0bfc11 342 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto 109:9296ab0bfc11 343
Kojto 109:9296ab0bfc11 344 /**
Kojto 109:9296ab0bfc11 345 * @}
Kojto 109:9296ab0bfc11 346 */
Kojto 109:9296ab0bfc11 347
Kojto 109:9296ab0bfc11 348 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
Kojto 109:9296ab0bfc11 349 * @{
Kojto 109:9296ab0bfc11 350 */
Kojto 109:9296ab0bfc11 351 #define RCC_HSI14_OFF ((uint32_t)0x00)
Kojto 109:9296ab0bfc11 352 #define RCC_HSI14_ON RCC_CR2_HSI14ON
Kojto 109:9296ab0bfc11 353 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
Kojto 109:9296ab0bfc11 354
Kojto 109:9296ab0bfc11 355 #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
Kojto 109:9296ab0bfc11 356 /**
Kojto 109:9296ab0bfc11 357 * @}
Kojto 109:9296ab0bfc11 358 */
Kojto 109:9296ab0bfc11 359
Kojto 109:9296ab0bfc11 360
Kojto 109:9296ab0bfc11 361 /** @defgroup RCC_LSI_Config LSI Config
Kojto 109:9296ab0bfc11 362 * @{
Kojto 109:9296ab0bfc11 363 */
Kojto 109:9296ab0bfc11 364 #define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
Kojto 109:9296ab0bfc11 365 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
Kojto 109:9296ab0bfc11 366
Kojto 109:9296ab0bfc11 367 /**
Kojto 109:9296ab0bfc11 368 * @}
Kojto 109:9296ab0bfc11 369 */
Kojto 109:9296ab0bfc11 370
Kojto 109:9296ab0bfc11 371 /** @defgroup RCC_PLL_Config PLL Config
Kojto 109:9296ab0bfc11 372 * @{
Kojto 109:9296ab0bfc11 373 */
Kojto 109:9296ab0bfc11 374 #define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
Kojto 109:9296ab0bfc11 375 #define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
Kojto 109:9296ab0bfc11 376 #define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
Kojto 109:9296ab0bfc11 377
Kojto 109:9296ab0bfc11 378 /**
Kojto 109:9296ab0bfc11 379 * @}
Kojto 109:9296ab0bfc11 380 */
Kojto 109:9296ab0bfc11 381
Kojto 109:9296ab0bfc11 382 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 109:9296ab0bfc11 383 * @{
Kojto 109:9296ab0bfc11 384 */
Kojto 109:9296ab0bfc11 385 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
Kojto 109:9296ab0bfc11 386 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
Kojto 109:9296ab0bfc11 387 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
Kojto 109:9296ab0bfc11 388
Kojto 109:9296ab0bfc11 389 /**
Kojto 109:9296ab0bfc11 390 * @}
Kojto 109:9296ab0bfc11 391 */
Kojto 109:9296ab0bfc11 392
Kojto 109:9296ab0bfc11 393 /** @defgroup RCC_System_Clock_Source System Clock Source
Kojto 109:9296ab0bfc11 394 * @{
Kojto 109:9296ab0bfc11 395 */
Kojto 109:9296ab0bfc11 396 #define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /*!< HSI selected as system clock */
Kojto 109:9296ab0bfc11 397 #define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /*!< HSE selected as system clock */
Kojto 109:9296ab0bfc11 398 #define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /*!< PLL selected as system clock */
Kojto 109:9296ab0bfc11 399
Kojto 109:9296ab0bfc11 400 /**
Kojto 109:9296ab0bfc11 401 * @}
Kojto 109:9296ab0bfc11 402 */
Kojto 109:9296ab0bfc11 403
Kojto 109:9296ab0bfc11 404 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 109:9296ab0bfc11 405 * @{
Kojto 109:9296ab0bfc11 406 */
Kojto 109:9296ab0bfc11 407 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 109:9296ab0bfc11 408 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 109:9296ab0bfc11 409 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 109:9296ab0bfc11 410
Kojto 109:9296ab0bfc11 411 /**
Kojto 109:9296ab0bfc11 412 * @}
Kojto 109:9296ab0bfc11 413 */
Kojto 109:9296ab0bfc11 414
Kojto 109:9296ab0bfc11 415 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 109:9296ab0bfc11 416 * @{
Kojto 109:9296ab0bfc11 417 */
Kojto 109:9296ab0bfc11 418 #define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
Kojto 109:9296ab0bfc11 419 #define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
Kojto 109:9296ab0bfc11 420 #define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
Kojto 109:9296ab0bfc11 421 #define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
Kojto 109:9296ab0bfc11 422 #define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
Kojto 109:9296ab0bfc11 423 #define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
Kojto 109:9296ab0bfc11 424 #define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
Kojto 109:9296ab0bfc11 425 #define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
Kojto 109:9296ab0bfc11 426 #define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
Kojto 109:9296ab0bfc11 427
Kojto 109:9296ab0bfc11 428 /**
Kojto 109:9296ab0bfc11 429 * @}
Kojto 109:9296ab0bfc11 430 */
Kojto 109:9296ab0bfc11 431
Kojto 109:9296ab0bfc11 432 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
Kojto 109:9296ab0bfc11 433 * @{
Kojto 109:9296ab0bfc11 434 */
Kojto 109:9296ab0bfc11 435 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
Kojto 109:9296ab0bfc11 436 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
Kojto 109:9296ab0bfc11 437 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
Kojto 109:9296ab0bfc11 438 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
Kojto 109:9296ab0bfc11 439 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
Kojto 109:9296ab0bfc11 440
Kojto 109:9296ab0bfc11 441 /**
Kojto 109:9296ab0bfc11 442 * @}
Kojto 109:9296ab0bfc11 443 */
Kojto 109:9296ab0bfc11 444
Kojto 109:9296ab0bfc11 445 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 109:9296ab0bfc11 446 * @{
Kojto 109:9296ab0bfc11 447 */
Kojto 109:9296ab0bfc11 448 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 449 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /*!< LSE oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 450 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /*!< LSI oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 451 #define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 32 used as RTC clock */
Kojto 109:9296ab0bfc11 452 /**
Kojto 109:9296ab0bfc11 453 * @}
Kojto 109:9296ab0bfc11 454 */
Kojto 109:9296ab0bfc11 455
Kojto 109:9296ab0bfc11 456 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
Kojto 109:9296ab0bfc11 457 * @{
Kojto 109:9296ab0bfc11 458 */
Kojto 109:9296ab0bfc11 459 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto 109:9296ab0bfc11 460 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto 109:9296ab0bfc11 461 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto 109:9296ab0bfc11 462 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto 109:9296ab0bfc11 463 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto 109:9296ab0bfc11 464 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto 109:9296ab0bfc11 465 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto 109:9296ab0bfc11 466 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto 109:9296ab0bfc11 467 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto 109:9296ab0bfc11 468 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto 109:9296ab0bfc11 469 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto 109:9296ab0bfc11 470 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto 109:9296ab0bfc11 471 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto 109:9296ab0bfc11 472 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto 109:9296ab0bfc11 473 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto 109:9296ab0bfc11 474 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto 109:9296ab0bfc11 475
Kojto 109:9296ab0bfc11 476 /**
Kojto 109:9296ab0bfc11 477 * @}
Kojto 109:9296ab0bfc11 478 */
Kojto 109:9296ab0bfc11 479
Kojto 109:9296ab0bfc11 480 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto 109:9296ab0bfc11 481 * @{
Kojto 109:9296ab0bfc11 482 */
Kojto 109:9296ab0bfc11 483 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
Kojto 109:9296ab0bfc11 484 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto 109:9296ab0bfc11 485 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto 109:9296ab0bfc11 486 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
Kojto 109:9296ab0bfc11 487 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto 109:9296ab0bfc11 488 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
Kojto 109:9296ab0bfc11 489 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto 109:9296ab0bfc11 490 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
Kojto 109:9296ab0bfc11 491 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
Kojto 109:9296ab0bfc11 492 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
Kojto 109:9296ab0bfc11 493 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto 109:9296ab0bfc11 494 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
Kojto 109:9296ab0bfc11 495 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
Kojto 109:9296ab0bfc11 496 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
Kojto 109:9296ab0bfc11 497 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto 109:9296ab0bfc11 498
Kojto 109:9296ab0bfc11 499 /**
Kojto 109:9296ab0bfc11 500 * @}
Kojto 109:9296ab0bfc11 501 */
Kojto 109:9296ab0bfc11 502
Kojto 109:9296ab0bfc11 503 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
Kojto 109:9296ab0bfc11 504 * @{
Kojto 109:9296ab0bfc11 505 */
Kojto 109:9296ab0bfc11 506 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
Kojto 109:9296ab0bfc11 507 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 109:9296ab0bfc11 508 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 109:9296ab0bfc11 509 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 109:9296ab0bfc11 510
Kojto 109:9296ab0bfc11 511 /**
Kojto 109:9296ab0bfc11 512 * @}
Kojto 109:9296ab0bfc11 513 */
Kojto 109:9296ab0bfc11 514
Kojto 109:9296ab0bfc11 515 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
Kojto 109:9296ab0bfc11 516 * @{
Kojto 109:9296ab0bfc11 517 */
Kojto 109:9296ab0bfc11 518 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
Kojto 109:9296ab0bfc11 519 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
Kojto 109:9296ab0bfc11 520
Kojto 109:9296ab0bfc11 521 /**
Kojto 109:9296ab0bfc11 522 * @}
Kojto 109:9296ab0bfc11 523 */
Kojto 109:9296ab0bfc11 524 /** @defgroup RCC_MCO_Index MCO Index
Kojto 109:9296ab0bfc11 525 * @{
Kojto 109:9296ab0bfc11 526 */
Kojto 109:9296ab0bfc11 527 #define RCC_MCO1 ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 528 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
Kojto 109:9296ab0bfc11 529
Kojto 109:9296ab0bfc11 530 /**
Kojto 109:9296ab0bfc11 531 * @}
Kojto 109:9296ab0bfc11 532 */
Kojto 109:9296ab0bfc11 533
Kojto 109:9296ab0bfc11 534 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
Kojto 109:9296ab0bfc11 535 * @{
Kojto 109:9296ab0bfc11 536 */
Kojto 109:9296ab0bfc11 537 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto 109:9296ab0bfc11 538 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 109:9296ab0bfc11 539 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 109:9296ab0bfc11 540 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 109:9296ab0bfc11 541 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 109:9296ab0bfc11 542 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 109:9296ab0bfc11 543 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto 109:9296ab0bfc11 544 #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
Kojto 109:9296ab0bfc11 545
Kojto 109:9296ab0bfc11 546 /**
Kojto 109:9296ab0bfc11 547 * @}
Kojto 109:9296ab0bfc11 548 */
Kojto 109:9296ab0bfc11 549
Kojto 109:9296ab0bfc11 550 /** @defgroup RCC_Interrupt Interrupts
Kojto 109:9296ab0bfc11 551 * @{
Kojto 109:9296ab0bfc11 552 */
Kojto 109:9296ab0bfc11 553 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 554 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 555 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 556 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 557 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
Kojto 109:9296ab0bfc11 558 #define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */
Kojto 109:9296ab0bfc11 559 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
Kojto 109:9296ab0bfc11 560 /**
Kojto 109:9296ab0bfc11 561 * @}
Kojto 109:9296ab0bfc11 562 */
Kojto 109:9296ab0bfc11 563
Kojto 109:9296ab0bfc11 564 /** @defgroup RCC_Flag Flags
Kojto 109:9296ab0bfc11 565 * Elements values convention: XXXYYYYYb
Kojto 109:9296ab0bfc11 566 * - YYYYY : Flag position in the register
Kojto 109:9296ab0bfc11 567 * - XXX : Register index
Kojto 109:9296ab0bfc11 568 * - 001: CR register
Kojto 109:9296ab0bfc11 569 * - 010: CR2 register
Kojto 109:9296ab0bfc11 570 * - 011: BDCR register
Kojto 109:9296ab0bfc11 571 * - 0100: CSR register
Kojto 109:9296ab0bfc11 572 * @{
Kojto 109:9296ab0bfc11 573 */
Kojto 109:9296ab0bfc11 574 /* Flags in the CR register */
Kojto 109:9296ab0bfc11 575 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
Kojto 109:9296ab0bfc11 576 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
Kojto 109:9296ab0bfc11 577 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
Kojto 109:9296ab0bfc11 578
Kojto 109:9296ab0bfc11 579 /* Flags in the CR2 register */
Kojto 109:9296ab0bfc11 580 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
Kojto 109:9296ab0bfc11 581
Kojto 109:9296ab0bfc11 582
Kojto 109:9296ab0bfc11 583 /* Flags in the CSR register */
Kojto 109:9296ab0bfc11 584 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
Kojto 109:9296ab0bfc11 585 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
Kojto 109:9296ab0bfc11 586 #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
Kojto 109:9296ab0bfc11 587 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
Kojto 109:9296ab0bfc11 588 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber))
Kojto 109:9296ab0bfc11 589 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber))
Kojto 109:9296ab0bfc11 590 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber))
Kojto 109:9296ab0bfc11 591 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
Kojto 109:9296ab0bfc11 592 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
Kojto 109:9296ab0bfc11 593 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
Kojto 109:9296ab0bfc11 594
Kojto 109:9296ab0bfc11 595 /* Flags in the BDCR register */
Kojto 109:9296ab0bfc11 596 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
Kojto 109:9296ab0bfc11 597
Kojto 109:9296ab0bfc11 598 /**
Kojto 109:9296ab0bfc11 599 * @}
Kojto 109:9296ab0bfc11 600 */
Kojto 109:9296ab0bfc11 601
Kojto 109:9296ab0bfc11 602 /**
Kojto 109:9296ab0bfc11 603 * @}
Kojto 109:9296ab0bfc11 604 */
Kojto 109:9296ab0bfc11 605
Kojto 109:9296ab0bfc11 606 /* Exported macro ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 607
Kojto 109:9296ab0bfc11 608 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 109:9296ab0bfc11 609 * @{
Kojto 109:9296ab0bfc11 610 */
Kojto 109:9296ab0bfc11 611
Kojto 109:9296ab0bfc11 612 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
Kojto 109:9296ab0bfc11 613 * @brief Enable or disable the AHB peripheral clock.
Kojto 109:9296ab0bfc11 614 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 615 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 616 * using it.
Kojto 109:9296ab0bfc11 617 * @{
Kojto 109:9296ab0bfc11 618 */
Kojto 109:9296ab0bfc11 619 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 620 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 621 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto 109:9296ab0bfc11 622 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 623 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto 109:9296ab0bfc11 624 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 625 } while(0)
Kojto 109:9296ab0bfc11 626 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 627 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 628 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto 109:9296ab0bfc11 629 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 630 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto 109:9296ab0bfc11 631 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 632 } while(0)
Kojto 109:9296ab0bfc11 633 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 634 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 635 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto 109:9296ab0bfc11 636 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 637 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto 109:9296ab0bfc11 638 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 639 } while(0)
Kojto 109:9296ab0bfc11 640 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 641 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 642 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto 109:9296ab0bfc11 643 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 644 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto 109:9296ab0bfc11 645 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 646 } while(0)
Kojto 109:9296ab0bfc11 647 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 648 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 649 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto 109:9296ab0bfc11 650 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 651 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto 109:9296ab0bfc11 652 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 653 } while(0)
Kojto 109:9296ab0bfc11 654 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 655 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 656 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto 109:9296ab0bfc11 657 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 658 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto 109:9296ab0bfc11 659 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 660 } while(0)
Kojto 109:9296ab0bfc11 661 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 662 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 663 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto 109:9296ab0bfc11 664 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 665 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto 109:9296ab0bfc11 666 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 667 } while(0)
Kojto 109:9296ab0bfc11 668 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 669 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 670 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto 109:9296ab0bfc11 671 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 672 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto 109:9296ab0bfc11 673 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 674 } while(0)
Kojto 109:9296ab0bfc11 675
Kojto 109:9296ab0bfc11 676 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto 109:9296ab0bfc11 677 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto 109:9296ab0bfc11 678 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto 109:9296ab0bfc11 679 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto 109:9296ab0bfc11 680 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto 109:9296ab0bfc11 681 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto 109:9296ab0bfc11 682 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto 109:9296ab0bfc11 683 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto 109:9296ab0bfc11 684 /**
Kojto 109:9296ab0bfc11 685 * @}
Kojto 109:9296ab0bfc11 686 */
Kojto 109:9296ab0bfc11 687
Kojto 109:9296ab0bfc11 688 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
Kojto 109:9296ab0bfc11 689 * @brief Get the enable or disable status of the AHB peripheral clock.
Kojto 109:9296ab0bfc11 690 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 691 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 692 * using it.
Kojto 109:9296ab0bfc11 693 * @{
Kojto 109:9296ab0bfc11 694 */
Kojto 109:9296ab0bfc11 695 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
Kojto 109:9296ab0bfc11 696 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
Kojto 109:9296ab0bfc11 697 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
Kojto 109:9296ab0bfc11 698 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
Kojto 109:9296ab0bfc11 699 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
Kojto 109:9296ab0bfc11 700 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
Kojto 109:9296ab0bfc11 701 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
Kojto 109:9296ab0bfc11 702 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
Kojto 109:9296ab0bfc11 703 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
Kojto 109:9296ab0bfc11 704 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
Kojto 109:9296ab0bfc11 705 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
Kojto 109:9296ab0bfc11 706 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
Kojto 109:9296ab0bfc11 707 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Kojto 109:9296ab0bfc11 708 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Kojto 109:9296ab0bfc11 709 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
Kojto 109:9296ab0bfc11 710 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
Kojto 109:9296ab0bfc11 711 /**
Kojto 109:9296ab0bfc11 712 * @}
Kojto 109:9296ab0bfc11 713 */
Kojto 109:9296ab0bfc11 714
Kojto 109:9296ab0bfc11 715 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
Kojto 109:9296ab0bfc11 716 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 109:9296ab0bfc11 717 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 718 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 719 * using it.
Kojto 109:9296ab0bfc11 720 * @{
Kojto 109:9296ab0bfc11 721 */
Kojto 109:9296ab0bfc11 722 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 723 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 724 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 109:9296ab0bfc11 725 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 726 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 109:9296ab0bfc11 727 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 728 } while(0)
Kojto 109:9296ab0bfc11 729 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 730 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 731 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 109:9296ab0bfc11 732 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 733 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 109:9296ab0bfc11 734 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 735 } while(0)
Kojto 109:9296ab0bfc11 736 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 737 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 738 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 109:9296ab0bfc11 739 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 740 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 109:9296ab0bfc11 741 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 742 } while(0)
Kojto 109:9296ab0bfc11 743 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 744 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 745 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 109:9296ab0bfc11 746 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 747 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 109:9296ab0bfc11 748 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 749 } while(0)
Kojto 109:9296ab0bfc11 750 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 751 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 752 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 109:9296ab0bfc11 753 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 754 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 109:9296ab0bfc11 755 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 756 } while(0)
Kojto 109:9296ab0bfc11 757
Kojto 109:9296ab0bfc11 758 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 759 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 109:9296ab0bfc11 760 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 109:9296ab0bfc11 761 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 109:9296ab0bfc11 762 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 109:9296ab0bfc11 763 /**
Kojto 109:9296ab0bfc11 764 * @}
Kojto 109:9296ab0bfc11 765 */
Kojto 109:9296ab0bfc11 766
Kojto 109:9296ab0bfc11 767 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 109:9296ab0bfc11 768 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 109:9296ab0bfc11 769 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 770 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 771 * using it.
Kojto 109:9296ab0bfc11 772 * @{
Kojto 109:9296ab0bfc11 773 */
Kojto 109:9296ab0bfc11 774 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 109:9296ab0bfc11 775 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 109:9296ab0bfc11 776 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto 109:9296ab0bfc11 777 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 109:9296ab0bfc11 778 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto 109:9296ab0bfc11 779 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 109:9296ab0bfc11 780 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 109:9296ab0bfc11 781 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto 109:9296ab0bfc11 782 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 109:9296ab0bfc11 783 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto 109:9296ab0bfc11 784 /**
Kojto 109:9296ab0bfc11 785 * @}
Kojto 109:9296ab0bfc11 786 */
Kojto 109:9296ab0bfc11 787
Kojto 109:9296ab0bfc11 788
Kojto 109:9296ab0bfc11 789 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
Kojto 109:9296ab0bfc11 790 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 109:9296ab0bfc11 791 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 792 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 793 * using it.
Kojto 109:9296ab0bfc11 794 * @{
Kojto 109:9296ab0bfc11 795 */
Kojto 109:9296ab0bfc11 796 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 797 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 798 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 109:9296ab0bfc11 799 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 800 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 109:9296ab0bfc11 801 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 802 } while(0)
Kojto 109:9296ab0bfc11 803 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 804 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 805 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 109:9296ab0bfc11 806 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 807 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 109:9296ab0bfc11 808 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 809 } while(0)
Kojto 109:9296ab0bfc11 810 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 811 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 812 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 109:9296ab0bfc11 813 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 814 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 109:9296ab0bfc11 815 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 816 } while(0)
Kojto 109:9296ab0bfc11 817 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 818 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 819 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 109:9296ab0bfc11 820 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 821 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 109:9296ab0bfc11 822 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 823 } while(0)
Kojto 109:9296ab0bfc11 824 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 825 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 826 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto 109:9296ab0bfc11 827 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 828 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto 109:9296ab0bfc11 829 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 830 } while(0)
Kojto 109:9296ab0bfc11 831 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 832 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 833 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto 109:9296ab0bfc11 834 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 835 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto 109:9296ab0bfc11 836 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 837 } while(0)
Kojto 109:9296ab0bfc11 838 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 839 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 840 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 109:9296ab0bfc11 841 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 842 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 109:9296ab0bfc11 843 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 844 } while(0)
Kojto 109:9296ab0bfc11 845 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
Kojto 109:9296ab0bfc11 846 __IO uint32_t tmpreg; \
Kojto 109:9296ab0bfc11 847 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
Kojto 109:9296ab0bfc11 848 /* Delay after an RCC peripheral clock enabling */ \
Kojto 109:9296ab0bfc11 849 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
Kojto 109:9296ab0bfc11 850 UNUSED(tmpreg); \
Kojto 109:9296ab0bfc11 851 } while(0)
Kojto 109:9296ab0bfc11 852
Kojto 109:9296ab0bfc11 853 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 109:9296ab0bfc11 854 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 109:9296ab0bfc11 855 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 109:9296ab0bfc11 856 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 857 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto 109:9296ab0bfc11 858 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto 109:9296ab0bfc11 859 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 109:9296ab0bfc11 860 #define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
Kojto 109:9296ab0bfc11 861 /**
Kojto 109:9296ab0bfc11 862 * @}
Kojto 109:9296ab0bfc11 863 */
Kojto 109:9296ab0bfc11 864
Kojto 109:9296ab0bfc11 865 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 109:9296ab0bfc11 866 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 109:9296ab0bfc11 867 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 868 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 869 * using it.
Kojto 109:9296ab0bfc11 870 * @{
Kojto 109:9296ab0bfc11 871 */
Kojto 109:9296ab0bfc11 872 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto 109:9296ab0bfc11 873 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 109:9296ab0bfc11 874 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 109:9296ab0bfc11 875 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 109:9296ab0bfc11 876 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
Kojto 109:9296ab0bfc11 877 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
Kojto 109:9296ab0bfc11 878 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 109:9296ab0bfc11 879 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
Kojto 109:9296ab0bfc11 880 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto 109:9296ab0bfc11 881 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 109:9296ab0bfc11 882 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 109:9296ab0bfc11 883 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 109:9296ab0bfc11 884 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
Kojto 109:9296ab0bfc11 885 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
Kojto 109:9296ab0bfc11 886 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 109:9296ab0bfc11 887 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
Kojto 109:9296ab0bfc11 888 /**
Kojto 109:9296ab0bfc11 889 * @}
Kojto 109:9296ab0bfc11 890 */
Kojto 109:9296ab0bfc11 891
Kojto 109:9296ab0bfc11 892 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
Kojto 109:9296ab0bfc11 893 * @brief Force or release AHB peripheral reset.
Kojto 109:9296ab0bfc11 894 * @{
Kojto 109:9296ab0bfc11 895 */
Kojto 109:9296ab0bfc11 896 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto 109:9296ab0bfc11 897 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
Kojto 109:9296ab0bfc11 898 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
Kojto 109:9296ab0bfc11 899 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
Kojto 109:9296ab0bfc11 900 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
Kojto 109:9296ab0bfc11 901
Kojto 109:9296ab0bfc11 902 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto 109:9296ab0bfc11 903 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto 109:9296ab0bfc11 904 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto 109:9296ab0bfc11 905 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto 109:9296ab0bfc11 906 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto 109:9296ab0bfc11 907 /**
Kojto 109:9296ab0bfc11 908 * @}
Kojto 109:9296ab0bfc11 909 */
Kojto 109:9296ab0bfc11 910
Kojto 109:9296ab0bfc11 911 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
Kojto 109:9296ab0bfc11 912 * @brief Force or release APB1 peripheral reset.
Kojto 109:9296ab0bfc11 913 * @{
Kojto 109:9296ab0bfc11 914 */
Kojto 109:9296ab0bfc11 915 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 109:9296ab0bfc11 916 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 917 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 109:9296ab0bfc11 918 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 109:9296ab0bfc11 919 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 109:9296ab0bfc11 920 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 109:9296ab0bfc11 921
Kojto 109:9296ab0bfc11 922 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 109:9296ab0bfc11 923 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 924 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 109:9296ab0bfc11 925 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 109:9296ab0bfc11 926 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 109:9296ab0bfc11 927 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 109:9296ab0bfc11 928 /**
Kojto 109:9296ab0bfc11 929 * @}
Kojto 109:9296ab0bfc11 930 */
Kojto 109:9296ab0bfc11 931
Kojto 109:9296ab0bfc11 932 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
Kojto 109:9296ab0bfc11 933 * @brief Force or release APB2 peripheral reset.
Kojto 109:9296ab0bfc11 934 * @{
Kojto 109:9296ab0bfc11 935 */
Kojto 109:9296ab0bfc11 936 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 109:9296ab0bfc11 937 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 109:9296ab0bfc11 938 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
Kojto 109:9296ab0bfc11 939 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 109:9296ab0bfc11 940 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 941 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 109:9296ab0bfc11 942 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
Kojto 109:9296ab0bfc11 943 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
Kojto 109:9296ab0bfc11 944 #define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
Kojto 109:9296ab0bfc11 945
Kojto 109:9296ab0bfc11 946 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 109:9296ab0bfc11 947 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 109:9296ab0bfc11 948 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto 109:9296ab0bfc11 949 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 109:9296ab0bfc11 950 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 951 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 109:9296ab0bfc11 952 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto 109:9296ab0bfc11 953 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto 109:9296ab0bfc11 954 #define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
Kojto 109:9296ab0bfc11 955 /**
Kojto 109:9296ab0bfc11 956 * @}
Kojto 109:9296ab0bfc11 957 */
Kojto 109:9296ab0bfc11 958 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 109:9296ab0bfc11 959 * @{
Kojto 109:9296ab0bfc11 960 */
Kojto 109:9296ab0bfc11 961
Kojto 109:9296ab0bfc11 962 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 109:9296ab0bfc11 963 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 964 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 109:9296ab0bfc11 965 * you have to select another source of the system clock then stop the HSI.
Kojto 109:9296ab0bfc11 966 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 109:9296ab0bfc11 967 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 109:9296ab0bfc11 968 * system clock source.
Kojto 109:9296ab0bfc11 969 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 109:9296ab0bfc11 970 * clock cycles.
Kojto 109:9296ab0bfc11 971 */
Kojto 109:9296ab0bfc11 972 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto 109:9296ab0bfc11 973 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto 109:9296ab0bfc11 974
Kojto 109:9296ab0bfc11 975 /** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 109:9296ab0bfc11 976 * @note The calibration is used to compensate for the variations in voltage
Kojto 109:9296ab0bfc11 977 * and temperature that influence the frequency of the internal HSI RC.
Kojto 109:9296ab0bfc11 978 * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto 109:9296ab0bfc11 979 * (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 109:9296ab0bfc11 980 * This parameter must be a number between 0 and 0x1F.
Kojto 109:9296ab0bfc11 981 */
Kojto 109:9296ab0bfc11 982 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto 109:9296ab0bfc11 983 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
Kojto 109:9296ab0bfc11 984
Kojto 109:9296ab0bfc11 985 /**
Kojto 109:9296ab0bfc11 986 * @}
Kojto 109:9296ab0bfc11 987 */
Kojto 109:9296ab0bfc11 988
Kojto 109:9296ab0bfc11 989 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 109:9296ab0bfc11 990 * @{
Kojto 109:9296ab0bfc11 991 */
Kojto 109:9296ab0bfc11 992
Kojto 109:9296ab0bfc11 993 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 109:9296ab0bfc11 994 * @note After enabling the LSI, the application software should wait on
Kojto 109:9296ab0bfc11 995 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 109:9296ab0bfc11 996 * be used to clock the IWDG and/or the RTC.
Kojto 109:9296ab0bfc11 997 * @note LSI can not be disabled if the IWDG is running.
Kojto 109:9296ab0bfc11 998 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 109:9296ab0bfc11 999 * clock cycles.
Kojto 109:9296ab0bfc11 1000 */
Kojto 109:9296ab0bfc11 1001 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 109:9296ab0bfc11 1002 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 109:9296ab0bfc11 1003
Kojto 109:9296ab0bfc11 1004 /**
Kojto 109:9296ab0bfc11 1005 * @}
Kojto 109:9296ab0bfc11 1006 */
Kojto 109:9296ab0bfc11 1007
Kojto 109:9296ab0bfc11 1008 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 109:9296ab0bfc11 1009 * @{
Kojto 109:9296ab0bfc11 1010 */
Kojto 109:9296ab0bfc11 1011
Kojto 109:9296ab0bfc11 1012 /**
Kojto 109:9296ab0bfc11 1013 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 109:9296ab0bfc11 1014 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto 109:9296ab0bfc11 1015 * supported by this macro. User should request a transition to HSE Off
Kojto 109:9296ab0bfc11 1016 * first and then HSE On or HSE Bypass.
Kojto 109:9296ab0bfc11 1017 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 109:9296ab0bfc11 1018 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 109:9296ab0bfc11 1019 * is stable and can be used to clock the PLL and/or system clock.
Kojto 109:9296ab0bfc11 1020 * @note HSE state can not be changed if it is used directly or through the
Kojto 109:9296ab0bfc11 1021 * PLL as system clock. In this case, you have to select another source
Kojto 109:9296ab0bfc11 1022 * of the system clock then change the HSE state (ex. disable it).
Kojto 109:9296ab0bfc11 1023 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 1024 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
Kojto 109:9296ab0bfc11 1025 * was previously enabled you have to enable it again after calling this
Kojto 109:9296ab0bfc11 1026 * function.
Kojto 109:9296ab0bfc11 1027 * @param __STATE__: specifies the new state of the HSE.
Kojto 109:9296ab0bfc11 1028 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1029 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 109:9296ab0bfc11 1030 * 6 HSE oscillator clock cycles.
Kojto 109:9296ab0bfc11 1031 * @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto 109:9296ab0bfc11 1032 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto 109:9296ab0bfc11 1033 */
Kojto 109:9296ab0bfc11 1034 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto 109:9296ab0bfc11 1035 do{ \
Kojto 109:9296ab0bfc11 1036 if ((__STATE__) == RCC_HSE_ON) \
Kojto 109:9296ab0bfc11 1037 { \
Kojto 109:9296ab0bfc11 1038 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 109:9296ab0bfc11 1039 } \
Kojto 109:9296ab0bfc11 1040 else if ((__STATE__) == RCC_HSE_OFF) \
Kojto 109:9296ab0bfc11 1041 { \
Kojto 109:9296ab0bfc11 1042 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 109:9296ab0bfc11 1043 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 109:9296ab0bfc11 1044 } \
Kojto 109:9296ab0bfc11 1045 else if ((__STATE__) == RCC_HSE_BYPASS) \
Kojto 109:9296ab0bfc11 1046 { \
Kojto 109:9296ab0bfc11 1047 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 109:9296ab0bfc11 1048 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 109:9296ab0bfc11 1049 } \
Kojto 109:9296ab0bfc11 1050 else \
Kojto 109:9296ab0bfc11 1051 { \
Kojto 109:9296ab0bfc11 1052 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 109:9296ab0bfc11 1053 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 109:9296ab0bfc11 1054 } \
Kojto 109:9296ab0bfc11 1055 }while(0)
Kojto 109:9296ab0bfc11 1056
Kojto 109:9296ab0bfc11 1057 /**
Kojto 109:9296ab0bfc11 1058 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto 109:9296ab0bfc11 1059 * @note Predivision factor can not be changed if PLL is used as system clock
Kojto 109:9296ab0bfc11 1060 * In this case, you have to select another source of the system clock, disable the PLL and
Kojto 109:9296ab0bfc11 1061 * then change the HSE predivision factor.
Kojto 109:9296ab0bfc11 1062 * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
Kojto 109:9296ab0bfc11 1063 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto 109:9296ab0bfc11 1064 */
Kojto 109:9296ab0bfc11 1065 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
Kojto 109:9296ab0bfc11 1066 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
Kojto 109:9296ab0bfc11 1067
Kojto 109:9296ab0bfc11 1068 /**
Kojto 109:9296ab0bfc11 1069 * @}
Kojto 109:9296ab0bfc11 1070 */
Kojto 109:9296ab0bfc11 1071
Kojto 109:9296ab0bfc11 1072 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 109:9296ab0bfc11 1073 * @{
Kojto 109:9296ab0bfc11 1074 */
Kojto 109:9296ab0bfc11 1075
Kojto 109:9296ab0bfc11 1076 /**
Kojto 109:9296ab0bfc11 1077 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 109:9296ab0bfc11 1078 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 109:9296ab0bfc11 1079 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 109:9296ab0bfc11 1080 * this domain after reset, you have to enable write access using
Kojto 109:9296ab0bfc11 1081 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 109:9296ab0bfc11 1082 * (to be done once after reset).
Kojto 109:9296ab0bfc11 1083 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 109:9296ab0bfc11 1084 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 109:9296ab0bfc11 1085 * is stable and can be used to clock the RTC.
Kojto 109:9296ab0bfc11 1086 * @param __STATE__: specifies the new state of the LSE.
Kojto 109:9296ab0bfc11 1087 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1088 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 109:9296ab0bfc11 1089 * 6 LSE oscillator clock cycles.
Kojto 109:9296ab0bfc11 1090 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto 109:9296ab0bfc11 1091 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto 109:9296ab0bfc11 1092 */
Kojto 109:9296ab0bfc11 1093 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 109:9296ab0bfc11 1094 do{ \
Kojto 109:9296ab0bfc11 1095 if ((__STATE__) == RCC_LSE_ON) \
Kojto 109:9296ab0bfc11 1096 { \
Kojto 109:9296ab0bfc11 1097 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 109:9296ab0bfc11 1098 } \
Kojto 109:9296ab0bfc11 1099 else if ((__STATE__) == RCC_LSE_OFF) \
Kojto 109:9296ab0bfc11 1100 { \
Kojto 109:9296ab0bfc11 1101 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 109:9296ab0bfc11 1102 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 109:9296ab0bfc11 1103 } \
Kojto 109:9296ab0bfc11 1104 else if ((__STATE__) == RCC_LSE_BYPASS) \
Kojto 109:9296ab0bfc11 1105 { \
Kojto 109:9296ab0bfc11 1106 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 109:9296ab0bfc11 1107 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 109:9296ab0bfc11 1108 } \
Kojto 109:9296ab0bfc11 1109 else \
Kojto 109:9296ab0bfc11 1110 { \
Kojto 109:9296ab0bfc11 1111 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 109:9296ab0bfc11 1112 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 109:9296ab0bfc11 1113 } \
Kojto 109:9296ab0bfc11 1114 }while(0)
Kojto 109:9296ab0bfc11 1115
Kojto 109:9296ab0bfc11 1116 /**
Kojto 109:9296ab0bfc11 1117 * @}
Kojto 109:9296ab0bfc11 1118 */
Kojto 109:9296ab0bfc11 1119
Kojto 109:9296ab0bfc11 1120 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
Kojto 109:9296ab0bfc11 1121 * @{
Kojto 109:9296ab0bfc11 1122 */
Kojto 109:9296ab0bfc11 1123
Kojto 109:9296ab0bfc11 1124 /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
Kojto 109:9296ab0bfc11 1125 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 1126 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
Kojto 109:9296ab0bfc11 1127 * you have to select another source of the system clock then stop the HSI14.
Kojto 109:9296ab0bfc11 1128 * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
Kojto 109:9296ab0bfc11 1129 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
Kojto 109:9296ab0bfc11 1130 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto 109:9296ab0bfc11 1131 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
Kojto 109:9296ab0bfc11 1132 * clock cycles.
Kojto 109:9296ab0bfc11 1133 */
Kojto 109:9296ab0bfc11 1134 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto 109:9296ab0bfc11 1135 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto 109:9296ab0bfc11 1136
Kojto 109:9296ab0bfc11 1137 /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
Kojto 109:9296ab0bfc11 1138 */
Kojto 109:9296ab0bfc11 1139 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto 109:9296ab0bfc11 1140 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto 109:9296ab0bfc11 1141
Kojto 109:9296ab0bfc11 1142 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
Kojto 109:9296ab0bfc11 1143 * @note The calibration is used to compensate for the variations in voltage
Kojto 109:9296ab0bfc11 1144 * and temperature that influence the frequency of the internal HSI14 RC.
Kojto 109:9296ab0bfc11 1145 * @param __HSI14CalibrationValue__: specifies the calibration trimming value
Kojto 109:9296ab0bfc11 1146 * (default is RCC_HSI14CALIBRATION_DEFAULT).
Kojto 109:9296ab0bfc11 1147 * This parameter must be a number between 0 and 0x1F.
Kojto 109:9296ab0bfc11 1148 */
Kojto 109:9296ab0bfc11 1149 #define RCC_CR2_HSI14TRIM_BitNumber 3
Kojto 109:9296ab0bfc11 1150 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
Kojto 109:9296ab0bfc11 1151 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
Kojto 109:9296ab0bfc11 1152 /**
Kojto 109:9296ab0bfc11 1153 * @}
Kojto 109:9296ab0bfc11 1154 */
Kojto 109:9296ab0bfc11 1155
Kojto 109:9296ab0bfc11 1156 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
Kojto 109:9296ab0bfc11 1157 * @{
Kojto 109:9296ab0bfc11 1158 */
Kojto 109:9296ab0bfc11 1159
Kojto 109:9296ab0bfc11 1160 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 109:9296ab0bfc11 1161 * @param __USART1CLKSource__: specifies the USART1 clock source.
Kojto 109:9296ab0bfc11 1162 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1163 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
Kojto 109:9296ab0bfc11 1164 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 109:9296ab0bfc11 1165 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 109:9296ab0bfc11 1166 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 109:9296ab0bfc11 1167 */
Kojto 109:9296ab0bfc11 1168 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
Kojto 109:9296ab0bfc11 1169 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
Kojto 109:9296ab0bfc11 1170
Kojto 109:9296ab0bfc11 1171 /** @brief Macro to get the USART1 clock source.
Kojto 109:9296ab0bfc11 1172 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 1173 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
Kojto 109:9296ab0bfc11 1174 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 109:9296ab0bfc11 1175 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 109:9296ab0bfc11 1176 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 109:9296ab0bfc11 1177 */
Kojto 109:9296ab0bfc11 1178 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Kojto 109:9296ab0bfc11 1179 /**
Kojto 109:9296ab0bfc11 1180 * @}
Kojto 109:9296ab0bfc11 1181 */
Kojto 109:9296ab0bfc11 1182
Kojto 109:9296ab0bfc11 1183 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
Kojto 109:9296ab0bfc11 1184 * @{
Kojto 109:9296ab0bfc11 1185 */
Kojto 109:9296ab0bfc11 1186
Kojto 109:9296ab0bfc11 1187 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 109:9296ab0bfc11 1188 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
Kojto 109:9296ab0bfc11 1189 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1190 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 109:9296ab0bfc11 1191 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 109:9296ab0bfc11 1192 */
Kojto 109:9296ab0bfc11 1193 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
Kojto 109:9296ab0bfc11 1194 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
Kojto 109:9296ab0bfc11 1195
Kojto 109:9296ab0bfc11 1196 /** @brief Macro to get the I2C1 clock source.
Kojto 109:9296ab0bfc11 1197 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 1198 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 109:9296ab0bfc11 1199 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 109:9296ab0bfc11 1200 */
Kojto 109:9296ab0bfc11 1201 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Kojto 109:9296ab0bfc11 1202 /**
Kojto 109:9296ab0bfc11 1203 * @}
Kojto 109:9296ab0bfc11 1204 */
Kojto 109:9296ab0bfc11 1205
Kojto 109:9296ab0bfc11 1206
Kojto 109:9296ab0bfc11 1207 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 109:9296ab0bfc11 1208 * @{
Kojto 109:9296ab0bfc11 1209 */
Kojto 109:9296ab0bfc11 1210
Kojto 109:9296ab0bfc11 1211 /** @brief Macros to enable the main PLL.
Kojto 109:9296ab0bfc11 1212 * @note After enabling the main PLL, the application software should wait on
Kojto 109:9296ab0bfc11 1213 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 109:9296ab0bfc11 1214 * be used as system clock source.
Kojto 109:9296ab0bfc11 1215 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 1216 */
Kojto 109:9296ab0bfc11 1217 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 109:9296ab0bfc11 1218
Kojto 109:9296ab0bfc11 1219 /** @brief Macros to disable the main PLL.
Kojto 109:9296ab0bfc11 1220 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 109:9296ab0bfc11 1221 */
Kojto 109:9296ab0bfc11 1222 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 109:9296ab0bfc11 1223
Kojto 109:9296ab0bfc11 1224 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto 109:9296ab0bfc11 1225 * @note This function must be used only when the main PLL is disabled.
Kojto 109:9296ab0bfc11 1226 *
Kojto 109:9296ab0bfc11 1227 * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
Kojto 109:9296ab0bfc11 1228 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1229 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 109:9296ab0bfc11 1230 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 109:9296ab0bfc11 1231 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
Kojto 109:9296ab0bfc11 1232 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1233 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto 109:9296ab0bfc11 1234 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 1235 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto 109:9296ab0bfc11 1236 *
Kojto 109:9296ab0bfc11 1237 */
Kojto 109:9296ab0bfc11 1238 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
Kojto 109:9296ab0bfc11 1239 do { \
Kojto 109:9296ab0bfc11 1240 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto 109:9296ab0bfc11 1241 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
Kojto 109:9296ab0bfc11 1242 } while(0)
Kojto 109:9296ab0bfc11 1243
Kojto 109:9296ab0bfc11 1244 /** @brief Get oscillator clock selected as PLL input clock
Kojto 109:9296ab0bfc11 1245 * @retval The clock source used for PLL entry. The returned value can be one
Kojto 109:9296ab0bfc11 1246 * of the following:
Kojto 109:9296ab0bfc11 1247 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
Kojto 109:9296ab0bfc11 1248 */
Kojto 109:9296ab0bfc11 1249 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto 109:9296ab0bfc11 1250
Kojto 109:9296ab0bfc11 1251 /**
Kojto 109:9296ab0bfc11 1252 * @}
Kojto 109:9296ab0bfc11 1253 */
Kojto 109:9296ab0bfc11 1254
Kojto 109:9296ab0bfc11 1255 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 109:9296ab0bfc11 1256 * @{
Kojto 109:9296ab0bfc11 1257 */
Kojto 109:9296ab0bfc11 1258
Kojto 109:9296ab0bfc11 1259 /**
Kojto 109:9296ab0bfc11 1260 * @brief Macro to configure the system clock source.
Kojto 109:9296ab0bfc11 1261 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 109:9296ab0bfc11 1262 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1263 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
Kojto 109:9296ab0bfc11 1264 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 109:9296ab0bfc11 1265 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 109:9296ab0bfc11 1266 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 109:9296ab0bfc11 1267 */
Kojto 109:9296ab0bfc11 1268 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
Kojto 109:9296ab0bfc11 1269 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto 109:9296ab0bfc11 1270
Kojto 109:9296ab0bfc11 1271 /** @brief Macro to get the clock source used as system clock.
Kojto 109:9296ab0bfc11 1272 * @retval The clock source used as system clock. The returned value can be one
Kojto 109:9296ab0bfc11 1273 * of the following:
Kojto 109:9296ab0bfc11 1274 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto 109:9296ab0bfc11 1275 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto 109:9296ab0bfc11 1276 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto 109:9296ab0bfc11 1277 */
Kojto 109:9296ab0bfc11 1278 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto 109:9296ab0bfc11 1279
Kojto 109:9296ab0bfc11 1280 /**
Kojto 109:9296ab0bfc11 1281 * @}
Kojto 109:9296ab0bfc11 1282 */
Kojto 109:9296ab0bfc11 1283
Kojto 109:9296ab0bfc11 1284 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 109:9296ab0bfc11 1285 * @{
Kojto 109:9296ab0bfc11 1286 */
Kojto 109:9296ab0bfc11 1287
Kojto 109:9296ab0bfc11 1288 /** @brief Macro to configures the RTC clock (RTCCLK).
Kojto 109:9296ab0bfc11 1289 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 109:9296ab0bfc11 1290 * access is denied to this domain after reset, you have to enable write
Kojto 109:9296ab0bfc11 1291 * access using the Power Backup Access macro before to configure
Kojto 109:9296ab0bfc11 1292 * the RTC clock source (to be done once after reset).
Kojto 109:9296ab0bfc11 1293 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 109:9296ab0bfc11 1294 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto 109:9296ab0bfc11 1295 * a Power On Reset (POR).
Kojto 109:9296ab0bfc11 1296 *
Kojto 109:9296ab0bfc11 1297 * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto 109:9296ab0bfc11 1298 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1299 * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
Kojto 109:9296ab0bfc11 1300 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto 109:9296ab0bfc11 1301 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto 109:9296ab0bfc11 1302 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto 109:9296ab0bfc11 1303 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 109:9296ab0bfc11 1304 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 109:9296ab0bfc11 1305 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
Kojto 109:9296ab0bfc11 1306 * the RTC cannot be used in STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 1307 * @note The system must always be configured so as to get a PCLK frequency greater than or
Kojto 109:9296ab0bfc11 1308 * equal to the RTCCLK frequency for a proper operation of the RTC.
Kojto 109:9296ab0bfc11 1309 */
Kojto 109:9296ab0bfc11 1310 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto 109:9296ab0bfc11 1311
Kojto 109:9296ab0bfc11 1312 /** @brief macros to get the RTC clock source.
Kojto 109:9296ab0bfc11 1313 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 1314 * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
Kojto 109:9296ab0bfc11 1315 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto 109:9296ab0bfc11 1316 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto 109:9296ab0bfc11 1317 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto 109:9296ab0bfc11 1318 */
Kojto 109:9296ab0bfc11 1319 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Kojto 109:9296ab0bfc11 1320
Kojto 109:9296ab0bfc11 1321 /** @brief Macros to enable the the RTC clock.
Kojto 109:9296ab0bfc11 1322 * @note These macros must be used only after the RTC clock source was selected.
Kojto 109:9296ab0bfc11 1323 */
Kojto 109:9296ab0bfc11 1324 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 109:9296ab0bfc11 1325
Kojto 109:9296ab0bfc11 1326 /** @brief Macros to disable the the RTC clock.
Kojto 109:9296ab0bfc11 1327 * @note These macros must be used only after the RTC clock source was selected.
Kojto 109:9296ab0bfc11 1328 */
Kojto 109:9296ab0bfc11 1329 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 109:9296ab0bfc11 1330
Kojto 109:9296ab0bfc11 1331 /** @brief Macros to force the Backup domain reset.
Kojto 109:9296ab0bfc11 1332 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 109:9296ab0bfc11 1333 * and the RTC clock source selection in RCC_BDCR register.
Kojto 109:9296ab0bfc11 1334 */
Kojto 109:9296ab0bfc11 1335 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 109:9296ab0bfc11 1336
Kojto 109:9296ab0bfc11 1337 /** @brief Macros to release the Backup domain reset.
Kojto 109:9296ab0bfc11 1338 */
Kojto 109:9296ab0bfc11 1339 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 109:9296ab0bfc11 1340
Kojto 109:9296ab0bfc11 1341 /**
Kojto 109:9296ab0bfc11 1342 * @}
Kojto 109:9296ab0bfc11 1343 */
Kojto 109:9296ab0bfc11 1344
Kojto 109:9296ab0bfc11 1345 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 109:9296ab0bfc11 1346 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 109:9296ab0bfc11 1347 * @{
Kojto 109:9296ab0bfc11 1348 */
Kojto 109:9296ab0bfc11 1349
Kojto 109:9296ab0bfc11 1350 /** @brief Enable RCC interrupt.
Kojto 109:9296ab0bfc11 1351 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 109:9296ab0bfc11 1352 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 1353 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto 109:9296ab0bfc11 1354 * @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto 109:9296ab0bfc11 1355 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto 109:9296ab0bfc11 1356 * @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto 109:9296ab0bfc11 1357 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto 109:9296ab0bfc11 1358 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto 109:9296ab0bfc11 1359 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto 109:9296ab0bfc11 1360 */
Kojto 109:9296ab0bfc11 1361 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 109:9296ab0bfc11 1362
Kojto 109:9296ab0bfc11 1363 /** @brief Disable RCC interrupt.
Kojto 109:9296ab0bfc11 1364 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 109:9296ab0bfc11 1365 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 1366 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto 109:9296ab0bfc11 1367 * @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto 109:9296ab0bfc11 1368 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto 109:9296ab0bfc11 1369 * @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto 109:9296ab0bfc11 1370 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto 109:9296ab0bfc11 1371 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto 109:9296ab0bfc11 1372 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto 109:9296ab0bfc11 1373 */
Kojto 109:9296ab0bfc11 1374 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 109:9296ab0bfc11 1375
Kojto 109:9296ab0bfc11 1376 /** @brief Clear the RCC's interrupt pending bits.
Kojto 109:9296ab0bfc11 1377 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 109:9296ab0bfc11 1378 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 1379 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 109:9296ab0bfc11 1380 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 109:9296ab0bfc11 1381 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 109:9296ab0bfc11 1382 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 109:9296ab0bfc11 1383 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 109:9296ab0bfc11 1384 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 109:9296ab0bfc11 1385 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto 109:9296ab0bfc11 1386 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto 109:9296ab0bfc11 1387 */
Kojto 109:9296ab0bfc11 1388 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto 109:9296ab0bfc11 1389
Kojto 109:9296ab0bfc11 1390 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 109:9296ab0bfc11 1391 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 109:9296ab0bfc11 1392 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1393 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 109:9296ab0bfc11 1394 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 109:9296ab0bfc11 1395 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 109:9296ab0bfc11 1396 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 109:9296ab0bfc11 1397 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 109:9296ab0bfc11 1398 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 109:9296ab0bfc11 1399 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto 109:9296ab0bfc11 1400 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto 109:9296ab0bfc11 1401 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 109:9296ab0bfc11 1402 */
Kojto 109:9296ab0bfc11 1403 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 109:9296ab0bfc11 1404
Kojto 109:9296ab0bfc11 1405 /** @brief Set RMVF bit to clear the reset flags.
Kojto 109:9296ab0bfc11 1406 * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto 109:9296ab0bfc11 1407 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto 109:9296ab0bfc11 1408 */
Kojto 109:9296ab0bfc11 1409 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 109:9296ab0bfc11 1410
Kojto 109:9296ab0bfc11 1411 /** @brief Check RCC flag is set or not.
Kojto 109:9296ab0bfc11 1412 * @param __FLAG__: specifies the flag to check.
Kojto 109:9296ab0bfc11 1413 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1414 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto 109:9296ab0bfc11 1415 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto 109:9296ab0bfc11 1416 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto 109:9296ab0bfc11 1417 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
Kojto 109:9296ab0bfc11 1418 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
Kojto 109:9296ab0bfc11 1419 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto 109:9296ab0bfc11 1420 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto 109:9296ab0bfc11 1421 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
Kojto 109:9296ab0bfc11 1422 * @arg RCC_FLAG_PINRST: Pin reset.
Kojto 109:9296ab0bfc11 1423 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto 109:9296ab0bfc11 1424 * @arg RCC_FLAG_SFTRST: Software reset.
Kojto 109:9296ab0bfc11 1425 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto 109:9296ab0bfc11 1426 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto 109:9296ab0bfc11 1427 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto 109:9296ab0bfc11 1428 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 109:9296ab0bfc11 1429 */
Kojto 109:9296ab0bfc11 1430 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
Kojto 109:9296ab0bfc11 1431 (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
Kojto 109:9296ab0bfc11 1432 (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
Kojto 109:9296ab0bfc11 1433 RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto 109:9296ab0bfc11 1434
Kojto 109:9296ab0bfc11 1435 /**
Kojto 109:9296ab0bfc11 1436 * @}
Kojto 109:9296ab0bfc11 1437 */
Kojto 109:9296ab0bfc11 1438
Kojto 109:9296ab0bfc11 1439 /**
Kojto 109:9296ab0bfc11 1440 * @}
Kojto 109:9296ab0bfc11 1441 */
Kojto 109:9296ab0bfc11 1442
Kojto 109:9296ab0bfc11 1443 /* Include RCC HAL Extension module */
Kojto 109:9296ab0bfc11 1444 #include "stm32f0xx_hal_rcc_ex.h"
Kojto 109:9296ab0bfc11 1445
Kojto 109:9296ab0bfc11 1446 /* Exported functions --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 1447 /** @addtogroup RCC_Exported_Functions
Kojto 109:9296ab0bfc11 1448 * @{
Kojto 109:9296ab0bfc11 1449 */
Kojto 109:9296ab0bfc11 1450
Kojto 109:9296ab0bfc11 1451 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 109:9296ab0bfc11 1452 * @{
Kojto 109:9296ab0bfc11 1453 */
Kojto 109:9296ab0bfc11 1454
Kojto 109:9296ab0bfc11 1455 /* Initialization and de-initialization functions ******************************/
Kojto 109:9296ab0bfc11 1456 void HAL_RCC_DeInit(void);
Kojto 109:9296ab0bfc11 1457 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 109:9296ab0bfc11 1458 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 109:9296ab0bfc11 1459
Kojto 109:9296ab0bfc11 1460 /**
Kojto 109:9296ab0bfc11 1461 * @}
Kojto 109:9296ab0bfc11 1462 */
Kojto 109:9296ab0bfc11 1463
Kojto 109:9296ab0bfc11 1464 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 109:9296ab0bfc11 1465 * @{
Kojto 109:9296ab0bfc11 1466 */
Kojto 109:9296ab0bfc11 1467
Kojto 109:9296ab0bfc11 1468 /* Peripheral Control functions ************************************************/
Kojto 109:9296ab0bfc11 1469 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 109:9296ab0bfc11 1470 void HAL_RCC_EnableCSS(void);
Kojto 109:9296ab0bfc11 1471 void HAL_RCC_DisableCSS(void);
Kojto 109:9296ab0bfc11 1472 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 109:9296ab0bfc11 1473 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 109:9296ab0bfc11 1474 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 109:9296ab0bfc11 1475 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 109:9296ab0bfc11 1476 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 109:9296ab0bfc11 1477
Kojto 109:9296ab0bfc11 1478 /* CSS NMI IRQ handler */
Kojto 109:9296ab0bfc11 1479 void HAL_RCC_NMI_IRQHandler(void);
Kojto 109:9296ab0bfc11 1480
Kojto 109:9296ab0bfc11 1481 /* User Callbacks in non blocking mode (IT mode) */
Kojto 109:9296ab0bfc11 1482 void HAL_RCC_CSSCallback(void);
Kojto 109:9296ab0bfc11 1483
Kojto 109:9296ab0bfc11 1484 /**
Kojto 109:9296ab0bfc11 1485 * @}
Kojto 109:9296ab0bfc11 1486 */
Kojto 109:9296ab0bfc11 1487
Kojto 109:9296ab0bfc11 1488 /**
Kojto 109:9296ab0bfc11 1489 * @}
Kojto 109:9296ab0bfc11 1490 */
Kojto 109:9296ab0bfc11 1491
Kojto 109:9296ab0bfc11 1492 /**
Kojto 109:9296ab0bfc11 1493 * @}
Kojto 109:9296ab0bfc11 1494 */
Kojto 109:9296ab0bfc11 1495
Kojto 109:9296ab0bfc11 1496 /**
Kojto 109:9296ab0bfc11 1497 * @}
Kojto 109:9296ab0bfc11 1498 */
Kojto 109:9296ab0bfc11 1499
Kojto 109:9296ab0bfc11 1500 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 1501 }
Kojto 109:9296ab0bfc11 1502 #endif
Kojto 109:9296ab0bfc11 1503
Kojto 109:9296ab0bfc11 1504 #endif /* __STM32F0xx_HAL_RCC_H */
Kojto 109:9296ab0bfc11 1505
Kojto 109:9296ab0bfc11 1506 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 109:9296ab0bfc11 1507