Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NRF51_MICROBIT_B/nrf51_bitfields.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
104:b9ad9a133dc7 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 104:b9ad9a133dc7 1 /* Copyright (c) 2013, Nordic Semiconductor ASA
Kojto 104:b9ad9a133dc7 2 * All rights reserved.
Kojto 104:b9ad9a133dc7 3 *
Kojto 104:b9ad9a133dc7 4 * Redistribution and use in source and binary forms, with or without
Kojto 104:b9ad9a133dc7 5 * modification, are permitted provided that the following conditions are met:
Kojto 104:b9ad9a133dc7 6 *
Kojto 104:b9ad9a133dc7 7 * * Redistributions of source code must retain the above copyright notice, this
Kojto 104:b9ad9a133dc7 8 * list of conditions and the following disclaimer.
Kojto 104:b9ad9a133dc7 9 *
Kojto 104:b9ad9a133dc7 10 * * Redistributions in binary form must reproduce the above copyright notice,
Kojto 104:b9ad9a133dc7 11 * this list of conditions and the following disclaimer in the documentation
Kojto 104:b9ad9a133dc7 12 * and/or other materials provided with the distribution.
Kojto 104:b9ad9a133dc7 13 *
Kojto 104:b9ad9a133dc7 14 * * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto 104:b9ad9a133dc7 15 * contributors may be used to endorse or promote products derived from
Kojto 104:b9ad9a133dc7 16 * this software without specific prior written permission.
Kojto 104:b9ad9a133dc7 17 *
Kojto 104:b9ad9a133dc7 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 104:b9ad9a133dc7 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 104:b9ad9a133dc7 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 104:b9ad9a133dc7 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 104:b9ad9a133dc7 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 104:b9ad9a133dc7 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 104:b9ad9a133dc7 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 104:b9ad9a133dc7 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 104:b9ad9a133dc7 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 104:b9ad9a133dc7 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 104:b9ad9a133dc7 28 *
Kojto 104:b9ad9a133dc7 29 */
Kojto 104:b9ad9a133dc7 30 #ifndef __NRF51_BITS_H
Kojto 104:b9ad9a133dc7 31 #define __NRF51_BITS_H
Kojto 104:b9ad9a133dc7 32
Kojto 104:b9ad9a133dc7 33 /*lint ++flb "Enter library region */
Kojto 104:b9ad9a133dc7 34
Kojto 104:b9ad9a133dc7 35 #include <core_cm0.h>
Kojto 104:b9ad9a133dc7 36
Kojto 104:b9ad9a133dc7 37 /* Peripheral: AAR */
Kojto 104:b9ad9a133dc7 38 /* Description: Accelerated Address Resolver. */
Kojto 104:b9ad9a133dc7 39
Kojto 104:b9ad9a133dc7 40 /* Register: AAR_INTENSET */
Kojto 104:b9ad9a133dc7 41 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 42
Kojto 104:b9ad9a133dc7 43 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
Kojto 104:b9ad9a133dc7 44 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
Kojto 104:b9ad9a133dc7 45 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
Kojto 104:b9ad9a133dc7 46 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 47 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 48 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 49
Kojto 104:b9ad9a133dc7 50 /* Bit 1 : Enable interrupt on RESOLVED event. */
Kojto 104:b9ad9a133dc7 51 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
Kojto 104:b9ad9a133dc7 52 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
Kojto 104:b9ad9a133dc7 53 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 54 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 55 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 56
Kojto 104:b9ad9a133dc7 57 /* Bit 0 : Enable interrupt on END event. */
Kojto 104:b9ad9a133dc7 58 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 59 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 60 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 61 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 62 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 63
Kojto 104:b9ad9a133dc7 64 /* Register: AAR_INTENCLR */
Kojto 104:b9ad9a133dc7 65 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 66
Kojto 104:b9ad9a133dc7 67 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
Kojto 104:b9ad9a133dc7 68 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
Kojto 104:b9ad9a133dc7 69 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
Kojto 104:b9ad9a133dc7 70 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 71 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 72 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 73
Kojto 104:b9ad9a133dc7 74 /* Bit 1 : Disable interrupt on RESOLVED event. */
Kojto 104:b9ad9a133dc7 75 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
Kojto 104:b9ad9a133dc7 76 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
Kojto 104:b9ad9a133dc7 77 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 78 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 79 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 80
Kojto 104:b9ad9a133dc7 81 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto 104:b9ad9a133dc7 82 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 83 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 84 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 85 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 86 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 87
Kojto 104:b9ad9a133dc7 88 /* Register: AAR_STATUS */
Kojto 104:b9ad9a133dc7 89 /* Description: Resolution status. */
Kojto 104:b9ad9a133dc7 90
Kojto 104:b9ad9a133dc7 91 /* Bits 3..0 : The IRK used last time an address was resolved. */
Kojto 104:b9ad9a133dc7 92 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Kojto 104:b9ad9a133dc7 93 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
Kojto 104:b9ad9a133dc7 94
Kojto 104:b9ad9a133dc7 95 /* Register: AAR_ENABLE */
Kojto 104:b9ad9a133dc7 96 /* Description: Enable AAR. */
Kojto 104:b9ad9a133dc7 97
Kojto 104:b9ad9a133dc7 98 /* Bits 1..0 : Enable AAR. */
Kojto 104:b9ad9a133dc7 99 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 100 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 101 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
Kojto 104:b9ad9a133dc7 102 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
Kojto 104:b9ad9a133dc7 103
Kojto 104:b9ad9a133dc7 104 /* Register: AAR_NIRK */
Kojto 104:b9ad9a133dc7 105 /* Description: Number of Identity root Keys in the IRK data structure. */
Kojto 104:b9ad9a133dc7 106
Kojto 104:b9ad9a133dc7 107 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
Kojto 104:b9ad9a133dc7 108 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
Kojto 104:b9ad9a133dc7 109 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
Kojto 104:b9ad9a133dc7 110
Kojto 104:b9ad9a133dc7 111 /* Register: AAR_POWER */
Kojto 104:b9ad9a133dc7 112 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 113
Kojto 104:b9ad9a133dc7 114 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 115 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 116 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 117 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 118 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 119
Kojto 104:b9ad9a133dc7 120
Kojto 104:b9ad9a133dc7 121 /* Peripheral: ADC */
Kojto 104:b9ad9a133dc7 122 /* Description: Analog to digital converter. */
Kojto 104:b9ad9a133dc7 123
Kojto 104:b9ad9a133dc7 124 /* Register: ADC_INTENSET */
Kojto 104:b9ad9a133dc7 125 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 126
Kojto 104:b9ad9a133dc7 127 /* Bit 0 : Enable interrupt on END event. */
Kojto 104:b9ad9a133dc7 128 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 129 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 130 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 131 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 132 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 133
Kojto 104:b9ad9a133dc7 134 /* Register: ADC_INTENCLR */
Kojto 104:b9ad9a133dc7 135 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 136
Kojto 104:b9ad9a133dc7 137 /* Bit 0 : Disable interrupt on END event. */
Kojto 104:b9ad9a133dc7 138 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 139 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 140 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 141 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 142 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 143
Kojto 104:b9ad9a133dc7 144 /* Register: ADC_BUSY */
Kojto 104:b9ad9a133dc7 145 /* Description: ADC busy register. */
Kojto 104:b9ad9a133dc7 146
Kojto 104:b9ad9a133dc7 147 /* Bit 0 : ADC busy register. */
Kojto 104:b9ad9a133dc7 148 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
Kojto 104:b9ad9a133dc7 149 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
Kojto 104:b9ad9a133dc7 150 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
Kojto 104:b9ad9a133dc7 151 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
Kojto 104:b9ad9a133dc7 152
Kojto 104:b9ad9a133dc7 153 /* Register: ADC_ENABLE */
Kojto 104:b9ad9a133dc7 154 /* Description: ADC enable. */
Kojto 104:b9ad9a133dc7 155
Kojto 104:b9ad9a133dc7 156 /* Bits 1..0 : ADC enable. */
Kojto 104:b9ad9a133dc7 157 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 158 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 159 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
Kojto 104:b9ad9a133dc7 160 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
Kojto 104:b9ad9a133dc7 161
Kojto 104:b9ad9a133dc7 162 /* Register: ADC_CONFIG */
Kojto 104:b9ad9a133dc7 163 /* Description: ADC configuration register. */
Kojto 104:b9ad9a133dc7 164
Kojto 104:b9ad9a133dc7 165 /* Bits 17..16 : ADC external reference pin selection. */
Kojto 104:b9ad9a133dc7 166 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
Kojto 104:b9ad9a133dc7 167 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Kojto 104:b9ad9a133dc7 168 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
Kojto 104:b9ad9a133dc7 169 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
Kojto 104:b9ad9a133dc7 170 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
Kojto 104:b9ad9a133dc7 171
Kojto 104:b9ad9a133dc7 172 /* Bits 15..8 : ADC analog pin selection. */
Kojto 104:b9ad9a133dc7 173 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
Kojto 104:b9ad9a133dc7 174 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 104:b9ad9a133dc7 175 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
Kojto 104:b9ad9a133dc7 176 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
Kojto 104:b9ad9a133dc7 177 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
Kojto 104:b9ad9a133dc7 178 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
Kojto 104:b9ad9a133dc7 179 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
Kojto 104:b9ad9a133dc7 180 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
Kojto 104:b9ad9a133dc7 181 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
Kojto 104:b9ad9a133dc7 182 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
Kojto 104:b9ad9a133dc7 183 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
Kojto 104:b9ad9a133dc7 184
Kojto 104:b9ad9a133dc7 185 /* Bits 6..5 : ADC reference selection. */
Kojto 104:b9ad9a133dc7 186 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
Kojto 104:b9ad9a133dc7 187 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Kojto 104:b9ad9a133dc7 188 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
Kojto 104:b9ad9a133dc7 189 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
Kojto 104:b9ad9a133dc7 190 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
Kojto 104:b9ad9a133dc7 191 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
Kojto 104:b9ad9a133dc7 192
Kojto 104:b9ad9a133dc7 193 /* Bits 4..2 : ADC input selection. */
Kojto 104:b9ad9a133dc7 194 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
Kojto 104:b9ad9a133dc7 195 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
Kojto 104:b9ad9a133dc7 196 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
Kojto 104:b9ad9a133dc7 197 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
Kojto 104:b9ad9a133dc7 198 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
Kojto 104:b9ad9a133dc7 199 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
Kojto 104:b9ad9a133dc7 200 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
Kojto 104:b9ad9a133dc7 201
Kojto 104:b9ad9a133dc7 202 /* Bits 1..0 : ADC resolution. */
Kojto 104:b9ad9a133dc7 203 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
Kojto 104:b9ad9a133dc7 204 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
Kojto 104:b9ad9a133dc7 205 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
Kojto 104:b9ad9a133dc7 206 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
Kojto 104:b9ad9a133dc7 207 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
Kojto 104:b9ad9a133dc7 208
Kojto 104:b9ad9a133dc7 209 /* Register: ADC_RESULT */
Kojto 104:b9ad9a133dc7 210 /* Description: Result of ADC conversion. */
Kojto 104:b9ad9a133dc7 211
Kojto 104:b9ad9a133dc7 212 /* Bits 9..0 : Result of ADC conversion. */
Kojto 104:b9ad9a133dc7 213 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Kojto 104:b9ad9a133dc7 214 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Kojto 104:b9ad9a133dc7 215
Kojto 104:b9ad9a133dc7 216 /* Register: ADC_POWER */
Kojto 104:b9ad9a133dc7 217 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 218
Kojto 104:b9ad9a133dc7 219 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 220 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 221 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 222 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 223 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 224
Kojto 104:b9ad9a133dc7 225
Kojto 104:b9ad9a133dc7 226 /* Peripheral: AMLI */
Kojto 104:b9ad9a133dc7 227 /* Description: AHB Multi-Layer Interface. */
Kojto 104:b9ad9a133dc7 228
Kojto 104:b9ad9a133dc7 229 /* Register: AMLI_RAMPRI_CPU0 */
Kojto 104:b9ad9a133dc7 230 /* Description: Configurable priority configuration register for CPU0. */
Kojto 104:b9ad9a133dc7 231
Kojto 104:b9ad9a133dc7 232 /* Bits 31..28 : Configuration field for RAM block 7. */
Kojto 104:b9ad9a133dc7 233 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Kojto 104:b9ad9a133dc7 234 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Kojto 104:b9ad9a133dc7 235 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 236 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 237 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 238 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 239 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 240 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 241 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 242 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 243
Kojto 104:b9ad9a133dc7 244 /* Bits 27..24 : Configuration field for RAM block 6. */
Kojto 104:b9ad9a133dc7 245 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Kojto 104:b9ad9a133dc7 246 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Kojto 104:b9ad9a133dc7 247 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 248 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 249 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 250 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 251 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 252 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 253 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 254 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 255
Kojto 104:b9ad9a133dc7 256 /* Bits 23..20 : Configuration field for RAM block 5. */
Kojto 104:b9ad9a133dc7 257 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Kojto 104:b9ad9a133dc7 258 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Kojto 104:b9ad9a133dc7 259 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 260 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 261 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 262 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 263 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 264 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 265 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 266 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 267
Kojto 104:b9ad9a133dc7 268 /* Bits 19..16 : Configuration field for RAM block 4. */
Kojto 104:b9ad9a133dc7 269 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Kojto 104:b9ad9a133dc7 270 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Kojto 104:b9ad9a133dc7 271 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 272 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 273 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 274 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 275 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 276 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 277 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 278 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 279
Kojto 104:b9ad9a133dc7 280 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 104:b9ad9a133dc7 281 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 104:b9ad9a133dc7 282 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 104:b9ad9a133dc7 283 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 284 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 285 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 286 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 287 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 288 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 289 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 290 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 291
Kojto 104:b9ad9a133dc7 292 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 104:b9ad9a133dc7 293 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 104:b9ad9a133dc7 294 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 104:b9ad9a133dc7 295 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 296 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 297 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 298 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 299 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 300 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 301 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 302 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 303
Kojto 104:b9ad9a133dc7 304 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 104:b9ad9a133dc7 305 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 104:b9ad9a133dc7 306 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 104:b9ad9a133dc7 307 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 308 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 309 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 310 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 311 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 312 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 313 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 314 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 315
Kojto 104:b9ad9a133dc7 316 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 104:b9ad9a133dc7 317 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 104:b9ad9a133dc7 318 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 104:b9ad9a133dc7 319 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 320 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 321 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 322 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 323 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 324 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 325 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 326 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 327
Kojto 104:b9ad9a133dc7 328 /* Register: AMLI_RAMPRI_SPIS1 */
Kojto 104:b9ad9a133dc7 329 /* Description: Configurable priority configuration register for SPIS1. */
Kojto 104:b9ad9a133dc7 330
Kojto 104:b9ad9a133dc7 331 /* Bits 31..28 : Configuration field for RAM block 7. */
Kojto 104:b9ad9a133dc7 332 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Kojto 104:b9ad9a133dc7 333 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Kojto 104:b9ad9a133dc7 334 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 335 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 336 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 337 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 338 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 339 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 340 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 342
Kojto 104:b9ad9a133dc7 343 /* Bits 27..24 : Configuration field for RAM block 6. */
Kojto 104:b9ad9a133dc7 344 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Kojto 104:b9ad9a133dc7 345 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Kojto 104:b9ad9a133dc7 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 348 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 349 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 350 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 351 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 352 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 354
Kojto 104:b9ad9a133dc7 355 /* Bits 23..20 : Configuration field for RAM block 5. */
Kojto 104:b9ad9a133dc7 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Kojto 104:b9ad9a133dc7 357 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Kojto 104:b9ad9a133dc7 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 366
Kojto 104:b9ad9a133dc7 367 /* Bits 19..16 : Configuration field for RAM block 4. */
Kojto 104:b9ad9a133dc7 368 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Kojto 104:b9ad9a133dc7 369 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Kojto 104:b9ad9a133dc7 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 371 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 378
Kojto 104:b9ad9a133dc7 379 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 104:b9ad9a133dc7 380 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 104:b9ad9a133dc7 381 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 104:b9ad9a133dc7 382 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 383 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 390
Kojto 104:b9ad9a133dc7 391 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 104:b9ad9a133dc7 392 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 104:b9ad9a133dc7 393 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 104:b9ad9a133dc7 394 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 395 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 396 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 397 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 398 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 399 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 400 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 402
Kojto 104:b9ad9a133dc7 403 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 104:b9ad9a133dc7 404 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 104:b9ad9a133dc7 405 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 104:b9ad9a133dc7 406 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 407 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 408 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 409 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 410 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 411 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 412 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 414
Kojto 104:b9ad9a133dc7 415 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 104:b9ad9a133dc7 416 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 104:b9ad9a133dc7 417 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 104:b9ad9a133dc7 418 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 419 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 420 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 421 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 422 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 423 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 424 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 426
Kojto 104:b9ad9a133dc7 427 /* Register: AMLI_RAMPRI_RADIO */
Kojto 104:b9ad9a133dc7 428 /* Description: Configurable priority configuration register for RADIO. */
Kojto 104:b9ad9a133dc7 429
Kojto 104:b9ad9a133dc7 430 /* Bits 31..28 : Configuration field for RAM block 7. */
Kojto 104:b9ad9a133dc7 431 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Kojto 104:b9ad9a133dc7 432 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Kojto 104:b9ad9a133dc7 433 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 434 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 435 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 436 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 437 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 438 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 439 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 440 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 441
Kojto 104:b9ad9a133dc7 442 /* Bits 27..24 : Configuration field for RAM block 6. */
Kojto 104:b9ad9a133dc7 443 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Kojto 104:b9ad9a133dc7 444 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Kojto 104:b9ad9a133dc7 445 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 446 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 447 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 448 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 449 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 450 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 451 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 452 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 453
Kojto 104:b9ad9a133dc7 454 /* Bits 23..20 : Configuration field for RAM block 5. */
Kojto 104:b9ad9a133dc7 455 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Kojto 104:b9ad9a133dc7 456 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Kojto 104:b9ad9a133dc7 457 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 458 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 459 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 460 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 461 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 462 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 463 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 464 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 465
Kojto 104:b9ad9a133dc7 466 /* Bits 19..16 : Configuration field for RAM block 4. */
Kojto 104:b9ad9a133dc7 467 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Kojto 104:b9ad9a133dc7 468 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Kojto 104:b9ad9a133dc7 469 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 470 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 471 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 472 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 473 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 474 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 475 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 476 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 477
Kojto 104:b9ad9a133dc7 478 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 104:b9ad9a133dc7 479 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 104:b9ad9a133dc7 480 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 104:b9ad9a133dc7 481 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 482 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 483 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 484 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 485 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 486 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 487 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 488 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 489
Kojto 104:b9ad9a133dc7 490 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 104:b9ad9a133dc7 491 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 104:b9ad9a133dc7 492 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 104:b9ad9a133dc7 493 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 494 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 495 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 496 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 497 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 498 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 499 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 500 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 501
Kojto 104:b9ad9a133dc7 502 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 104:b9ad9a133dc7 503 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 104:b9ad9a133dc7 504 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 104:b9ad9a133dc7 505 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 506 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 507 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 508 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 509 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 510 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 511 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 512 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 513
Kojto 104:b9ad9a133dc7 514 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 104:b9ad9a133dc7 515 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 104:b9ad9a133dc7 516 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 104:b9ad9a133dc7 517 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 518 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 519 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 520 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 521 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 522 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 523 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 524 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 525
Kojto 104:b9ad9a133dc7 526 /* Register: AMLI_RAMPRI_ECB */
Kojto 104:b9ad9a133dc7 527 /* Description: Configurable priority configuration register for ECB. */
Kojto 104:b9ad9a133dc7 528
Kojto 104:b9ad9a133dc7 529 /* Bits 31..28 : Configuration field for RAM block 7. */
Kojto 104:b9ad9a133dc7 530 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Kojto 104:b9ad9a133dc7 531 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Kojto 104:b9ad9a133dc7 532 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 533 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 534 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 535 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 536 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 537 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 538 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 539 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 540
Kojto 104:b9ad9a133dc7 541 /* Bits 27..24 : Configuration field for RAM block 6. */
Kojto 104:b9ad9a133dc7 542 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Kojto 104:b9ad9a133dc7 543 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Kojto 104:b9ad9a133dc7 544 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 545 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 546 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 547 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 548 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 549 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 550 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 551 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 552
Kojto 104:b9ad9a133dc7 553 /* Bits 23..20 : Configuration field for RAM block 5. */
Kojto 104:b9ad9a133dc7 554 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Kojto 104:b9ad9a133dc7 555 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Kojto 104:b9ad9a133dc7 556 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 557 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 558 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 559 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 560 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 561 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 562 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 563 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 564
Kojto 104:b9ad9a133dc7 565 /* Bits 19..16 : Configuration field for RAM block 4. */
Kojto 104:b9ad9a133dc7 566 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Kojto 104:b9ad9a133dc7 567 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Kojto 104:b9ad9a133dc7 568 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 569 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 570 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 571 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 572 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 573 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 574 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 575 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 576
Kojto 104:b9ad9a133dc7 577 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 104:b9ad9a133dc7 578 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 104:b9ad9a133dc7 579 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 104:b9ad9a133dc7 580 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 581 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 582 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 583 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 584 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 585 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 586 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 587 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 588
Kojto 104:b9ad9a133dc7 589 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 104:b9ad9a133dc7 590 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 104:b9ad9a133dc7 591 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 104:b9ad9a133dc7 592 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 593 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 594 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 595 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 596 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 597 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 598 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 599 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 600
Kojto 104:b9ad9a133dc7 601 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 104:b9ad9a133dc7 602 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 104:b9ad9a133dc7 603 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 104:b9ad9a133dc7 604 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 605 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 606 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 607 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 608 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 609 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 610 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 611 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 612
Kojto 104:b9ad9a133dc7 613 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 104:b9ad9a133dc7 614 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 104:b9ad9a133dc7 615 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 104:b9ad9a133dc7 616 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 617 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 618 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 619 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 620 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 621 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 622 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 623 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 624
Kojto 104:b9ad9a133dc7 625 /* Register: AMLI_RAMPRI_CCM */
Kojto 104:b9ad9a133dc7 626 /* Description: Configurable priority configuration register for CCM. */
Kojto 104:b9ad9a133dc7 627
Kojto 104:b9ad9a133dc7 628 /* Bits 31..28 : Configuration field for RAM block 7. */
Kojto 104:b9ad9a133dc7 629 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Kojto 104:b9ad9a133dc7 630 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Kojto 104:b9ad9a133dc7 631 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 632 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 633 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 634 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 635 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 636 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 637 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 638 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 639
Kojto 104:b9ad9a133dc7 640 /* Bits 27..24 : Configuration field for RAM block 6. */
Kojto 104:b9ad9a133dc7 641 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Kojto 104:b9ad9a133dc7 642 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Kojto 104:b9ad9a133dc7 643 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 644 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 645 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 646 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 647 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 648 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 649 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 650 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 651
Kojto 104:b9ad9a133dc7 652 /* Bits 23..20 : Configuration field for RAM block 5. */
Kojto 104:b9ad9a133dc7 653 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Kojto 104:b9ad9a133dc7 654 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Kojto 104:b9ad9a133dc7 655 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 656 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 657 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 658 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 659 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 660 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 661 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 662 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 663
Kojto 104:b9ad9a133dc7 664 /* Bits 19..16 : Configuration field for RAM block 4. */
Kojto 104:b9ad9a133dc7 665 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Kojto 104:b9ad9a133dc7 666 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Kojto 104:b9ad9a133dc7 667 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 668 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 669 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 670 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 671 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 672 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 673 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 674 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 675
Kojto 104:b9ad9a133dc7 676 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 104:b9ad9a133dc7 677 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 104:b9ad9a133dc7 678 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 104:b9ad9a133dc7 679 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 680 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 681 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 682 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 683 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 684 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 685 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 686 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 687
Kojto 104:b9ad9a133dc7 688 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 104:b9ad9a133dc7 689 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 104:b9ad9a133dc7 690 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 104:b9ad9a133dc7 691 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 692 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 693 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 694 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 695 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 696 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 697 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 698 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 699
Kojto 104:b9ad9a133dc7 700 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 104:b9ad9a133dc7 701 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 104:b9ad9a133dc7 702 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 104:b9ad9a133dc7 703 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 704 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 705 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 706 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 707 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 708 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 709 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 710 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 711
Kojto 104:b9ad9a133dc7 712 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 104:b9ad9a133dc7 713 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 104:b9ad9a133dc7 714 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 104:b9ad9a133dc7 715 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 716 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 717 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 718 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 719 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 720 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 721 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 722 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 723
Kojto 104:b9ad9a133dc7 724 /* Register: AMLI_RAMPRI_AAR */
Kojto 104:b9ad9a133dc7 725 /* Description: Configurable priority configuration register for AAR. */
Kojto 104:b9ad9a133dc7 726
Kojto 104:b9ad9a133dc7 727 /* Bits 31..28 : Configuration field for RAM block 7. */
Kojto 104:b9ad9a133dc7 728 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Kojto 104:b9ad9a133dc7 729 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Kojto 104:b9ad9a133dc7 730 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 731 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 732 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 733 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 734 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 735 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 736 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 737 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 738
Kojto 104:b9ad9a133dc7 739 /* Bits 27..24 : Configuration field for RAM block 6. */
Kojto 104:b9ad9a133dc7 740 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Kojto 104:b9ad9a133dc7 741 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Kojto 104:b9ad9a133dc7 742 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 743 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 744 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 745 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 746 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 747 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 748 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 749 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 750
Kojto 104:b9ad9a133dc7 751 /* Bits 23..20 : Configuration field for RAM block 5. */
Kojto 104:b9ad9a133dc7 752 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Kojto 104:b9ad9a133dc7 753 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Kojto 104:b9ad9a133dc7 754 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 755 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 756 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 757 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 758 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 759 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 760 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 761 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 762
Kojto 104:b9ad9a133dc7 763 /* Bits 19..16 : Configuration field for RAM block 4. */
Kojto 104:b9ad9a133dc7 764 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Kojto 104:b9ad9a133dc7 765 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Kojto 104:b9ad9a133dc7 766 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 767 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 768 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 769 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 770 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 771 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 772 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 773 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 774
Kojto 104:b9ad9a133dc7 775 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 104:b9ad9a133dc7 776 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 104:b9ad9a133dc7 777 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 104:b9ad9a133dc7 778 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 779 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 780 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 781 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 782 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 783 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 784 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 785 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 786
Kojto 104:b9ad9a133dc7 787 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 104:b9ad9a133dc7 788 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 104:b9ad9a133dc7 789 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 104:b9ad9a133dc7 790 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 791 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 792 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 793 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 794 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 795 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 796 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 797 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 798
Kojto 104:b9ad9a133dc7 799 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 104:b9ad9a133dc7 800 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 104:b9ad9a133dc7 801 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 104:b9ad9a133dc7 802 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 803 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 804 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 805 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 806 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 807 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 808 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 809 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 810
Kojto 104:b9ad9a133dc7 811 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 104:b9ad9a133dc7 812 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 104:b9ad9a133dc7 813 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 104:b9ad9a133dc7 814 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
Kojto 104:b9ad9a133dc7 815 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
Kojto 104:b9ad9a133dc7 816 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
Kojto 104:b9ad9a133dc7 817 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
Kojto 104:b9ad9a133dc7 818 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
Kojto 104:b9ad9a133dc7 819 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
Kojto 104:b9ad9a133dc7 820 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
Kojto 104:b9ad9a133dc7 821 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
Kojto 104:b9ad9a133dc7 822
Kojto 104:b9ad9a133dc7 823 /* Peripheral: CCM */
Kojto 104:b9ad9a133dc7 824 /* Description: AES CCM Mode Encryption. */
Kojto 104:b9ad9a133dc7 825
Kojto 104:b9ad9a133dc7 826 /* Register: CCM_SHORTS */
Kojto 104:b9ad9a133dc7 827 /* Description: Shortcuts for the CCM. */
Kojto 104:b9ad9a133dc7 828
Kojto 104:b9ad9a133dc7 829 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
Kojto 104:b9ad9a133dc7 830 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
Kojto 104:b9ad9a133dc7 831 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
Kojto 104:b9ad9a133dc7 832 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 833 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 834
Kojto 104:b9ad9a133dc7 835 /* Register: CCM_INTENSET */
Kojto 104:b9ad9a133dc7 836 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 837
Kojto 104:b9ad9a133dc7 838 /* Bit 2 : Enable interrupt on ERROR event. */
Kojto 104:b9ad9a133dc7 839 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
Kojto 104:b9ad9a133dc7 840 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 104:b9ad9a133dc7 841 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 842 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 843 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 844
Kojto 104:b9ad9a133dc7 845 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
Kojto 104:b9ad9a133dc7 846 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
Kojto 104:b9ad9a133dc7 847 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
Kojto 104:b9ad9a133dc7 848 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 849 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 850 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 851
Kojto 104:b9ad9a133dc7 852 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
Kojto 104:b9ad9a133dc7 853 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
Kojto 104:b9ad9a133dc7 854 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
Kojto 104:b9ad9a133dc7 855 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 856 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 857 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 858
Kojto 104:b9ad9a133dc7 859 /* Register: CCM_INTENCLR */
Kojto 104:b9ad9a133dc7 860 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 861
Kojto 104:b9ad9a133dc7 862 /* Bit 2 : Disable interrupt on ERROR event. */
Kojto 104:b9ad9a133dc7 863 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
Kojto 104:b9ad9a133dc7 864 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 104:b9ad9a133dc7 865 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 866 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 867 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 868
Kojto 104:b9ad9a133dc7 869 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
Kojto 104:b9ad9a133dc7 870 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
Kojto 104:b9ad9a133dc7 871 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
Kojto 104:b9ad9a133dc7 872 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 873 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 874 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 875
Kojto 104:b9ad9a133dc7 876 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto 104:b9ad9a133dc7 877 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
Kojto 104:b9ad9a133dc7 878 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
Kojto 104:b9ad9a133dc7 879 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 880 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 881 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 882
Kojto 104:b9ad9a133dc7 883 /* Register: CCM_MICSTATUS */
Kojto 104:b9ad9a133dc7 884 /* Description: CCM RX MIC check result. */
Kojto 104:b9ad9a133dc7 885
Kojto 104:b9ad9a133dc7 886 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
Kojto 104:b9ad9a133dc7 887 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
Kojto 104:b9ad9a133dc7 888 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
Kojto 104:b9ad9a133dc7 889 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
Kojto 104:b9ad9a133dc7 890 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
Kojto 104:b9ad9a133dc7 891
Kojto 104:b9ad9a133dc7 892 /* Register: CCM_ENABLE */
Kojto 104:b9ad9a133dc7 893 /* Description: CCM enable. */
Kojto 104:b9ad9a133dc7 894
Kojto 104:b9ad9a133dc7 895 /* Bits 1..0 : CCM enable. */
Kojto 104:b9ad9a133dc7 896 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 897 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 898 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
Kojto 104:b9ad9a133dc7 899 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
Kojto 104:b9ad9a133dc7 900
Kojto 104:b9ad9a133dc7 901 /* Register: CCM_MODE */
Kojto 104:b9ad9a133dc7 902 /* Description: Operation mode. */
Kojto 104:b9ad9a133dc7 903
Kojto 104:b9ad9a133dc7 904 /* Bit 0 : CCM mode operation. */
Kojto 104:b9ad9a133dc7 905 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 104:b9ad9a133dc7 906 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 104:b9ad9a133dc7 907 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
Kojto 104:b9ad9a133dc7 908 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
Kojto 104:b9ad9a133dc7 909
Kojto 104:b9ad9a133dc7 910 /* Register: CCM_POWER */
Kojto 104:b9ad9a133dc7 911 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 912
Kojto 104:b9ad9a133dc7 913 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 914 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 915 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 916 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 917 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 918
Kojto 104:b9ad9a133dc7 919
Kojto 104:b9ad9a133dc7 920 /* Peripheral: CLOCK */
Kojto 104:b9ad9a133dc7 921 /* Description: Clock control. */
Kojto 104:b9ad9a133dc7 922
Kojto 104:b9ad9a133dc7 923 /* Register: CLOCK_INTENSET */
Kojto 104:b9ad9a133dc7 924 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 925
Kojto 104:b9ad9a133dc7 926 /* Bit 4 : Enable interrupt on CTTO event. */
Kojto 104:b9ad9a133dc7 927 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
Kojto 104:b9ad9a133dc7 928 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
Kojto 104:b9ad9a133dc7 929 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 930 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 931 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 932
Kojto 104:b9ad9a133dc7 933 /* Bit 3 : Enable interrupt on DONE event. */
Kojto 104:b9ad9a133dc7 934 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
Kojto 104:b9ad9a133dc7 935 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
Kojto 104:b9ad9a133dc7 936 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 937 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 938 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 939
Kojto 104:b9ad9a133dc7 940 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
Kojto 104:b9ad9a133dc7 941 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 942 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 943 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 944 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 945 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 946
Kojto 104:b9ad9a133dc7 947 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
Kojto 104:b9ad9a133dc7 948 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 949 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 950 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 951 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 952 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 953
Kojto 104:b9ad9a133dc7 954 /* Register: CLOCK_INTENCLR */
Kojto 104:b9ad9a133dc7 955 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 956
Kojto 104:b9ad9a133dc7 957 /* Bit 4 : Disable interrupt on CTTO event. */
Kojto 104:b9ad9a133dc7 958 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
Kojto 104:b9ad9a133dc7 959 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
Kojto 104:b9ad9a133dc7 960 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 961 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 962 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 963
Kojto 104:b9ad9a133dc7 964 /* Bit 3 : Disable interrupt on DONE event. */
Kojto 104:b9ad9a133dc7 965 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
Kojto 104:b9ad9a133dc7 966 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
Kojto 104:b9ad9a133dc7 967 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 968 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 969 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 970
Kojto 104:b9ad9a133dc7 971 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
Kojto 104:b9ad9a133dc7 972 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 973 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 974 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 975 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 976 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 977
Kojto 104:b9ad9a133dc7 978 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
Kojto 104:b9ad9a133dc7 979 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 980 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
Kojto 104:b9ad9a133dc7 981 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 982 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 983 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 984
Kojto 104:b9ad9a133dc7 985 /* Register: CLOCK_HFCLKRUN */
Kojto 104:b9ad9a133dc7 986 /* Description: Task HFCLKSTART trigger status. */
Kojto 104:b9ad9a133dc7 987
Kojto 104:b9ad9a133dc7 988 /* Bit 0 : Task HFCLKSTART trigger status. */
Kojto 104:b9ad9a133dc7 989 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Kojto 104:b9ad9a133dc7 990 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
Kojto 104:b9ad9a133dc7 991 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
Kojto 104:b9ad9a133dc7 992 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
Kojto 104:b9ad9a133dc7 993
Kojto 104:b9ad9a133dc7 994 /* Register: CLOCK_HFCLKSTAT */
Kojto 104:b9ad9a133dc7 995 /* Description: High frequency clock status. */
Kojto 104:b9ad9a133dc7 996
Kojto 104:b9ad9a133dc7 997 /* Bit 16 : State for the HFCLK. */
Kojto 104:b9ad9a133dc7 998 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
Kojto 104:b9ad9a133dc7 999 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
Kojto 104:b9ad9a133dc7 1000 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
Kojto 104:b9ad9a133dc7 1001 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
Kojto 104:b9ad9a133dc7 1002
Kojto 104:b9ad9a133dc7 1003 /* Bit 0 : Active clock source for the HF clock. */
Kojto 104:b9ad9a133dc7 1004 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 104:b9ad9a133dc7 1005 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 104:b9ad9a133dc7 1006 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
Kojto 104:b9ad9a133dc7 1007 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
Kojto 104:b9ad9a133dc7 1008
Kojto 104:b9ad9a133dc7 1009 /* Register: CLOCK_LFCLKRUN */
Kojto 104:b9ad9a133dc7 1010 /* Description: Task LFCLKSTART triggered status. */
Kojto 104:b9ad9a133dc7 1011
Kojto 104:b9ad9a133dc7 1012 /* Bit 0 : Task LFCLKSTART triggered status. */
Kojto 104:b9ad9a133dc7 1013 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Kojto 104:b9ad9a133dc7 1014 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
Kojto 104:b9ad9a133dc7 1015 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
Kojto 104:b9ad9a133dc7 1016 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
Kojto 104:b9ad9a133dc7 1017
Kojto 104:b9ad9a133dc7 1018 /* Register: CLOCK_LFCLKSTAT */
Kojto 104:b9ad9a133dc7 1019 /* Description: Low frequency clock status. */
Kojto 104:b9ad9a133dc7 1020
Kojto 104:b9ad9a133dc7 1021 /* Bit 16 : State for the LF clock. */
Kojto 104:b9ad9a133dc7 1022 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
Kojto 104:b9ad9a133dc7 1023 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
Kojto 104:b9ad9a133dc7 1024 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
Kojto 104:b9ad9a133dc7 1025 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
Kojto 104:b9ad9a133dc7 1026
Kojto 104:b9ad9a133dc7 1027 /* Bits 1..0 : Active clock source for the LF clock. */
Kojto 104:b9ad9a133dc7 1028 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 104:b9ad9a133dc7 1029 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 104:b9ad9a133dc7 1030 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
Kojto 104:b9ad9a133dc7 1031 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
Kojto 104:b9ad9a133dc7 1032 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
Kojto 104:b9ad9a133dc7 1033
Kojto 104:b9ad9a133dc7 1034 /* Register: CLOCK_LFCLKSRCCOPY */
Kojto 104:b9ad9a133dc7 1035 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto 104:b9ad9a133dc7 1036
Kojto 104:b9ad9a133dc7 1037 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto 104:b9ad9a133dc7 1038 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 104:b9ad9a133dc7 1039 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 104:b9ad9a133dc7 1040 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
Kojto 104:b9ad9a133dc7 1041 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
Kojto 104:b9ad9a133dc7 1042 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
Kojto 104:b9ad9a133dc7 1043
Kojto 104:b9ad9a133dc7 1044 /* Register: CLOCK_LFCLKSRC */
Kojto 104:b9ad9a133dc7 1045 /* Description: Clock source for the LFCLK clock. */
Kojto 104:b9ad9a133dc7 1046
Kojto 104:b9ad9a133dc7 1047 /* Bits 1..0 : Clock source. */
Kojto 104:b9ad9a133dc7 1048 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 104:b9ad9a133dc7 1049 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 104:b9ad9a133dc7 1050 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
Kojto 104:b9ad9a133dc7 1051 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
Kojto 104:b9ad9a133dc7 1052 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
Kojto 104:b9ad9a133dc7 1053
Kojto 104:b9ad9a133dc7 1054 /* Register: CLOCK_CTIV */
Kojto 104:b9ad9a133dc7 1055 /* Description: Calibration timer interval. */
Kojto 104:b9ad9a133dc7 1056
Kojto 104:b9ad9a133dc7 1057 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
Kojto 104:b9ad9a133dc7 1058 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
Kojto 104:b9ad9a133dc7 1059 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
Kojto 104:b9ad9a133dc7 1060
Kojto 104:b9ad9a133dc7 1061 /* Register: CLOCK_XTALFREQ */
Kojto 104:b9ad9a133dc7 1062 /* Description: Crystal frequency. */
Kojto 104:b9ad9a133dc7 1063
Kojto 104:b9ad9a133dc7 1064 /* Bits 7..0 : External Xtal frequency selection. */
Kojto 104:b9ad9a133dc7 1065 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
Kojto 104:b9ad9a133dc7 1066 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
Kojto 104:b9ad9a133dc7 1067 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
Kojto 104:b9ad9a133dc7 1068 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
Kojto 104:b9ad9a133dc7 1069
Kojto 104:b9ad9a133dc7 1070
Kojto 104:b9ad9a133dc7 1071 /* Peripheral: ECB */
Kojto 104:b9ad9a133dc7 1072 /* Description: AES ECB Mode Encryption. */
Kojto 104:b9ad9a133dc7 1073
Kojto 104:b9ad9a133dc7 1074 /* Register: ECB_INTENSET */
Kojto 104:b9ad9a133dc7 1075 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 1076
Kojto 104:b9ad9a133dc7 1077 /* Bit 1 : Enable interrupt on ERRORECB event. */
Kojto 104:b9ad9a133dc7 1078 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
Kojto 104:b9ad9a133dc7 1079 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
Kojto 104:b9ad9a133dc7 1080 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 1081 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 1082 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 1083
Kojto 104:b9ad9a133dc7 1084 /* Bit 0 : Enable interrupt on ENDECB event. */
Kojto 104:b9ad9a133dc7 1085 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
Kojto 104:b9ad9a133dc7 1086 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
Kojto 104:b9ad9a133dc7 1087 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 1088 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 1089 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 1090
Kojto 104:b9ad9a133dc7 1091 /* Register: ECB_INTENCLR */
Kojto 104:b9ad9a133dc7 1092 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 1093
Kojto 104:b9ad9a133dc7 1094 /* Bit 1 : Disable interrupt on ERRORECB event. */
Kojto 104:b9ad9a133dc7 1095 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
Kojto 104:b9ad9a133dc7 1096 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
Kojto 104:b9ad9a133dc7 1097 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 1098 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 1099 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 1100
Kojto 104:b9ad9a133dc7 1101 /* Bit 0 : Disable interrupt on ENDECB event. */
Kojto 104:b9ad9a133dc7 1102 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
Kojto 104:b9ad9a133dc7 1103 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
Kojto 104:b9ad9a133dc7 1104 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 1105 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 1106 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 1107
Kojto 104:b9ad9a133dc7 1108 /* Register: ECB_POWER */
Kojto 104:b9ad9a133dc7 1109 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 1110
Kojto 104:b9ad9a133dc7 1111 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 1112 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 1113 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 1114 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 1115 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 1116
Kojto 104:b9ad9a133dc7 1117
Kojto 104:b9ad9a133dc7 1118 /* Peripheral: FICR */
Kojto 104:b9ad9a133dc7 1119 /* Description: Factory Information Configuration. */
Kojto 104:b9ad9a133dc7 1120
Kojto 104:b9ad9a133dc7 1121 /* Register: FICR_PPFC */
Kojto 104:b9ad9a133dc7 1122 /* Description: Pre-programmed factory code present. */
Kojto 104:b9ad9a133dc7 1123
Kojto 104:b9ad9a133dc7 1124 /* Bits 7..0 : Pre-programmed factory code present. */
Kojto 104:b9ad9a133dc7 1125 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
Kojto 104:b9ad9a133dc7 1126 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
Kojto 104:b9ad9a133dc7 1127 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
Kojto 104:b9ad9a133dc7 1128 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
Kojto 104:b9ad9a133dc7 1129
Kojto 104:b9ad9a133dc7 1130 /* Register: FICR_CONFIGID */
Kojto 104:b9ad9a133dc7 1131 /* Description: Configuration identifier. */
Kojto 104:b9ad9a133dc7 1132
Kojto 104:b9ad9a133dc7 1133 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
Kojto 104:b9ad9a133dc7 1134 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
Kojto 104:b9ad9a133dc7 1135 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
Kojto 104:b9ad9a133dc7 1136
Kojto 104:b9ad9a133dc7 1137 /* Bits 15..0 : Hardware Identification Number. */
Kojto 104:b9ad9a133dc7 1138 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
Kojto 104:b9ad9a133dc7 1139 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
Kojto 104:b9ad9a133dc7 1140
Kojto 104:b9ad9a133dc7 1141 /* Register: FICR_DEVICEADDRTYPE */
Kojto 104:b9ad9a133dc7 1142 /* Description: Device address type. */
Kojto 104:b9ad9a133dc7 1143
Kojto 104:b9ad9a133dc7 1144 /* Bit 0 : Device address type. */
Kojto 104:b9ad9a133dc7 1145 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
Kojto 104:b9ad9a133dc7 1146 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
Kojto 104:b9ad9a133dc7 1147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
Kojto 104:b9ad9a133dc7 1148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
Kojto 104:b9ad9a133dc7 1149
Kojto 104:b9ad9a133dc7 1150 /* Register: FICR_OVERRIDEEN */
Kojto 104:b9ad9a133dc7 1151 /* Description: Radio calibration override enable. */
Kojto 104:b9ad9a133dc7 1152
Kojto 104:b9ad9a133dc7 1153 /* Bit 3 : Override default values for BLE_1Mbit mode. */
Kojto 104:b9ad9a133dc7 1154 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
Kojto 104:b9ad9a133dc7 1155 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
Kojto 104:b9ad9a133dc7 1156 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
Kojto 104:b9ad9a133dc7 1157 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
Kojto 104:b9ad9a133dc7 1158
Kojto 104:b9ad9a133dc7 1159 /* Bit 0 : Override default values for NRF_1Mbit mode. */
Kojto 104:b9ad9a133dc7 1160 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
Kojto 104:b9ad9a133dc7 1161 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
Kojto 104:b9ad9a133dc7 1162 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
Kojto 104:b9ad9a133dc7 1163 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
Kojto 104:b9ad9a133dc7 1164
Kojto 104:b9ad9a133dc7 1165 /* Register: FICR_INFO_PART */
Kojto 104:b9ad9a133dc7 1166 /* Description: Part code */
Kojto 104:b9ad9a133dc7 1167
Kojto 104:b9ad9a133dc7 1168 /* Bits 31..0 : Part code */
Kojto 104:b9ad9a133dc7 1169 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
Kojto 104:b9ad9a133dc7 1170 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
Kojto 104:b9ad9a133dc7 1171 #define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
Kojto 104:b9ad9a133dc7 1172 #define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
Kojto 104:b9ad9a133dc7 1173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Kojto 104:b9ad9a133dc7 1174
Kojto 104:b9ad9a133dc7 1175 /* Register: FICR_INFO_VARIANT */
Kojto 104:b9ad9a133dc7 1176 /* Description: Part variant */
Kojto 104:b9ad9a133dc7 1177
Kojto 104:b9ad9a133dc7 1178 /* Bits 31..0 : Part variant */
Kojto 104:b9ad9a133dc7 1179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
Kojto 104:b9ad9a133dc7 1180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
Kojto 104:b9ad9a133dc7 1181 #define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
Kojto 104:b9ad9a133dc7 1182 #define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
Kojto 104:b9ad9a133dc7 1183 #define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
Kojto 104:b9ad9a133dc7 1184 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Kojto 104:b9ad9a133dc7 1185
Kojto 104:b9ad9a133dc7 1186 /* Register: FICR_INFO_PACKAGE */
Kojto 104:b9ad9a133dc7 1187 /* Description: Package option */
Kojto 104:b9ad9a133dc7 1188
Kojto 104:b9ad9a133dc7 1189 /* Bits 31..0 : Package option */
Kojto 104:b9ad9a133dc7 1190 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
Kojto 104:b9ad9a133dc7 1191 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
Kojto 104:b9ad9a133dc7 1192 #define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
Kojto 104:b9ad9a133dc7 1193 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
Kojto 104:b9ad9a133dc7 1194 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
Kojto 104:b9ad9a133dc7 1195 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
Kojto 104:b9ad9a133dc7 1196 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
Kojto 104:b9ad9a133dc7 1197 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Kojto 104:b9ad9a133dc7 1198
Kojto 104:b9ad9a133dc7 1199 /* Register: FICR_INFO_RAM */
Kojto 104:b9ad9a133dc7 1200 /* Description: RAM variant */
Kojto 104:b9ad9a133dc7 1201
Kojto 104:b9ad9a133dc7 1202 /* Bits 31..0 : RAM variant */
Kojto 104:b9ad9a133dc7 1203 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
Kojto 104:b9ad9a133dc7 1204 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
Kojto 104:b9ad9a133dc7 1205 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Kojto 104:b9ad9a133dc7 1206 #define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
Kojto 104:b9ad9a133dc7 1207 #define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
Kojto 104:b9ad9a133dc7 1208
Kojto 104:b9ad9a133dc7 1209 /* Register: FICR_INFO_FLASH */
Kojto 104:b9ad9a133dc7 1210 /* Description: Flash variant */
Kojto 104:b9ad9a133dc7 1211
Kojto 104:b9ad9a133dc7 1212 /* Bits 31..0 : Flash variant */
Kojto 104:b9ad9a133dc7 1213 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
Kojto 104:b9ad9a133dc7 1214 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
Kojto 104:b9ad9a133dc7 1215 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Kojto 104:b9ad9a133dc7 1216 #define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
Kojto 104:b9ad9a133dc7 1217 #define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
Kojto 104:b9ad9a133dc7 1218
Kojto 104:b9ad9a133dc7 1219
Kojto 104:b9ad9a133dc7 1220 /* Peripheral: GPIO */
Kojto 104:b9ad9a133dc7 1221 /* Description: General purpose input and output. */
Kojto 104:b9ad9a133dc7 1222
Kojto 104:b9ad9a133dc7 1223 /* Register: GPIO_OUT */
Kojto 104:b9ad9a133dc7 1224 /* Description: Write GPIO port. */
Kojto 104:b9ad9a133dc7 1225
Kojto 104:b9ad9a133dc7 1226 /* Bit 31 : Pin 31. */
Kojto 104:b9ad9a133dc7 1227 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 1228 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 1229 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1230 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1231
Kojto 104:b9ad9a133dc7 1232 /* Bit 30 : Pin 30. */
Kojto 104:b9ad9a133dc7 1233 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 1234 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 1235 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1236 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1237
Kojto 104:b9ad9a133dc7 1238 /* Bit 29 : Pin 29. */
Kojto 104:b9ad9a133dc7 1239 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 1240 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 1241 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1242 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1243
Kojto 104:b9ad9a133dc7 1244 /* Bit 28 : Pin 28. */
Kojto 104:b9ad9a133dc7 1245 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 1246 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 1247 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1248 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1249
Kojto 104:b9ad9a133dc7 1250 /* Bit 27 : Pin 27. */
Kojto 104:b9ad9a133dc7 1251 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 1252 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 1253 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1254 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1255
Kojto 104:b9ad9a133dc7 1256 /* Bit 26 : Pin 26. */
Kojto 104:b9ad9a133dc7 1257 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 1258 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 1259 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1260 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1261
Kojto 104:b9ad9a133dc7 1262 /* Bit 25 : Pin 25. */
Kojto 104:b9ad9a133dc7 1263 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 1264 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 1265 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1266 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1267
Kojto 104:b9ad9a133dc7 1268 /* Bit 24 : Pin 24. */
Kojto 104:b9ad9a133dc7 1269 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 1270 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 1271 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1272 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1273
Kojto 104:b9ad9a133dc7 1274 /* Bit 23 : Pin 23. */
Kojto 104:b9ad9a133dc7 1275 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 1276 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 1277 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1278 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1279
Kojto 104:b9ad9a133dc7 1280 /* Bit 22 : Pin 22. */
Kojto 104:b9ad9a133dc7 1281 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 1282 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 1283 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1284 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1285
Kojto 104:b9ad9a133dc7 1286 /* Bit 21 : Pin 21. */
Kojto 104:b9ad9a133dc7 1287 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 1288 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 1289 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1290 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1291
Kojto 104:b9ad9a133dc7 1292 /* Bit 20 : Pin 20. */
Kojto 104:b9ad9a133dc7 1293 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 1294 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 1295 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1296 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1297
Kojto 104:b9ad9a133dc7 1298 /* Bit 19 : Pin 19. */
Kojto 104:b9ad9a133dc7 1299 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 1300 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 1301 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1302 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1303
Kojto 104:b9ad9a133dc7 1304 /* Bit 18 : Pin 18. */
Kojto 104:b9ad9a133dc7 1305 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 1306 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 1307 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1308 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1309
Kojto 104:b9ad9a133dc7 1310 /* Bit 17 : Pin 17. */
Kojto 104:b9ad9a133dc7 1311 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 1312 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 1313 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1314 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1315
Kojto 104:b9ad9a133dc7 1316 /* Bit 16 : Pin 16. */
Kojto 104:b9ad9a133dc7 1317 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 1318 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 1319 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1320 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1321
Kojto 104:b9ad9a133dc7 1322 /* Bit 15 : Pin 15. */
Kojto 104:b9ad9a133dc7 1323 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 1324 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 1325 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1326 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1327
Kojto 104:b9ad9a133dc7 1328 /* Bit 14 : Pin 14. */
Kojto 104:b9ad9a133dc7 1329 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 1330 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 1331 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1332 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1333
Kojto 104:b9ad9a133dc7 1334 /* Bit 13 : Pin 13. */
Kojto 104:b9ad9a133dc7 1335 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 1336 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 1337 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1338 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1339
Kojto 104:b9ad9a133dc7 1340 /* Bit 12 : Pin 12. */
Kojto 104:b9ad9a133dc7 1341 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 1342 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 1343 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1344 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1345
Kojto 104:b9ad9a133dc7 1346 /* Bit 11 : Pin 11. */
Kojto 104:b9ad9a133dc7 1347 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 1348 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 1349 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1350 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1351
Kojto 104:b9ad9a133dc7 1352 /* Bit 10 : Pin 10. */
Kojto 104:b9ad9a133dc7 1353 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 1354 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 1355 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1356 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1357
Kojto 104:b9ad9a133dc7 1358 /* Bit 9 : Pin 9. */
Kojto 104:b9ad9a133dc7 1359 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 1360 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 1361 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1362 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1363
Kojto 104:b9ad9a133dc7 1364 /* Bit 8 : Pin 8. */
Kojto 104:b9ad9a133dc7 1365 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 1366 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 1367 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1368 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1369
Kojto 104:b9ad9a133dc7 1370 /* Bit 7 : Pin 7. */
Kojto 104:b9ad9a133dc7 1371 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 1372 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 1373 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1374 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1375
Kojto 104:b9ad9a133dc7 1376 /* Bit 6 : Pin 6. */
Kojto 104:b9ad9a133dc7 1377 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 1378 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 1379 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1380 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1381
Kojto 104:b9ad9a133dc7 1382 /* Bit 5 : Pin 5. */
Kojto 104:b9ad9a133dc7 1383 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 1384 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 1385 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1386 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1387
Kojto 104:b9ad9a133dc7 1388 /* Bit 4 : Pin 4. */
Kojto 104:b9ad9a133dc7 1389 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 1390 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 1391 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1392 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1393
Kojto 104:b9ad9a133dc7 1394 /* Bit 3 : Pin 3. */
Kojto 104:b9ad9a133dc7 1395 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 1396 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 1397 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1398 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1399
Kojto 104:b9ad9a133dc7 1400 /* Bit 2 : Pin 2. */
Kojto 104:b9ad9a133dc7 1401 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 1402 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 1403 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1404 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1405
Kojto 104:b9ad9a133dc7 1406 /* Bit 1 : Pin 1. */
Kojto 104:b9ad9a133dc7 1407 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 1408 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 1409 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1410 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1411
Kojto 104:b9ad9a133dc7 1412 /* Bit 0 : Pin 0. */
Kojto 104:b9ad9a133dc7 1413 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 1414 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 1415 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1416 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1417
Kojto 104:b9ad9a133dc7 1418 /* Register: GPIO_OUTSET */
Kojto 104:b9ad9a133dc7 1419 /* Description: Set individual bits in GPIO port. */
Kojto 104:b9ad9a133dc7 1420
Kojto 104:b9ad9a133dc7 1421 /* Bit 31 : Pin 31. */
Kojto 104:b9ad9a133dc7 1422 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 1423 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 1424 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1425 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1426 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1427
Kojto 104:b9ad9a133dc7 1428 /* Bit 30 : Pin 30. */
Kojto 104:b9ad9a133dc7 1429 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 1430 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 1431 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1432 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1433 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1434
Kojto 104:b9ad9a133dc7 1435 /* Bit 29 : Pin 29. */
Kojto 104:b9ad9a133dc7 1436 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 1437 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 1438 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1439 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1440 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1441
Kojto 104:b9ad9a133dc7 1442 /* Bit 28 : Pin 28. */
Kojto 104:b9ad9a133dc7 1443 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 1444 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 1445 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1446 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1447 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1448
Kojto 104:b9ad9a133dc7 1449 /* Bit 27 : Pin 27. */
Kojto 104:b9ad9a133dc7 1450 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 1451 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 1452 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1453 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1454 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1455
Kojto 104:b9ad9a133dc7 1456 /* Bit 26 : Pin 26. */
Kojto 104:b9ad9a133dc7 1457 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 1458 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 1459 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1460 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1461 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1462
Kojto 104:b9ad9a133dc7 1463 /* Bit 25 : Pin 25. */
Kojto 104:b9ad9a133dc7 1464 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 1465 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 1466 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1467 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1468 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1469
Kojto 104:b9ad9a133dc7 1470 /* Bit 24 : Pin 24. */
Kojto 104:b9ad9a133dc7 1471 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 1472 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 1473 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1474 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1475 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1476
Kojto 104:b9ad9a133dc7 1477 /* Bit 23 : Pin 23. */
Kojto 104:b9ad9a133dc7 1478 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 1479 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 1480 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1481 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1482 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1483
Kojto 104:b9ad9a133dc7 1484 /* Bit 22 : Pin 22. */
Kojto 104:b9ad9a133dc7 1485 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 1486 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 1487 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1488 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1489 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1490
Kojto 104:b9ad9a133dc7 1491 /* Bit 21 : Pin 21. */
Kojto 104:b9ad9a133dc7 1492 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 1493 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 1494 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1495 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1496 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1497
Kojto 104:b9ad9a133dc7 1498 /* Bit 20 : Pin 20. */
Kojto 104:b9ad9a133dc7 1499 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 1500 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 1501 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1502 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1503 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1504
Kojto 104:b9ad9a133dc7 1505 /* Bit 19 : Pin 19. */
Kojto 104:b9ad9a133dc7 1506 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 1507 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 1508 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1509 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1510 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1511
Kojto 104:b9ad9a133dc7 1512 /* Bit 18 : Pin 18. */
Kojto 104:b9ad9a133dc7 1513 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 1514 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 1515 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1516 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1517 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1518
Kojto 104:b9ad9a133dc7 1519 /* Bit 17 : Pin 17. */
Kojto 104:b9ad9a133dc7 1520 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 1521 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 1522 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1523 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1524 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1525
Kojto 104:b9ad9a133dc7 1526 /* Bit 16 : Pin 16. */
Kojto 104:b9ad9a133dc7 1527 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 1528 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 1529 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1530 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1531 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1532
Kojto 104:b9ad9a133dc7 1533 /* Bit 15 : Pin 15. */
Kojto 104:b9ad9a133dc7 1534 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 1535 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 1536 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1537 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1538 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1539
Kojto 104:b9ad9a133dc7 1540 /* Bit 14 : Pin 14. */
Kojto 104:b9ad9a133dc7 1541 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 1542 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 1543 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1544 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1545 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1546
Kojto 104:b9ad9a133dc7 1547 /* Bit 13 : Pin 13. */
Kojto 104:b9ad9a133dc7 1548 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 1549 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 1550 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1551 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1552 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1553
Kojto 104:b9ad9a133dc7 1554 /* Bit 12 : Pin 12. */
Kojto 104:b9ad9a133dc7 1555 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 1556 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 1557 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1558 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1559 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1560
Kojto 104:b9ad9a133dc7 1561 /* Bit 11 : Pin 11. */
Kojto 104:b9ad9a133dc7 1562 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 1563 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 1564 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1565 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1566 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1567
Kojto 104:b9ad9a133dc7 1568 /* Bit 10 : Pin 10. */
Kojto 104:b9ad9a133dc7 1569 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 1570 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 1571 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1572 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1573 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1574
Kojto 104:b9ad9a133dc7 1575 /* Bit 9 : Pin 9. */
Kojto 104:b9ad9a133dc7 1576 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 1577 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 1578 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1579 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1580 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1581
Kojto 104:b9ad9a133dc7 1582 /* Bit 8 : Pin 8. */
Kojto 104:b9ad9a133dc7 1583 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 1584 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 1585 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1586 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1587 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1588
Kojto 104:b9ad9a133dc7 1589 /* Bit 7 : Pin 7. */
Kojto 104:b9ad9a133dc7 1590 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 1591 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 1592 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1593 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1594 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1595
Kojto 104:b9ad9a133dc7 1596 /* Bit 6 : Pin 6. */
Kojto 104:b9ad9a133dc7 1597 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 1598 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 1599 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1600 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1601 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1602
Kojto 104:b9ad9a133dc7 1603 /* Bit 5 : Pin 5. */
Kojto 104:b9ad9a133dc7 1604 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 1605 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 1606 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1607 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1608 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1609
Kojto 104:b9ad9a133dc7 1610 /* Bit 4 : Pin 4. */
Kojto 104:b9ad9a133dc7 1611 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 1612 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 1613 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1614 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1615 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1616
Kojto 104:b9ad9a133dc7 1617 /* Bit 3 : Pin 3. */
Kojto 104:b9ad9a133dc7 1618 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 1619 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 1620 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1621 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1622 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1623
Kojto 104:b9ad9a133dc7 1624 /* Bit 2 : Pin 2. */
Kojto 104:b9ad9a133dc7 1625 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 1626 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 1627 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1628 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1629 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1630
Kojto 104:b9ad9a133dc7 1631 /* Bit 1 : Pin 1. */
Kojto 104:b9ad9a133dc7 1632 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 1633 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 1634 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1635 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1636 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1637
Kojto 104:b9ad9a133dc7 1638 /* Bit 0 : Pin 0. */
Kojto 104:b9ad9a133dc7 1639 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 1640 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 1641 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1642 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1643 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
Kojto 104:b9ad9a133dc7 1644
Kojto 104:b9ad9a133dc7 1645 /* Register: GPIO_OUTCLR */
Kojto 104:b9ad9a133dc7 1646 /* Description: Clear individual bits in GPIO port. */
Kojto 104:b9ad9a133dc7 1647
Kojto 104:b9ad9a133dc7 1648 /* Bit 31 : Pin 31. */
Kojto 104:b9ad9a133dc7 1649 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 1650 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 1651 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1652 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1653 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1654
Kojto 104:b9ad9a133dc7 1655 /* Bit 30 : Pin 30. */
Kojto 104:b9ad9a133dc7 1656 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 1657 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 1658 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1659 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1660 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1661
Kojto 104:b9ad9a133dc7 1662 /* Bit 29 : Pin 29. */
Kojto 104:b9ad9a133dc7 1663 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 1664 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 1665 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1666 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1667 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1668
Kojto 104:b9ad9a133dc7 1669 /* Bit 28 : Pin 28. */
Kojto 104:b9ad9a133dc7 1670 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 1671 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 1672 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1673 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1674 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1675
Kojto 104:b9ad9a133dc7 1676 /* Bit 27 : Pin 27. */
Kojto 104:b9ad9a133dc7 1677 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 1678 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 1679 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1680 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1681 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1682
Kojto 104:b9ad9a133dc7 1683 /* Bit 26 : Pin 26. */
Kojto 104:b9ad9a133dc7 1684 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 1685 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 1686 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1687 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1688 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1689
Kojto 104:b9ad9a133dc7 1690 /* Bit 25 : Pin 25. */
Kojto 104:b9ad9a133dc7 1691 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 1692 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 1693 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1694 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1695 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1696
Kojto 104:b9ad9a133dc7 1697 /* Bit 24 : Pin 24. */
Kojto 104:b9ad9a133dc7 1698 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 1699 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 1700 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1701 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1702 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1703
Kojto 104:b9ad9a133dc7 1704 /* Bit 23 : Pin 23. */
Kojto 104:b9ad9a133dc7 1705 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 1706 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 1707 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1708 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1709 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1710
Kojto 104:b9ad9a133dc7 1711 /* Bit 22 : Pin 22. */
Kojto 104:b9ad9a133dc7 1712 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 1713 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 1714 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1715 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1716 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1717
Kojto 104:b9ad9a133dc7 1718 /* Bit 21 : Pin 21. */
Kojto 104:b9ad9a133dc7 1719 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 1720 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 1721 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1722 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1723 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1724
Kojto 104:b9ad9a133dc7 1725 /* Bit 20 : Pin 20. */
Kojto 104:b9ad9a133dc7 1726 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 1727 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 1728 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1729 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1730 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1731
Kojto 104:b9ad9a133dc7 1732 /* Bit 19 : Pin 19. */
Kojto 104:b9ad9a133dc7 1733 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 1734 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 1735 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1736 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1737 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1738
Kojto 104:b9ad9a133dc7 1739 /* Bit 18 : Pin 18. */
Kojto 104:b9ad9a133dc7 1740 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 1741 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 1742 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1743 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1744 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1745
Kojto 104:b9ad9a133dc7 1746 /* Bit 17 : Pin 17. */
Kojto 104:b9ad9a133dc7 1747 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 1748 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 1749 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1750 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1751 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1752
Kojto 104:b9ad9a133dc7 1753 /* Bit 16 : Pin 16. */
Kojto 104:b9ad9a133dc7 1754 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 1755 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 1756 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1757 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1758 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1759
Kojto 104:b9ad9a133dc7 1760 /* Bit 15 : Pin 15. */
Kojto 104:b9ad9a133dc7 1761 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 1762 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 1763 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1764 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1765 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1766
Kojto 104:b9ad9a133dc7 1767 /* Bit 14 : Pin 14. */
Kojto 104:b9ad9a133dc7 1768 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 1769 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 1770 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1771 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1772 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1773
Kojto 104:b9ad9a133dc7 1774 /* Bit 13 : Pin 13. */
Kojto 104:b9ad9a133dc7 1775 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 1776 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 1777 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1778 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1779 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1780
Kojto 104:b9ad9a133dc7 1781 /* Bit 12 : Pin 12. */
Kojto 104:b9ad9a133dc7 1782 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 1783 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 1784 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1785 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1786 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1787
Kojto 104:b9ad9a133dc7 1788 /* Bit 11 : Pin 11. */
Kojto 104:b9ad9a133dc7 1789 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 1790 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 1791 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1792 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1793 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1794
Kojto 104:b9ad9a133dc7 1795 /* Bit 10 : Pin 10. */
Kojto 104:b9ad9a133dc7 1796 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 1797 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 1798 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1799 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1800 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1801
Kojto 104:b9ad9a133dc7 1802 /* Bit 9 : Pin 9. */
Kojto 104:b9ad9a133dc7 1803 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 1804 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 1805 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1806 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1807 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1808
Kojto 104:b9ad9a133dc7 1809 /* Bit 8 : Pin 8. */
Kojto 104:b9ad9a133dc7 1810 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 1811 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 1812 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1813 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1814 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1815
Kojto 104:b9ad9a133dc7 1816 /* Bit 7 : Pin 7. */
Kojto 104:b9ad9a133dc7 1817 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 1818 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 1819 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1820 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1821 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1822
Kojto 104:b9ad9a133dc7 1823 /* Bit 6 : Pin 6. */
Kojto 104:b9ad9a133dc7 1824 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 1825 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 1826 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1827 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1828 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1829
Kojto 104:b9ad9a133dc7 1830 /* Bit 5 : Pin 5. */
Kojto 104:b9ad9a133dc7 1831 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 1832 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 1833 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1834 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1835 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1836
Kojto 104:b9ad9a133dc7 1837 /* Bit 4 : Pin 4. */
Kojto 104:b9ad9a133dc7 1838 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 1839 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 1840 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1841 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1842 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1843
Kojto 104:b9ad9a133dc7 1844 /* Bit 3 : Pin 3. */
Kojto 104:b9ad9a133dc7 1845 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 1846 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 1847 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1848 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1849 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1850
Kojto 104:b9ad9a133dc7 1851 /* Bit 2 : Pin 2. */
Kojto 104:b9ad9a133dc7 1852 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 1853 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 1854 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1855 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1856 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1857
Kojto 104:b9ad9a133dc7 1858 /* Bit 1 : Pin 1. */
Kojto 104:b9ad9a133dc7 1859 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 1860 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 1861 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1862 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1863 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1864
Kojto 104:b9ad9a133dc7 1865 /* Bit 0 : Pin 0. */
Kojto 104:b9ad9a133dc7 1866 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 1867 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 1868 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
Kojto 104:b9ad9a133dc7 1869 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
Kojto 104:b9ad9a133dc7 1870 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
Kojto 104:b9ad9a133dc7 1871
Kojto 104:b9ad9a133dc7 1872 /* Register: GPIO_IN */
Kojto 104:b9ad9a133dc7 1873 /* Description: Read GPIO port. */
Kojto 104:b9ad9a133dc7 1874
Kojto 104:b9ad9a133dc7 1875 /* Bit 31 : Pin 31. */
Kojto 104:b9ad9a133dc7 1876 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 1877 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 1878 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1879 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1880
Kojto 104:b9ad9a133dc7 1881 /* Bit 30 : Pin 30. */
Kojto 104:b9ad9a133dc7 1882 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 1883 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 1884 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1885 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1886
Kojto 104:b9ad9a133dc7 1887 /* Bit 29 : Pin 29. */
Kojto 104:b9ad9a133dc7 1888 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 1889 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 1890 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1891 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1892
Kojto 104:b9ad9a133dc7 1893 /* Bit 28 : Pin 28. */
Kojto 104:b9ad9a133dc7 1894 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 1895 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 1896 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1897 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1898
Kojto 104:b9ad9a133dc7 1899 /* Bit 27 : Pin 27. */
Kojto 104:b9ad9a133dc7 1900 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 1901 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 1902 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1903 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1904
Kojto 104:b9ad9a133dc7 1905 /* Bit 26 : Pin 26. */
Kojto 104:b9ad9a133dc7 1906 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 1907 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 1908 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1909 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1910
Kojto 104:b9ad9a133dc7 1911 /* Bit 25 : Pin 25. */
Kojto 104:b9ad9a133dc7 1912 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 1913 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 1914 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1915 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1916
Kojto 104:b9ad9a133dc7 1917 /* Bit 24 : Pin 24. */
Kojto 104:b9ad9a133dc7 1918 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 1919 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 1920 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1921 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1922
Kojto 104:b9ad9a133dc7 1923 /* Bit 23 : Pin 23. */
Kojto 104:b9ad9a133dc7 1924 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 1925 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 1926 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1927 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1928
Kojto 104:b9ad9a133dc7 1929 /* Bit 22 : Pin 22. */
Kojto 104:b9ad9a133dc7 1930 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 1931 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 1932 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1933 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1934
Kojto 104:b9ad9a133dc7 1935 /* Bit 21 : Pin 21. */
Kojto 104:b9ad9a133dc7 1936 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 1937 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 1938 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1939 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1940
Kojto 104:b9ad9a133dc7 1941 /* Bit 20 : Pin 20. */
Kojto 104:b9ad9a133dc7 1942 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 1943 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 1944 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1945 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1946
Kojto 104:b9ad9a133dc7 1947 /* Bit 19 : Pin 19. */
Kojto 104:b9ad9a133dc7 1948 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 1949 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 1950 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1951 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1952
Kojto 104:b9ad9a133dc7 1953 /* Bit 18 : Pin 18. */
Kojto 104:b9ad9a133dc7 1954 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 1955 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 1956 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1957 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1958
Kojto 104:b9ad9a133dc7 1959 /* Bit 17 : Pin 17. */
Kojto 104:b9ad9a133dc7 1960 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 1961 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 1962 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1963 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1964
Kojto 104:b9ad9a133dc7 1965 /* Bit 16 : Pin 16. */
Kojto 104:b9ad9a133dc7 1966 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 1967 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 1968 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1969 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1970
Kojto 104:b9ad9a133dc7 1971 /* Bit 15 : Pin 15. */
Kojto 104:b9ad9a133dc7 1972 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 1973 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 1974 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1975 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1976
Kojto 104:b9ad9a133dc7 1977 /* Bit 14 : Pin 14. */
Kojto 104:b9ad9a133dc7 1978 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 1979 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 1980 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1981 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1982
Kojto 104:b9ad9a133dc7 1983 /* Bit 13 : Pin 13. */
Kojto 104:b9ad9a133dc7 1984 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 1985 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 1986 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1987 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1988
Kojto 104:b9ad9a133dc7 1989 /* Bit 12 : Pin 12. */
Kojto 104:b9ad9a133dc7 1990 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 1991 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 1992 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1993 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 1994
Kojto 104:b9ad9a133dc7 1995 /* Bit 11 : Pin 11. */
Kojto 104:b9ad9a133dc7 1996 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 1997 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 1998 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 1999 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2000
Kojto 104:b9ad9a133dc7 2001 /* Bit 10 : Pin 10. */
Kojto 104:b9ad9a133dc7 2002 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 2003 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 2004 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2005 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2006
Kojto 104:b9ad9a133dc7 2007 /* Bit 9 : Pin 9. */
Kojto 104:b9ad9a133dc7 2008 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 2009 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 2010 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2011 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2012
Kojto 104:b9ad9a133dc7 2013 /* Bit 8 : Pin 8. */
Kojto 104:b9ad9a133dc7 2014 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 2015 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 2016 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2017 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2018
Kojto 104:b9ad9a133dc7 2019 /* Bit 7 : Pin 7. */
Kojto 104:b9ad9a133dc7 2020 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 2021 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 2022 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2023 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2024
Kojto 104:b9ad9a133dc7 2025 /* Bit 6 : Pin 6. */
Kojto 104:b9ad9a133dc7 2026 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 2027 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 2028 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2029 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2030
Kojto 104:b9ad9a133dc7 2031 /* Bit 5 : Pin 5. */
Kojto 104:b9ad9a133dc7 2032 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 2033 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 2034 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2035 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2036
Kojto 104:b9ad9a133dc7 2037 /* Bit 4 : Pin 4. */
Kojto 104:b9ad9a133dc7 2038 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 2039 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 2040 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2041 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2042
Kojto 104:b9ad9a133dc7 2043 /* Bit 3 : Pin 3. */
Kojto 104:b9ad9a133dc7 2044 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 2045 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 2046 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2047 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2048
Kojto 104:b9ad9a133dc7 2049 /* Bit 2 : Pin 2. */
Kojto 104:b9ad9a133dc7 2050 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 2051 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 2052 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2053 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2054
Kojto 104:b9ad9a133dc7 2055 /* Bit 1 : Pin 1. */
Kojto 104:b9ad9a133dc7 2056 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 2057 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 2058 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2059 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2060
Kojto 104:b9ad9a133dc7 2061 /* Bit 0 : Pin 0. */
Kojto 104:b9ad9a133dc7 2062 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 2063 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 2064 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
Kojto 104:b9ad9a133dc7 2065 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
Kojto 104:b9ad9a133dc7 2066
Kojto 104:b9ad9a133dc7 2067 /* Register: GPIO_DIR */
Kojto 104:b9ad9a133dc7 2068 /* Description: Direction of GPIO pins. */
Kojto 104:b9ad9a133dc7 2069
Kojto 104:b9ad9a133dc7 2070 /* Bit 31 : Pin 31. */
Kojto 104:b9ad9a133dc7 2071 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 2072 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 2073 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2074 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2075
Kojto 104:b9ad9a133dc7 2076 /* Bit 30 : Pin 30. */
Kojto 104:b9ad9a133dc7 2077 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 2078 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 2079 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2080 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2081
Kojto 104:b9ad9a133dc7 2082 /* Bit 29 : Pin 29. */
Kojto 104:b9ad9a133dc7 2083 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 2084 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 2085 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2086 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2087
Kojto 104:b9ad9a133dc7 2088 /* Bit 28 : Pin 28. */
Kojto 104:b9ad9a133dc7 2089 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 2090 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 2091 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2092 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2093
Kojto 104:b9ad9a133dc7 2094 /* Bit 27 : Pin 27. */
Kojto 104:b9ad9a133dc7 2095 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 2096 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 2097 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2098 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2099
Kojto 104:b9ad9a133dc7 2100 /* Bit 26 : Pin 26. */
Kojto 104:b9ad9a133dc7 2101 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 2102 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 2103 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2104 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2105
Kojto 104:b9ad9a133dc7 2106 /* Bit 25 : Pin 25. */
Kojto 104:b9ad9a133dc7 2107 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 2108 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 2109 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2110 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2111
Kojto 104:b9ad9a133dc7 2112 /* Bit 24 : Pin 24. */
Kojto 104:b9ad9a133dc7 2113 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 2114 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 2115 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2116 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2117
Kojto 104:b9ad9a133dc7 2118 /* Bit 23 : Pin 23. */
Kojto 104:b9ad9a133dc7 2119 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 2120 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 2121 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2122 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2123
Kojto 104:b9ad9a133dc7 2124 /* Bit 22 : Pin 22. */
Kojto 104:b9ad9a133dc7 2125 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 2126 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 2127 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2128 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2129
Kojto 104:b9ad9a133dc7 2130 /* Bit 21 : Pin 21. */
Kojto 104:b9ad9a133dc7 2131 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 2132 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 2133 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2134 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2135
Kojto 104:b9ad9a133dc7 2136 /* Bit 20 : Pin 20. */
Kojto 104:b9ad9a133dc7 2137 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 2138 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 2139 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2140 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2141
Kojto 104:b9ad9a133dc7 2142 /* Bit 19 : Pin 19. */
Kojto 104:b9ad9a133dc7 2143 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 2144 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 2145 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2146 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2147
Kojto 104:b9ad9a133dc7 2148 /* Bit 18 : Pin 18. */
Kojto 104:b9ad9a133dc7 2149 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 2150 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 2151 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2152 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2153
Kojto 104:b9ad9a133dc7 2154 /* Bit 17 : Pin 17. */
Kojto 104:b9ad9a133dc7 2155 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 2156 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 2157 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2158 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2159
Kojto 104:b9ad9a133dc7 2160 /* Bit 16 : Pin 16. */
Kojto 104:b9ad9a133dc7 2161 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 2162 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 2163 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2164 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2165
Kojto 104:b9ad9a133dc7 2166 /* Bit 15 : Pin 15. */
Kojto 104:b9ad9a133dc7 2167 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 2168 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 2169 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2170 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2171
Kojto 104:b9ad9a133dc7 2172 /* Bit 14 : Pin 14. */
Kojto 104:b9ad9a133dc7 2173 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 2174 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 2175 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2176 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2177
Kojto 104:b9ad9a133dc7 2178 /* Bit 13 : Pin 13. */
Kojto 104:b9ad9a133dc7 2179 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 2180 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 2181 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2182 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2183
Kojto 104:b9ad9a133dc7 2184 /* Bit 12 : Pin 12. */
Kojto 104:b9ad9a133dc7 2185 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 2186 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 2187 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2188 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2189
Kojto 104:b9ad9a133dc7 2190 /* Bit 11 : Pin 11. */
Kojto 104:b9ad9a133dc7 2191 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 2192 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 2193 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2194 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2195
Kojto 104:b9ad9a133dc7 2196 /* Bit 10 : Pin 10. */
Kojto 104:b9ad9a133dc7 2197 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 2198 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 2199 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2200 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2201
Kojto 104:b9ad9a133dc7 2202 /* Bit 9 : Pin 9. */
Kojto 104:b9ad9a133dc7 2203 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 2204 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 2205 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2206 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2207
Kojto 104:b9ad9a133dc7 2208 /* Bit 8 : Pin 8. */
Kojto 104:b9ad9a133dc7 2209 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 2210 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 2211 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2212 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2213
Kojto 104:b9ad9a133dc7 2214 /* Bit 7 : Pin 7. */
Kojto 104:b9ad9a133dc7 2215 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 2216 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 2217 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2218 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2219
Kojto 104:b9ad9a133dc7 2220 /* Bit 6 : Pin 6. */
Kojto 104:b9ad9a133dc7 2221 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 2222 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 2223 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2224 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2225
Kojto 104:b9ad9a133dc7 2226 /* Bit 5 : Pin 5. */
Kojto 104:b9ad9a133dc7 2227 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 2228 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 2229 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2230 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2231
Kojto 104:b9ad9a133dc7 2232 /* Bit 4 : Pin 4. */
Kojto 104:b9ad9a133dc7 2233 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 2234 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 2235 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2236 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2237
Kojto 104:b9ad9a133dc7 2238 /* Bit 3 : Pin 3. */
Kojto 104:b9ad9a133dc7 2239 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 2240 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 2241 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2242 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2243
Kojto 104:b9ad9a133dc7 2244 /* Bit 2 : Pin 2. */
Kojto 104:b9ad9a133dc7 2245 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 2246 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 2247 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2248 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2249
Kojto 104:b9ad9a133dc7 2250 /* Bit 1 : Pin 1. */
Kojto 104:b9ad9a133dc7 2251 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 2252 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 2253 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2254 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2255
Kojto 104:b9ad9a133dc7 2256 /* Bit 0 : Pin 0. */
Kojto 104:b9ad9a133dc7 2257 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 2258 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 2259 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2260 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2261
Kojto 104:b9ad9a133dc7 2262 /* Register: GPIO_DIRSET */
Kojto 104:b9ad9a133dc7 2263 /* Description: DIR set register. */
Kojto 104:b9ad9a133dc7 2264
Kojto 104:b9ad9a133dc7 2265 /* Bit 31 : Set as output pin 31. */
Kojto 104:b9ad9a133dc7 2266 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 2267 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 2268 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2269 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2270 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2271
Kojto 104:b9ad9a133dc7 2272 /* Bit 30 : Set as output pin 30. */
Kojto 104:b9ad9a133dc7 2273 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 2274 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 2275 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2276 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2277 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2278
Kojto 104:b9ad9a133dc7 2279 /* Bit 29 : Set as output pin 29. */
Kojto 104:b9ad9a133dc7 2280 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 2281 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 2282 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2283 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2284 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2285
Kojto 104:b9ad9a133dc7 2286 /* Bit 28 : Set as output pin 28. */
Kojto 104:b9ad9a133dc7 2287 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 2288 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 2289 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2290 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2291 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2292
Kojto 104:b9ad9a133dc7 2293 /* Bit 27 : Set as output pin 27. */
Kojto 104:b9ad9a133dc7 2294 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 2295 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 2296 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2297 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2298 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2299
Kojto 104:b9ad9a133dc7 2300 /* Bit 26 : Set as output pin 26. */
Kojto 104:b9ad9a133dc7 2301 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 2302 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 2303 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2304 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2305 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2306
Kojto 104:b9ad9a133dc7 2307 /* Bit 25 : Set as output pin 25. */
Kojto 104:b9ad9a133dc7 2308 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 2309 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 2310 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2311 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2312 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2313
Kojto 104:b9ad9a133dc7 2314 /* Bit 24 : Set as output pin 24. */
Kojto 104:b9ad9a133dc7 2315 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 2316 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 2317 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2318 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2319 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2320
Kojto 104:b9ad9a133dc7 2321 /* Bit 23 : Set as output pin 23. */
Kojto 104:b9ad9a133dc7 2322 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 2323 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 2324 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2325 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2326 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2327
Kojto 104:b9ad9a133dc7 2328 /* Bit 22 : Set as output pin 22. */
Kojto 104:b9ad9a133dc7 2329 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 2330 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 2331 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2332 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2333 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2334
Kojto 104:b9ad9a133dc7 2335 /* Bit 21 : Set as output pin 21. */
Kojto 104:b9ad9a133dc7 2336 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 2337 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 2338 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2339 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2340 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2341
Kojto 104:b9ad9a133dc7 2342 /* Bit 20 : Set as output pin 20. */
Kojto 104:b9ad9a133dc7 2343 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 2344 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 2345 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2346 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2347 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2348
Kojto 104:b9ad9a133dc7 2349 /* Bit 19 : Set as output pin 19. */
Kojto 104:b9ad9a133dc7 2350 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 2351 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 2352 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2353 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2354 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2355
Kojto 104:b9ad9a133dc7 2356 /* Bit 18 : Set as output pin 18. */
Kojto 104:b9ad9a133dc7 2357 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 2358 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 2359 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2360 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2361 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2362
Kojto 104:b9ad9a133dc7 2363 /* Bit 17 : Set as output pin 17. */
Kojto 104:b9ad9a133dc7 2364 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 2365 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 2366 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2367 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2368 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2369
Kojto 104:b9ad9a133dc7 2370 /* Bit 16 : Set as output pin 16. */
Kojto 104:b9ad9a133dc7 2371 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 2372 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 2373 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2374 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2375 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2376
Kojto 104:b9ad9a133dc7 2377 /* Bit 15 : Set as output pin 15. */
Kojto 104:b9ad9a133dc7 2378 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 2379 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 2380 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2381 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2382 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2383
Kojto 104:b9ad9a133dc7 2384 /* Bit 14 : Set as output pin 14. */
Kojto 104:b9ad9a133dc7 2385 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 2386 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 2387 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2388 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2389 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2390
Kojto 104:b9ad9a133dc7 2391 /* Bit 13 : Set as output pin 13. */
Kojto 104:b9ad9a133dc7 2392 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 2393 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 2394 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2395 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2396 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2397
Kojto 104:b9ad9a133dc7 2398 /* Bit 12 : Set as output pin 12. */
Kojto 104:b9ad9a133dc7 2399 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 2400 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 2401 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2402 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2403 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2404
Kojto 104:b9ad9a133dc7 2405 /* Bit 11 : Set as output pin 11. */
Kojto 104:b9ad9a133dc7 2406 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 2407 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 2408 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2409 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2410 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2411
Kojto 104:b9ad9a133dc7 2412 /* Bit 10 : Set as output pin 10. */
Kojto 104:b9ad9a133dc7 2413 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 2414 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 2415 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2416 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2417 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2418
Kojto 104:b9ad9a133dc7 2419 /* Bit 9 : Set as output pin 9. */
Kojto 104:b9ad9a133dc7 2420 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 2421 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 2422 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2423 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2424 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2425
Kojto 104:b9ad9a133dc7 2426 /* Bit 8 : Set as output pin 8. */
Kojto 104:b9ad9a133dc7 2427 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 2428 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 2429 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2430 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2431 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2432
Kojto 104:b9ad9a133dc7 2433 /* Bit 7 : Set as output pin 7. */
Kojto 104:b9ad9a133dc7 2434 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 2435 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 2436 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2437 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2438 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2439
Kojto 104:b9ad9a133dc7 2440 /* Bit 6 : Set as output pin 6. */
Kojto 104:b9ad9a133dc7 2441 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 2442 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 2443 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2444 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2445 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2446
Kojto 104:b9ad9a133dc7 2447 /* Bit 5 : Set as output pin 5. */
Kojto 104:b9ad9a133dc7 2448 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 2449 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 2450 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2451 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2452 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2453
Kojto 104:b9ad9a133dc7 2454 /* Bit 4 : Set as output pin 4. */
Kojto 104:b9ad9a133dc7 2455 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 2456 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 2457 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2458 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2459 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2460
Kojto 104:b9ad9a133dc7 2461 /* Bit 3 : Set as output pin 3. */
Kojto 104:b9ad9a133dc7 2462 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 2463 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 2464 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2465 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2466 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2467
Kojto 104:b9ad9a133dc7 2468 /* Bit 2 : Set as output pin 2. */
Kojto 104:b9ad9a133dc7 2469 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 2470 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 2471 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2472 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2473 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2474
Kojto 104:b9ad9a133dc7 2475 /* Bit 1 : Set as output pin 1. */
Kojto 104:b9ad9a133dc7 2476 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 2477 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 2478 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2479 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2480 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2481
Kojto 104:b9ad9a133dc7 2482 /* Bit 0 : Set as output pin 0. */
Kojto 104:b9ad9a133dc7 2483 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 2484 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 2485 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2486 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2487 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
Kojto 104:b9ad9a133dc7 2488
Kojto 104:b9ad9a133dc7 2489 /* Register: GPIO_DIRCLR */
Kojto 104:b9ad9a133dc7 2490 /* Description: DIR clear register. */
Kojto 104:b9ad9a133dc7 2491
Kojto 104:b9ad9a133dc7 2492 /* Bit 31 : Set as input pin 31. */
Kojto 104:b9ad9a133dc7 2493 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 104:b9ad9a133dc7 2494 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 104:b9ad9a133dc7 2495 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2496 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2497 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2498
Kojto 104:b9ad9a133dc7 2499 /* Bit 30 : Set as input pin 30. */
Kojto 104:b9ad9a133dc7 2500 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 104:b9ad9a133dc7 2501 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 104:b9ad9a133dc7 2502 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2503 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2504 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2505
Kojto 104:b9ad9a133dc7 2506 /* Bit 29 : Set as input pin 29. */
Kojto 104:b9ad9a133dc7 2507 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 104:b9ad9a133dc7 2508 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 104:b9ad9a133dc7 2509 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2510 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2511 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2512
Kojto 104:b9ad9a133dc7 2513 /* Bit 28 : Set as input pin 28. */
Kojto 104:b9ad9a133dc7 2514 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 104:b9ad9a133dc7 2515 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 104:b9ad9a133dc7 2516 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2517 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2518 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2519
Kojto 104:b9ad9a133dc7 2520 /* Bit 27 : Set as input pin 27. */
Kojto 104:b9ad9a133dc7 2521 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 104:b9ad9a133dc7 2522 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 104:b9ad9a133dc7 2523 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2524 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2525 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2526
Kojto 104:b9ad9a133dc7 2527 /* Bit 26 : Set as input pin 26. */
Kojto 104:b9ad9a133dc7 2528 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 104:b9ad9a133dc7 2529 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 104:b9ad9a133dc7 2530 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2531 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2532 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2533
Kojto 104:b9ad9a133dc7 2534 /* Bit 25 : Set as input pin 25. */
Kojto 104:b9ad9a133dc7 2535 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 104:b9ad9a133dc7 2536 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 104:b9ad9a133dc7 2537 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2538 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2539 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2540
Kojto 104:b9ad9a133dc7 2541 /* Bit 24 : Set as input pin 24. */
Kojto 104:b9ad9a133dc7 2542 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 104:b9ad9a133dc7 2543 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 104:b9ad9a133dc7 2544 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2545 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2546 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2547
Kojto 104:b9ad9a133dc7 2548 /* Bit 23 : Set as input pin 23. */
Kojto 104:b9ad9a133dc7 2549 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 104:b9ad9a133dc7 2550 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 104:b9ad9a133dc7 2551 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2552 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2553 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2554
Kojto 104:b9ad9a133dc7 2555 /* Bit 22 : Set as input pin 22. */
Kojto 104:b9ad9a133dc7 2556 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 104:b9ad9a133dc7 2557 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 104:b9ad9a133dc7 2558 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2559 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2560 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2561
Kojto 104:b9ad9a133dc7 2562 /* Bit 21 : Set as input pin 21. */
Kojto 104:b9ad9a133dc7 2563 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 104:b9ad9a133dc7 2564 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 104:b9ad9a133dc7 2565 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2566 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2567 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2568
Kojto 104:b9ad9a133dc7 2569 /* Bit 20 : Set as input pin 20. */
Kojto 104:b9ad9a133dc7 2570 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 104:b9ad9a133dc7 2571 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 104:b9ad9a133dc7 2572 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2573 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2574 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2575
Kojto 104:b9ad9a133dc7 2576 /* Bit 19 : Set as input pin 19. */
Kojto 104:b9ad9a133dc7 2577 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 104:b9ad9a133dc7 2578 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 104:b9ad9a133dc7 2579 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2580 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2581 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2582
Kojto 104:b9ad9a133dc7 2583 /* Bit 18 : Set as input pin 18. */
Kojto 104:b9ad9a133dc7 2584 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 104:b9ad9a133dc7 2585 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 104:b9ad9a133dc7 2586 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2587 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2588 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2589
Kojto 104:b9ad9a133dc7 2590 /* Bit 17 : Set as input pin 17. */
Kojto 104:b9ad9a133dc7 2591 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 104:b9ad9a133dc7 2592 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 104:b9ad9a133dc7 2593 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2594 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2595 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2596
Kojto 104:b9ad9a133dc7 2597 /* Bit 16 : Set as input pin 16. */
Kojto 104:b9ad9a133dc7 2598 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 104:b9ad9a133dc7 2599 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 104:b9ad9a133dc7 2600 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2601 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2602 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2603
Kojto 104:b9ad9a133dc7 2604 /* Bit 15 : Set as input pin 15. */
Kojto 104:b9ad9a133dc7 2605 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 104:b9ad9a133dc7 2606 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 104:b9ad9a133dc7 2607 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2608 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2609 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2610
Kojto 104:b9ad9a133dc7 2611 /* Bit 14 : Set as input pin 14. */
Kojto 104:b9ad9a133dc7 2612 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 104:b9ad9a133dc7 2613 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 104:b9ad9a133dc7 2614 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2615 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2616 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2617
Kojto 104:b9ad9a133dc7 2618 /* Bit 13 : Set as input pin 13. */
Kojto 104:b9ad9a133dc7 2619 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 104:b9ad9a133dc7 2620 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 104:b9ad9a133dc7 2621 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2622 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2623 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2624
Kojto 104:b9ad9a133dc7 2625 /* Bit 12 : Set as input pin 12. */
Kojto 104:b9ad9a133dc7 2626 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 104:b9ad9a133dc7 2627 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 104:b9ad9a133dc7 2628 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2629 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2630 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2631
Kojto 104:b9ad9a133dc7 2632 /* Bit 11 : Set as input pin 11. */
Kojto 104:b9ad9a133dc7 2633 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 104:b9ad9a133dc7 2634 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 104:b9ad9a133dc7 2635 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2636 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2637 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2638
Kojto 104:b9ad9a133dc7 2639 /* Bit 10 : Set as input pin 10. */
Kojto 104:b9ad9a133dc7 2640 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 104:b9ad9a133dc7 2641 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 104:b9ad9a133dc7 2642 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2643 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2644 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2645
Kojto 104:b9ad9a133dc7 2646 /* Bit 9 : Set as input pin 9. */
Kojto 104:b9ad9a133dc7 2647 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 104:b9ad9a133dc7 2648 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 104:b9ad9a133dc7 2649 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2650 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2651 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2652
Kojto 104:b9ad9a133dc7 2653 /* Bit 8 : Set as input pin 8. */
Kojto 104:b9ad9a133dc7 2654 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 104:b9ad9a133dc7 2655 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 104:b9ad9a133dc7 2656 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2657 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2658 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2659
Kojto 104:b9ad9a133dc7 2660 /* Bit 7 : Set as input pin 7. */
Kojto 104:b9ad9a133dc7 2661 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 104:b9ad9a133dc7 2662 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 104:b9ad9a133dc7 2663 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2664 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2665 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2666
Kojto 104:b9ad9a133dc7 2667 /* Bit 6 : Set as input pin 6. */
Kojto 104:b9ad9a133dc7 2668 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 104:b9ad9a133dc7 2669 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 104:b9ad9a133dc7 2670 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2671 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2672 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2673
Kojto 104:b9ad9a133dc7 2674 /* Bit 5 : Set as input pin 5. */
Kojto 104:b9ad9a133dc7 2675 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 104:b9ad9a133dc7 2676 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 104:b9ad9a133dc7 2677 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2678 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2679 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2680
Kojto 104:b9ad9a133dc7 2681 /* Bit 4 : Set as input pin 4. */
Kojto 104:b9ad9a133dc7 2682 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 104:b9ad9a133dc7 2683 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 104:b9ad9a133dc7 2684 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2685 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2686 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2687
Kojto 104:b9ad9a133dc7 2688 /* Bit 3 : Set as input pin 3. */
Kojto 104:b9ad9a133dc7 2689 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 104:b9ad9a133dc7 2690 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 104:b9ad9a133dc7 2691 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2692 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2693 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2694
Kojto 104:b9ad9a133dc7 2695 /* Bit 2 : Set as input pin 2. */
Kojto 104:b9ad9a133dc7 2696 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 104:b9ad9a133dc7 2697 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 104:b9ad9a133dc7 2698 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2699 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2700 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2701
Kojto 104:b9ad9a133dc7 2702 /* Bit 1 : Set as input pin 1. */
Kojto 104:b9ad9a133dc7 2703 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 104:b9ad9a133dc7 2704 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 104:b9ad9a133dc7 2705 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2706 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2707 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2708
Kojto 104:b9ad9a133dc7 2709 /* Bit 0 : Set as input pin 0. */
Kojto 104:b9ad9a133dc7 2710 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 104:b9ad9a133dc7 2711 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 104:b9ad9a133dc7 2712 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
Kojto 104:b9ad9a133dc7 2713 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
Kojto 104:b9ad9a133dc7 2714 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
Kojto 104:b9ad9a133dc7 2715
Kojto 104:b9ad9a133dc7 2716 /* Register: GPIO_PIN_CNF */
Kojto 104:b9ad9a133dc7 2717 /* Description: Configuration of GPIO pins. */
Kojto 104:b9ad9a133dc7 2718
Kojto 104:b9ad9a133dc7 2719 /* Bits 17..16 : Pin sensing mechanism. */
Kojto 104:b9ad9a133dc7 2720 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
Kojto 104:b9ad9a133dc7 2721 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
Kojto 104:b9ad9a133dc7 2722 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 2723 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
Kojto 104:b9ad9a133dc7 2724 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
Kojto 104:b9ad9a133dc7 2725
Kojto 104:b9ad9a133dc7 2726 /* Bits 10..8 : Drive configuration. */
Kojto 104:b9ad9a133dc7 2727 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
Kojto 104:b9ad9a133dc7 2728 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
Kojto 104:b9ad9a133dc7 2729 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
Kojto 104:b9ad9a133dc7 2730 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
Kojto 104:b9ad9a133dc7 2731 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
Kojto 104:b9ad9a133dc7 2732 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
Kojto 104:b9ad9a133dc7 2733 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
Kojto 104:b9ad9a133dc7 2734 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
Kojto 104:b9ad9a133dc7 2735 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
Kojto 104:b9ad9a133dc7 2736 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
Kojto 104:b9ad9a133dc7 2737
Kojto 104:b9ad9a133dc7 2738 /* Bits 3..2 : Pull-up or -down configuration. */
Kojto 104:b9ad9a133dc7 2739 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
Kojto 104:b9ad9a133dc7 2740 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
Kojto 104:b9ad9a133dc7 2741 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
Kojto 104:b9ad9a133dc7 2742 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
Kojto 104:b9ad9a133dc7 2743 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
Kojto 104:b9ad9a133dc7 2744
Kojto 104:b9ad9a133dc7 2745 /* Bit 1 : Connect or disconnect input path. */
Kojto 104:b9ad9a133dc7 2746 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
Kojto 104:b9ad9a133dc7 2747 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
Kojto 104:b9ad9a133dc7 2748 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
Kojto 104:b9ad9a133dc7 2749 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
Kojto 104:b9ad9a133dc7 2750
Kojto 104:b9ad9a133dc7 2751 /* Bit 0 : Pin direction. */
Kojto 104:b9ad9a133dc7 2752 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
Kojto 104:b9ad9a133dc7 2753 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
Kojto 104:b9ad9a133dc7 2754 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
Kojto 104:b9ad9a133dc7 2755 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
Kojto 104:b9ad9a133dc7 2756
Kojto 104:b9ad9a133dc7 2757
Kojto 104:b9ad9a133dc7 2758 /* Peripheral: GPIOTE */
Kojto 104:b9ad9a133dc7 2759 /* Description: GPIO tasks and events. */
Kojto 104:b9ad9a133dc7 2760
Kojto 104:b9ad9a133dc7 2761 /* Register: GPIOTE_INTENSET */
Kojto 104:b9ad9a133dc7 2762 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 2763
Kojto 104:b9ad9a133dc7 2764 /* Bit 31 : Enable interrupt on PORT event. */
Kojto 104:b9ad9a133dc7 2765 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
Kojto 104:b9ad9a133dc7 2766 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
Kojto 104:b9ad9a133dc7 2767 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2768 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2769 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2770
Kojto 104:b9ad9a133dc7 2771 /* Bit 3 : Enable interrupt on IN[3] event. */
Kojto 104:b9ad9a133dc7 2772 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
Kojto 104:b9ad9a133dc7 2773 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
Kojto 104:b9ad9a133dc7 2774 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2775 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2776 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2777
Kojto 104:b9ad9a133dc7 2778 /* Bit 2 : Enable interrupt on IN[2] event. */
Kojto 104:b9ad9a133dc7 2779 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
Kojto 104:b9ad9a133dc7 2780 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
Kojto 104:b9ad9a133dc7 2781 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2782 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2783 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2784
Kojto 104:b9ad9a133dc7 2785 /* Bit 1 : Enable interrupt on IN[1] event. */
Kojto 104:b9ad9a133dc7 2786 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
Kojto 104:b9ad9a133dc7 2787 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
Kojto 104:b9ad9a133dc7 2788 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2789 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2790 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2791
Kojto 104:b9ad9a133dc7 2792 /* Bit 0 : Enable interrupt on IN[0] event. */
Kojto 104:b9ad9a133dc7 2793 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
Kojto 104:b9ad9a133dc7 2794 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
Kojto 104:b9ad9a133dc7 2795 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2796 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2797 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2798
Kojto 104:b9ad9a133dc7 2799 /* Register: GPIOTE_INTENCLR */
Kojto 104:b9ad9a133dc7 2800 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 2801
Kojto 104:b9ad9a133dc7 2802 /* Bit 31 : Disable interrupt on PORT event. */
Kojto 104:b9ad9a133dc7 2803 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
Kojto 104:b9ad9a133dc7 2804 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
Kojto 104:b9ad9a133dc7 2805 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2806 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2807 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2808
Kojto 104:b9ad9a133dc7 2809 /* Bit 3 : Disable interrupt on IN[3] event. */
Kojto 104:b9ad9a133dc7 2810 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
Kojto 104:b9ad9a133dc7 2811 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
Kojto 104:b9ad9a133dc7 2812 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2813 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2814 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2815
Kojto 104:b9ad9a133dc7 2816 /* Bit 2 : Disable interrupt on IN[2] event. */
Kojto 104:b9ad9a133dc7 2817 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
Kojto 104:b9ad9a133dc7 2818 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
Kojto 104:b9ad9a133dc7 2819 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2820 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2821 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2822
Kojto 104:b9ad9a133dc7 2823 /* Bit 1 : Disable interrupt on IN[1] event. */
Kojto 104:b9ad9a133dc7 2824 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
Kojto 104:b9ad9a133dc7 2825 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
Kojto 104:b9ad9a133dc7 2826 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2827 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2828 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2829
Kojto 104:b9ad9a133dc7 2830 /* Bit 0 : Disable interrupt on IN[0] event. */
Kojto 104:b9ad9a133dc7 2831 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
Kojto 104:b9ad9a133dc7 2832 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
Kojto 104:b9ad9a133dc7 2833 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2834 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2835 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2836
Kojto 104:b9ad9a133dc7 2837 /* Register: GPIOTE_CONFIG */
Kojto 104:b9ad9a133dc7 2838 /* Description: Channel configuration registers. */
Kojto 104:b9ad9a133dc7 2839
Kojto 104:b9ad9a133dc7 2840 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
Kojto 104:b9ad9a133dc7 2841 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
Kojto 104:b9ad9a133dc7 2842 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
Kojto 104:b9ad9a133dc7 2843 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
Kojto 104:b9ad9a133dc7 2844 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
Kojto 104:b9ad9a133dc7 2845
Kojto 104:b9ad9a133dc7 2846 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
Kojto 104:b9ad9a133dc7 2847 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
Kojto 104:b9ad9a133dc7 2848 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
Kojto 104:b9ad9a133dc7 2849 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
Kojto 104:b9ad9a133dc7 2850 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
Kojto 104:b9ad9a133dc7 2851 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
Kojto 104:b9ad9a133dc7 2852
Kojto 104:b9ad9a133dc7 2853 /* Bits 12..8 : Pin select. */
Kojto 104:b9ad9a133dc7 2854 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
Kojto 104:b9ad9a133dc7 2855 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 104:b9ad9a133dc7 2856
Kojto 104:b9ad9a133dc7 2857 /* Bits 1..0 : Mode */
Kojto 104:b9ad9a133dc7 2858 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 104:b9ad9a133dc7 2859 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 104:b9ad9a133dc7 2860 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 2861 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
Kojto 104:b9ad9a133dc7 2862 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
Kojto 104:b9ad9a133dc7 2863
Kojto 104:b9ad9a133dc7 2864 /* Register: GPIOTE_POWER */
Kojto 104:b9ad9a133dc7 2865 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 2866
Kojto 104:b9ad9a133dc7 2867 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 2868 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 2869 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 2870 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 2871 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 2872
Kojto 104:b9ad9a133dc7 2873
Kojto 104:b9ad9a133dc7 2874 /* Peripheral: LPCOMP */
Kojto 104:b9ad9a133dc7 2875 /* Description: Low power comparator. */
Kojto 104:b9ad9a133dc7 2876
Kojto 104:b9ad9a133dc7 2877 /* Register: LPCOMP_SHORTS */
Kojto 104:b9ad9a133dc7 2878 /* Description: Shortcuts for the LPCOMP. */
Kojto 104:b9ad9a133dc7 2879
Kojto 104:b9ad9a133dc7 2880 /* Bit 4 : Shortcut between CROSS event and STOP task. */
Kojto 104:b9ad9a133dc7 2881 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
Kojto 104:b9ad9a133dc7 2882 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
Kojto 104:b9ad9a133dc7 2883 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 2884 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 2885
Kojto 104:b9ad9a133dc7 2886 /* Bit 3 : Shortcut between UP event and STOP task. */
Kojto 104:b9ad9a133dc7 2887 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
Kojto 104:b9ad9a133dc7 2888 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
Kojto 104:b9ad9a133dc7 2889 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 2890 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 2891
Kojto 104:b9ad9a133dc7 2892 /* Bit 2 : Shortcut between DOWN event and STOP task. */
Kojto 104:b9ad9a133dc7 2893 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
Kojto 104:b9ad9a133dc7 2894 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
Kojto 104:b9ad9a133dc7 2895 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 2896 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 2897
Kojto 104:b9ad9a133dc7 2898 /* Bit 1 : Shortcut between RADY event and STOP task. */
Kojto 104:b9ad9a133dc7 2899 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
Kojto 104:b9ad9a133dc7 2900 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
Kojto 104:b9ad9a133dc7 2901 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 2902 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 2903
Kojto 104:b9ad9a133dc7 2904 /* Bit 0 : Shortcut between READY event and SAMPLE task. */
Kojto 104:b9ad9a133dc7 2905 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
Kojto 104:b9ad9a133dc7 2906 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
Kojto 104:b9ad9a133dc7 2907 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 2908 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 2909
Kojto 104:b9ad9a133dc7 2910 /* Register: LPCOMP_INTENSET */
Kojto 104:b9ad9a133dc7 2911 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 2912
Kojto 104:b9ad9a133dc7 2913 /* Bit 3 : Enable interrupt on CROSS event. */
Kojto 104:b9ad9a133dc7 2914 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Kojto 104:b9ad9a133dc7 2915 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
Kojto 104:b9ad9a133dc7 2916 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2917 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2918 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2919
Kojto 104:b9ad9a133dc7 2920 /* Bit 2 : Enable interrupt on UP event. */
Kojto 104:b9ad9a133dc7 2921 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
Kojto 104:b9ad9a133dc7 2922 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
Kojto 104:b9ad9a133dc7 2923 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2924 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2925 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2926
Kojto 104:b9ad9a133dc7 2927 /* Bit 1 : Enable interrupt on DOWN event. */
Kojto 104:b9ad9a133dc7 2928 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Kojto 104:b9ad9a133dc7 2929 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
Kojto 104:b9ad9a133dc7 2930 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2931 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2932 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2933
Kojto 104:b9ad9a133dc7 2934 /* Bit 0 : Enable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 2935 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 2936 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 2937 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2938 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2939 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 2940
Kojto 104:b9ad9a133dc7 2941 /* Register: LPCOMP_INTENCLR */
Kojto 104:b9ad9a133dc7 2942 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 2943
Kojto 104:b9ad9a133dc7 2944 /* Bit 3 : Disable interrupt on CROSS event. */
Kojto 104:b9ad9a133dc7 2945 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Kojto 104:b9ad9a133dc7 2946 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
Kojto 104:b9ad9a133dc7 2947 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2948 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2949 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2950
Kojto 104:b9ad9a133dc7 2951 /* Bit 2 : Disable interrupt on UP event. */
Kojto 104:b9ad9a133dc7 2952 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
Kojto 104:b9ad9a133dc7 2953 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
Kojto 104:b9ad9a133dc7 2954 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2955 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2956 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2957
Kojto 104:b9ad9a133dc7 2958 /* Bit 1 : Disable interrupt on DOWN event. */
Kojto 104:b9ad9a133dc7 2959 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Kojto 104:b9ad9a133dc7 2960 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
Kojto 104:b9ad9a133dc7 2961 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2962 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2963 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2964
Kojto 104:b9ad9a133dc7 2965 /* Bit 0 : Disable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 2966 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 2967 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 2968 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 2969 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 2970 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 2971
Kojto 104:b9ad9a133dc7 2972 /* Register: LPCOMP_RESULT */
Kojto 104:b9ad9a133dc7 2973 /* Description: Result of last compare. */
Kojto 104:b9ad9a133dc7 2974
Kojto 104:b9ad9a133dc7 2975 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Kojto 104:b9ad9a133dc7 2976 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Kojto 104:b9ad9a133dc7 2977 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Kojto 104:b9ad9a133dc7 2978 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
Kojto 104:b9ad9a133dc7 2979 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
Kojto 104:b9ad9a133dc7 2980
Kojto 104:b9ad9a133dc7 2981 /* Register: LPCOMP_ENABLE */
Kojto 104:b9ad9a133dc7 2982 /* Description: Enable the LPCOMP. */
Kojto 104:b9ad9a133dc7 2983
Kojto 104:b9ad9a133dc7 2984 /* Bits 1..0 : Enable or disable LPCOMP. */
Kojto 104:b9ad9a133dc7 2985 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 2986 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 2987 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
Kojto 104:b9ad9a133dc7 2988 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
Kojto 104:b9ad9a133dc7 2989
Kojto 104:b9ad9a133dc7 2990 /* Register: LPCOMP_PSEL */
Kojto 104:b9ad9a133dc7 2991 /* Description: Input pin select. */
Kojto 104:b9ad9a133dc7 2992
Kojto 104:b9ad9a133dc7 2993 /* Bits 2..0 : Analog input pin select. */
Kojto 104:b9ad9a133dc7 2994 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
Kojto 104:b9ad9a133dc7 2995 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 104:b9ad9a133dc7 2996 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
Kojto 104:b9ad9a133dc7 2997 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
Kojto 104:b9ad9a133dc7 2998 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
Kojto 104:b9ad9a133dc7 2999 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
Kojto 104:b9ad9a133dc7 3000 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
Kojto 104:b9ad9a133dc7 3001 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
Kojto 104:b9ad9a133dc7 3002 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
Kojto 104:b9ad9a133dc7 3003 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
Kojto 104:b9ad9a133dc7 3004
Kojto 104:b9ad9a133dc7 3005 /* Register: LPCOMP_REFSEL */
Kojto 104:b9ad9a133dc7 3006 /* Description: Reference select. */
Kojto 104:b9ad9a133dc7 3007
Kojto 104:b9ad9a133dc7 3008 /* Bits 2..0 : Reference select. */
Kojto 104:b9ad9a133dc7 3009 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
Kojto 104:b9ad9a133dc7 3010 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Kojto 104:b9ad9a133dc7 3011 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3012 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3013 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3014 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3015 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3016 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3017 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
Kojto 104:b9ad9a133dc7 3018 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
Kojto 104:b9ad9a133dc7 3019
Kojto 104:b9ad9a133dc7 3020 /* Register: LPCOMP_EXTREFSEL */
Kojto 104:b9ad9a133dc7 3021 /* Description: External reference select. */
Kojto 104:b9ad9a133dc7 3022
Kojto 104:b9ad9a133dc7 3023 /* Bit 0 : External analog reference pin selection. */
Kojto 104:b9ad9a133dc7 3024 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
Kojto 104:b9ad9a133dc7 3025 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Kojto 104:b9ad9a133dc7 3026 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
Kojto 104:b9ad9a133dc7 3027 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
Kojto 104:b9ad9a133dc7 3028
Kojto 104:b9ad9a133dc7 3029 /* Register: LPCOMP_ANADETECT */
Kojto 104:b9ad9a133dc7 3030 /* Description: Analog detect configuration. */
Kojto 104:b9ad9a133dc7 3031
Kojto 104:b9ad9a133dc7 3032 /* Bits 1..0 : Analog detect configuration. */
Kojto 104:b9ad9a133dc7 3033 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
Kojto 104:b9ad9a133dc7 3034 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
Kojto 104:b9ad9a133dc7 3035 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
Kojto 104:b9ad9a133dc7 3036 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
Kojto 104:b9ad9a133dc7 3037 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
Kojto 104:b9ad9a133dc7 3038
Kojto 104:b9ad9a133dc7 3039 /* Register: LPCOMP_POWER */
Kojto 104:b9ad9a133dc7 3040 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 3041
Kojto 104:b9ad9a133dc7 3042 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 3043 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 3044 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 3045 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 3046 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 3047
Kojto 104:b9ad9a133dc7 3048
Kojto 104:b9ad9a133dc7 3049 /* Peripheral: MPU */
Kojto 104:b9ad9a133dc7 3050 /* Description: Memory Protection Unit. */
Kojto 104:b9ad9a133dc7 3051
Kojto 104:b9ad9a133dc7 3052 /* Register: MPU_PERR0 */
Kojto 104:b9ad9a133dc7 3053 /* Description: Configuration of peripherals in mpu regions. */
Kojto 104:b9ad9a133dc7 3054
Kojto 104:b9ad9a133dc7 3055 /* Bit 31 : PPI region configuration. */
Kojto 104:b9ad9a133dc7 3056 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
Kojto 104:b9ad9a133dc7 3057 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
Kojto 104:b9ad9a133dc7 3058 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3059 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3060
Kojto 104:b9ad9a133dc7 3061 /* Bit 30 : NVMC region configuration. */
Kojto 104:b9ad9a133dc7 3062 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
Kojto 104:b9ad9a133dc7 3063 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
Kojto 104:b9ad9a133dc7 3064 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3065 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3066
Kojto 104:b9ad9a133dc7 3067 /* Bit 19 : LPCOMP region configuration. */
Kojto 104:b9ad9a133dc7 3068 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
Kojto 104:b9ad9a133dc7 3069 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
Kojto 104:b9ad9a133dc7 3070 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3071 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3072
Kojto 104:b9ad9a133dc7 3073 /* Bit 18 : QDEC region configuration. */
Kojto 104:b9ad9a133dc7 3074 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
Kojto 104:b9ad9a133dc7 3075 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
Kojto 104:b9ad9a133dc7 3076 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3077 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3078
Kojto 104:b9ad9a133dc7 3079 /* Bit 17 : RTC1 region configuration. */
Kojto 104:b9ad9a133dc7 3080 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
Kojto 104:b9ad9a133dc7 3081 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
Kojto 104:b9ad9a133dc7 3082 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3083 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3084
Kojto 104:b9ad9a133dc7 3085 /* Bit 16 : WDT region configuration. */
Kojto 104:b9ad9a133dc7 3086 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
Kojto 104:b9ad9a133dc7 3087 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
Kojto 104:b9ad9a133dc7 3088 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3089 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3090
Kojto 104:b9ad9a133dc7 3091 /* Bit 15 : CCM and AAR region configuration. */
Kojto 104:b9ad9a133dc7 3092 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
Kojto 104:b9ad9a133dc7 3093 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
Kojto 104:b9ad9a133dc7 3094 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3095 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3096
Kojto 104:b9ad9a133dc7 3097 /* Bit 14 : ECB region configuration. */
Kojto 104:b9ad9a133dc7 3098 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
Kojto 104:b9ad9a133dc7 3099 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
Kojto 104:b9ad9a133dc7 3100 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3101 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3102
Kojto 104:b9ad9a133dc7 3103 /* Bit 13 : RNG region configuration. */
Kojto 104:b9ad9a133dc7 3104 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
Kojto 104:b9ad9a133dc7 3105 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
Kojto 104:b9ad9a133dc7 3106 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3107 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3108
Kojto 104:b9ad9a133dc7 3109 /* Bit 12 : TEMP region configuration. */
Kojto 104:b9ad9a133dc7 3110 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
Kojto 104:b9ad9a133dc7 3111 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
Kojto 104:b9ad9a133dc7 3112 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3113 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3114
Kojto 104:b9ad9a133dc7 3115 /* Bit 11 : RTC0 region configuration. */
Kojto 104:b9ad9a133dc7 3116 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
Kojto 104:b9ad9a133dc7 3117 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
Kojto 104:b9ad9a133dc7 3118 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3119 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3120
Kojto 104:b9ad9a133dc7 3121 /* Bit 10 : TIMER2 region configuration. */
Kojto 104:b9ad9a133dc7 3122 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
Kojto 104:b9ad9a133dc7 3123 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
Kojto 104:b9ad9a133dc7 3124 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3125 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3126
Kojto 104:b9ad9a133dc7 3127 /* Bit 9 : TIMER1 region configuration. */
Kojto 104:b9ad9a133dc7 3128 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
Kojto 104:b9ad9a133dc7 3129 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
Kojto 104:b9ad9a133dc7 3130 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3131 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3132
Kojto 104:b9ad9a133dc7 3133 /* Bit 8 : TIMER0 region configuration. */
Kojto 104:b9ad9a133dc7 3134 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
Kojto 104:b9ad9a133dc7 3135 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
Kojto 104:b9ad9a133dc7 3136 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3137 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3138
Kojto 104:b9ad9a133dc7 3139 /* Bit 7 : ADC region configuration. */
Kojto 104:b9ad9a133dc7 3140 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
Kojto 104:b9ad9a133dc7 3141 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
Kojto 104:b9ad9a133dc7 3142 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3143 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3144
Kojto 104:b9ad9a133dc7 3145 /* Bit 6 : GPIOTE region configuration. */
Kojto 104:b9ad9a133dc7 3146 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
Kojto 104:b9ad9a133dc7 3147 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
Kojto 104:b9ad9a133dc7 3148 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3149 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3150
Kojto 104:b9ad9a133dc7 3151 /* Bit 4 : SPI1 and TWI1 region configuration. */
Kojto 104:b9ad9a133dc7 3152 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
Kojto 104:b9ad9a133dc7 3153 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
Kojto 104:b9ad9a133dc7 3154 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3155 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3156
Kojto 104:b9ad9a133dc7 3157 /* Bit 3 : SPI0 and TWI0 region configuration. */
Kojto 104:b9ad9a133dc7 3158 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
Kojto 104:b9ad9a133dc7 3159 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
Kojto 104:b9ad9a133dc7 3160 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3161 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3162
Kojto 104:b9ad9a133dc7 3163 /* Bit 2 : UART0 region configuration. */
Kojto 104:b9ad9a133dc7 3164 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
Kojto 104:b9ad9a133dc7 3165 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
Kojto 104:b9ad9a133dc7 3166 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3167 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3168
Kojto 104:b9ad9a133dc7 3169 /* Bit 1 : RADIO region configuration. */
Kojto 104:b9ad9a133dc7 3170 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
Kojto 104:b9ad9a133dc7 3171 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
Kojto 104:b9ad9a133dc7 3172 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3173 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3174
Kojto 104:b9ad9a133dc7 3175 /* Bit 0 : POWER_CLOCK region configuration. */
Kojto 104:b9ad9a133dc7 3176 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
Kojto 104:b9ad9a133dc7 3177 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
Kojto 104:b9ad9a133dc7 3178 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 104:b9ad9a133dc7 3179 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 104:b9ad9a133dc7 3180
Kojto 104:b9ad9a133dc7 3181 /* Register: MPU_PROTENSET0 */
Kojto 104:b9ad9a133dc7 3182 /* Description: Erase and write protection bit enable set register. */
Kojto 104:b9ad9a133dc7 3183
Kojto 104:b9ad9a133dc7 3184 /* Bit 31 : Protection enable for region 31. */
Kojto 104:b9ad9a133dc7 3185 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
Kojto 104:b9ad9a133dc7 3186 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
Kojto 104:b9ad9a133dc7 3187 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3188 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3189 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3190
Kojto 104:b9ad9a133dc7 3191 /* Bit 30 : Protection enable for region 30. */
Kojto 104:b9ad9a133dc7 3192 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
Kojto 104:b9ad9a133dc7 3193 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
Kojto 104:b9ad9a133dc7 3194 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3195 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3196 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3197
Kojto 104:b9ad9a133dc7 3198 /* Bit 29 : Protection enable for region 29. */
Kojto 104:b9ad9a133dc7 3199 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
Kojto 104:b9ad9a133dc7 3200 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
Kojto 104:b9ad9a133dc7 3201 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3202 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3203 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3204
Kojto 104:b9ad9a133dc7 3205 /* Bit 28 : Protection enable for region 28. */
Kojto 104:b9ad9a133dc7 3206 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
Kojto 104:b9ad9a133dc7 3207 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
Kojto 104:b9ad9a133dc7 3208 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3209 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3210 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3211
Kojto 104:b9ad9a133dc7 3212 /* Bit 27 : Protection enable for region 27. */
Kojto 104:b9ad9a133dc7 3213 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
Kojto 104:b9ad9a133dc7 3214 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
Kojto 104:b9ad9a133dc7 3215 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3216 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3217 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3218
Kojto 104:b9ad9a133dc7 3219 /* Bit 26 : Protection enable for region 26. */
Kojto 104:b9ad9a133dc7 3220 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
Kojto 104:b9ad9a133dc7 3221 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
Kojto 104:b9ad9a133dc7 3222 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3223 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3224 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3225
Kojto 104:b9ad9a133dc7 3226 /* Bit 25 : Protection enable for region 25. */
Kojto 104:b9ad9a133dc7 3227 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
Kojto 104:b9ad9a133dc7 3228 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
Kojto 104:b9ad9a133dc7 3229 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3230 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3231 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3232
Kojto 104:b9ad9a133dc7 3233 /* Bit 24 : Protection enable for region 24. */
Kojto 104:b9ad9a133dc7 3234 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
Kojto 104:b9ad9a133dc7 3235 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
Kojto 104:b9ad9a133dc7 3236 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3237 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3238 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3239
Kojto 104:b9ad9a133dc7 3240 /* Bit 23 : Protection enable for region 23. */
Kojto 104:b9ad9a133dc7 3241 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
Kojto 104:b9ad9a133dc7 3242 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
Kojto 104:b9ad9a133dc7 3243 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3244 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3245 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3246
Kojto 104:b9ad9a133dc7 3247 /* Bit 22 : Protection enable for region 22. */
Kojto 104:b9ad9a133dc7 3248 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
Kojto 104:b9ad9a133dc7 3249 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
Kojto 104:b9ad9a133dc7 3250 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3251 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3252 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3253
Kojto 104:b9ad9a133dc7 3254 /* Bit 21 : Protection enable for region 21. */
Kojto 104:b9ad9a133dc7 3255 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
Kojto 104:b9ad9a133dc7 3256 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
Kojto 104:b9ad9a133dc7 3257 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3258 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3259 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3260
Kojto 104:b9ad9a133dc7 3261 /* Bit 20 : Protection enable for region 20. */
Kojto 104:b9ad9a133dc7 3262 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
Kojto 104:b9ad9a133dc7 3263 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
Kojto 104:b9ad9a133dc7 3264 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3265 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3266 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3267
Kojto 104:b9ad9a133dc7 3268 /* Bit 19 : Protection enable for region 19. */
Kojto 104:b9ad9a133dc7 3269 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
Kojto 104:b9ad9a133dc7 3270 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
Kojto 104:b9ad9a133dc7 3271 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3272 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3273 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3274
Kojto 104:b9ad9a133dc7 3275 /* Bit 18 : Protection enable for region 18. */
Kojto 104:b9ad9a133dc7 3276 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
Kojto 104:b9ad9a133dc7 3277 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
Kojto 104:b9ad9a133dc7 3278 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3279 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3280 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3281
Kojto 104:b9ad9a133dc7 3282 /* Bit 17 : Protection enable for region 17. */
Kojto 104:b9ad9a133dc7 3283 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
Kojto 104:b9ad9a133dc7 3284 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
Kojto 104:b9ad9a133dc7 3285 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3286 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3287 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3288
Kojto 104:b9ad9a133dc7 3289 /* Bit 16 : Protection enable for region 16. */
Kojto 104:b9ad9a133dc7 3290 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
Kojto 104:b9ad9a133dc7 3291 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
Kojto 104:b9ad9a133dc7 3292 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3293 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3294 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3295
Kojto 104:b9ad9a133dc7 3296 /* Bit 15 : Protection enable for region 15. */
Kojto 104:b9ad9a133dc7 3297 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
Kojto 104:b9ad9a133dc7 3298 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
Kojto 104:b9ad9a133dc7 3299 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3300 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3301 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3302
Kojto 104:b9ad9a133dc7 3303 /* Bit 14 : Protection enable for region 14. */
Kojto 104:b9ad9a133dc7 3304 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
Kojto 104:b9ad9a133dc7 3305 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
Kojto 104:b9ad9a133dc7 3306 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3307 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3308 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3309
Kojto 104:b9ad9a133dc7 3310 /* Bit 13 : Protection enable for region 13. */
Kojto 104:b9ad9a133dc7 3311 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
Kojto 104:b9ad9a133dc7 3312 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
Kojto 104:b9ad9a133dc7 3313 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3314 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3315 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3316
Kojto 104:b9ad9a133dc7 3317 /* Bit 12 : Protection enable for region 12. */
Kojto 104:b9ad9a133dc7 3318 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
Kojto 104:b9ad9a133dc7 3319 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
Kojto 104:b9ad9a133dc7 3320 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3321 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3322 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3323
Kojto 104:b9ad9a133dc7 3324 /* Bit 11 : Protection enable for region 11. */
Kojto 104:b9ad9a133dc7 3325 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
Kojto 104:b9ad9a133dc7 3326 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
Kojto 104:b9ad9a133dc7 3327 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3328 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3329 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3330
Kojto 104:b9ad9a133dc7 3331 /* Bit 10 : Protection enable for region 10. */
Kojto 104:b9ad9a133dc7 3332 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
Kojto 104:b9ad9a133dc7 3333 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
Kojto 104:b9ad9a133dc7 3334 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3335 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3336 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3337
Kojto 104:b9ad9a133dc7 3338 /* Bit 9 : Protection enable for region 9. */
Kojto 104:b9ad9a133dc7 3339 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
Kojto 104:b9ad9a133dc7 3340 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
Kojto 104:b9ad9a133dc7 3341 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3342 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3343 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3344
Kojto 104:b9ad9a133dc7 3345 /* Bit 8 : Protection enable for region 8. */
Kojto 104:b9ad9a133dc7 3346 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
Kojto 104:b9ad9a133dc7 3347 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
Kojto 104:b9ad9a133dc7 3348 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3349 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3350 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3351
Kojto 104:b9ad9a133dc7 3352 /* Bit 7 : Protection enable for region 7. */
Kojto 104:b9ad9a133dc7 3353 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
Kojto 104:b9ad9a133dc7 3354 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
Kojto 104:b9ad9a133dc7 3355 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3356 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3357 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3358
Kojto 104:b9ad9a133dc7 3359 /* Bit 6 : Protection enable for region 6. */
Kojto 104:b9ad9a133dc7 3360 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
Kojto 104:b9ad9a133dc7 3361 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
Kojto 104:b9ad9a133dc7 3362 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3363 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3364 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3365
Kojto 104:b9ad9a133dc7 3366 /* Bit 5 : Protection enable for region 5. */
Kojto 104:b9ad9a133dc7 3367 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
Kojto 104:b9ad9a133dc7 3368 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
Kojto 104:b9ad9a133dc7 3369 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3370 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3371 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3372
Kojto 104:b9ad9a133dc7 3373 /* Bit 4 : Protection enable for region 4. */
Kojto 104:b9ad9a133dc7 3374 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
Kojto 104:b9ad9a133dc7 3375 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
Kojto 104:b9ad9a133dc7 3376 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3377 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3378 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3379
Kojto 104:b9ad9a133dc7 3380 /* Bit 3 : Protection enable for region 3. */
Kojto 104:b9ad9a133dc7 3381 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
Kojto 104:b9ad9a133dc7 3382 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
Kojto 104:b9ad9a133dc7 3383 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3384 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3385 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3386
Kojto 104:b9ad9a133dc7 3387 /* Bit 2 : Protection enable for region 2. */
Kojto 104:b9ad9a133dc7 3388 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
Kojto 104:b9ad9a133dc7 3389 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
Kojto 104:b9ad9a133dc7 3390 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3391 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3392 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3393
Kojto 104:b9ad9a133dc7 3394 /* Bit 1 : Protection enable for region 1. */
Kojto 104:b9ad9a133dc7 3395 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
Kojto 104:b9ad9a133dc7 3396 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
Kojto 104:b9ad9a133dc7 3397 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3398 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3399 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3400
Kojto 104:b9ad9a133dc7 3401 /* Bit 0 : Protection enable for region 0. */
Kojto 104:b9ad9a133dc7 3402 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
Kojto 104:b9ad9a133dc7 3403 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
Kojto 104:b9ad9a133dc7 3404 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3405 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3406 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3407
Kojto 104:b9ad9a133dc7 3408 /* Register: MPU_PROTENSET1 */
Kojto 104:b9ad9a133dc7 3409 /* Description: Erase and write protection bit enable set register. */
Kojto 104:b9ad9a133dc7 3410
Kojto 104:b9ad9a133dc7 3411 /* Bit 31 : Protection enable for region 63. */
Kojto 104:b9ad9a133dc7 3412 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
Kojto 104:b9ad9a133dc7 3413 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
Kojto 104:b9ad9a133dc7 3414 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3415 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3416 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3417
Kojto 104:b9ad9a133dc7 3418 /* Bit 30 : Protection enable for region 62. */
Kojto 104:b9ad9a133dc7 3419 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
Kojto 104:b9ad9a133dc7 3420 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
Kojto 104:b9ad9a133dc7 3421 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3422 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3423 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3424
Kojto 104:b9ad9a133dc7 3425 /* Bit 29 : Protection enable for region 61. */
Kojto 104:b9ad9a133dc7 3426 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
Kojto 104:b9ad9a133dc7 3427 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
Kojto 104:b9ad9a133dc7 3428 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3429 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3430 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3431
Kojto 104:b9ad9a133dc7 3432 /* Bit 28 : Protection enable for region 60. */
Kojto 104:b9ad9a133dc7 3433 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
Kojto 104:b9ad9a133dc7 3434 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
Kojto 104:b9ad9a133dc7 3435 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3436 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3437 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3438
Kojto 104:b9ad9a133dc7 3439 /* Bit 27 : Protection enable for region 59. */
Kojto 104:b9ad9a133dc7 3440 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
Kojto 104:b9ad9a133dc7 3441 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
Kojto 104:b9ad9a133dc7 3442 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3443 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3444 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3445
Kojto 104:b9ad9a133dc7 3446 /* Bit 26 : Protection enable for region 58. */
Kojto 104:b9ad9a133dc7 3447 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
Kojto 104:b9ad9a133dc7 3448 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
Kojto 104:b9ad9a133dc7 3449 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3450 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3451 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3452
Kojto 104:b9ad9a133dc7 3453 /* Bit 25 : Protection enable for region 57. */
Kojto 104:b9ad9a133dc7 3454 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
Kojto 104:b9ad9a133dc7 3455 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
Kojto 104:b9ad9a133dc7 3456 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3457 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3458 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3459
Kojto 104:b9ad9a133dc7 3460 /* Bit 24 : Protection enable for region 56. */
Kojto 104:b9ad9a133dc7 3461 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
Kojto 104:b9ad9a133dc7 3462 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
Kojto 104:b9ad9a133dc7 3463 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3464 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3465 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3466
Kojto 104:b9ad9a133dc7 3467 /* Bit 23 : Protection enable for region 55. */
Kojto 104:b9ad9a133dc7 3468 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
Kojto 104:b9ad9a133dc7 3469 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
Kojto 104:b9ad9a133dc7 3470 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3471 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3472 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3473
Kojto 104:b9ad9a133dc7 3474 /* Bit 22 : Protection enable for region 54. */
Kojto 104:b9ad9a133dc7 3475 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
Kojto 104:b9ad9a133dc7 3476 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
Kojto 104:b9ad9a133dc7 3477 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3478 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3479 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3480
Kojto 104:b9ad9a133dc7 3481 /* Bit 21 : Protection enable for region 53. */
Kojto 104:b9ad9a133dc7 3482 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
Kojto 104:b9ad9a133dc7 3483 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
Kojto 104:b9ad9a133dc7 3484 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3485 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3486 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3487
Kojto 104:b9ad9a133dc7 3488 /* Bit 20 : Protection enable for region 52. */
Kojto 104:b9ad9a133dc7 3489 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
Kojto 104:b9ad9a133dc7 3490 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
Kojto 104:b9ad9a133dc7 3491 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3492 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3493 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3494
Kojto 104:b9ad9a133dc7 3495 /* Bit 19 : Protection enable for region 51. */
Kojto 104:b9ad9a133dc7 3496 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
Kojto 104:b9ad9a133dc7 3497 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
Kojto 104:b9ad9a133dc7 3498 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3499 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3500 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3501
Kojto 104:b9ad9a133dc7 3502 /* Bit 18 : Protection enable for region 50. */
Kojto 104:b9ad9a133dc7 3503 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
Kojto 104:b9ad9a133dc7 3504 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
Kojto 104:b9ad9a133dc7 3505 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3506 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3507 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3508
Kojto 104:b9ad9a133dc7 3509 /* Bit 17 : Protection enable for region 49. */
Kojto 104:b9ad9a133dc7 3510 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
Kojto 104:b9ad9a133dc7 3511 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
Kojto 104:b9ad9a133dc7 3512 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3513 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3514 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3515
Kojto 104:b9ad9a133dc7 3516 /* Bit 16 : Protection enable for region 48. */
Kojto 104:b9ad9a133dc7 3517 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
Kojto 104:b9ad9a133dc7 3518 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
Kojto 104:b9ad9a133dc7 3519 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3520 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3521 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3522
Kojto 104:b9ad9a133dc7 3523 /* Bit 15 : Protection enable for region 47. */
Kojto 104:b9ad9a133dc7 3524 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
Kojto 104:b9ad9a133dc7 3525 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
Kojto 104:b9ad9a133dc7 3526 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3527 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3528 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3529
Kojto 104:b9ad9a133dc7 3530 /* Bit 14 : Protection enable for region 46. */
Kojto 104:b9ad9a133dc7 3531 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
Kojto 104:b9ad9a133dc7 3532 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
Kojto 104:b9ad9a133dc7 3533 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3534 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3535 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3536
Kojto 104:b9ad9a133dc7 3537 /* Bit 13 : Protection enable for region 45. */
Kojto 104:b9ad9a133dc7 3538 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
Kojto 104:b9ad9a133dc7 3539 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
Kojto 104:b9ad9a133dc7 3540 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3541 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3542 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3543
Kojto 104:b9ad9a133dc7 3544 /* Bit 12 : Protection enable for region 44. */
Kojto 104:b9ad9a133dc7 3545 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
Kojto 104:b9ad9a133dc7 3546 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
Kojto 104:b9ad9a133dc7 3547 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3548 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3549 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3550
Kojto 104:b9ad9a133dc7 3551 /* Bit 11 : Protection enable for region 43. */
Kojto 104:b9ad9a133dc7 3552 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
Kojto 104:b9ad9a133dc7 3553 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
Kojto 104:b9ad9a133dc7 3554 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3555 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3556 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3557
Kojto 104:b9ad9a133dc7 3558 /* Bit 10 : Protection enable for region 42. */
Kojto 104:b9ad9a133dc7 3559 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
Kojto 104:b9ad9a133dc7 3560 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
Kojto 104:b9ad9a133dc7 3561 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3562 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3563 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3564
Kojto 104:b9ad9a133dc7 3565 /* Bit 9 : Protection enable for region 41. */
Kojto 104:b9ad9a133dc7 3566 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
Kojto 104:b9ad9a133dc7 3567 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
Kojto 104:b9ad9a133dc7 3568 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3569 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3570 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3571
Kojto 104:b9ad9a133dc7 3572 /* Bit 8 : Protection enable for region 40. */
Kojto 104:b9ad9a133dc7 3573 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
Kojto 104:b9ad9a133dc7 3574 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
Kojto 104:b9ad9a133dc7 3575 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3576 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3577 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3578
Kojto 104:b9ad9a133dc7 3579 /* Bit 7 : Protection enable for region 39. */
Kojto 104:b9ad9a133dc7 3580 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
Kojto 104:b9ad9a133dc7 3581 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
Kojto 104:b9ad9a133dc7 3582 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3583 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3584 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3585
Kojto 104:b9ad9a133dc7 3586 /* Bit 6 : Protection enable for region 38. */
Kojto 104:b9ad9a133dc7 3587 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
Kojto 104:b9ad9a133dc7 3588 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
Kojto 104:b9ad9a133dc7 3589 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3590 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3591 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3592
Kojto 104:b9ad9a133dc7 3593 /* Bit 5 : Protection enable for region 37. */
Kojto 104:b9ad9a133dc7 3594 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
Kojto 104:b9ad9a133dc7 3595 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
Kojto 104:b9ad9a133dc7 3596 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3597 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3598 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3599
Kojto 104:b9ad9a133dc7 3600 /* Bit 4 : Protection enable for region 36. */
Kojto 104:b9ad9a133dc7 3601 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
Kojto 104:b9ad9a133dc7 3602 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
Kojto 104:b9ad9a133dc7 3603 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3604 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3605 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3606
Kojto 104:b9ad9a133dc7 3607 /* Bit 3 : Protection enable for region 35. */
Kojto 104:b9ad9a133dc7 3608 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
Kojto 104:b9ad9a133dc7 3609 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
Kojto 104:b9ad9a133dc7 3610 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3611 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3612 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3613
Kojto 104:b9ad9a133dc7 3614 /* Bit 2 : Protection enable for region 34. */
Kojto 104:b9ad9a133dc7 3615 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
Kojto 104:b9ad9a133dc7 3616 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
Kojto 104:b9ad9a133dc7 3617 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3618 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3619 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3620
Kojto 104:b9ad9a133dc7 3621 /* Bit 1 : Protection enable for region 33. */
Kojto 104:b9ad9a133dc7 3622 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
Kojto 104:b9ad9a133dc7 3623 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
Kojto 104:b9ad9a133dc7 3624 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3625 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3626 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3627
Kojto 104:b9ad9a133dc7 3628 /* Bit 0 : Protection enable for region 32. */
Kojto 104:b9ad9a133dc7 3629 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
Kojto 104:b9ad9a133dc7 3630 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
Kojto 104:b9ad9a133dc7 3631 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3632 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3633 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
Kojto 104:b9ad9a133dc7 3634
Kojto 104:b9ad9a133dc7 3635 /* Register: MPU_DISABLEINDEBUG */
Kojto 104:b9ad9a133dc7 3636 /* Description: Disable erase and write protection mechanism in debug mode. */
Kojto 104:b9ad9a133dc7 3637
Kojto 104:b9ad9a133dc7 3638 /* Bit 0 : Disable protection mechanism in debug mode. */
Kojto 104:b9ad9a133dc7 3639 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
Kojto 104:b9ad9a133dc7 3640 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
Kojto 104:b9ad9a133dc7 3641 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
Kojto 104:b9ad9a133dc7 3642 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
Kojto 104:b9ad9a133dc7 3643
Kojto 104:b9ad9a133dc7 3644 /* Register: MPU_PROTBLOCKSIZE */
Kojto 104:b9ad9a133dc7 3645 /* Description: Erase and write protection block size. */
Kojto 104:b9ad9a133dc7 3646
Kojto 104:b9ad9a133dc7 3647 /* Bits 1..0 : Erase and write protection block size. */
Kojto 104:b9ad9a133dc7 3648 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
Kojto 104:b9ad9a133dc7 3649 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
Kojto 104:b9ad9a133dc7 3650 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
Kojto 104:b9ad9a133dc7 3651
Kojto 104:b9ad9a133dc7 3652
Kojto 104:b9ad9a133dc7 3653 /* Peripheral: NVMC */
Kojto 104:b9ad9a133dc7 3654 /* Description: Non Volatile Memory Controller. */
Kojto 104:b9ad9a133dc7 3655
Kojto 104:b9ad9a133dc7 3656 /* Register: NVMC_READY */
Kojto 104:b9ad9a133dc7 3657 /* Description: Ready flag. */
Kojto 104:b9ad9a133dc7 3658
Kojto 104:b9ad9a133dc7 3659 /* Bit 0 : NVMC ready. */
Kojto 104:b9ad9a133dc7 3660 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 3661 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 3662 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
Kojto 104:b9ad9a133dc7 3663 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
Kojto 104:b9ad9a133dc7 3664
Kojto 104:b9ad9a133dc7 3665 /* Register: NVMC_CONFIG */
Kojto 104:b9ad9a133dc7 3666 /* Description: Configuration register. */
Kojto 104:b9ad9a133dc7 3667
Kojto 104:b9ad9a133dc7 3668 /* Bits 1..0 : Program write enable. */
Kojto 104:b9ad9a133dc7 3669 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
Kojto 104:b9ad9a133dc7 3670 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
Kojto 104:b9ad9a133dc7 3671 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
Kojto 104:b9ad9a133dc7 3672 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
Kojto 104:b9ad9a133dc7 3673 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
Kojto 104:b9ad9a133dc7 3674
Kojto 104:b9ad9a133dc7 3675 /* Register: NVMC_ERASEALL */
Kojto 104:b9ad9a133dc7 3676 /* Description: Register for erasing all non-volatile user memory. */
Kojto 104:b9ad9a133dc7 3677
Kojto 104:b9ad9a133dc7 3678 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
Kojto 104:b9ad9a133dc7 3679 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
Kojto 104:b9ad9a133dc7 3680 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
Kojto 104:b9ad9a133dc7 3681 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
Kojto 104:b9ad9a133dc7 3682 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
Kojto 104:b9ad9a133dc7 3683
Kojto 104:b9ad9a133dc7 3684 /* Register: NVMC_ERASEUICR */
Kojto 104:b9ad9a133dc7 3685 /* Description: Register for start erasing User Information Congfiguration Registers. */
Kojto 104:b9ad9a133dc7 3686
Kojto 104:b9ad9a133dc7 3687 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
Kojto 104:b9ad9a133dc7 3688 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
Kojto 104:b9ad9a133dc7 3689 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
Kojto 104:b9ad9a133dc7 3690 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
Kojto 104:b9ad9a133dc7 3691 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
Kojto 104:b9ad9a133dc7 3692
Kojto 104:b9ad9a133dc7 3693
Kojto 104:b9ad9a133dc7 3694 /* Peripheral: POWER */
Kojto 104:b9ad9a133dc7 3695 /* Description: Power Control. */
Kojto 104:b9ad9a133dc7 3696
Kojto 104:b9ad9a133dc7 3697 /* Register: POWER_INTENSET */
Kojto 104:b9ad9a133dc7 3698 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 3699
Kojto 104:b9ad9a133dc7 3700 /* Bit 2 : Enable interrupt on POFWARN event. */
Kojto 104:b9ad9a133dc7 3701 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
Kojto 104:b9ad9a133dc7 3702 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
Kojto 104:b9ad9a133dc7 3703 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 3704 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 3705 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 3706
Kojto 104:b9ad9a133dc7 3707 /* Register: POWER_INTENCLR */
Kojto 104:b9ad9a133dc7 3708 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 3709
Kojto 104:b9ad9a133dc7 3710 /* Bit 2 : Disable interrupt on POFWARN event. */
Kojto 104:b9ad9a133dc7 3711 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
Kojto 104:b9ad9a133dc7 3712 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
Kojto 104:b9ad9a133dc7 3713 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 3714 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 3715 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 3716
Kojto 104:b9ad9a133dc7 3717 /* Register: POWER_RESETREAS */
Kojto 104:b9ad9a133dc7 3718 /* Description: Reset reason. */
Kojto 104:b9ad9a133dc7 3719
Kojto 104:b9ad9a133dc7 3720 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
Kojto 104:b9ad9a133dc7 3721 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
Kojto 104:b9ad9a133dc7 3722 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
Kojto 104:b9ad9a133dc7 3723
Kojto 104:b9ad9a133dc7 3724 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
Kojto 104:b9ad9a133dc7 3725 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
Kojto 104:b9ad9a133dc7 3726 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
Kojto 104:b9ad9a133dc7 3727
Kojto 104:b9ad9a133dc7 3728 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
Kojto 104:b9ad9a133dc7 3729 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
Kojto 104:b9ad9a133dc7 3730 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
Kojto 104:b9ad9a133dc7 3731
Kojto 104:b9ad9a133dc7 3732 /* Bit 3 : Reset from CPU lock-up detected. */
Kojto 104:b9ad9a133dc7 3733 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
Kojto 104:b9ad9a133dc7 3734 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
Kojto 104:b9ad9a133dc7 3735
Kojto 104:b9ad9a133dc7 3736 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
Kojto 104:b9ad9a133dc7 3737 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
Kojto 104:b9ad9a133dc7 3738 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
Kojto 104:b9ad9a133dc7 3739
Kojto 104:b9ad9a133dc7 3740 /* Bit 1 : Reset from watchdog detected. */
Kojto 104:b9ad9a133dc7 3741 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
Kojto 104:b9ad9a133dc7 3742 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
Kojto 104:b9ad9a133dc7 3743
Kojto 104:b9ad9a133dc7 3744 /* Bit 0 : Reset from pin-reset detected. */
Kojto 104:b9ad9a133dc7 3745 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
Kojto 104:b9ad9a133dc7 3746 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
Kojto 104:b9ad9a133dc7 3747
Kojto 104:b9ad9a133dc7 3748 /* Register: POWER_RAMSTATUS */
Kojto 104:b9ad9a133dc7 3749 /* Description: Ram status register. */
Kojto 104:b9ad9a133dc7 3750
Kojto 104:b9ad9a133dc7 3751 /* Bit 3 : RAM block 3 status. */
Kojto 104:b9ad9a133dc7 3752 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
Kojto 104:b9ad9a133dc7 3753 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
Kojto 104:b9ad9a133dc7 3754 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
Kojto 104:b9ad9a133dc7 3755 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
Kojto 104:b9ad9a133dc7 3756
Kojto 104:b9ad9a133dc7 3757 /* Bit 2 : RAM block 2 status. */
Kojto 104:b9ad9a133dc7 3758 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
Kojto 104:b9ad9a133dc7 3759 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
Kojto 104:b9ad9a133dc7 3760 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
Kojto 104:b9ad9a133dc7 3761 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
Kojto 104:b9ad9a133dc7 3762
Kojto 104:b9ad9a133dc7 3763 /* Bit 1 : RAM block 1 status. */
Kojto 104:b9ad9a133dc7 3764 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
Kojto 104:b9ad9a133dc7 3765 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
Kojto 104:b9ad9a133dc7 3766 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
Kojto 104:b9ad9a133dc7 3767 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
Kojto 104:b9ad9a133dc7 3768
Kojto 104:b9ad9a133dc7 3769 /* Bit 0 : RAM block 0 status. */
Kojto 104:b9ad9a133dc7 3770 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
Kojto 104:b9ad9a133dc7 3771 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
Kojto 104:b9ad9a133dc7 3772 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
Kojto 104:b9ad9a133dc7 3773 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
Kojto 104:b9ad9a133dc7 3774
Kojto 104:b9ad9a133dc7 3775 /* Register: POWER_SYSTEMOFF */
Kojto 104:b9ad9a133dc7 3776 /* Description: System off register. */
Kojto 104:b9ad9a133dc7 3777
Kojto 104:b9ad9a133dc7 3778 /* Bit 0 : Enter system off mode. */
Kojto 104:b9ad9a133dc7 3779 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
Kojto 104:b9ad9a133dc7 3780 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
Kojto 104:b9ad9a133dc7 3781 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
Kojto 104:b9ad9a133dc7 3782
Kojto 104:b9ad9a133dc7 3783 /* Register: POWER_POFCON */
Kojto 104:b9ad9a133dc7 3784 /* Description: Power failure configuration. */
Kojto 104:b9ad9a133dc7 3785
Kojto 104:b9ad9a133dc7 3786 /* Bits 2..1 : Set threshold level. */
Kojto 104:b9ad9a133dc7 3787 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
Kojto 104:b9ad9a133dc7 3788 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
Kojto 104:b9ad9a133dc7 3789 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
Kojto 104:b9ad9a133dc7 3790 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
Kojto 104:b9ad9a133dc7 3791 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
Kojto 104:b9ad9a133dc7 3792 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
Kojto 104:b9ad9a133dc7 3793
Kojto 104:b9ad9a133dc7 3794 /* Bit 0 : Power failure comparator enable. */
Kojto 104:b9ad9a133dc7 3795 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
Kojto 104:b9ad9a133dc7 3796 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
Kojto 104:b9ad9a133dc7 3797 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 3798 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 3799
Kojto 104:b9ad9a133dc7 3800 /* Register: POWER_GPREGRET */
Kojto 104:b9ad9a133dc7 3801 /* Description: General purpose retention register. This register is a retained register. */
Kojto 104:b9ad9a133dc7 3802
Kojto 104:b9ad9a133dc7 3803 /* Bits 7..0 : General purpose retention register. */
Kojto 104:b9ad9a133dc7 3804 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
Kojto 104:b9ad9a133dc7 3805 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
Kojto 104:b9ad9a133dc7 3806
Kojto 104:b9ad9a133dc7 3807 /* Register: POWER_RAMON */
Kojto 104:b9ad9a133dc7 3808 /* Description: Ram on/off. */
Kojto 104:b9ad9a133dc7 3809
Kojto 104:b9ad9a133dc7 3810 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
Kojto 104:b9ad9a133dc7 3811 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
Kojto 104:b9ad9a133dc7 3812 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
Kojto 104:b9ad9a133dc7 3813 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
Kojto 104:b9ad9a133dc7 3814 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
Kojto 104:b9ad9a133dc7 3815
Kojto 104:b9ad9a133dc7 3816 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
Kojto 104:b9ad9a133dc7 3817 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
Kojto 104:b9ad9a133dc7 3818 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
Kojto 104:b9ad9a133dc7 3819 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
Kojto 104:b9ad9a133dc7 3820 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
Kojto 104:b9ad9a133dc7 3821
Kojto 104:b9ad9a133dc7 3822 /* Bit 1 : RAM block 1 behaviour in ON mode. */
Kojto 104:b9ad9a133dc7 3823 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
Kojto 104:b9ad9a133dc7 3824 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
Kojto 104:b9ad9a133dc7 3825 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
Kojto 104:b9ad9a133dc7 3826 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
Kojto 104:b9ad9a133dc7 3827
Kojto 104:b9ad9a133dc7 3828 /* Bit 0 : RAM block 0 behaviour in ON mode. */
Kojto 104:b9ad9a133dc7 3829 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
Kojto 104:b9ad9a133dc7 3830 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
Kojto 104:b9ad9a133dc7 3831 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
Kojto 104:b9ad9a133dc7 3832 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
Kojto 104:b9ad9a133dc7 3833
Kojto 104:b9ad9a133dc7 3834 /* Register: POWER_RESET */
Kojto 104:b9ad9a133dc7 3835 /* Description: Pin reset functionality configuration register. This register is a retained register. */
Kojto 104:b9ad9a133dc7 3836
Kojto 104:b9ad9a133dc7 3837 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
Kojto 104:b9ad9a133dc7 3838 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
Kojto 104:b9ad9a133dc7 3839 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
Kojto 104:b9ad9a133dc7 3840 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
Kojto 104:b9ad9a133dc7 3841 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
Kojto 104:b9ad9a133dc7 3842
Kojto 104:b9ad9a133dc7 3843 /* Register: POWER_RAMONB */
Kojto 104:b9ad9a133dc7 3844 /* Description: Ram on/off. */
Kojto 104:b9ad9a133dc7 3845
Kojto 104:b9ad9a133dc7 3846 /* Bit 17 : RAM block 3 behaviour in OFF mode. */
Kojto 104:b9ad9a133dc7 3847 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
Kojto 104:b9ad9a133dc7 3848 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
Kojto 104:b9ad9a133dc7 3849 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
Kojto 104:b9ad9a133dc7 3850 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
Kojto 104:b9ad9a133dc7 3851
Kojto 104:b9ad9a133dc7 3852 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
Kojto 104:b9ad9a133dc7 3853 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
Kojto 104:b9ad9a133dc7 3854 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
Kojto 104:b9ad9a133dc7 3855 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
Kojto 104:b9ad9a133dc7 3856 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
Kojto 104:b9ad9a133dc7 3857
Kojto 104:b9ad9a133dc7 3858 /* Bit 1 : RAM block 3 behaviour in ON mode. */
Kojto 104:b9ad9a133dc7 3859 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
Kojto 104:b9ad9a133dc7 3860 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
Kojto 104:b9ad9a133dc7 3861 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
Kojto 104:b9ad9a133dc7 3862 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
Kojto 104:b9ad9a133dc7 3863
Kojto 104:b9ad9a133dc7 3864 /* Bit 0 : RAM block 2 behaviour in ON mode. */
Kojto 104:b9ad9a133dc7 3865 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
Kojto 104:b9ad9a133dc7 3866 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
Kojto 104:b9ad9a133dc7 3867 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
Kojto 104:b9ad9a133dc7 3868 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
Kojto 104:b9ad9a133dc7 3869
Kojto 104:b9ad9a133dc7 3870 /* Register: POWER_DCDCEN */
Kojto 104:b9ad9a133dc7 3871 /* Description: DCDC converter enable configuration register. */
Kojto 104:b9ad9a133dc7 3872
Kojto 104:b9ad9a133dc7 3873 /* Bit 0 : Enable DCDC converter. */
Kojto 104:b9ad9a133dc7 3874 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
Kojto 104:b9ad9a133dc7 3875 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
Kojto 104:b9ad9a133dc7 3876 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
Kojto 104:b9ad9a133dc7 3877 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
Kojto 104:b9ad9a133dc7 3878
Kojto 104:b9ad9a133dc7 3879 /* Register: POWER_DCDCFORCE */
Kojto 104:b9ad9a133dc7 3880 /* Description: DCDC power-up force register. */
Kojto 104:b9ad9a133dc7 3881
Kojto 104:b9ad9a133dc7 3882 /* Bit 1 : DCDC power-up force on. */
Kojto 104:b9ad9a133dc7 3883 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
Kojto 104:b9ad9a133dc7 3884 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
Kojto 104:b9ad9a133dc7 3885 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
Kojto 104:b9ad9a133dc7 3886 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
Kojto 104:b9ad9a133dc7 3887
Kojto 104:b9ad9a133dc7 3888 /* Bit 0 : DCDC power-up force off. */
Kojto 104:b9ad9a133dc7 3889 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
Kojto 104:b9ad9a133dc7 3890 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
Kojto 104:b9ad9a133dc7 3891 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
Kojto 104:b9ad9a133dc7 3892 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
Kojto 104:b9ad9a133dc7 3893
Kojto 104:b9ad9a133dc7 3894
Kojto 104:b9ad9a133dc7 3895 /* Peripheral: PPI */
Kojto 104:b9ad9a133dc7 3896 /* Description: PPI controller. */
Kojto 104:b9ad9a133dc7 3897
Kojto 104:b9ad9a133dc7 3898 /* Register: PPI_CHEN */
Kojto 104:b9ad9a133dc7 3899 /* Description: Channel enable. */
Kojto 104:b9ad9a133dc7 3900
Kojto 104:b9ad9a133dc7 3901 /* Bit 31 : Enable PPI channel 31. */
Kojto 104:b9ad9a133dc7 3902 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 104:b9ad9a133dc7 3903 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 104:b9ad9a133dc7 3904 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3905 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3906
Kojto 104:b9ad9a133dc7 3907 /* Bit 30 : Enable PPI channel 30. */
Kojto 104:b9ad9a133dc7 3908 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 104:b9ad9a133dc7 3909 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 104:b9ad9a133dc7 3910 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3911 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3912
Kojto 104:b9ad9a133dc7 3913 /* Bit 29 : Enable PPI channel 29. */
Kojto 104:b9ad9a133dc7 3914 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 104:b9ad9a133dc7 3915 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 104:b9ad9a133dc7 3916 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3917 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3918
Kojto 104:b9ad9a133dc7 3919 /* Bit 28 : Enable PPI channel 28. */
Kojto 104:b9ad9a133dc7 3920 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 104:b9ad9a133dc7 3921 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 104:b9ad9a133dc7 3922 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3923 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3924
Kojto 104:b9ad9a133dc7 3925 /* Bit 27 : Enable PPI channel 27. */
Kojto 104:b9ad9a133dc7 3926 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 104:b9ad9a133dc7 3927 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 104:b9ad9a133dc7 3928 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3929 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3930
Kojto 104:b9ad9a133dc7 3931 /* Bit 26 : Enable PPI channel 26. */
Kojto 104:b9ad9a133dc7 3932 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 104:b9ad9a133dc7 3933 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 104:b9ad9a133dc7 3934 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3935 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3936
Kojto 104:b9ad9a133dc7 3937 /* Bit 25 : Enable PPI channel 25. */
Kojto 104:b9ad9a133dc7 3938 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 104:b9ad9a133dc7 3939 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 104:b9ad9a133dc7 3940 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3941 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3942
Kojto 104:b9ad9a133dc7 3943 /* Bit 24 : Enable PPI channel 24. */
Kojto 104:b9ad9a133dc7 3944 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 104:b9ad9a133dc7 3945 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 104:b9ad9a133dc7 3946 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3947 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3948
Kojto 104:b9ad9a133dc7 3949 /* Bit 23 : Enable PPI channel 23. */
Kojto 104:b9ad9a133dc7 3950 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 104:b9ad9a133dc7 3951 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 104:b9ad9a133dc7 3952 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3953 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3954
Kojto 104:b9ad9a133dc7 3955 /* Bit 22 : Enable PPI channel 22. */
Kojto 104:b9ad9a133dc7 3956 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 104:b9ad9a133dc7 3957 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 104:b9ad9a133dc7 3958 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3959 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3960
Kojto 104:b9ad9a133dc7 3961 /* Bit 21 : Enable PPI channel 21. */
Kojto 104:b9ad9a133dc7 3962 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 104:b9ad9a133dc7 3963 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 104:b9ad9a133dc7 3964 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3965 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3966
Kojto 104:b9ad9a133dc7 3967 /* Bit 20 : Enable PPI channel 20. */
Kojto 104:b9ad9a133dc7 3968 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 104:b9ad9a133dc7 3969 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 104:b9ad9a133dc7 3970 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3971 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3972
Kojto 104:b9ad9a133dc7 3973 /* Bit 15 : Enable PPI channel 15. */
Kojto 104:b9ad9a133dc7 3974 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 104:b9ad9a133dc7 3975 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 104:b9ad9a133dc7 3976 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3977 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3978
Kojto 104:b9ad9a133dc7 3979 /* Bit 14 : Enable PPI channel 14. */
Kojto 104:b9ad9a133dc7 3980 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 104:b9ad9a133dc7 3981 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 104:b9ad9a133dc7 3982 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3983 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3984
Kojto 104:b9ad9a133dc7 3985 /* Bit 13 : Enable PPI channel 13. */
Kojto 104:b9ad9a133dc7 3986 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 104:b9ad9a133dc7 3987 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 104:b9ad9a133dc7 3988 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3989 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3990
Kojto 104:b9ad9a133dc7 3991 /* Bit 12 : Enable PPI channel 12. */
Kojto 104:b9ad9a133dc7 3992 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 104:b9ad9a133dc7 3993 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 104:b9ad9a133dc7 3994 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 3995 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 3996
Kojto 104:b9ad9a133dc7 3997 /* Bit 11 : Enable PPI channel 11. */
Kojto 104:b9ad9a133dc7 3998 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 104:b9ad9a133dc7 3999 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 104:b9ad9a133dc7 4000 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4001 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4002
Kojto 104:b9ad9a133dc7 4003 /* Bit 10 : Enable PPI channel 10. */
Kojto 104:b9ad9a133dc7 4004 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 104:b9ad9a133dc7 4005 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 104:b9ad9a133dc7 4006 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4007 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4008
Kojto 104:b9ad9a133dc7 4009 /* Bit 9 : Enable PPI channel 9. */
Kojto 104:b9ad9a133dc7 4010 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 104:b9ad9a133dc7 4011 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 104:b9ad9a133dc7 4012 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4013 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4014
Kojto 104:b9ad9a133dc7 4015 /* Bit 8 : Enable PPI channel 8. */
Kojto 104:b9ad9a133dc7 4016 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 104:b9ad9a133dc7 4017 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 104:b9ad9a133dc7 4018 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4019 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4020
Kojto 104:b9ad9a133dc7 4021 /* Bit 7 : Enable PPI channel 7. */
Kojto 104:b9ad9a133dc7 4022 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 104:b9ad9a133dc7 4023 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 104:b9ad9a133dc7 4024 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4025 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4026
Kojto 104:b9ad9a133dc7 4027 /* Bit 6 : Enable PPI channel 6. */
Kojto 104:b9ad9a133dc7 4028 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 104:b9ad9a133dc7 4029 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 104:b9ad9a133dc7 4030 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4031 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4032
Kojto 104:b9ad9a133dc7 4033 /* Bit 5 : Enable PPI channel 5. */
Kojto 104:b9ad9a133dc7 4034 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 104:b9ad9a133dc7 4035 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 104:b9ad9a133dc7 4036 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4037 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4038
Kojto 104:b9ad9a133dc7 4039 /* Bit 4 : Enable PPI channel 4. */
Kojto 104:b9ad9a133dc7 4040 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 104:b9ad9a133dc7 4041 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 104:b9ad9a133dc7 4042 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4043 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4044
Kojto 104:b9ad9a133dc7 4045 /* Bit 3 : Enable PPI channel 3. */
Kojto 104:b9ad9a133dc7 4046 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 104:b9ad9a133dc7 4047 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 104:b9ad9a133dc7 4048 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
Kojto 104:b9ad9a133dc7 4049 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
Kojto 104:b9ad9a133dc7 4050
Kojto 104:b9ad9a133dc7 4051 /* Bit 2 : Enable PPI channel 2. */
Kojto 104:b9ad9a133dc7 4052 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 104:b9ad9a133dc7 4053 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 104:b9ad9a133dc7 4054 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4055 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4056
Kojto 104:b9ad9a133dc7 4057 /* Bit 1 : Enable PPI channel 1. */
Kojto 104:b9ad9a133dc7 4058 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 104:b9ad9a133dc7 4059 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 104:b9ad9a133dc7 4060 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4061 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4062
Kojto 104:b9ad9a133dc7 4063 /* Bit 0 : Enable PPI channel 0. */
Kojto 104:b9ad9a133dc7 4064 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 104:b9ad9a133dc7 4065 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 104:b9ad9a133dc7 4066 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4067 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4068
Kojto 104:b9ad9a133dc7 4069 /* Register: PPI_CHENSET */
Kojto 104:b9ad9a133dc7 4070 /* Description: Channel enable set. */
Kojto 104:b9ad9a133dc7 4071
Kojto 104:b9ad9a133dc7 4072 /* Bit 31 : Enable PPI channel 31. */
Kojto 104:b9ad9a133dc7 4073 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 104:b9ad9a133dc7 4074 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 104:b9ad9a133dc7 4075 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4076 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4077 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4078
Kojto 104:b9ad9a133dc7 4079 /* Bit 30 : Enable PPI channel 30. */
Kojto 104:b9ad9a133dc7 4080 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 104:b9ad9a133dc7 4081 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 104:b9ad9a133dc7 4082 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4083 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4084 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4085
Kojto 104:b9ad9a133dc7 4086 /* Bit 29 : Enable PPI channel 29. */
Kojto 104:b9ad9a133dc7 4087 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 104:b9ad9a133dc7 4088 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 104:b9ad9a133dc7 4089 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4090 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4091 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4092
Kojto 104:b9ad9a133dc7 4093 /* Bit 28 : Enable PPI channel 28. */
Kojto 104:b9ad9a133dc7 4094 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 104:b9ad9a133dc7 4095 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 104:b9ad9a133dc7 4096 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4097 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4098 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4099
Kojto 104:b9ad9a133dc7 4100 /* Bit 27 : Enable PPI channel 27. */
Kojto 104:b9ad9a133dc7 4101 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 104:b9ad9a133dc7 4102 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 104:b9ad9a133dc7 4103 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4104 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4105 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4106
Kojto 104:b9ad9a133dc7 4107 /* Bit 26 : Enable PPI channel 26. */
Kojto 104:b9ad9a133dc7 4108 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 104:b9ad9a133dc7 4109 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 104:b9ad9a133dc7 4110 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4111 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4112 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4113
Kojto 104:b9ad9a133dc7 4114 /* Bit 25 : Enable PPI channel 25. */
Kojto 104:b9ad9a133dc7 4115 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 104:b9ad9a133dc7 4116 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 104:b9ad9a133dc7 4117 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4118 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4119 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4120
Kojto 104:b9ad9a133dc7 4121 /* Bit 24 : Enable PPI channel 24. */
Kojto 104:b9ad9a133dc7 4122 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 104:b9ad9a133dc7 4123 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 104:b9ad9a133dc7 4124 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4125 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4126 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4127
Kojto 104:b9ad9a133dc7 4128 /* Bit 23 : Enable PPI channel 23. */
Kojto 104:b9ad9a133dc7 4129 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 104:b9ad9a133dc7 4130 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 104:b9ad9a133dc7 4131 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4132 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4133 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4134
Kojto 104:b9ad9a133dc7 4135 /* Bit 22 : Enable PPI channel 22. */
Kojto 104:b9ad9a133dc7 4136 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 104:b9ad9a133dc7 4137 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 104:b9ad9a133dc7 4138 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4139 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4140 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4141
Kojto 104:b9ad9a133dc7 4142 /* Bit 21 : Enable PPI channel 21. */
Kojto 104:b9ad9a133dc7 4143 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 104:b9ad9a133dc7 4144 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 104:b9ad9a133dc7 4145 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4146 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4147 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4148
Kojto 104:b9ad9a133dc7 4149 /* Bit 20 : Enable PPI channel 20. */
Kojto 104:b9ad9a133dc7 4150 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 104:b9ad9a133dc7 4151 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 104:b9ad9a133dc7 4152 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4153 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4154 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4155
Kojto 104:b9ad9a133dc7 4156 /* Bit 15 : Enable PPI channel 15. */
Kojto 104:b9ad9a133dc7 4157 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 104:b9ad9a133dc7 4158 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 104:b9ad9a133dc7 4159 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4160 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4161 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4162
Kojto 104:b9ad9a133dc7 4163 /* Bit 14 : Enable PPI channel 14. */
Kojto 104:b9ad9a133dc7 4164 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 104:b9ad9a133dc7 4165 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 104:b9ad9a133dc7 4166 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4167 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4168 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4169
Kojto 104:b9ad9a133dc7 4170 /* Bit 13 : Enable PPI channel 13. */
Kojto 104:b9ad9a133dc7 4171 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 104:b9ad9a133dc7 4172 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 104:b9ad9a133dc7 4173 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4174 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4175 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4176
Kojto 104:b9ad9a133dc7 4177 /* Bit 12 : Enable PPI channel 12. */
Kojto 104:b9ad9a133dc7 4178 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 104:b9ad9a133dc7 4179 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 104:b9ad9a133dc7 4180 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4181 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4182 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4183
Kojto 104:b9ad9a133dc7 4184 /* Bit 11 : Enable PPI channel 11. */
Kojto 104:b9ad9a133dc7 4185 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 104:b9ad9a133dc7 4186 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 104:b9ad9a133dc7 4187 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4188 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4189 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4190
Kojto 104:b9ad9a133dc7 4191 /* Bit 10 : Enable PPI channel 10. */
Kojto 104:b9ad9a133dc7 4192 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 104:b9ad9a133dc7 4193 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 104:b9ad9a133dc7 4194 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4195 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4196 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4197
Kojto 104:b9ad9a133dc7 4198 /* Bit 9 : Enable PPI channel 9. */
Kojto 104:b9ad9a133dc7 4199 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 104:b9ad9a133dc7 4200 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 104:b9ad9a133dc7 4201 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4202 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4203 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4204
Kojto 104:b9ad9a133dc7 4205 /* Bit 8 : Enable PPI channel 8. */
Kojto 104:b9ad9a133dc7 4206 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 104:b9ad9a133dc7 4207 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 104:b9ad9a133dc7 4208 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4209 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4210 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4211
Kojto 104:b9ad9a133dc7 4212 /* Bit 7 : Enable PPI channel 7. */
Kojto 104:b9ad9a133dc7 4213 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 104:b9ad9a133dc7 4214 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 104:b9ad9a133dc7 4215 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4216 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4217 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4218
Kojto 104:b9ad9a133dc7 4219 /* Bit 6 : Enable PPI channel 6. */
Kojto 104:b9ad9a133dc7 4220 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 104:b9ad9a133dc7 4221 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 104:b9ad9a133dc7 4222 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4223 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4224 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4225
Kojto 104:b9ad9a133dc7 4226 /* Bit 5 : Enable PPI channel 5. */
Kojto 104:b9ad9a133dc7 4227 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 104:b9ad9a133dc7 4228 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 104:b9ad9a133dc7 4229 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4230 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4231 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4232
Kojto 104:b9ad9a133dc7 4233 /* Bit 4 : Enable PPI channel 4. */
Kojto 104:b9ad9a133dc7 4234 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 104:b9ad9a133dc7 4235 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 104:b9ad9a133dc7 4236 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4237 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4238 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4239
Kojto 104:b9ad9a133dc7 4240 /* Bit 3 : Enable PPI channel 3. */
Kojto 104:b9ad9a133dc7 4241 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 104:b9ad9a133dc7 4242 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 104:b9ad9a133dc7 4243 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4244 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4245 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4246
Kojto 104:b9ad9a133dc7 4247 /* Bit 2 : Enable PPI channel 2. */
Kojto 104:b9ad9a133dc7 4248 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 104:b9ad9a133dc7 4249 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 104:b9ad9a133dc7 4250 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4251 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4252 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4253
Kojto 104:b9ad9a133dc7 4254 /* Bit 1 : Enable PPI channel 1. */
Kojto 104:b9ad9a133dc7 4255 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 104:b9ad9a133dc7 4256 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 104:b9ad9a133dc7 4257 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4258 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4259 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4260
Kojto 104:b9ad9a133dc7 4261 /* Bit 0 : Enable PPI channel 0. */
Kojto 104:b9ad9a133dc7 4262 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 104:b9ad9a133dc7 4263 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 104:b9ad9a133dc7 4264 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4265 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4266 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
Kojto 104:b9ad9a133dc7 4267
Kojto 104:b9ad9a133dc7 4268 /* Register: PPI_CHENCLR */
Kojto 104:b9ad9a133dc7 4269 /* Description: Channel enable clear. */
Kojto 104:b9ad9a133dc7 4270
Kojto 104:b9ad9a133dc7 4271 /* Bit 31 : Disable PPI channel 31. */
Kojto 104:b9ad9a133dc7 4272 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 104:b9ad9a133dc7 4273 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 104:b9ad9a133dc7 4274 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4275 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4276 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4277
Kojto 104:b9ad9a133dc7 4278 /* Bit 30 : Disable PPI channel 30. */
Kojto 104:b9ad9a133dc7 4279 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 104:b9ad9a133dc7 4280 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 104:b9ad9a133dc7 4281 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4282 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4283 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4284
Kojto 104:b9ad9a133dc7 4285 /* Bit 29 : Disable PPI channel 29. */
Kojto 104:b9ad9a133dc7 4286 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 104:b9ad9a133dc7 4287 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 104:b9ad9a133dc7 4288 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4289 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4290 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4291
Kojto 104:b9ad9a133dc7 4292 /* Bit 28 : Disable PPI channel 28. */
Kojto 104:b9ad9a133dc7 4293 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 104:b9ad9a133dc7 4294 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 104:b9ad9a133dc7 4295 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4296 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4297 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4298
Kojto 104:b9ad9a133dc7 4299 /* Bit 27 : Disable PPI channel 27. */
Kojto 104:b9ad9a133dc7 4300 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 104:b9ad9a133dc7 4301 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 104:b9ad9a133dc7 4302 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4303 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4304 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4305
Kojto 104:b9ad9a133dc7 4306 /* Bit 26 : Disable PPI channel 26. */
Kojto 104:b9ad9a133dc7 4307 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 104:b9ad9a133dc7 4308 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 104:b9ad9a133dc7 4309 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4310 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4311 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4312
Kojto 104:b9ad9a133dc7 4313 /* Bit 25 : Disable PPI channel 25. */
Kojto 104:b9ad9a133dc7 4314 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 104:b9ad9a133dc7 4315 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 104:b9ad9a133dc7 4316 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4317 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4318 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4319
Kojto 104:b9ad9a133dc7 4320 /* Bit 24 : Disable PPI channel 24. */
Kojto 104:b9ad9a133dc7 4321 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 104:b9ad9a133dc7 4322 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 104:b9ad9a133dc7 4323 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4324 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4325 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4326
Kojto 104:b9ad9a133dc7 4327 /* Bit 23 : Disable PPI channel 23. */
Kojto 104:b9ad9a133dc7 4328 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 104:b9ad9a133dc7 4329 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 104:b9ad9a133dc7 4330 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4331 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4332 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4333
Kojto 104:b9ad9a133dc7 4334 /* Bit 22 : Disable PPI channel 22. */
Kojto 104:b9ad9a133dc7 4335 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 104:b9ad9a133dc7 4336 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 104:b9ad9a133dc7 4337 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4338 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4339 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4340
Kojto 104:b9ad9a133dc7 4341 /* Bit 21 : Disable PPI channel 21. */
Kojto 104:b9ad9a133dc7 4342 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 104:b9ad9a133dc7 4343 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 104:b9ad9a133dc7 4344 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4345 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4346 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4347
Kojto 104:b9ad9a133dc7 4348 /* Bit 20 : Disable PPI channel 20. */
Kojto 104:b9ad9a133dc7 4349 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 104:b9ad9a133dc7 4350 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 104:b9ad9a133dc7 4351 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4352 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4353 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4354
Kojto 104:b9ad9a133dc7 4355 /* Bit 15 : Disable PPI channel 15. */
Kojto 104:b9ad9a133dc7 4356 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 104:b9ad9a133dc7 4357 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 104:b9ad9a133dc7 4358 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4359 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4360 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4361
Kojto 104:b9ad9a133dc7 4362 /* Bit 14 : Disable PPI channel 14. */
Kojto 104:b9ad9a133dc7 4363 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 104:b9ad9a133dc7 4364 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 104:b9ad9a133dc7 4365 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4366 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4367 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4368
Kojto 104:b9ad9a133dc7 4369 /* Bit 13 : Disable PPI channel 13. */
Kojto 104:b9ad9a133dc7 4370 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 104:b9ad9a133dc7 4371 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 104:b9ad9a133dc7 4372 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4373 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4374 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4375
Kojto 104:b9ad9a133dc7 4376 /* Bit 12 : Disable PPI channel 12. */
Kojto 104:b9ad9a133dc7 4377 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 104:b9ad9a133dc7 4378 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 104:b9ad9a133dc7 4379 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4380 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4381 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4382
Kojto 104:b9ad9a133dc7 4383 /* Bit 11 : Disable PPI channel 11. */
Kojto 104:b9ad9a133dc7 4384 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 104:b9ad9a133dc7 4385 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 104:b9ad9a133dc7 4386 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4387 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4388 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4389
Kojto 104:b9ad9a133dc7 4390 /* Bit 10 : Disable PPI channel 10. */
Kojto 104:b9ad9a133dc7 4391 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 104:b9ad9a133dc7 4392 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 104:b9ad9a133dc7 4393 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4394 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4395 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4396
Kojto 104:b9ad9a133dc7 4397 /* Bit 9 : Disable PPI channel 9. */
Kojto 104:b9ad9a133dc7 4398 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 104:b9ad9a133dc7 4399 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 104:b9ad9a133dc7 4400 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4401 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4402 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4403
Kojto 104:b9ad9a133dc7 4404 /* Bit 8 : Disable PPI channel 8. */
Kojto 104:b9ad9a133dc7 4405 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 104:b9ad9a133dc7 4406 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 104:b9ad9a133dc7 4407 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4408 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4409 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4410
Kojto 104:b9ad9a133dc7 4411 /* Bit 7 : Disable PPI channel 7. */
Kojto 104:b9ad9a133dc7 4412 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 104:b9ad9a133dc7 4413 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 104:b9ad9a133dc7 4414 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4415 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4416 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4417
Kojto 104:b9ad9a133dc7 4418 /* Bit 6 : Disable PPI channel 6. */
Kojto 104:b9ad9a133dc7 4419 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 104:b9ad9a133dc7 4420 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 104:b9ad9a133dc7 4421 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4422 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4423 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4424
Kojto 104:b9ad9a133dc7 4425 /* Bit 5 : Disable PPI channel 5. */
Kojto 104:b9ad9a133dc7 4426 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 104:b9ad9a133dc7 4427 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 104:b9ad9a133dc7 4428 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4429 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4430 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4431
Kojto 104:b9ad9a133dc7 4432 /* Bit 4 : Disable PPI channel 4. */
Kojto 104:b9ad9a133dc7 4433 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 104:b9ad9a133dc7 4434 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 104:b9ad9a133dc7 4435 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4436 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4437 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4438
Kojto 104:b9ad9a133dc7 4439 /* Bit 3 : Disable PPI channel 3. */
Kojto 104:b9ad9a133dc7 4440 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 104:b9ad9a133dc7 4441 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 104:b9ad9a133dc7 4442 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4443 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4444 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4445
Kojto 104:b9ad9a133dc7 4446 /* Bit 2 : Disable PPI channel 2. */
Kojto 104:b9ad9a133dc7 4447 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 104:b9ad9a133dc7 4448 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 104:b9ad9a133dc7 4449 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4450 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4451 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4452
Kojto 104:b9ad9a133dc7 4453 /* Bit 1 : Disable PPI channel 1. */
Kojto 104:b9ad9a133dc7 4454 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 104:b9ad9a133dc7 4455 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 104:b9ad9a133dc7 4456 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4457 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4458 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4459
Kojto 104:b9ad9a133dc7 4460 /* Bit 0 : Disable PPI channel 0. */
Kojto 104:b9ad9a133dc7 4461 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 104:b9ad9a133dc7 4462 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 104:b9ad9a133dc7 4463 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
Kojto 104:b9ad9a133dc7 4464 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
Kojto 104:b9ad9a133dc7 4465 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
Kojto 104:b9ad9a133dc7 4466
Kojto 104:b9ad9a133dc7 4467 /* Register: PPI_CHG */
Kojto 104:b9ad9a133dc7 4468 /* Description: Channel group configuration. */
Kojto 104:b9ad9a133dc7 4469
Kojto 104:b9ad9a133dc7 4470 /* Bit 31 : Include CH31 in channel group. */
Kojto 104:b9ad9a133dc7 4471 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 104:b9ad9a133dc7 4472 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 104:b9ad9a133dc7 4473 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4474 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4475
Kojto 104:b9ad9a133dc7 4476 /* Bit 30 : Include CH30 in channel group. */
Kojto 104:b9ad9a133dc7 4477 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 104:b9ad9a133dc7 4478 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 104:b9ad9a133dc7 4479 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4480 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4481
Kojto 104:b9ad9a133dc7 4482 /* Bit 29 : Include CH29 in channel group. */
Kojto 104:b9ad9a133dc7 4483 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 104:b9ad9a133dc7 4484 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 104:b9ad9a133dc7 4485 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4486 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4487
Kojto 104:b9ad9a133dc7 4488 /* Bit 28 : Include CH28 in channel group. */
Kojto 104:b9ad9a133dc7 4489 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 104:b9ad9a133dc7 4490 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 104:b9ad9a133dc7 4491 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4492 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4493
Kojto 104:b9ad9a133dc7 4494 /* Bit 27 : Include CH27 in channel group. */
Kojto 104:b9ad9a133dc7 4495 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 104:b9ad9a133dc7 4496 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 104:b9ad9a133dc7 4497 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4498 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4499
Kojto 104:b9ad9a133dc7 4500 /* Bit 26 : Include CH26 in channel group. */
Kojto 104:b9ad9a133dc7 4501 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 104:b9ad9a133dc7 4502 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 104:b9ad9a133dc7 4503 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4504 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4505
Kojto 104:b9ad9a133dc7 4506 /* Bit 25 : Include CH25 in channel group. */
Kojto 104:b9ad9a133dc7 4507 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 104:b9ad9a133dc7 4508 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 104:b9ad9a133dc7 4509 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4510 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4511
Kojto 104:b9ad9a133dc7 4512 /* Bit 24 : Include CH24 in channel group. */
Kojto 104:b9ad9a133dc7 4513 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 104:b9ad9a133dc7 4514 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 104:b9ad9a133dc7 4515 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4516 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4517
Kojto 104:b9ad9a133dc7 4518 /* Bit 23 : Include CH23 in channel group. */
Kojto 104:b9ad9a133dc7 4519 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 104:b9ad9a133dc7 4520 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 104:b9ad9a133dc7 4521 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4522 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4523
Kojto 104:b9ad9a133dc7 4524 /* Bit 22 : Include CH22 in channel group. */
Kojto 104:b9ad9a133dc7 4525 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 104:b9ad9a133dc7 4526 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 104:b9ad9a133dc7 4527 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4528 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4529
Kojto 104:b9ad9a133dc7 4530 /* Bit 21 : Include CH21 in channel group. */
Kojto 104:b9ad9a133dc7 4531 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 104:b9ad9a133dc7 4532 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 104:b9ad9a133dc7 4533 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4534 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4535
Kojto 104:b9ad9a133dc7 4536 /* Bit 20 : Include CH20 in channel group. */
Kojto 104:b9ad9a133dc7 4537 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 104:b9ad9a133dc7 4538 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 104:b9ad9a133dc7 4539 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4540 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4541
Kojto 104:b9ad9a133dc7 4542 /* Bit 15 : Include CH15 in channel group. */
Kojto 104:b9ad9a133dc7 4543 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 104:b9ad9a133dc7 4544 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 104:b9ad9a133dc7 4545 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4546 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4547
Kojto 104:b9ad9a133dc7 4548 /* Bit 14 : Include CH14 in channel group. */
Kojto 104:b9ad9a133dc7 4549 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 104:b9ad9a133dc7 4550 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 104:b9ad9a133dc7 4551 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4552 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4553
Kojto 104:b9ad9a133dc7 4554 /* Bit 13 : Include CH13 in channel group. */
Kojto 104:b9ad9a133dc7 4555 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 104:b9ad9a133dc7 4556 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 104:b9ad9a133dc7 4557 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4558 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4559
Kojto 104:b9ad9a133dc7 4560 /* Bit 12 : Include CH12 in channel group. */
Kojto 104:b9ad9a133dc7 4561 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 104:b9ad9a133dc7 4562 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 104:b9ad9a133dc7 4563 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4564 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4565
Kojto 104:b9ad9a133dc7 4566 /* Bit 11 : Include CH11 in channel group. */
Kojto 104:b9ad9a133dc7 4567 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 104:b9ad9a133dc7 4568 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 104:b9ad9a133dc7 4569 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4570 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4571
Kojto 104:b9ad9a133dc7 4572 /* Bit 10 : Include CH10 in channel group. */
Kojto 104:b9ad9a133dc7 4573 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 104:b9ad9a133dc7 4574 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 104:b9ad9a133dc7 4575 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4576 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4577
Kojto 104:b9ad9a133dc7 4578 /* Bit 9 : Include CH9 in channel group. */
Kojto 104:b9ad9a133dc7 4579 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 104:b9ad9a133dc7 4580 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 104:b9ad9a133dc7 4581 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4582 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4583
Kojto 104:b9ad9a133dc7 4584 /* Bit 8 : Include CH8 in channel group. */
Kojto 104:b9ad9a133dc7 4585 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 104:b9ad9a133dc7 4586 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 104:b9ad9a133dc7 4587 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4588 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4589
Kojto 104:b9ad9a133dc7 4590 /* Bit 7 : Include CH7 in channel group. */
Kojto 104:b9ad9a133dc7 4591 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 104:b9ad9a133dc7 4592 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 104:b9ad9a133dc7 4593 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4594 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4595
Kojto 104:b9ad9a133dc7 4596 /* Bit 6 : Include CH6 in channel group. */
Kojto 104:b9ad9a133dc7 4597 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 104:b9ad9a133dc7 4598 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 104:b9ad9a133dc7 4599 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4600 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4601
Kojto 104:b9ad9a133dc7 4602 /* Bit 5 : Include CH5 in channel group. */
Kojto 104:b9ad9a133dc7 4603 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 104:b9ad9a133dc7 4604 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 104:b9ad9a133dc7 4605 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4606 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4607
Kojto 104:b9ad9a133dc7 4608 /* Bit 4 : Include CH4 in channel group. */
Kojto 104:b9ad9a133dc7 4609 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 104:b9ad9a133dc7 4610 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 104:b9ad9a133dc7 4611 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4612 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4613
Kojto 104:b9ad9a133dc7 4614 /* Bit 3 : Include CH3 in channel group. */
Kojto 104:b9ad9a133dc7 4615 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 104:b9ad9a133dc7 4616 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 104:b9ad9a133dc7 4617 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4618 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4619
Kojto 104:b9ad9a133dc7 4620 /* Bit 2 : Include CH2 in channel group. */
Kojto 104:b9ad9a133dc7 4621 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 104:b9ad9a133dc7 4622 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 104:b9ad9a133dc7 4623 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4624 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4625
Kojto 104:b9ad9a133dc7 4626 /* Bit 1 : Include CH1 in channel group. */
Kojto 104:b9ad9a133dc7 4627 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 104:b9ad9a133dc7 4628 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 104:b9ad9a133dc7 4629 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4630 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4631
Kojto 104:b9ad9a133dc7 4632 /* Bit 0 : Include CH0 in channel group. */
Kojto 104:b9ad9a133dc7 4633 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 104:b9ad9a133dc7 4634 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 104:b9ad9a133dc7 4635 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
Kojto 104:b9ad9a133dc7 4636 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
Kojto 104:b9ad9a133dc7 4637
Kojto 104:b9ad9a133dc7 4638
Kojto 104:b9ad9a133dc7 4639 /* Peripheral: PU */
Kojto 104:b9ad9a133dc7 4640 /* Description: Patch unit. */
Kojto 104:b9ad9a133dc7 4641
Kojto 104:b9ad9a133dc7 4642 /* Register: PU_PATCHADDR */
Kojto 104:b9ad9a133dc7 4643 /* Description: Relative address of patch instructions. */
Kojto 104:b9ad9a133dc7 4644
Kojto 104:b9ad9a133dc7 4645 /* Bits 24..0 : Relative address of patch instructions. */
Kojto 104:b9ad9a133dc7 4646 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
Kojto 104:b9ad9a133dc7 4647 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
Kojto 104:b9ad9a133dc7 4648
Kojto 104:b9ad9a133dc7 4649 /* Register: PU_PATCHEN */
Kojto 104:b9ad9a133dc7 4650 /* Description: Patch enable register. */
Kojto 104:b9ad9a133dc7 4651
Kojto 104:b9ad9a133dc7 4652 /* Bit 7 : Patch 7 enabled. */
Kojto 104:b9ad9a133dc7 4653 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
Kojto 104:b9ad9a133dc7 4654 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
Kojto 104:b9ad9a133dc7 4655 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4656 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4657
Kojto 104:b9ad9a133dc7 4658 /* Bit 6 : Patch 6 enabled. */
Kojto 104:b9ad9a133dc7 4659 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
Kojto 104:b9ad9a133dc7 4660 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
Kojto 104:b9ad9a133dc7 4661 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4662 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4663
Kojto 104:b9ad9a133dc7 4664 /* Bit 5 : Patch 5 enabled. */
Kojto 104:b9ad9a133dc7 4665 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
Kojto 104:b9ad9a133dc7 4666 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
Kojto 104:b9ad9a133dc7 4667 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4668 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4669
Kojto 104:b9ad9a133dc7 4670 /* Bit 4 : Patch 4 enabled. */
Kojto 104:b9ad9a133dc7 4671 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
Kojto 104:b9ad9a133dc7 4672 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
Kojto 104:b9ad9a133dc7 4673 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4674 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4675
Kojto 104:b9ad9a133dc7 4676 /* Bit 3 : Patch 3 enabled. */
Kojto 104:b9ad9a133dc7 4677 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
Kojto 104:b9ad9a133dc7 4678 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
Kojto 104:b9ad9a133dc7 4679 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4680 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4681
Kojto 104:b9ad9a133dc7 4682 /* Bit 2 : Patch 2 enabled. */
Kojto 104:b9ad9a133dc7 4683 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
Kojto 104:b9ad9a133dc7 4684 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
Kojto 104:b9ad9a133dc7 4685 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4686 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4687
Kojto 104:b9ad9a133dc7 4688 /* Bit 1 : Patch 1 enabled. */
Kojto 104:b9ad9a133dc7 4689 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
Kojto 104:b9ad9a133dc7 4690 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
Kojto 104:b9ad9a133dc7 4691 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4692 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4693
Kojto 104:b9ad9a133dc7 4694 /* Bit 0 : Patch 0 enabled. */
Kojto 104:b9ad9a133dc7 4695 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
Kojto 104:b9ad9a133dc7 4696 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
Kojto 104:b9ad9a133dc7 4697 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4698 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4699
Kojto 104:b9ad9a133dc7 4700 /* Register: PU_PATCHENSET */
Kojto 104:b9ad9a133dc7 4701 /* Description: Patch enable register. */
Kojto 104:b9ad9a133dc7 4702
Kojto 104:b9ad9a133dc7 4703 /* Bit 7 : Patch 7 enabled. */
Kojto 104:b9ad9a133dc7 4704 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
Kojto 104:b9ad9a133dc7 4705 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
Kojto 104:b9ad9a133dc7 4706 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4707 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4708 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4709
Kojto 104:b9ad9a133dc7 4710 /* Bit 6 : Patch 6 enabled. */
Kojto 104:b9ad9a133dc7 4711 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
Kojto 104:b9ad9a133dc7 4712 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
Kojto 104:b9ad9a133dc7 4713 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4714 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4715 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4716
Kojto 104:b9ad9a133dc7 4717 /* Bit 5 : Patch 5 enabled. */
Kojto 104:b9ad9a133dc7 4718 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
Kojto 104:b9ad9a133dc7 4719 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
Kojto 104:b9ad9a133dc7 4720 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4721 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4722 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4723
Kojto 104:b9ad9a133dc7 4724 /* Bit 4 : Patch 4 enabled. */
Kojto 104:b9ad9a133dc7 4725 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
Kojto 104:b9ad9a133dc7 4726 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
Kojto 104:b9ad9a133dc7 4727 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4728 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4729 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4730
Kojto 104:b9ad9a133dc7 4731 /* Bit 3 : Patch 3 enabled. */
Kojto 104:b9ad9a133dc7 4732 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
Kojto 104:b9ad9a133dc7 4733 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
Kojto 104:b9ad9a133dc7 4734 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4735 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4736 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4737
Kojto 104:b9ad9a133dc7 4738 /* Bit 2 : Patch 2 enabled. */
Kojto 104:b9ad9a133dc7 4739 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
Kojto 104:b9ad9a133dc7 4740 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
Kojto 104:b9ad9a133dc7 4741 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4742 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4743 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4744
Kojto 104:b9ad9a133dc7 4745 /* Bit 1 : Patch 1 enabled. */
Kojto 104:b9ad9a133dc7 4746 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
Kojto 104:b9ad9a133dc7 4747 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
Kojto 104:b9ad9a133dc7 4748 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4749 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4750 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4751
Kojto 104:b9ad9a133dc7 4752 /* Bit 0 : Patch 0 enabled. */
Kojto 104:b9ad9a133dc7 4753 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
Kojto 104:b9ad9a133dc7 4754 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
Kojto 104:b9ad9a133dc7 4755 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4756 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4757 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
Kojto 104:b9ad9a133dc7 4758
Kojto 104:b9ad9a133dc7 4759 /* Register: PU_PATCHENCLR */
Kojto 104:b9ad9a133dc7 4760 /* Description: Patch disable register. */
Kojto 104:b9ad9a133dc7 4761
Kojto 104:b9ad9a133dc7 4762 /* Bit 7 : Patch 7 enabled. */
Kojto 104:b9ad9a133dc7 4763 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
Kojto 104:b9ad9a133dc7 4764 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
Kojto 104:b9ad9a133dc7 4765 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4766 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4767 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4768
Kojto 104:b9ad9a133dc7 4769 /* Bit 6 : Patch 6 enabled. */
Kojto 104:b9ad9a133dc7 4770 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
Kojto 104:b9ad9a133dc7 4771 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
Kojto 104:b9ad9a133dc7 4772 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4773 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4774 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4775
Kojto 104:b9ad9a133dc7 4776 /* Bit 5 : Patch 5 enabled. */
Kojto 104:b9ad9a133dc7 4777 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
Kojto 104:b9ad9a133dc7 4778 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
Kojto 104:b9ad9a133dc7 4779 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4780 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4781 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4782
Kojto 104:b9ad9a133dc7 4783 /* Bit 4 : Patch 4 enabled. */
Kojto 104:b9ad9a133dc7 4784 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
Kojto 104:b9ad9a133dc7 4785 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
Kojto 104:b9ad9a133dc7 4786 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4787 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4788 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4789
Kojto 104:b9ad9a133dc7 4790 /* Bit 3 : Patch 3 enabled. */
Kojto 104:b9ad9a133dc7 4791 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
Kojto 104:b9ad9a133dc7 4792 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
Kojto 104:b9ad9a133dc7 4793 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4794 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4795 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4796
Kojto 104:b9ad9a133dc7 4797 /* Bit 2 : Patch 2 enabled. */
Kojto 104:b9ad9a133dc7 4798 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
Kojto 104:b9ad9a133dc7 4799 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
Kojto 104:b9ad9a133dc7 4800 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4801 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4802 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4803
Kojto 104:b9ad9a133dc7 4804 /* Bit 1 : Patch 1 enabled. */
Kojto 104:b9ad9a133dc7 4805 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
Kojto 104:b9ad9a133dc7 4806 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
Kojto 104:b9ad9a133dc7 4807 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4808 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4809 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4810
Kojto 104:b9ad9a133dc7 4811 /* Bit 0 : Patch 0 enabled. */
Kojto 104:b9ad9a133dc7 4812 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
Kojto 104:b9ad9a133dc7 4813 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
Kojto 104:b9ad9a133dc7 4814 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
Kojto 104:b9ad9a133dc7 4815 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
Kojto 104:b9ad9a133dc7 4816 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
Kojto 104:b9ad9a133dc7 4817
Kojto 104:b9ad9a133dc7 4818
Kojto 104:b9ad9a133dc7 4819 /* Peripheral: QDEC */
Kojto 104:b9ad9a133dc7 4820 /* Description: Rotary decoder. */
Kojto 104:b9ad9a133dc7 4821
Kojto 104:b9ad9a133dc7 4822 /* Register: QDEC_SHORTS */
Kojto 104:b9ad9a133dc7 4823 /* Description: Shortcuts for the QDEC. */
Kojto 104:b9ad9a133dc7 4824
Kojto 104:b9ad9a133dc7 4825 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
Kojto 104:b9ad9a133dc7 4826 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
Kojto 104:b9ad9a133dc7 4827 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
Kojto 104:b9ad9a133dc7 4828 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 4829 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 4830
Kojto 104:b9ad9a133dc7 4831 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
Kojto 104:b9ad9a133dc7 4832 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
Kojto 104:b9ad9a133dc7 4833 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
Kojto 104:b9ad9a133dc7 4834 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 4835 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 4836
Kojto 104:b9ad9a133dc7 4837 /* Register: QDEC_INTENSET */
Kojto 104:b9ad9a133dc7 4838 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 4839
Kojto 104:b9ad9a133dc7 4840 /* Bit 2 : Enable interrupt on ACCOF event. */
Kojto 104:b9ad9a133dc7 4841 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
Kojto 104:b9ad9a133dc7 4842 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
Kojto 104:b9ad9a133dc7 4843 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 4844 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 4845 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 4846
Kojto 104:b9ad9a133dc7 4847 /* Bit 1 : Enable interrupt on REPORTRDY event. */
Kojto 104:b9ad9a133dc7 4848 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
Kojto 104:b9ad9a133dc7 4849 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
Kojto 104:b9ad9a133dc7 4850 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 4851 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 4852 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 4853
Kojto 104:b9ad9a133dc7 4854 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
Kojto 104:b9ad9a133dc7 4855 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
Kojto 104:b9ad9a133dc7 4856 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
Kojto 104:b9ad9a133dc7 4857 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 4858 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 4859 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 4860
Kojto 104:b9ad9a133dc7 4861 /* Register: QDEC_INTENCLR */
Kojto 104:b9ad9a133dc7 4862 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 4863
Kojto 104:b9ad9a133dc7 4864 /* Bit 2 : Disable interrupt on ACCOF event. */
Kojto 104:b9ad9a133dc7 4865 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
Kojto 104:b9ad9a133dc7 4866 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
Kojto 104:b9ad9a133dc7 4867 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 4868 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 4869 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 4870
Kojto 104:b9ad9a133dc7 4871 /* Bit 1 : Disable interrupt on REPORTRDY event. */
Kojto 104:b9ad9a133dc7 4872 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
Kojto 104:b9ad9a133dc7 4873 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
Kojto 104:b9ad9a133dc7 4874 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 4875 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 4876 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 4877
Kojto 104:b9ad9a133dc7 4878 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
Kojto 104:b9ad9a133dc7 4879 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
Kojto 104:b9ad9a133dc7 4880 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
Kojto 104:b9ad9a133dc7 4881 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 4882 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 4883 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 4884
Kojto 104:b9ad9a133dc7 4885 /* Register: QDEC_ENABLE */
Kojto 104:b9ad9a133dc7 4886 /* Description: Enable the QDEC. */
Kojto 104:b9ad9a133dc7 4887
Kojto 104:b9ad9a133dc7 4888 /* Bit 0 : Enable or disable QDEC. */
Kojto 104:b9ad9a133dc7 4889 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 4890 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 4891 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
Kojto 104:b9ad9a133dc7 4892 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
Kojto 104:b9ad9a133dc7 4893
Kojto 104:b9ad9a133dc7 4894 /* Register: QDEC_LEDPOL */
Kojto 104:b9ad9a133dc7 4895 /* Description: LED output pin polarity. */
Kojto 104:b9ad9a133dc7 4896
Kojto 104:b9ad9a133dc7 4897 /* Bit 0 : LED output pin polarity. */
Kojto 104:b9ad9a133dc7 4898 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
Kojto 104:b9ad9a133dc7 4899 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
Kojto 104:b9ad9a133dc7 4900 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
Kojto 104:b9ad9a133dc7 4901 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
Kojto 104:b9ad9a133dc7 4902
Kojto 104:b9ad9a133dc7 4903 /* Register: QDEC_SAMPLEPER */
Kojto 104:b9ad9a133dc7 4904 /* Description: Sample period. */
Kojto 104:b9ad9a133dc7 4905
Kojto 104:b9ad9a133dc7 4906 /* Bits 2..0 : Sample period. */
Kojto 104:b9ad9a133dc7 4907 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
Kojto 104:b9ad9a133dc7 4908 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
Kojto 104:b9ad9a133dc7 4909 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
Kojto 104:b9ad9a133dc7 4910 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
Kojto 104:b9ad9a133dc7 4911 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
Kojto 104:b9ad9a133dc7 4912 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
Kojto 104:b9ad9a133dc7 4913 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
Kojto 104:b9ad9a133dc7 4914 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
Kojto 104:b9ad9a133dc7 4915 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
Kojto 104:b9ad9a133dc7 4916 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
Kojto 104:b9ad9a133dc7 4917
Kojto 104:b9ad9a133dc7 4918 /* Register: QDEC_SAMPLE */
Kojto 104:b9ad9a133dc7 4919 /* Description: Motion sample value. */
Kojto 104:b9ad9a133dc7 4920
Kojto 104:b9ad9a133dc7 4921 /* Bits 31..0 : Last sample taken in compliment to 2. */
Kojto 104:b9ad9a133dc7 4922 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
Kojto 104:b9ad9a133dc7 4923 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
Kojto 104:b9ad9a133dc7 4924
Kojto 104:b9ad9a133dc7 4925 /* Register: QDEC_REPORTPER */
Kojto 104:b9ad9a133dc7 4926 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
Kojto 104:b9ad9a133dc7 4927
Kojto 104:b9ad9a133dc7 4928 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
Kojto 104:b9ad9a133dc7 4929 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
Kojto 104:b9ad9a133dc7 4930 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
Kojto 104:b9ad9a133dc7 4931 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
Kojto 104:b9ad9a133dc7 4932 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
Kojto 104:b9ad9a133dc7 4933 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
Kojto 104:b9ad9a133dc7 4934 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
Kojto 104:b9ad9a133dc7 4935 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
Kojto 104:b9ad9a133dc7 4936 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
Kojto 104:b9ad9a133dc7 4937 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
Kojto 104:b9ad9a133dc7 4938 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
Kojto 104:b9ad9a133dc7 4939
Kojto 104:b9ad9a133dc7 4940 /* Register: QDEC_DBFEN */
Kojto 104:b9ad9a133dc7 4941 /* Description: Enable debouncer input filters. */
Kojto 104:b9ad9a133dc7 4942
Kojto 104:b9ad9a133dc7 4943 /* Bit 0 : Enable debounce input filters. */
Kojto 104:b9ad9a133dc7 4944 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
Kojto 104:b9ad9a133dc7 4945 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
Kojto 104:b9ad9a133dc7 4946 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
Kojto 104:b9ad9a133dc7 4947 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
Kojto 104:b9ad9a133dc7 4948
Kojto 104:b9ad9a133dc7 4949 /* Register: QDEC_LEDPRE */
Kojto 104:b9ad9a133dc7 4950 /* Description: Time LED is switched ON before the sample. */
Kojto 104:b9ad9a133dc7 4951
Kojto 104:b9ad9a133dc7 4952 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
Kojto 104:b9ad9a133dc7 4953 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
Kojto 104:b9ad9a133dc7 4954 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
Kojto 104:b9ad9a133dc7 4955
Kojto 104:b9ad9a133dc7 4956 /* Register: QDEC_ACCDBL */
Kojto 104:b9ad9a133dc7 4957 /* Description: Accumulated double (error) transitions register. */
Kojto 104:b9ad9a133dc7 4958
Kojto 104:b9ad9a133dc7 4959 /* Bits 3..0 : Accumulated double (error) transitions. */
Kojto 104:b9ad9a133dc7 4960 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
Kojto 104:b9ad9a133dc7 4961 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
Kojto 104:b9ad9a133dc7 4962
Kojto 104:b9ad9a133dc7 4963 /* Register: QDEC_ACCDBLREAD */
Kojto 104:b9ad9a133dc7 4964 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
Kojto 104:b9ad9a133dc7 4965
Kojto 104:b9ad9a133dc7 4966 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
Kojto 104:b9ad9a133dc7 4967 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
Kojto 104:b9ad9a133dc7 4968 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
Kojto 104:b9ad9a133dc7 4969
Kojto 104:b9ad9a133dc7 4970 /* Register: QDEC_POWER */
Kojto 104:b9ad9a133dc7 4971 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 4972
Kojto 104:b9ad9a133dc7 4973 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 4974 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 4975 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 4976 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 4977 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 4978
Kojto 104:b9ad9a133dc7 4979
Kojto 104:b9ad9a133dc7 4980 /* Peripheral: RADIO */
Kojto 104:b9ad9a133dc7 4981 /* Description: The radio. */
Kojto 104:b9ad9a133dc7 4982
Kojto 104:b9ad9a133dc7 4983 /* Register: RADIO_SHORTS */
Kojto 104:b9ad9a133dc7 4984 /* Description: Shortcuts for the radio. */
Kojto 104:b9ad9a133dc7 4985
Kojto 104:b9ad9a133dc7 4986 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
Kojto 104:b9ad9a133dc7 4987 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
Kojto 104:b9ad9a133dc7 4988 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
Kojto 104:b9ad9a133dc7 4989 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 4990 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 4991
Kojto 104:b9ad9a133dc7 4992 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
Kojto 104:b9ad9a133dc7 4993 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
Kojto 104:b9ad9a133dc7 4994 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
Kojto 104:b9ad9a133dc7 4995 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 4996 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 4997
Kojto 104:b9ad9a133dc7 4998 /* Bit 5 : Shortcut between END event and START task. */
Kojto 104:b9ad9a133dc7 4999 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
Kojto 104:b9ad9a133dc7 5000 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
Kojto 104:b9ad9a133dc7 5001 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5002 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5003
Kojto 104:b9ad9a133dc7 5004 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
Kojto 104:b9ad9a133dc7 5005 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
Kojto 104:b9ad9a133dc7 5006 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
Kojto 104:b9ad9a133dc7 5007 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5008 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5009
Kojto 104:b9ad9a133dc7 5010 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
Kojto 104:b9ad9a133dc7 5011 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
Kojto 104:b9ad9a133dc7 5012 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
Kojto 104:b9ad9a133dc7 5013 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5014 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5015
Kojto 104:b9ad9a133dc7 5016 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
Kojto 104:b9ad9a133dc7 5017 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
Kojto 104:b9ad9a133dc7 5018 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
Kojto 104:b9ad9a133dc7 5019 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5020 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5021
Kojto 104:b9ad9a133dc7 5022 /* Bit 1 : Shortcut between END event and DISABLE task. */
Kojto 104:b9ad9a133dc7 5023 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
Kojto 104:b9ad9a133dc7 5024 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
Kojto 104:b9ad9a133dc7 5025 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5026 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5027
Kojto 104:b9ad9a133dc7 5028 /* Bit 0 : Shortcut between READY event and START task. */
Kojto 104:b9ad9a133dc7 5029 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
Kojto 104:b9ad9a133dc7 5030 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
Kojto 104:b9ad9a133dc7 5031 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5032 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5033
Kojto 104:b9ad9a133dc7 5034 /* Register: RADIO_INTENSET */
Kojto 104:b9ad9a133dc7 5035 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 5036
Kojto 104:b9ad9a133dc7 5037 /* Bit 10 : Enable interrupt on BCMATCH event. */
Kojto 104:b9ad9a133dc7 5038 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
Kojto 104:b9ad9a133dc7 5039 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
Kojto 104:b9ad9a133dc7 5040 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5041 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5042 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5043
Kojto 104:b9ad9a133dc7 5044 /* Bit 7 : Enable interrupt on RSSIEND event. */
Kojto 104:b9ad9a133dc7 5045 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
Kojto 104:b9ad9a133dc7 5046 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
Kojto 104:b9ad9a133dc7 5047 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5048 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5049 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5050
Kojto 104:b9ad9a133dc7 5051 /* Bit 6 : Enable interrupt on DEVMISS event. */
Kojto 104:b9ad9a133dc7 5052 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
Kojto 104:b9ad9a133dc7 5053 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
Kojto 104:b9ad9a133dc7 5054 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5055 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5056 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5057
Kojto 104:b9ad9a133dc7 5058 /* Bit 5 : Enable interrupt on DEVMATCH event. */
Kojto 104:b9ad9a133dc7 5059 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
Kojto 104:b9ad9a133dc7 5060 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
Kojto 104:b9ad9a133dc7 5061 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5062 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5063 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5064
Kojto 104:b9ad9a133dc7 5065 /* Bit 4 : Enable interrupt on DISABLED event. */
Kojto 104:b9ad9a133dc7 5066 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
Kojto 104:b9ad9a133dc7 5067 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
Kojto 104:b9ad9a133dc7 5068 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5069 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5070 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5071
Kojto 104:b9ad9a133dc7 5072 /* Bit 3 : Enable interrupt on END event. */
Kojto 104:b9ad9a133dc7 5073 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 5074 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 5075 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5076 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5077 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5078
Kojto 104:b9ad9a133dc7 5079 /* Bit 2 : Enable interrupt on PAYLOAD event. */
Kojto 104:b9ad9a133dc7 5080 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
Kojto 104:b9ad9a133dc7 5081 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
Kojto 104:b9ad9a133dc7 5082 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5083 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5084 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5085
Kojto 104:b9ad9a133dc7 5086 /* Bit 1 : Enable interrupt on ADDRESS event. */
Kojto 104:b9ad9a133dc7 5087 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
Kojto 104:b9ad9a133dc7 5088 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Kojto 104:b9ad9a133dc7 5089 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5090 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5091 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5092
Kojto 104:b9ad9a133dc7 5093 /* Bit 0 : Enable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 5094 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 5095 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 5096 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5097 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5098 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5099
Kojto 104:b9ad9a133dc7 5100 /* Register: RADIO_INTENCLR */
Kojto 104:b9ad9a133dc7 5101 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 5102
Kojto 104:b9ad9a133dc7 5103 /* Bit 10 : Disable interrupt on BCMATCH event. */
Kojto 104:b9ad9a133dc7 5104 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
Kojto 104:b9ad9a133dc7 5105 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
Kojto 104:b9ad9a133dc7 5106 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5107 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5108 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5109
Kojto 104:b9ad9a133dc7 5110 /* Bit 7 : Disable interrupt on RSSIEND event. */
Kojto 104:b9ad9a133dc7 5111 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
Kojto 104:b9ad9a133dc7 5112 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
Kojto 104:b9ad9a133dc7 5113 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5114 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5115 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5116
Kojto 104:b9ad9a133dc7 5117 /* Bit 6 : Disable interrupt on DEVMISS event. */
Kojto 104:b9ad9a133dc7 5118 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
Kojto 104:b9ad9a133dc7 5119 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
Kojto 104:b9ad9a133dc7 5120 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5121 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5122 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5123
Kojto 104:b9ad9a133dc7 5124 /* Bit 5 : Disable interrupt on DEVMATCH event. */
Kojto 104:b9ad9a133dc7 5125 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
Kojto 104:b9ad9a133dc7 5126 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
Kojto 104:b9ad9a133dc7 5127 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5128 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5129 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5130
Kojto 104:b9ad9a133dc7 5131 /* Bit 4 : Disable interrupt on DISABLED event. */
Kojto 104:b9ad9a133dc7 5132 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
Kojto 104:b9ad9a133dc7 5133 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
Kojto 104:b9ad9a133dc7 5134 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5135 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5136 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5137
Kojto 104:b9ad9a133dc7 5138 /* Bit 3 : Disable interrupt on END event. */
Kojto 104:b9ad9a133dc7 5139 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 5140 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 5141 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5142 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5143 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5144
Kojto 104:b9ad9a133dc7 5145 /* Bit 2 : Disable interrupt on PAYLOAD event. */
Kojto 104:b9ad9a133dc7 5146 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
Kojto 104:b9ad9a133dc7 5147 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
Kojto 104:b9ad9a133dc7 5148 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5149 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5150 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5151
Kojto 104:b9ad9a133dc7 5152 /* Bit 1 : Disable interrupt on ADDRESS event. */
Kojto 104:b9ad9a133dc7 5153 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
Kojto 104:b9ad9a133dc7 5154 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Kojto 104:b9ad9a133dc7 5155 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5156 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5157 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5158
Kojto 104:b9ad9a133dc7 5159 /* Bit 0 : Disable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 5160 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 5161 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 5162 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5163 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5164 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5165
Kojto 104:b9ad9a133dc7 5166 /* Register: RADIO_CRCSTATUS */
Kojto 104:b9ad9a133dc7 5167 /* Description: CRC status of received packet. */
Kojto 104:b9ad9a133dc7 5168
Kojto 104:b9ad9a133dc7 5169 /* Bit 0 : CRC status of received packet. */
Kojto 104:b9ad9a133dc7 5170 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
Kojto 104:b9ad9a133dc7 5171 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
Kojto 104:b9ad9a133dc7 5172 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
Kojto 104:b9ad9a133dc7 5173 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
Kojto 104:b9ad9a133dc7 5174
Kojto 104:b9ad9a133dc7 5175 /* Register: RADIO_CD */
Kojto 104:b9ad9a133dc7 5176 /* Description: Carrier detect. */
Kojto 104:b9ad9a133dc7 5177
Kojto 104:b9ad9a133dc7 5178 /* Bit 0 : Carrier detect. */
Kojto 104:b9ad9a133dc7 5179 #define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
Kojto 104:b9ad9a133dc7 5180 #define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
Kojto 104:b9ad9a133dc7 5181
Kojto 104:b9ad9a133dc7 5182 /* Register: RADIO_RXMATCH */
Kojto 104:b9ad9a133dc7 5183 /* Description: Received address. */
Kojto 104:b9ad9a133dc7 5184
Kojto 104:b9ad9a133dc7 5185 /* Bits 2..0 : Logical address in which previous packet was received. */
Kojto 104:b9ad9a133dc7 5186 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
Kojto 104:b9ad9a133dc7 5187 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
Kojto 104:b9ad9a133dc7 5188
Kojto 104:b9ad9a133dc7 5189 /* Register: RADIO_RXCRC */
Kojto 104:b9ad9a133dc7 5190 /* Description: Received CRC. */
Kojto 104:b9ad9a133dc7 5191
Kojto 104:b9ad9a133dc7 5192 /* Bits 23..0 : CRC field of previously received packet. */
Kojto 104:b9ad9a133dc7 5193 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
Kojto 104:b9ad9a133dc7 5194 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
Kojto 104:b9ad9a133dc7 5195
Kojto 104:b9ad9a133dc7 5196 /* Register: RADIO_DAI */
Kojto 104:b9ad9a133dc7 5197 /* Description: Device address match index. */
Kojto 104:b9ad9a133dc7 5198
Kojto 104:b9ad9a133dc7 5199 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
Kojto 104:b9ad9a133dc7 5200 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
Kojto 104:b9ad9a133dc7 5201 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
Kojto 104:b9ad9a133dc7 5202
Kojto 104:b9ad9a133dc7 5203 /* Register: RADIO_FREQUENCY */
Kojto 104:b9ad9a133dc7 5204 /* Description: Frequency. */
Kojto 104:b9ad9a133dc7 5205
Kojto 104:b9ad9a133dc7 5206 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
Kojto 104:b9ad9a133dc7 5207 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 5208 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 5209
Kojto 104:b9ad9a133dc7 5210 /* Register: RADIO_TXPOWER */
Kojto 104:b9ad9a133dc7 5211 /* Description: Output power. */
Kojto 104:b9ad9a133dc7 5212
Kojto 104:b9ad9a133dc7 5213 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
Kojto 104:b9ad9a133dc7 5214 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
Kojto 104:b9ad9a133dc7 5215 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
Kojto 104:b9ad9a133dc7 5216 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
Kojto 104:b9ad9a133dc7 5217 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
Kojto 104:b9ad9a133dc7 5218 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
Kojto 104:b9ad9a133dc7 5219 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
Kojto 104:b9ad9a133dc7 5220 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
Kojto 104:b9ad9a133dc7 5221 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
Kojto 104:b9ad9a133dc7 5222 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
Kojto 104:b9ad9a133dc7 5223 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
Kojto 104:b9ad9a133dc7 5224
Kojto 104:b9ad9a133dc7 5225 /* Register: RADIO_MODE */
Kojto 104:b9ad9a133dc7 5226 /* Description: Data rate and modulation. */
Kojto 104:b9ad9a133dc7 5227
Kojto 104:b9ad9a133dc7 5228 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
Kojto 104:b9ad9a133dc7 5229 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 104:b9ad9a133dc7 5230 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 104:b9ad9a133dc7 5231 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
Kojto 104:b9ad9a133dc7 5232 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
Kojto 104:b9ad9a133dc7 5233 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
Kojto 104:b9ad9a133dc7 5234 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
Kojto 104:b9ad9a133dc7 5235
Kojto 104:b9ad9a133dc7 5236 /* Register: RADIO_PCNF0 */
Kojto 104:b9ad9a133dc7 5237 /* Description: Packet configuration 0. */
Kojto 104:b9ad9a133dc7 5238
Kojto 104:b9ad9a133dc7 5239 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5240 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
Kojto 104:b9ad9a133dc7 5241 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
Kojto 104:b9ad9a133dc7 5242
Kojto 104:b9ad9a133dc7 5243 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5244 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
Kojto 104:b9ad9a133dc7 5245 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
Kojto 104:b9ad9a133dc7 5246
Kojto 104:b9ad9a133dc7 5247 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5248 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
Kojto 104:b9ad9a133dc7 5249 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
Kojto 104:b9ad9a133dc7 5250
Kojto 104:b9ad9a133dc7 5251 /* Register: RADIO_PCNF1 */
Kojto 104:b9ad9a133dc7 5252 /* Description: Packet configuration 1. */
Kojto 104:b9ad9a133dc7 5253
Kojto 104:b9ad9a133dc7 5254 /* Bit 25 : Packet whitening enable. */
Kojto 104:b9ad9a133dc7 5255 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
Kojto 104:b9ad9a133dc7 5256 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
Kojto 104:b9ad9a133dc7 5257 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
Kojto 104:b9ad9a133dc7 5258 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
Kojto 104:b9ad9a133dc7 5259
Kojto 104:b9ad9a133dc7 5260 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5261 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
Kojto 104:b9ad9a133dc7 5262 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
Kojto 104:b9ad9a133dc7 5263 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
Kojto 104:b9ad9a133dc7 5264 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
Kojto 104:b9ad9a133dc7 5265
Kojto 104:b9ad9a133dc7 5266 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5267 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
Kojto 104:b9ad9a133dc7 5268 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
Kojto 104:b9ad9a133dc7 5269
Kojto 104:b9ad9a133dc7 5270 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5271 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
Kojto 104:b9ad9a133dc7 5272 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
Kojto 104:b9ad9a133dc7 5273
Kojto 104:b9ad9a133dc7 5274 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
Kojto 104:b9ad9a133dc7 5275 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
Kojto 104:b9ad9a133dc7 5276 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
Kojto 104:b9ad9a133dc7 5277
Kojto 104:b9ad9a133dc7 5278 /* Register: RADIO_PREFIX0 */
Kojto 104:b9ad9a133dc7 5279 /* Description: Prefixes bytes for logical addresses 0 to 3. */
Kojto 104:b9ad9a133dc7 5280
Kojto 104:b9ad9a133dc7 5281 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5282 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
Kojto 104:b9ad9a133dc7 5283 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
Kojto 104:b9ad9a133dc7 5284
Kojto 104:b9ad9a133dc7 5285 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5286 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
Kojto 104:b9ad9a133dc7 5287 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
Kojto 104:b9ad9a133dc7 5288
Kojto 104:b9ad9a133dc7 5289 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5290 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
Kojto 104:b9ad9a133dc7 5291 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
Kojto 104:b9ad9a133dc7 5292
Kojto 104:b9ad9a133dc7 5293 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5294 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
Kojto 104:b9ad9a133dc7 5295 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
Kojto 104:b9ad9a133dc7 5296
Kojto 104:b9ad9a133dc7 5297 /* Register: RADIO_PREFIX1 */
Kojto 104:b9ad9a133dc7 5298 /* Description: Prefixes bytes for logical addresses 4 to 7. */
Kojto 104:b9ad9a133dc7 5299
Kojto 104:b9ad9a133dc7 5300 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5301 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
Kojto 104:b9ad9a133dc7 5302 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
Kojto 104:b9ad9a133dc7 5303
Kojto 104:b9ad9a133dc7 5304 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5305 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
Kojto 104:b9ad9a133dc7 5306 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
Kojto 104:b9ad9a133dc7 5307
Kojto 104:b9ad9a133dc7 5308 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5309 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
Kojto 104:b9ad9a133dc7 5310 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
Kojto 104:b9ad9a133dc7 5311
Kojto 104:b9ad9a133dc7 5312 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5313 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
Kojto 104:b9ad9a133dc7 5314 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
Kojto 104:b9ad9a133dc7 5315
Kojto 104:b9ad9a133dc7 5316 /* Register: RADIO_TXADDRESS */
Kojto 104:b9ad9a133dc7 5317 /* Description: Transmit address select. */
Kojto 104:b9ad9a133dc7 5318
Kojto 104:b9ad9a133dc7 5319 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5320 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
Kojto 104:b9ad9a133dc7 5321 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
Kojto 104:b9ad9a133dc7 5322
Kojto 104:b9ad9a133dc7 5323 /* Register: RADIO_RXADDRESSES */
Kojto 104:b9ad9a133dc7 5324 /* Description: Receive address select. */
Kojto 104:b9ad9a133dc7 5325
Kojto 104:b9ad9a133dc7 5326 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5327 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
Kojto 104:b9ad9a133dc7 5328 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
Kojto 104:b9ad9a133dc7 5329 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5330 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5331
Kojto 104:b9ad9a133dc7 5332 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5333 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
Kojto 104:b9ad9a133dc7 5334 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
Kojto 104:b9ad9a133dc7 5335 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5336 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5337
Kojto 104:b9ad9a133dc7 5338 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5339 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
Kojto 104:b9ad9a133dc7 5340 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
Kojto 104:b9ad9a133dc7 5341 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5342 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5343
Kojto 104:b9ad9a133dc7 5344 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5345 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
Kojto 104:b9ad9a133dc7 5346 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
Kojto 104:b9ad9a133dc7 5347 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5348 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5349
Kojto 104:b9ad9a133dc7 5350 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5351 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
Kojto 104:b9ad9a133dc7 5352 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
Kojto 104:b9ad9a133dc7 5353 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5354 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5355
Kojto 104:b9ad9a133dc7 5356 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5357 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
Kojto 104:b9ad9a133dc7 5358 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
Kojto 104:b9ad9a133dc7 5359 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5360 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5361
Kojto 104:b9ad9a133dc7 5362 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5363 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
Kojto 104:b9ad9a133dc7 5364 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
Kojto 104:b9ad9a133dc7 5365 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5366 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5367
Kojto 104:b9ad9a133dc7 5368 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5369 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
Kojto 104:b9ad9a133dc7 5370 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
Kojto 104:b9ad9a133dc7 5371 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
Kojto 104:b9ad9a133dc7 5372 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
Kojto 104:b9ad9a133dc7 5373
Kojto 104:b9ad9a133dc7 5374 /* Register: RADIO_CRCCNF */
Kojto 104:b9ad9a133dc7 5375 /* Description: CRC configuration. */
Kojto 104:b9ad9a133dc7 5376
Kojto 104:b9ad9a133dc7 5377 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5378 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
Kojto 104:b9ad9a133dc7 5379 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
Kojto 104:b9ad9a133dc7 5380 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
Kojto 104:b9ad9a133dc7 5381 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
Kojto 104:b9ad9a133dc7 5382
Kojto 104:b9ad9a133dc7 5383 /* Bits 1..0 : CRC length. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5384 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
Kojto 104:b9ad9a133dc7 5385 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
Kojto 104:b9ad9a133dc7 5386 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
Kojto 104:b9ad9a133dc7 5387 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
Kojto 104:b9ad9a133dc7 5388 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
Kojto 104:b9ad9a133dc7 5389 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
Kojto 104:b9ad9a133dc7 5390
Kojto 104:b9ad9a133dc7 5391 /* Register: RADIO_CRCPOLY */
Kojto 104:b9ad9a133dc7 5392 /* Description: CRC polynomial. */
Kojto 104:b9ad9a133dc7 5393
Kojto 104:b9ad9a133dc7 5394 /* Bits 23..0 : CRC polynomial. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5395 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
Kojto 104:b9ad9a133dc7 5396 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
Kojto 104:b9ad9a133dc7 5397
Kojto 104:b9ad9a133dc7 5398 /* Register: RADIO_CRCINIT */
Kojto 104:b9ad9a133dc7 5399 /* Description: CRC initial value. */
Kojto 104:b9ad9a133dc7 5400
Kojto 104:b9ad9a133dc7 5401 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
Kojto 104:b9ad9a133dc7 5402 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
Kojto 104:b9ad9a133dc7 5403 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
Kojto 104:b9ad9a133dc7 5404
Kojto 104:b9ad9a133dc7 5405 /* Register: RADIO_TEST */
Kojto 104:b9ad9a133dc7 5406 /* Description: Test features enable register. */
Kojto 104:b9ad9a133dc7 5407
Kojto 104:b9ad9a133dc7 5408 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto 104:b9ad9a133dc7 5409 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
Kojto 104:b9ad9a133dc7 5410 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
Kojto 104:b9ad9a133dc7 5411 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
Kojto 104:b9ad9a133dc7 5412 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
Kojto 104:b9ad9a133dc7 5413
Kojto 104:b9ad9a133dc7 5414 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto 104:b9ad9a133dc7 5415 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
Kojto 104:b9ad9a133dc7 5416 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
Kojto 104:b9ad9a133dc7 5417 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
Kojto 104:b9ad9a133dc7 5418 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
Kojto 104:b9ad9a133dc7 5419
Kojto 104:b9ad9a133dc7 5420 /* Register: RADIO_TIFS */
Kojto 104:b9ad9a133dc7 5421 /* Description: Inter Frame Spacing in microseconds. */
Kojto 104:b9ad9a133dc7 5422
Kojto 104:b9ad9a133dc7 5423 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
Kojto 104:b9ad9a133dc7 5424 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
Kojto 104:b9ad9a133dc7 5425 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
Kojto 104:b9ad9a133dc7 5426
Kojto 104:b9ad9a133dc7 5427 /* Register: RADIO_RSSISAMPLE */
Kojto 104:b9ad9a133dc7 5428 /* Description: RSSI sample. */
Kojto 104:b9ad9a133dc7 5429
Kojto 104:b9ad9a133dc7 5430 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
Kojto 104:b9ad9a133dc7 5431 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
Kojto 104:b9ad9a133dc7 5432 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
Kojto 104:b9ad9a133dc7 5433
Kojto 104:b9ad9a133dc7 5434 /* Register: RADIO_STATE */
Kojto 104:b9ad9a133dc7 5435 /* Description: Current radio state. */
Kojto 104:b9ad9a133dc7 5436
Kojto 104:b9ad9a133dc7 5437 /* Bits 3..0 : Current radio state. */
Kojto 104:b9ad9a133dc7 5438 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
Kojto 104:b9ad9a133dc7 5439 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
Kojto 104:b9ad9a133dc7 5440 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
Kojto 104:b9ad9a133dc7 5441 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
Kojto 104:b9ad9a133dc7 5442 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
Kojto 104:b9ad9a133dc7 5443 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
Kojto 104:b9ad9a133dc7 5444 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
Kojto 104:b9ad9a133dc7 5445 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
Kojto 104:b9ad9a133dc7 5446 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
Kojto 104:b9ad9a133dc7 5447 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
Kojto 104:b9ad9a133dc7 5448 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
Kojto 104:b9ad9a133dc7 5449
Kojto 104:b9ad9a133dc7 5450 /* Register: RADIO_DATAWHITEIV */
Kojto 104:b9ad9a133dc7 5451 /* Description: Data whitening initial value. */
Kojto 104:b9ad9a133dc7 5452
Kojto 104:b9ad9a133dc7 5453 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
Kojto 104:b9ad9a133dc7 5454 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
Kojto 104:b9ad9a133dc7 5455 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
Kojto 104:b9ad9a133dc7 5456
Kojto 104:b9ad9a133dc7 5457 /* Register: RADIO_DAP */
Kojto 104:b9ad9a133dc7 5458 /* Description: Device address prefix. */
Kojto 104:b9ad9a133dc7 5459
Kojto 104:b9ad9a133dc7 5460 /* Bits 15..0 : Device address prefix. */
Kojto 104:b9ad9a133dc7 5461 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
Kojto 104:b9ad9a133dc7 5462 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
Kojto 104:b9ad9a133dc7 5463
Kojto 104:b9ad9a133dc7 5464 /* Register: RADIO_DACNF */
Kojto 104:b9ad9a133dc7 5465 /* Description: Device address match configuration. */
Kojto 104:b9ad9a133dc7 5466
Kojto 104:b9ad9a133dc7 5467 /* Bit 15 : TxAdd for device address 7. */
Kojto 104:b9ad9a133dc7 5468 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
Kojto 104:b9ad9a133dc7 5469 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
Kojto 104:b9ad9a133dc7 5470
Kojto 104:b9ad9a133dc7 5471 /* Bit 14 : TxAdd for device address 6. */
Kojto 104:b9ad9a133dc7 5472 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
Kojto 104:b9ad9a133dc7 5473 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
Kojto 104:b9ad9a133dc7 5474
Kojto 104:b9ad9a133dc7 5475 /* Bit 13 : TxAdd for device address 5. */
Kojto 104:b9ad9a133dc7 5476 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
Kojto 104:b9ad9a133dc7 5477 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
Kojto 104:b9ad9a133dc7 5478
Kojto 104:b9ad9a133dc7 5479 /* Bit 12 : TxAdd for device address 4. */
Kojto 104:b9ad9a133dc7 5480 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
Kojto 104:b9ad9a133dc7 5481 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
Kojto 104:b9ad9a133dc7 5482
Kojto 104:b9ad9a133dc7 5483 /* Bit 11 : TxAdd for device address 3. */
Kojto 104:b9ad9a133dc7 5484 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
Kojto 104:b9ad9a133dc7 5485 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
Kojto 104:b9ad9a133dc7 5486
Kojto 104:b9ad9a133dc7 5487 /* Bit 10 : TxAdd for device address 2. */
Kojto 104:b9ad9a133dc7 5488 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
Kojto 104:b9ad9a133dc7 5489 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
Kojto 104:b9ad9a133dc7 5490
Kojto 104:b9ad9a133dc7 5491 /* Bit 9 : TxAdd for device address 1. */
Kojto 104:b9ad9a133dc7 5492 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
Kojto 104:b9ad9a133dc7 5493 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
Kojto 104:b9ad9a133dc7 5494
Kojto 104:b9ad9a133dc7 5495 /* Bit 8 : TxAdd for device address 0. */
Kojto 104:b9ad9a133dc7 5496 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
Kojto 104:b9ad9a133dc7 5497 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
Kojto 104:b9ad9a133dc7 5498
Kojto 104:b9ad9a133dc7 5499 /* Bit 7 : Enable or disable device address matching using device address 7. */
Kojto 104:b9ad9a133dc7 5500 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
Kojto 104:b9ad9a133dc7 5501 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
Kojto 104:b9ad9a133dc7 5502 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5503 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5504
Kojto 104:b9ad9a133dc7 5505 /* Bit 6 : Enable or disable device address matching using device address 6. */
Kojto 104:b9ad9a133dc7 5506 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
Kojto 104:b9ad9a133dc7 5507 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
Kojto 104:b9ad9a133dc7 5508 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5509 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5510
Kojto 104:b9ad9a133dc7 5511 /* Bit 5 : Enable or disable device address matching using device address 5. */
Kojto 104:b9ad9a133dc7 5512 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
Kojto 104:b9ad9a133dc7 5513 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
Kojto 104:b9ad9a133dc7 5514 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5515 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5516
Kojto 104:b9ad9a133dc7 5517 /* Bit 4 : Enable or disable device address matching using device address 4. */
Kojto 104:b9ad9a133dc7 5518 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
Kojto 104:b9ad9a133dc7 5519 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
Kojto 104:b9ad9a133dc7 5520 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5521 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5522
Kojto 104:b9ad9a133dc7 5523 /* Bit 3 : Enable or disable device address matching using device address 3. */
Kojto 104:b9ad9a133dc7 5524 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
Kojto 104:b9ad9a133dc7 5525 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
Kojto 104:b9ad9a133dc7 5526 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5527 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5528
Kojto 104:b9ad9a133dc7 5529 /* Bit 2 : Enable or disable device address matching using device address 2. */
Kojto 104:b9ad9a133dc7 5530 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
Kojto 104:b9ad9a133dc7 5531 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
Kojto 104:b9ad9a133dc7 5532 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5533 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5534
Kojto 104:b9ad9a133dc7 5535 /* Bit 1 : Enable or disable device address matching using device address 1. */
Kojto 104:b9ad9a133dc7 5536 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
Kojto 104:b9ad9a133dc7 5537 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
Kojto 104:b9ad9a133dc7 5538 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5539 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5540
Kojto 104:b9ad9a133dc7 5541 /* Bit 0 : Enable or disable device address matching using device address 0. */
Kojto 104:b9ad9a133dc7 5542 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
Kojto 104:b9ad9a133dc7 5543 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
Kojto 104:b9ad9a133dc7 5544 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 5545 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 5546
Kojto 104:b9ad9a133dc7 5547 /* Register: RADIO_OVERRIDE0 */
Kojto 104:b9ad9a133dc7 5548 /* Description: Trim value override register 0. */
Kojto 104:b9ad9a133dc7 5549
Kojto 104:b9ad9a133dc7 5550 /* Bits 31..0 : Trim value override 0. */
Kojto 104:b9ad9a133dc7 5551 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
Kojto 104:b9ad9a133dc7 5552 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
Kojto 104:b9ad9a133dc7 5553
Kojto 104:b9ad9a133dc7 5554 /* Register: RADIO_OVERRIDE1 */
Kojto 104:b9ad9a133dc7 5555 /* Description: Trim value override register 1. */
Kojto 104:b9ad9a133dc7 5556
Kojto 104:b9ad9a133dc7 5557 /* Bits 31..0 : Trim value override 1. */
Kojto 104:b9ad9a133dc7 5558 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
Kojto 104:b9ad9a133dc7 5559 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
Kojto 104:b9ad9a133dc7 5560
Kojto 104:b9ad9a133dc7 5561 /* Register: RADIO_OVERRIDE2 */
Kojto 104:b9ad9a133dc7 5562 /* Description: Trim value override register 2. */
Kojto 104:b9ad9a133dc7 5563
Kojto 104:b9ad9a133dc7 5564 /* Bits 31..0 : Trim value override 2. */
Kojto 104:b9ad9a133dc7 5565 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
Kojto 104:b9ad9a133dc7 5566 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
Kojto 104:b9ad9a133dc7 5567
Kojto 104:b9ad9a133dc7 5568 /* Register: RADIO_OVERRIDE3 */
Kojto 104:b9ad9a133dc7 5569 /* Description: Trim value override register 3. */
Kojto 104:b9ad9a133dc7 5570
Kojto 104:b9ad9a133dc7 5571 /* Bits 31..0 : Trim value override 3. */
Kojto 104:b9ad9a133dc7 5572 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
Kojto 104:b9ad9a133dc7 5573 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
Kojto 104:b9ad9a133dc7 5574
Kojto 104:b9ad9a133dc7 5575 /* Register: RADIO_OVERRIDE4 */
Kojto 104:b9ad9a133dc7 5576 /* Description: Trim value override register 4. */
Kojto 104:b9ad9a133dc7 5577
Kojto 104:b9ad9a133dc7 5578 /* Bit 31 : Enable or disable override of default trim values. */
Kojto 104:b9ad9a133dc7 5579 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 5580 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 5581 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
Kojto 104:b9ad9a133dc7 5582 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
Kojto 104:b9ad9a133dc7 5583
Kojto 104:b9ad9a133dc7 5584 /* Bits 27..0 : Trim value override 4. */
Kojto 104:b9ad9a133dc7 5585 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
Kojto 104:b9ad9a133dc7 5586 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
Kojto 104:b9ad9a133dc7 5587
Kojto 104:b9ad9a133dc7 5588 /* Register: RADIO_POWER */
Kojto 104:b9ad9a133dc7 5589 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 5590
Kojto 104:b9ad9a133dc7 5591 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 5592 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 5593 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 5594 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 5595 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 5596
Kojto 104:b9ad9a133dc7 5597
Kojto 104:b9ad9a133dc7 5598 /* Peripheral: RNG */
Kojto 104:b9ad9a133dc7 5599 /* Description: Random Number Generator. */
Kojto 104:b9ad9a133dc7 5600
Kojto 104:b9ad9a133dc7 5601 /* Register: RNG_SHORTS */
Kojto 104:b9ad9a133dc7 5602 /* Description: Shortcuts for the RNG. */
Kojto 104:b9ad9a133dc7 5603
Kojto 104:b9ad9a133dc7 5604 /* Bit 0 : Shortcut between VALRDY event and STOP task. */
Kojto 104:b9ad9a133dc7 5605 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
Kojto 104:b9ad9a133dc7 5606 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
Kojto 104:b9ad9a133dc7 5607 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 5608 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 5609
Kojto 104:b9ad9a133dc7 5610 /* Register: RNG_INTENSET */
Kojto 104:b9ad9a133dc7 5611 /* Description: Interrupt enable set register */
Kojto 104:b9ad9a133dc7 5612
Kojto 104:b9ad9a133dc7 5613 /* Bit 0 : Enable interrupt on VALRDY event. */
Kojto 104:b9ad9a133dc7 5614 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
Kojto 104:b9ad9a133dc7 5615 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
Kojto 104:b9ad9a133dc7 5616 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5617 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5618 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5619
Kojto 104:b9ad9a133dc7 5620 /* Register: RNG_INTENCLR */
Kojto 104:b9ad9a133dc7 5621 /* Description: Interrupt enable clear register */
Kojto 104:b9ad9a133dc7 5622
Kojto 104:b9ad9a133dc7 5623 /* Bit 0 : Disable interrupt on VALRDY event. */
Kojto 104:b9ad9a133dc7 5624 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
Kojto 104:b9ad9a133dc7 5625 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
Kojto 104:b9ad9a133dc7 5626 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5627 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5628 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5629
Kojto 104:b9ad9a133dc7 5630 /* Register: RNG_CONFIG */
Kojto 104:b9ad9a133dc7 5631 /* Description: Configuration register. */
Kojto 104:b9ad9a133dc7 5632
Kojto 104:b9ad9a133dc7 5633 /* Bit 0 : Digital error correction enable. */
Kojto 104:b9ad9a133dc7 5634 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
Kojto 104:b9ad9a133dc7 5635 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
Kojto 104:b9ad9a133dc7 5636 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
Kojto 104:b9ad9a133dc7 5637 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
Kojto 104:b9ad9a133dc7 5638
Kojto 104:b9ad9a133dc7 5639 /* Register: RNG_VALUE */
Kojto 104:b9ad9a133dc7 5640 /* Description: RNG random number. */
Kojto 104:b9ad9a133dc7 5641
Kojto 104:b9ad9a133dc7 5642 /* Bits 7..0 : Generated random number. */
Kojto 104:b9ad9a133dc7 5643 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
Kojto 104:b9ad9a133dc7 5644 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
Kojto 104:b9ad9a133dc7 5645
Kojto 104:b9ad9a133dc7 5646 /* Register: RNG_POWER */
Kojto 104:b9ad9a133dc7 5647 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 5648
Kojto 104:b9ad9a133dc7 5649 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 5650 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 5651 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 5652 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 5653 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 5654
Kojto 104:b9ad9a133dc7 5655
Kojto 104:b9ad9a133dc7 5656 /* Peripheral: RTC */
Kojto 104:b9ad9a133dc7 5657 /* Description: Real time counter 0. */
Kojto 104:b9ad9a133dc7 5658
Kojto 104:b9ad9a133dc7 5659 /* Register: RTC_INTENSET */
Kojto 104:b9ad9a133dc7 5660 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 5661
Kojto 104:b9ad9a133dc7 5662 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
Kojto 104:b9ad9a133dc7 5663 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5664 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5665 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5666 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5667 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5668
Kojto 104:b9ad9a133dc7 5669 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
Kojto 104:b9ad9a133dc7 5670 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5671 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5672 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5673 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5674 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5675
Kojto 104:b9ad9a133dc7 5676 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
Kojto 104:b9ad9a133dc7 5677 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5678 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5679 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5680 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5681 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5682
Kojto 104:b9ad9a133dc7 5683 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
Kojto 104:b9ad9a133dc7 5684 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5685 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5686 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5687 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5688 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5689
Kojto 104:b9ad9a133dc7 5690 /* Bit 1 : Enable interrupt on OVRFLW event. */
Kojto 104:b9ad9a133dc7 5691 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5692 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5693 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5694 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5695 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5696
Kojto 104:b9ad9a133dc7 5697 /* Bit 0 : Enable interrupt on TICK event. */
Kojto 104:b9ad9a133dc7 5698 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 104:b9ad9a133dc7 5699 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 104:b9ad9a133dc7 5700 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5701 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5702 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5703
Kojto 104:b9ad9a133dc7 5704 /* Register: RTC_INTENCLR */
Kojto 104:b9ad9a133dc7 5705 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 5706
Kojto 104:b9ad9a133dc7 5707 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
Kojto 104:b9ad9a133dc7 5708 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5709 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5710 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5711 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5712 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5713
Kojto 104:b9ad9a133dc7 5714 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
Kojto 104:b9ad9a133dc7 5715 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5716 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5717 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5718 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5719 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5720
Kojto 104:b9ad9a133dc7 5721 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
Kojto 104:b9ad9a133dc7 5722 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5723 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5724 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5725 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5726 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5727
Kojto 104:b9ad9a133dc7 5728 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
Kojto 104:b9ad9a133dc7 5729 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5730 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5731 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5732 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5733 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5734
Kojto 104:b9ad9a133dc7 5735 /* Bit 1 : Disable interrupt on OVRFLW event. */
Kojto 104:b9ad9a133dc7 5736 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5737 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5738 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5739 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5740 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5741
Kojto 104:b9ad9a133dc7 5742 /* Bit 0 : Disable interrupt on TICK event. */
Kojto 104:b9ad9a133dc7 5743 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 104:b9ad9a133dc7 5744 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 104:b9ad9a133dc7 5745 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5746 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5747 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5748
Kojto 104:b9ad9a133dc7 5749 /* Register: RTC_EVTEN */
Kojto 104:b9ad9a133dc7 5750 /* Description: Configures event enable routing to PPI for each RTC event. */
Kojto 104:b9ad9a133dc7 5751
Kojto 104:b9ad9a133dc7 5752 /* Bit 19 : COMPARE[3] event enable. */
Kojto 104:b9ad9a133dc7 5753 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5754 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5755 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5756 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5757
Kojto 104:b9ad9a133dc7 5758 /* Bit 18 : COMPARE[2] event enable. */
Kojto 104:b9ad9a133dc7 5759 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5760 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5761 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5762 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5763
Kojto 104:b9ad9a133dc7 5764 /* Bit 17 : COMPARE[1] event enable. */
Kojto 104:b9ad9a133dc7 5765 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5766 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5767 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5768 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5769
Kojto 104:b9ad9a133dc7 5770 /* Bit 16 : COMPARE[0] event enable. */
Kojto 104:b9ad9a133dc7 5771 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5772 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5773 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5774 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5775
Kojto 104:b9ad9a133dc7 5776 /* Bit 1 : OVRFLW event enable. */
Kojto 104:b9ad9a133dc7 5777 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5778 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5779 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5780 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5781
Kojto 104:b9ad9a133dc7 5782 /* Bit 0 : TICK event enable. */
Kojto 104:b9ad9a133dc7 5783 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 104:b9ad9a133dc7 5784 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 104:b9ad9a133dc7 5785 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5786 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5787
Kojto 104:b9ad9a133dc7 5788 /* Register: RTC_EVTENSET */
Kojto 104:b9ad9a133dc7 5789 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto 104:b9ad9a133dc7 5790
Kojto 104:b9ad9a133dc7 5791 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
Kojto 104:b9ad9a133dc7 5792 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5793 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5794 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5795 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5796 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
Kojto 104:b9ad9a133dc7 5797
Kojto 104:b9ad9a133dc7 5798 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
Kojto 104:b9ad9a133dc7 5799 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5800 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5801 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5802 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5803 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
Kojto 104:b9ad9a133dc7 5804
Kojto 104:b9ad9a133dc7 5805 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
Kojto 104:b9ad9a133dc7 5806 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5807 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5808 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5809 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5810 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
Kojto 104:b9ad9a133dc7 5811
Kojto 104:b9ad9a133dc7 5812 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
Kojto 104:b9ad9a133dc7 5813 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5814 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5815 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5816 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5817 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
Kojto 104:b9ad9a133dc7 5818
Kojto 104:b9ad9a133dc7 5819 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
Kojto 104:b9ad9a133dc7 5820 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5821 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5822 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5823 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5824 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
Kojto 104:b9ad9a133dc7 5825
Kojto 104:b9ad9a133dc7 5826 /* Bit 0 : Enable routing to PPI of TICK event. */
Kojto 104:b9ad9a133dc7 5827 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 104:b9ad9a133dc7 5828 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 104:b9ad9a133dc7 5829 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5830 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5831 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
Kojto 104:b9ad9a133dc7 5832
Kojto 104:b9ad9a133dc7 5833 /* Register: RTC_EVTENCLR */
Kojto 104:b9ad9a133dc7 5834 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto 104:b9ad9a133dc7 5835
Kojto 104:b9ad9a133dc7 5836 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
Kojto 104:b9ad9a133dc7 5837 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5838 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 5839 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5840 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5841 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
Kojto 104:b9ad9a133dc7 5842
Kojto 104:b9ad9a133dc7 5843 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
Kojto 104:b9ad9a133dc7 5844 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5845 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 5846 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5847 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5848 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
Kojto 104:b9ad9a133dc7 5849
Kojto 104:b9ad9a133dc7 5850 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
Kojto 104:b9ad9a133dc7 5851 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5852 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 5853 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5854 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5855 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
Kojto 104:b9ad9a133dc7 5856
Kojto 104:b9ad9a133dc7 5857 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
Kojto 104:b9ad9a133dc7 5858 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5859 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 5860 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5861 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5862 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
Kojto 104:b9ad9a133dc7 5863
Kojto 104:b9ad9a133dc7 5864 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
Kojto 104:b9ad9a133dc7 5865 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5866 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 104:b9ad9a133dc7 5867 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5868 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5869 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
Kojto 104:b9ad9a133dc7 5870
Kojto 104:b9ad9a133dc7 5871 /* Bit 0 : Disable routing to PPI of TICK event. */
Kojto 104:b9ad9a133dc7 5872 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 104:b9ad9a133dc7 5873 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 104:b9ad9a133dc7 5874 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
Kojto 104:b9ad9a133dc7 5875 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
Kojto 104:b9ad9a133dc7 5876 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
Kojto 104:b9ad9a133dc7 5877
Kojto 104:b9ad9a133dc7 5878 /* Register: RTC_COUNTER */
Kojto 104:b9ad9a133dc7 5879 /* Description: Current COUNTER value. */
Kojto 104:b9ad9a133dc7 5880
Kojto 104:b9ad9a133dc7 5881 /* Bits 23..0 : Counter value. */
Kojto 104:b9ad9a133dc7 5882 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
Kojto 104:b9ad9a133dc7 5883 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
Kojto 104:b9ad9a133dc7 5884
Kojto 104:b9ad9a133dc7 5885 /* Register: RTC_PRESCALER */
Kojto 104:b9ad9a133dc7 5886 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
Kojto 104:b9ad9a133dc7 5887
Kojto 104:b9ad9a133dc7 5888 /* Bits 11..0 : RTC PRESCALER value. */
Kojto 104:b9ad9a133dc7 5889 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Kojto 104:b9ad9a133dc7 5890 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Kojto 104:b9ad9a133dc7 5891
Kojto 104:b9ad9a133dc7 5892 /* Register: RTC_CC */
Kojto 104:b9ad9a133dc7 5893 /* Description: Capture/compare registers. */
Kojto 104:b9ad9a133dc7 5894
Kojto 104:b9ad9a133dc7 5895 /* Bits 23..0 : Compare value. */
Kojto 104:b9ad9a133dc7 5896 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
Kojto 104:b9ad9a133dc7 5897 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
Kojto 104:b9ad9a133dc7 5898
Kojto 104:b9ad9a133dc7 5899 /* Register: RTC_POWER */
Kojto 104:b9ad9a133dc7 5900 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 5901
Kojto 104:b9ad9a133dc7 5902 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 5903 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 5904 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 5905 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 5906 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 5907
Kojto 104:b9ad9a133dc7 5908
Kojto 104:b9ad9a133dc7 5909 /* Peripheral: SPI */
Kojto 104:b9ad9a133dc7 5910 /* Description: SPI master 0. */
Kojto 104:b9ad9a133dc7 5911
Kojto 104:b9ad9a133dc7 5912 /* Register: SPI_INTENSET */
Kojto 104:b9ad9a133dc7 5913 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 5914
Kojto 104:b9ad9a133dc7 5915 /* Bit 2 : Enable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 5916 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 5917 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 5918 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5919 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5920 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 5921
Kojto 104:b9ad9a133dc7 5922 /* Register: SPI_INTENCLR */
Kojto 104:b9ad9a133dc7 5923 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 5924
Kojto 104:b9ad9a133dc7 5925 /* Bit 2 : Disable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 5926 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
Kojto 104:b9ad9a133dc7 5927 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 104:b9ad9a133dc7 5928 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 5929 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 5930 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 5931
Kojto 104:b9ad9a133dc7 5932 /* Register: SPI_ENABLE */
Kojto 104:b9ad9a133dc7 5933 /* Description: Enable SPI. */
Kojto 104:b9ad9a133dc7 5934
Kojto 104:b9ad9a133dc7 5935 /* Bits 2..0 : Enable or disable SPI. */
Kojto 104:b9ad9a133dc7 5936 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 5937 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 5938 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
Kojto 104:b9ad9a133dc7 5939 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
Kojto 104:b9ad9a133dc7 5940
Kojto 104:b9ad9a133dc7 5941 /* Register: SPI_RXD */
Kojto 104:b9ad9a133dc7 5942 /* Description: RX data. */
Kojto 104:b9ad9a133dc7 5943
Kojto 104:b9ad9a133dc7 5944 /* Bits 7..0 : RX data from last transfer. */
Kojto 104:b9ad9a133dc7 5945 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 104:b9ad9a133dc7 5946 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 104:b9ad9a133dc7 5947
Kojto 104:b9ad9a133dc7 5948 /* Register: SPI_TXD */
Kojto 104:b9ad9a133dc7 5949 /* Description: TX data. */
Kojto 104:b9ad9a133dc7 5950
Kojto 104:b9ad9a133dc7 5951 /* Bits 7..0 : TX data for next transfer. */
Kojto 104:b9ad9a133dc7 5952 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 104:b9ad9a133dc7 5953 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 104:b9ad9a133dc7 5954
Kojto 104:b9ad9a133dc7 5955 /* Register: SPI_FREQUENCY */
Kojto 104:b9ad9a133dc7 5956 /* Description: SPI frequency */
Kojto 104:b9ad9a133dc7 5957
Kojto 104:b9ad9a133dc7 5958 /* Bits 31..0 : SPI data rate. */
Kojto 104:b9ad9a133dc7 5959 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 5960 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 5961 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
Kojto 104:b9ad9a133dc7 5962 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
Kojto 104:b9ad9a133dc7 5963 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
Kojto 104:b9ad9a133dc7 5964 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
Kojto 104:b9ad9a133dc7 5965 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
Kojto 104:b9ad9a133dc7 5966 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
Kojto 104:b9ad9a133dc7 5967 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
Kojto 104:b9ad9a133dc7 5968
Kojto 104:b9ad9a133dc7 5969 /* Register: SPI_CONFIG */
Kojto 104:b9ad9a133dc7 5970 /* Description: Configuration register. */
Kojto 104:b9ad9a133dc7 5971
Kojto 104:b9ad9a133dc7 5972 /* Bit 2 : Serial clock (SCK) polarity. */
Kojto 104:b9ad9a133dc7 5973 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Kojto 104:b9ad9a133dc7 5974 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Kojto 104:b9ad9a133dc7 5975 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
Kojto 104:b9ad9a133dc7 5976 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
Kojto 104:b9ad9a133dc7 5977
Kojto 104:b9ad9a133dc7 5978 /* Bit 1 : Serial clock (SCK) phase. */
Kojto 104:b9ad9a133dc7 5979 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Kojto 104:b9ad9a133dc7 5980 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Kojto 104:b9ad9a133dc7 5981 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
Kojto 104:b9ad9a133dc7 5982 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
Kojto 104:b9ad9a133dc7 5983
Kojto 104:b9ad9a133dc7 5984 /* Bit 0 : Bit order. */
Kojto 104:b9ad9a133dc7 5985 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Kojto 104:b9ad9a133dc7 5986 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Kojto 104:b9ad9a133dc7 5987 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
Kojto 104:b9ad9a133dc7 5988 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
Kojto 104:b9ad9a133dc7 5989
Kojto 104:b9ad9a133dc7 5990 /* Register: SPI_POWER */
Kojto 104:b9ad9a133dc7 5991 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 5992
Kojto 104:b9ad9a133dc7 5993 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 5994 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 5995 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 5996 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 5997 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 5998
Kojto 104:b9ad9a133dc7 5999
Kojto 104:b9ad9a133dc7 6000 /* Peripheral: SPIM */
Kojto 104:b9ad9a133dc7 6001 /* Description: SPI master with easyDMA 1. */
Kojto 104:b9ad9a133dc7 6002
Kojto 104:b9ad9a133dc7 6003 /* Register: SPIM_SHORTS */
Kojto 104:b9ad9a133dc7 6004 /* Description: Shortcuts for SPIM. */
Kojto 104:b9ad9a133dc7 6005
Kojto 104:b9ad9a133dc7 6006 /* Bit 17 : Shortcut between END event and START task. */
Kojto 104:b9ad9a133dc7 6007 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
Kojto 104:b9ad9a133dc7 6008 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
Kojto 104:b9ad9a133dc7 6009 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6010 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6011
Kojto 104:b9ad9a133dc7 6012 /* Register: SPIM_INTENSET */
Kojto 104:b9ad9a133dc7 6013 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6014
Kojto 104:b9ad9a133dc7 6015 /* Bit 19 : Enable interrupt on STARTED event. */
Kojto 104:b9ad9a133dc7 6016 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
Kojto 104:b9ad9a133dc7 6017 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
Kojto 104:b9ad9a133dc7 6018 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6019 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6020 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6021
Kojto 104:b9ad9a133dc7 6022 /* Bit 8 : Enable interrupt on ENDTX event. */
Kojto 104:b9ad9a133dc7 6023 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Kojto 104:b9ad9a133dc7 6024 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Kojto 104:b9ad9a133dc7 6025 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6026 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6027 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6028
Kojto 104:b9ad9a133dc7 6029 /* Bit 6 : Enable interrupt on END event. */
Kojto 104:b9ad9a133dc7 6030 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 6031 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 6032 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6033 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6034 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6035
Kojto 104:b9ad9a133dc7 6036 /* Bit 4 : Enable interrupt on ENDRX event. */
Kojto 104:b9ad9a133dc7 6037 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Kojto 104:b9ad9a133dc7 6038 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Kojto 104:b9ad9a133dc7 6039 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6040 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6041 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6042
Kojto 104:b9ad9a133dc7 6043 /* Bit 1 : Enable interrupt on STOPPED event. */
Kojto 104:b9ad9a133dc7 6044 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Kojto 104:b9ad9a133dc7 6045 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Kojto 104:b9ad9a133dc7 6046 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6047 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6048 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6049
Kojto 104:b9ad9a133dc7 6050 /* Register: SPIM_INTENCLR */
Kojto 104:b9ad9a133dc7 6051 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6052
Kojto 104:b9ad9a133dc7 6053 /* Bit 19 : Disable interrupt on STARTED event. */
Kojto 104:b9ad9a133dc7 6054 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
Kojto 104:b9ad9a133dc7 6055 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
Kojto 104:b9ad9a133dc7 6056 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6057 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6058 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6059
Kojto 104:b9ad9a133dc7 6060 /* Bit 8 : Disable interrupt on ENDTX event. */
Kojto 104:b9ad9a133dc7 6061 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Kojto 104:b9ad9a133dc7 6062 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Kojto 104:b9ad9a133dc7 6063 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6064 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6065 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6066
Kojto 104:b9ad9a133dc7 6067 /* Bit 6 : Disable interrupt on END event. */
Kojto 104:b9ad9a133dc7 6068 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 6069 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 6070 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6071 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6072 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6073
Kojto 104:b9ad9a133dc7 6074 /* Bit 4 : Disable interrupt on ENDRX event. */
Kojto 104:b9ad9a133dc7 6075 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Kojto 104:b9ad9a133dc7 6076 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Kojto 104:b9ad9a133dc7 6077 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6078 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6079 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6080
Kojto 104:b9ad9a133dc7 6081 /* Bit 1 : Disable interrupt on STOPPED event. */
Kojto 104:b9ad9a133dc7 6082 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Kojto 104:b9ad9a133dc7 6083 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Kojto 104:b9ad9a133dc7 6084 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6085 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6086 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6087
Kojto 104:b9ad9a133dc7 6088 /* Register: SPIM_ENABLE */
Kojto 104:b9ad9a133dc7 6089 /* Description: Enable SPIM. */
Kojto 104:b9ad9a133dc7 6090
Kojto 104:b9ad9a133dc7 6091 /* Bits 3..0 : Enable or disable SPIM. */
Kojto 104:b9ad9a133dc7 6092 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 6093 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 6094 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
Kojto 104:b9ad9a133dc7 6095 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
Kojto 104:b9ad9a133dc7 6096
Kojto 104:b9ad9a133dc7 6097 /* Register: SPIM_RXDDATA */
Kojto 104:b9ad9a133dc7 6098 /* Description: RXD register. */
Kojto 104:b9ad9a133dc7 6099
Kojto 104:b9ad9a133dc7 6100 /* Bits 7..0 : RX data received. Double buffered. */
Kojto 104:b9ad9a133dc7 6101 #define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 104:b9ad9a133dc7 6102 #define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 104:b9ad9a133dc7 6103
Kojto 104:b9ad9a133dc7 6104 /* Register: SPIM_TXDDATA */
Kojto 104:b9ad9a133dc7 6105 /* Description: TXD register. */
Kojto 104:b9ad9a133dc7 6106
Kojto 104:b9ad9a133dc7 6107 /* Bits 7..0 : TX data to send. Double buffered. */
Kojto 104:b9ad9a133dc7 6108 #define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 104:b9ad9a133dc7 6109 #define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 104:b9ad9a133dc7 6110
Kojto 104:b9ad9a133dc7 6111 /* Register: SPIM_FREQUENCY */
Kojto 104:b9ad9a133dc7 6112 /* Description: SPI frequency. */
Kojto 104:b9ad9a133dc7 6113
Kojto 104:b9ad9a133dc7 6114 /* Bits 31..0 : SPI master data rate. */
Kojto 104:b9ad9a133dc7 6115 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 6116 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 6117 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
Kojto 104:b9ad9a133dc7 6118 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
Kojto 104:b9ad9a133dc7 6119 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
Kojto 104:b9ad9a133dc7 6120 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
Kojto 104:b9ad9a133dc7 6121 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
Kojto 104:b9ad9a133dc7 6122 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
Kojto 104:b9ad9a133dc7 6123 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
Kojto 104:b9ad9a133dc7 6124
Kojto 104:b9ad9a133dc7 6125 /* Register: SPIM_CONFIG */
Kojto 104:b9ad9a133dc7 6126 /* Description: Configuration register. */
Kojto 104:b9ad9a133dc7 6127
Kojto 104:b9ad9a133dc7 6128 /* Bit 2 : Serial clock (SCK) polarity. */
Kojto 104:b9ad9a133dc7 6129 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Kojto 104:b9ad9a133dc7 6130 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Kojto 104:b9ad9a133dc7 6131 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
Kojto 104:b9ad9a133dc7 6132 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
Kojto 104:b9ad9a133dc7 6133
Kojto 104:b9ad9a133dc7 6134 /* Bit 1 : Serial clock (SCK) phase. */
Kojto 104:b9ad9a133dc7 6135 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Kojto 104:b9ad9a133dc7 6136 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Kojto 104:b9ad9a133dc7 6137 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
Kojto 104:b9ad9a133dc7 6138 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
Kojto 104:b9ad9a133dc7 6139
Kojto 104:b9ad9a133dc7 6140 /* Bit 0 : Bit order. */
Kojto 104:b9ad9a133dc7 6141 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Kojto 104:b9ad9a133dc7 6142 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Kojto 104:b9ad9a133dc7 6143 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
Kojto 104:b9ad9a133dc7 6144 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
Kojto 104:b9ad9a133dc7 6145
Kojto 104:b9ad9a133dc7 6146 /* Register: SPIM_ORC */
Kojto 104:b9ad9a133dc7 6147 /* Description: Over-read character. */
Kojto 104:b9ad9a133dc7 6148
Kojto 104:b9ad9a133dc7 6149 /* Bits 7..0 : Over-read character. */
Kojto 104:b9ad9a133dc7 6150 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
Kojto 104:b9ad9a133dc7 6151 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
Kojto 104:b9ad9a133dc7 6152
Kojto 104:b9ad9a133dc7 6153 /* Register: SPIM_POWER */
Kojto 104:b9ad9a133dc7 6154 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 6155
Kojto 104:b9ad9a133dc7 6156 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 6157 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 6158 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 6159 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 6160 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 6161
Kojto 104:b9ad9a133dc7 6162 /* Register: SPIM_RXD_PTR */
Kojto 104:b9ad9a133dc7 6163 /* Description: Data pointer. */
Kojto 104:b9ad9a133dc7 6164
Kojto 104:b9ad9a133dc7 6165 /* Bits 31..0 : Data pointer. */
Kojto 104:b9ad9a133dc7 6166 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Kojto 104:b9ad9a133dc7 6167 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Kojto 104:b9ad9a133dc7 6168
Kojto 104:b9ad9a133dc7 6169 /* Register: SPIM_RXD_MAXCNT */
Kojto 104:b9ad9a133dc7 6170 /* Description: Maximum number of buffer bytes to receive. */
Kojto 104:b9ad9a133dc7 6171
Kojto 104:b9ad9a133dc7 6172 /* Bits 7..0 : Maximum number of buffer bytes to receive. */
Kojto 104:b9ad9a133dc7 6173 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Kojto 104:b9ad9a133dc7 6174 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Kojto 104:b9ad9a133dc7 6175
Kojto 104:b9ad9a133dc7 6176 /* Register: SPIM_RXD_AMOUNT */
Kojto 104:b9ad9a133dc7 6177 /* Description: Number of bytes received in the last transaction. */
Kojto 104:b9ad9a133dc7 6178
Kojto 104:b9ad9a133dc7 6179 /* Bits 7..0 : Number of bytes received in the last transaction. */
Kojto 104:b9ad9a133dc7 6180 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Kojto 104:b9ad9a133dc7 6181 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Kojto 104:b9ad9a133dc7 6182
Kojto 104:b9ad9a133dc7 6183 /* Register: SPIM_TXD_PTR */
Kojto 104:b9ad9a133dc7 6184 /* Description: Data pointer. */
Kojto 104:b9ad9a133dc7 6185
Kojto 104:b9ad9a133dc7 6186 /* Bits 31..0 : Data pointer. */
Kojto 104:b9ad9a133dc7 6187 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Kojto 104:b9ad9a133dc7 6188 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Kojto 104:b9ad9a133dc7 6189
Kojto 104:b9ad9a133dc7 6190 /* Register: SPIM_TXD_MAXCNT */
Kojto 104:b9ad9a133dc7 6191 /* Description: Maximum number of buffer bytes to send. */
Kojto 104:b9ad9a133dc7 6192
Kojto 104:b9ad9a133dc7 6193 /* Bits 7..0 : Maximum number of buffer bytes to send. */
Kojto 104:b9ad9a133dc7 6194 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Kojto 104:b9ad9a133dc7 6195 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Kojto 104:b9ad9a133dc7 6196
Kojto 104:b9ad9a133dc7 6197 /* Register: SPIM_TXD_AMOUNT */
Kojto 104:b9ad9a133dc7 6198 /* Description: Number of bytes sent in the last transaction. */
Kojto 104:b9ad9a133dc7 6199
Kojto 104:b9ad9a133dc7 6200 /* Bits 7..0 : Number of bytes sent in the last transaction. */
Kojto 104:b9ad9a133dc7 6201 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Kojto 104:b9ad9a133dc7 6202 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Kojto 104:b9ad9a133dc7 6203
Kojto 104:b9ad9a133dc7 6204
Kojto 104:b9ad9a133dc7 6205 /* Peripheral: SPIS */
Kojto 104:b9ad9a133dc7 6206 /* Description: SPI slave 1. */
Kojto 104:b9ad9a133dc7 6207
Kojto 104:b9ad9a133dc7 6208 /* Register: SPIS_SHORTS */
Kojto 104:b9ad9a133dc7 6209 /* Description: Shortcuts for SPIS. */
Kojto 104:b9ad9a133dc7 6210
Kojto 104:b9ad9a133dc7 6211 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
Kojto 104:b9ad9a133dc7 6212 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
Kojto 104:b9ad9a133dc7 6213 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
Kojto 104:b9ad9a133dc7 6214 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6215 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6216
Kojto 104:b9ad9a133dc7 6217 /* Register: SPIS_INTENSET */
Kojto 104:b9ad9a133dc7 6218 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6219
Kojto 104:b9ad9a133dc7 6220 /* Bit 10 : Enable interrupt on ACQUIRED event. */
Kojto 104:b9ad9a133dc7 6221 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
Kojto 104:b9ad9a133dc7 6222 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
Kojto 104:b9ad9a133dc7 6223 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6224 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6225 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6226
Kojto 104:b9ad9a133dc7 6227 /* Bit 1 : Enable interrupt on END event. */
Kojto 104:b9ad9a133dc7 6228 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 6229 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 6230 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6231 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6232 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6233
Kojto 104:b9ad9a133dc7 6234 /* Register: SPIS_INTENCLR */
Kojto 104:b9ad9a133dc7 6235 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6236
Kojto 104:b9ad9a133dc7 6237 /* Bit 10 : Disable interrupt on ACQUIRED event. */
Kojto 104:b9ad9a133dc7 6238 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
Kojto 104:b9ad9a133dc7 6239 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
Kojto 104:b9ad9a133dc7 6240 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6241 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6242 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6243
Kojto 104:b9ad9a133dc7 6244 /* Bit 1 : Disable interrupt on END event. */
Kojto 104:b9ad9a133dc7 6245 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
Kojto 104:b9ad9a133dc7 6246 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 104:b9ad9a133dc7 6247 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6248 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6249 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6250
Kojto 104:b9ad9a133dc7 6251 /* Register: SPIS_SEMSTAT */
Kojto 104:b9ad9a133dc7 6252 /* Description: Semaphore status. */
Kojto 104:b9ad9a133dc7 6253
Kojto 104:b9ad9a133dc7 6254 /* Bits 1..0 : Semaphore status. */
Kojto 104:b9ad9a133dc7 6255 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
Kojto 104:b9ad9a133dc7 6256 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
Kojto 104:b9ad9a133dc7 6257 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
Kojto 104:b9ad9a133dc7 6258 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
Kojto 104:b9ad9a133dc7 6259 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
Kojto 104:b9ad9a133dc7 6260 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
Kojto 104:b9ad9a133dc7 6261
Kojto 104:b9ad9a133dc7 6262 /* Register: SPIS_STATUS */
Kojto 104:b9ad9a133dc7 6263 /* Description: Status from last transaction. */
Kojto 104:b9ad9a133dc7 6264
Kojto 104:b9ad9a133dc7 6265 /* Bit 1 : RX buffer overflow detected, and prevented. */
Kojto 104:b9ad9a133dc7 6266 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
Kojto 104:b9ad9a133dc7 6267 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
Kojto 104:b9ad9a133dc7 6268 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6269 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6270 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
Kojto 104:b9ad9a133dc7 6271
Kojto 104:b9ad9a133dc7 6272 /* Bit 0 : TX buffer overread detected, and prevented. */
Kojto 104:b9ad9a133dc7 6273 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
Kojto 104:b9ad9a133dc7 6274 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
Kojto 104:b9ad9a133dc7 6275 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6276 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6277 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
Kojto 104:b9ad9a133dc7 6278
Kojto 104:b9ad9a133dc7 6279 /* Register: SPIS_ENABLE */
Kojto 104:b9ad9a133dc7 6280 /* Description: Enable SPIS. */
Kojto 104:b9ad9a133dc7 6281
Kojto 104:b9ad9a133dc7 6282 /* Bits 2..0 : Enable or disable SPIS. */
Kojto 104:b9ad9a133dc7 6283 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 6284 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 6285 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
Kojto 104:b9ad9a133dc7 6286 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
Kojto 104:b9ad9a133dc7 6287
Kojto 104:b9ad9a133dc7 6288 /* Register: SPIS_MAXRX */
Kojto 104:b9ad9a133dc7 6289 /* Description: Maximum number of bytes in the receive buffer. */
Kojto 104:b9ad9a133dc7 6290
Kojto 104:b9ad9a133dc7 6291 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
Kojto 104:b9ad9a133dc7 6292 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
Kojto 104:b9ad9a133dc7 6293 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
Kojto 104:b9ad9a133dc7 6294
Kojto 104:b9ad9a133dc7 6295 /* Register: SPIS_AMOUNTRX */
Kojto 104:b9ad9a133dc7 6296 /* Description: Number of bytes received in last granted transaction. */
Kojto 104:b9ad9a133dc7 6297
Kojto 104:b9ad9a133dc7 6298 /* Bits 7..0 : Number of bytes received in last granted transaction. */
Kojto 104:b9ad9a133dc7 6299 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
Kojto 104:b9ad9a133dc7 6300 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
Kojto 104:b9ad9a133dc7 6301
Kojto 104:b9ad9a133dc7 6302 /* Register: SPIS_MAXTX */
Kojto 104:b9ad9a133dc7 6303 /* Description: Maximum number of bytes in the transmit buffer. */
Kojto 104:b9ad9a133dc7 6304
Kojto 104:b9ad9a133dc7 6305 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
Kojto 104:b9ad9a133dc7 6306 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
Kojto 104:b9ad9a133dc7 6307 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
Kojto 104:b9ad9a133dc7 6308
Kojto 104:b9ad9a133dc7 6309 /* Register: SPIS_AMOUNTTX */
Kojto 104:b9ad9a133dc7 6310 /* Description: Number of bytes transmitted in last granted transaction. */
Kojto 104:b9ad9a133dc7 6311
Kojto 104:b9ad9a133dc7 6312 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
Kojto 104:b9ad9a133dc7 6313 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
Kojto 104:b9ad9a133dc7 6314 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
Kojto 104:b9ad9a133dc7 6315
Kojto 104:b9ad9a133dc7 6316 /* Register: SPIS_CONFIG */
Kojto 104:b9ad9a133dc7 6317 /* Description: Configuration register. */
Kojto 104:b9ad9a133dc7 6318
Kojto 104:b9ad9a133dc7 6319 /* Bit 2 : Serial clock (SCK) polarity. */
Kojto 104:b9ad9a133dc7 6320 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Kojto 104:b9ad9a133dc7 6321 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Kojto 104:b9ad9a133dc7 6322 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
Kojto 104:b9ad9a133dc7 6323 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
Kojto 104:b9ad9a133dc7 6324
Kojto 104:b9ad9a133dc7 6325 /* Bit 1 : Serial clock (SCK) phase. */
Kojto 104:b9ad9a133dc7 6326 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Kojto 104:b9ad9a133dc7 6327 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Kojto 104:b9ad9a133dc7 6328 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
Kojto 104:b9ad9a133dc7 6329 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
Kojto 104:b9ad9a133dc7 6330
Kojto 104:b9ad9a133dc7 6331 /* Bit 0 : Bit order. */
Kojto 104:b9ad9a133dc7 6332 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Kojto 104:b9ad9a133dc7 6333 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Kojto 104:b9ad9a133dc7 6334 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
Kojto 104:b9ad9a133dc7 6335 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
Kojto 104:b9ad9a133dc7 6336
Kojto 104:b9ad9a133dc7 6337 /* Register: SPIS_DEF */
Kojto 104:b9ad9a133dc7 6338 /* Description: Default character. */
Kojto 104:b9ad9a133dc7 6339
Kojto 104:b9ad9a133dc7 6340 /* Bits 7..0 : Default character. */
Kojto 104:b9ad9a133dc7 6341 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
Kojto 104:b9ad9a133dc7 6342 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
Kojto 104:b9ad9a133dc7 6343
Kojto 104:b9ad9a133dc7 6344 /* Register: SPIS_ORC */
Kojto 104:b9ad9a133dc7 6345 /* Description: Over-read character. */
Kojto 104:b9ad9a133dc7 6346
Kojto 104:b9ad9a133dc7 6347 /* Bits 7..0 : Over-read character. */
Kojto 104:b9ad9a133dc7 6348 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
Kojto 104:b9ad9a133dc7 6349 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
Kojto 104:b9ad9a133dc7 6350
Kojto 104:b9ad9a133dc7 6351 /* Register: SPIS_POWER */
Kojto 104:b9ad9a133dc7 6352 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 6353
Kojto 104:b9ad9a133dc7 6354 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 6355 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 6356 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 6357 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 6358 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 6359
Kojto 104:b9ad9a133dc7 6360
Kojto 104:b9ad9a133dc7 6361 /* Peripheral: TEMP */
Kojto 104:b9ad9a133dc7 6362 /* Description: Temperature Sensor. */
Kojto 104:b9ad9a133dc7 6363
Kojto 104:b9ad9a133dc7 6364 /* Register: TEMP_INTENSET */
Kojto 104:b9ad9a133dc7 6365 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6366
Kojto 104:b9ad9a133dc7 6367 /* Bit 0 : Enable interrupt on DATARDY event. */
Kojto 104:b9ad9a133dc7 6368 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
Kojto 104:b9ad9a133dc7 6369 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
Kojto 104:b9ad9a133dc7 6370 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6371 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6372 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6373
Kojto 104:b9ad9a133dc7 6374 /* Register: TEMP_INTENCLR */
Kojto 104:b9ad9a133dc7 6375 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6376
Kojto 104:b9ad9a133dc7 6377 /* Bit 0 : Disable interrupt on DATARDY event. */
Kojto 104:b9ad9a133dc7 6378 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
Kojto 104:b9ad9a133dc7 6379 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
Kojto 104:b9ad9a133dc7 6380 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6381 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6382 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6383
Kojto 104:b9ad9a133dc7 6384 /* Register: TEMP_POWER */
Kojto 104:b9ad9a133dc7 6385 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 6386
Kojto 104:b9ad9a133dc7 6387 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 6388 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 6389 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 6390 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 6391 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 6392
Kojto 104:b9ad9a133dc7 6393
Kojto 104:b9ad9a133dc7 6394 /* Peripheral: TIMER */
Kojto 104:b9ad9a133dc7 6395 /* Description: Timer 0. */
Kojto 104:b9ad9a133dc7 6396
Kojto 104:b9ad9a133dc7 6397 /* Register: TIMER_SHORTS */
Kojto 104:b9ad9a133dc7 6398 /* Description: Shortcuts for Timer. */
Kojto 104:b9ad9a133dc7 6399
Kojto 104:b9ad9a133dc7 6400 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
Kojto 104:b9ad9a133dc7 6401 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
Kojto 104:b9ad9a133dc7 6402 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
Kojto 104:b9ad9a133dc7 6403 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6404 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6405
Kojto 104:b9ad9a133dc7 6406 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
Kojto 104:b9ad9a133dc7 6407 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
Kojto 104:b9ad9a133dc7 6408 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
Kojto 104:b9ad9a133dc7 6409 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6410 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6411
Kojto 104:b9ad9a133dc7 6412 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
Kojto 104:b9ad9a133dc7 6413 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
Kojto 104:b9ad9a133dc7 6414 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
Kojto 104:b9ad9a133dc7 6415 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6416 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6417
Kojto 104:b9ad9a133dc7 6418 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
Kojto 104:b9ad9a133dc7 6419 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
Kojto 104:b9ad9a133dc7 6420 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
Kojto 104:b9ad9a133dc7 6421 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6422 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6423
Kojto 104:b9ad9a133dc7 6424 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
Kojto 104:b9ad9a133dc7 6425 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
Kojto 104:b9ad9a133dc7 6426 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
Kojto 104:b9ad9a133dc7 6427 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6428 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6429
Kojto 104:b9ad9a133dc7 6430 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
Kojto 104:b9ad9a133dc7 6431 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
Kojto 104:b9ad9a133dc7 6432 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
Kojto 104:b9ad9a133dc7 6433 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6434 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6435
Kojto 104:b9ad9a133dc7 6436 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
Kojto 104:b9ad9a133dc7 6437 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
Kojto 104:b9ad9a133dc7 6438 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
Kojto 104:b9ad9a133dc7 6439 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6440 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6441
Kojto 104:b9ad9a133dc7 6442 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
Kojto 104:b9ad9a133dc7 6443 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
Kojto 104:b9ad9a133dc7 6444 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
Kojto 104:b9ad9a133dc7 6445 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6446 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6447
Kojto 104:b9ad9a133dc7 6448 /* Register: TIMER_INTENSET */
Kojto 104:b9ad9a133dc7 6449 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6450
Kojto 104:b9ad9a133dc7 6451 /* Bit 19 : Enable interrupt on COMPARE[3] */
Kojto 104:b9ad9a133dc7 6452 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 6453 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 6454 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6455 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6456 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6457
Kojto 104:b9ad9a133dc7 6458 /* Bit 18 : Enable interrupt on COMPARE[2] */
Kojto 104:b9ad9a133dc7 6459 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 6460 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 6461 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6462 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6463 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6464
Kojto 104:b9ad9a133dc7 6465 /* Bit 17 : Enable interrupt on COMPARE[1] */
Kojto 104:b9ad9a133dc7 6466 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 6467 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 6468 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6469 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6470 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6471
Kojto 104:b9ad9a133dc7 6472 /* Bit 16 : Enable interrupt on COMPARE[0] */
Kojto 104:b9ad9a133dc7 6473 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 6474 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 6475 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6476 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6477 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6478
Kojto 104:b9ad9a133dc7 6479 /* Register: TIMER_INTENCLR */
Kojto 104:b9ad9a133dc7 6480 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6481
Kojto 104:b9ad9a133dc7 6482 /* Bit 19 : Disable interrupt on COMPARE[3] */
Kojto 104:b9ad9a133dc7 6483 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 6484 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 104:b9ad9a133dc7 6485 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6486 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6487 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6488
Kojto 104:b9ad9a133dc7 6489 /* Bit 18 : Disable interrupt on COMPARE[2] */
Kojto 104:b9ad9a133dc7 6490 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 6491 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 104:b9ad9a133dc7 6492 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6493 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6494 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6495
Kojto 104:b9ad9a133dc7 6496 /* Bit 17 : Disable interrupt on COMPARE[1] */
Kojto 104:b9ad9a133dc7 6497 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 6498 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 104:b9ad9a133dc7 6499 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6500 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6501 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6502
Kojto 104:b9ad9a133dc7 6503 /* Bit 16 : Disable interrupt on COMPARE[0] */
Kojto 104:b9ad9a133dc7 6504 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 6505 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 104:b9ad9a133dc7 6506 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6507 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6508 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6509
Kojto 104:b9ad9a133dc7 6510 /* Register: TIMER_MODE */
Kojto 104:b9ad9a133dc7 6511 /* Description: Timer Mode selection. */
Kojto 104:b9ad9a133dc7 6512
Kojto 104:b9ad9a133dc7 6513 /* Bit 0 : Select Normal or Counter mode. */
Kojto 104:b9ad9a133dc7 6514 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 104:b9ad9a133dc7 6515 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 104:b9ad9a133dc7 6516 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
Kojto 104:b9ad9a133dc7 6517 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
Kojto 104:b9ad9a133dc7 6518
Kojto 104:b9ad9a133dc7 6519 /* Register: TIMER_BITMODE */
Kojto 104:b9ad9a133dc7 6520 /* Description: Sets timer behaviour. */
Kojto 104:b9ad9a133dc7 6521
Kojto 104:b9ad9a133dc7 6522 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
Kojto 104:b9ad9a133dc7 6523 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
Kojto 104:b9ad9a133dc7 6524 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
Kojto 104:b9ad9a133dc7 6525 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
Kojto 104:b9ad9a133dc7 6526 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
Kojto 104:b9ad9a133dc7 6527 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
Kojto 104:b9ad9a133dc7 6528 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
Kojto 104:b9ad9a133dc7 6529
Kojto 104:b9ad9a133dc7 6530 /* Register: TIMER_PRESCALER */
Kojto 104:b9ad9a133dc7 6531 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
Kojto 104:b9ad9a133dc7 6532
Kojto 104:b9ad9a133dc7 6533 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
Kojto 104:b9ad9a133dc7 6534 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Kojto 104:b9ad9a133dc7 6535 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Kojto 104:b9ad9a133dc7 6536
Kojto 104:b9ad9a133dc7 6537 /* Register: TIMER_POWER */
Kojto 104:b9ad9a133dc7 6538 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 6539
Kojto 104:b9ad9a133dc7 6540 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 6541 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 6542 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 6543 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 6544 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 6545
Kojto 104:b9ad9a133dc7 6546
Kojto 104:b9ad9a133dc7 6547 /* Peripheral: TWI */
Kojto 104:b9ad9a133dc7 6548 /* Description: Two-wire interface master 0. */
Kojto 104:b9ad9a133dc7 6549
Kojto 104:b9ad9a133dc7 6550 /* Register: TWI_SHORTS */
Kojto 104:b9ad9a133dc7 6551 /* Description: Shortcuts for TWI. */
Kojto 104:b9ad9a133dc7 6552
Kojto 104:b9ad9a133dc7 6553 /* Bit 1 : Shortcut between BB event and the STOP task. */
Kojto 104:b9ad9a133dc7 6554 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
Kojto 104:b9ad9a133dc7 6555 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
Kojto 104:b9ad9a133dc7 6556 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6557 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6558
Kojto 104:b9ad9a133dc7 6559 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
Kojto 104:b9ad9a133dc7 6560 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
Kojto 104:b9ad9a133dc7 6561 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
Kojto 104:b9ad9a133dc7 6562 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6563 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6564
Kojto 104:b9ad9a133dc7 6565 /* Register: TWI_INTENSET */
Kojto 104:b9ad9a133dc7 6566 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6567
Kojto 104:b9ad9a133dc7 6568 /* Bit 18 : Enable interrupt on SUSPENDED event. */
Kojto 104:b9ad9a133dc7 6569 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Kojto 104:b9ad9a133dc7 6570 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Kojto 104:b9ad9a133dc7 6571 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6572 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6573 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6574
Kojto 104:b9ad9a133dc7 6575 /* Bit 14 : Enable interrupt on BB event. */
Kojto 104:b9ad9a133dc7 6576 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
Kojto 104:b9ad9a133dc7 6577 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
Kojto 104:b9ad9a133dc7 6578 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6579 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6580 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6581
Kojto 104:b9ad9a133dc7 6582 /* Bit 9 : Enable interrupt on ERROR event. */
Kojto 104:b9ad9a133dc7 6583 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 104:b9ad9a133dc7 6584 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 104:b9ad9a133dc7 6585 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6586 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6587 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6588
Kojto 104:b9ad9a133dc7 6589 /* Bit 7 : Enable interrupt on TXDSENT event. */
Kojto 104:b9ad9a133dc7 6590 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
Kojto 104:b9ad9a133dc7 6591 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
Kojto 104:b9ad9a133dc7 6592 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6593 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6594 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6595
Kojto 104:b9ad9a133dc7 6596 /* Bit 2 : Enable interrupt on READY event. */
Kojto 104:b9ad9a133dc7 6597 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
Kojto 104:b9ad9a133dc7 6598 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
Kojto 104:b9ad9a133dc7 6599 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6600 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6601 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6602
Kojto 104:b9ad9a133dc7 6603 /* Bit 1 : Enable interrupt on STOPPED event. */
Kojto 104:b9ad9a133dc7 6604 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Kojto 104:b9ad9a133dc7 6605 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Kojto 104:b9ad9a133dc7 6606 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6607 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6608 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6609
Kojto 104:b9ad9a133dc7 6610 /* Register: TWI_INTENCLR */
Kojto 104:b9ad9a133dc7 6611 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6612
Kojto 104:b9ad9a133dc7 6613 /* Bit 18 : Disable interrupt on SUSPENDED event. */
Kojto 104:b9ad9a133dc7 6614 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Kojto 104:b9ad9a133dc7 6615 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Kojto 104:b9ad9a133dc7 6616 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6617 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6618 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6619
Kojto 104:b9ad9a133dc7 6620 /* Bit 14 : Disable interrupt on BB event. */
Kojto 104:b9ad9a133dc7 6621 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
Kojto 104:b9ad9a133dc7 6622 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
Kojto 104:b9ad9a133dc7 6623 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6624 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6625 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6626
Kojto 104:b9ad9a133dc7 6627 /* Bit 9 : Disable interrupt on ERROR event. */
Kojto 104:b9ad9a133dc7 6628 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 104:b9ad9a133dc7 6629 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 104:b9ad9a133dc7 6630 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6631 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6632 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6633
Kojto 104:b9ad9a133dc7 6634 /* Bit 7 : Disable interrupt on TXDSENT event. */
Kojto 104:b9ad9a133dc7 6635 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
Kojto 104:b9ad9a133dc7 6636 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
Kojto 104:b9ad9a133dc7 6637 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6638 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6639 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6640
Kojto 104:b9ad9a133dc7 6641 /* Bit 2 : Disable interrupt on RXDREADY event. */
Kojto 104:b9ad9a133dc7 6642 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
Kojto 104:b9ad9a133dc7 6643 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
Kojto 104:b9ad9a133dc7 6644 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6645 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6646 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6647
Kojto 104:b9ad9a133dc7 6648 /* Bit 1 : Disable interrupt on STOPPED event. */
Kojto 104:b9ad9a133dc7 6649 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Kojto 104:b9ad9a133dc7 6650 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Kojto 104:b9ad9a133dc7 6651 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6652 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6653 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6654
Kojto 104:b9ad9a133dc7 6655 /* Register: TWI_ERRORSRC */
Kojto 104:b9ad9a133dc7 6656 /* Description: Two-wire error source. Write error field to 1 to clear error. */
Kojto 104:b9ad9a133dc7 6657
Kojto 104:b9ad9a133dc7 6658 /* Bit 2 : NACK received after sending a data byte. */
Kojto 104:b9ad9a133dc7 6659 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
Kojto 104:b9ad9a133dc7 6660 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
Kojto 104:b9ad9a133dc7 6661 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6662 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6663 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
Kojto 104:b9ad9a133dc7 6664
Kojto 104:b9ad9a133dc7 6665 /* Bit 1 : NACK received after sending the address. */
Kojto 104:b9ad9a133dc7 6666 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
Kojto 104:b9ad9a133dc7 6667 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
Kojto 104:b9ad9a133dc7 6668 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6669 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6670 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
Kojto 104:b9ad9a133dc7 6671
Kojto 104:b9ad9a133dc7 6672 /* Register: TWI_ENABLE */
Kojto 104:b9ad9a133dc7 6673 /* Description: Enable two-wire master. */
Kojto 104:b9ad9a133dc7 6674
Kojto 104:b9ad9a133dc7 6675 /* Bits 2..0 : Enable or disable W2M */
Kojto 104:b9ad9a133dc7 6676 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 6677 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 6678 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 6679 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 6680
Kojto 104:b9ad9a133dc7 6681 /* Register: TWI_RXD */
Kojto 104:b9ad9a133dc7 6682 /* Description: RX data register. */
Kojto 104:b9ad9a133dc7 6683
Kojto 104:b9ad9a133dc7 6684 /* Bits 7..0 : RX data from last transfer. */
Kojto 104:b9ad9a133dc7 6685 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 104:b9ad9a133dc7 6686 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 104:b9ad9a133dc7 6687
Kojto 104:b9ad9a133dc7 6688 /* Register: TWI_TXD */
Kojto 104:b9ad9a133dc7 6689 /* Description: TX data register. */
Kojto 104:b9ad9a133dc7 6690
Kojto 104:b9ad9a133dc7 6691 /* Bits 7..0 : TX data for next transfer. */
Kojto 104:b9ad9a133dc7 6692 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 104:b9ad9a133dc7 6693 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 104:b9ad9a133dc7 6694
Kojto 104:b9ad9a133dc7 6695 /* Register: TWI_FREQUENCY */
Kojto 104:b9ad9a133dc7 6696 /* Description: Two-wire frequency. */
Kojto 104:b9ad9a133dc7 6697
Kojto 104:b9ad9a133dc7 6698 /* Bits 31..0 : Two-wire master clock frequency. */
Kojto 104:b9ad9a133dc7 6699 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 6700 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 104:b9ad9a133dc7 6701 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
Kojto 104:b9ad9a133dc7 6702 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
Kojto 104:b9ad9a133dc7 6703 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
Kojto 104:b9ad9a133dc7 6704
Kojto 104:b9ad9a133dc7 6705 /* Register: TWI_ADDRESS */
Kojto 104:b9ad9a133dc7 6706 /* Description: Address used in the two-wire transfer. */
Kojto 104:b9ad9a133dc7 6707
Kojto 104:b9ad9a133dc7 6708 /* Bits 6..0 : Two-wire address. */
Kojto 104:b9ad9a133dc7 6709 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
Kojto 104:b9ad9a133dc7 6710 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Kojto 104:b9ad9a133dc7 6711
Kojto 104:b9ad9a133dc7 6712 /* Register: TWI_POWER */
Kojto 104:b9ad9a133dc7 6713 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 6714
Kojto 104:b9ad9a133dc7 6715 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 6716 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 6717 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 6718 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 6719 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 6720
Kojto 104:b9ad9a133dc7 6721
Kojto 104:b9ad9a133dc7 6722 /* Peripheral: UART */
Kojto 104:b9ad9a133dc7 6723 /* Description: Universal Asynchronous Receiver/Transmitter. */
Kojto 104:b9ad9a133dc7 6724
Kojto 104:b9ad9a133dc7 6725 /* Register: UART_SHORTS */
Kojto 104:b9ad9a133dc7 6726 /* Description: Shortcuts for UART. */
Kojto 104:b9ad9a133dc7 6727
Kojto 104:b9ad9a133dc7 6728 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
Kojto 104:b9ad9a133dc7 6729 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
Kojto 104:b9ad9a133dc7 6730 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
Kojto 104:b9ad9a133dc7 6731 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6732 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6733
Kojto 104:b9ad9a133dc7 6734 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
Kojto 104:b9ad9a133dc7 6735 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
Kojto 104:b9ad9a133dc7 6736 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
Kojto 104:b9ad9a133dc7 6737 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 104:b9ad9a133dc7 6738 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 104:b9ad9a133dc7 6739
Kojto 104:b9ad9a133dc7 6740 /* Register: UART_INTENSET */
Kojto 104:b9ad9a133dc7 6741 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6742
Kojto 104:b9ad9a133dc7 6743 /* Bit 17 : Enable interrupt on RXTO event. */
Kojto 104:b9ad9a133dc7 6744 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Kojto 104:b9ad9a133dc7 6745 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
Kojto 104:b9ad9a133dc7 6746 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6747 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6748 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6749
Kojto 104:b9ad9a133dc7 6750 /* Bit 9 : Enable interrupt on ERROR event. */
Kojto 104:b9ad9a133dc7 6751 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 104:b9ad9a133dc7 6752 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 104:b9ad9a133dc7 6753 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6754 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6755 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6756
Kojto 104:b9ad9a133dc7 6757 /* Bit 7 : Enable interrupt on TXRDY event. */
Kojto 104:b9ad9a133dc7 6758 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
Kojto 104:b9ad9a133dc7 6759 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
Kojto 104:b9ad9a133dc7 6760 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6761 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6762 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6763
Kojto 104:b9ad9a133dc7 6764 /* Bit 2 : Enable interrupt on RXRDY event. */
Kojto 104:b9ad9a133dc7 6765 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
Kojto 104:b9ad9a133dc7 6766 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
Kojto 104:b9ad9a133dc7 6767 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6768 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6769 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6770
Kojto 104:b9ad9a133dc7 6771 /* Bit 1 : Enable interrupt on NCTS event. */
Kojto 104:b9ad9a133dc7 6772 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Kojto 104:b9ad9a133dc7 6773 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
Kojto 104:b9ad9a133dc7 6774 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6775 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6776 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6777
Kojto 104:b9ad9a133dc7 6778 /* Bit 0 : Enable interrupt on CTS event. */
Kojto 104:b9ad9a133dc7 6779 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
Kojto 104:b9ad9a133dc7 6780 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
Kojto 104:b9ad9a133dc7 6781 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6782 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6783 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6784
Kojto 104:b9ad9a133dc7 6785 /* Register: UART_INTENCLR */
Kojto 104:b9ad9a133dc7 6786 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6787
Kojto 104:b9ad9a133dc7 6788 /* Bit 17 : Disable interrupt on RXTO event. */
Kojto 104:b9ad9a133dc7 6789 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Kojto 104:b9ad9a133dc7 6790 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
Kojto 104:b9ad9a133dc7 6791 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6792 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6793 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6794
Kojto 104:b9ad9a133dc7 6795 /* Bit 9 : Disable interrupt on ERROR event. */
Kojto 104:b9ad9a133dc7 6796 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 104:b9ad9a133dc7 6797 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 104:b9ad9a133dc7 6798 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6799 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6800 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6801
Kojto 104:b9ad9a133dc7 6802 /* Bit 7 : Disable interrupt on TXRDY event. */
Kojto 104:b9ad9a133dc7 6803 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
Kojto 104:b9ad9a133dc7 6804 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
Kojto 104:b9ad9a133dc7 6805 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6806 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6807 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6808
Kojto 104:b9ad9a133dc7 6809 /* Bit 2 : Disable interrupt on RXRDY event. */
Kojto 104:b9ad9a133dc7 6810 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
Kojto 104:b9ad9a133dc7 6811 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
Kojto 104:b9ad9a133dc7 6812 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6813 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6814 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6815
Kojto 104:b9ad9a133dc7 6816 /* Bit 1 : Disable interrupt on NCTS event. */
Kojto 104:b9ad9a133dc7 6817 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Kojto 104:b9ad9a133dc7 6818 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
Kojto 104:b9ad9a133dc7 6819 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6820 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6821 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6822
Kojto 104:b9ad9a133dc7 6823 /* Bit 0 : Disable interrupt on CTS event. */
Kojto 104:b9ad9a133dc7 6824 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
Kojto 104:b9ad9a133dc7 6825 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
Kojto 104:b9ad9a133dc7 6826 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6827 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6828 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6829
Kojto 104:b9ad9a133dc7 6830 /* Register: UART_ERRORSRC */
Kojto 104:b9ad9a133dc7 6831 /* Description: Error source. Write error field to 1 to clear error. */
Kojto 104:b9ad9a133dc7 6832
Kojto 104:b9ad9a133dc7 6833 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
Kojto 104:b9ad9a133dc7 6834 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
Kojto 104:b9ad9a133dc7 6835 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
Kojto 104:b9ad9a133dc7 6836 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6837 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6838 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
Kojto 104:b9ad9a133dc7 6839
Kojto 104:b9ad9a133dc7 6840 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
Kojto 104:b9ad9a133dc7 6841 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
Kojto 104:b9ad9a133dc7 6842 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
Kojto 104:b9ad9a133dc7 6843 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6844 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6845 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
Kojto 104:b9ad9a133dc7 6846
Kojto 104:b9ad9a133dc7 6847 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
Kojto 104:b9ad9a133dc7 6848 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Kojto 104:b9ad9a133dc7 6849 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
Kojto 104:b9ad9a133dc7 6850 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6851 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6852 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
Kojto 104:b9ad9a133dc7 6853
Kojto 104:b9ad9a133dc7 6854 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
Kojto 104:b9ad9a133dc7 6855 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
Kojto 104:b9ad9a133dc7 6856 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
Kojto 104:b9ad9a133dc7 6857 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
Kojto 104:b9ad9a133dc7 6858 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
Kojto 104:b9ad9a133dc7 6859 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
Kojto 104:b9ad9a133dc7 6860
Kojto 104:b9ad9a133dc7 6861 /* Register: UART_ENABLE */
Kojto 104:b9ad9a133dc7 6862 /* Description: Enable UART and acquire IOs. */
Kojto 104:b9ad9a133dc7 6863
Kojto 104:b9ad9a133dc7 6864 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
Kojto 104:b9ad9a133dc7 6865 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 104:b9ad9a133dc7 6866 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 104:b9ad9a133dc7 6867 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
Kojto 104:b9ad9a133dc7 6868 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
Kojto 104:b9ad9a133dc7 6869
Kojto 104:b9ad9a133dc7 6870 /* Register: UART_RXD */
Kojto 104:b9ad9a133dc7 6871 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
Kojto 104:b9ad9a133dc7 6872
Kojto 104:b9ad9a133dc7 6873 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
Kojto 104:b9ad9a133dc7 6874 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 104:b9ad9a133dc7 6875 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 104:b9ad9a133dc7 6876
Kojto 104:b9ad9a133dc7 6877 /* Register: UART_TXD */
Kojto 104:b9ad9a133dc7 6878 /* Description: TXD register. */
Kojto 104:b9ad9a133dc7 6879
Kojto 104:b9ad9a133dc7 6880 /* Bits 7..0 : TX data for transfer. */
Kojto 104:b9ad9a133dc7 6881 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 104:b9ad9a133dc7 6882 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 104:b9ad9a133dc7 6883
Kojto 104:b9ad9a133dc7 6884 /* Register: UART_BAUDRATE */
Kojto 104:b9ad9a133dc7 6885 /* Description: UART Baudrate. */
Kojto 104:b9ad9a133dc7 6886
Kojto 104:b9ad9a133dc7 6887 /* Bits 31..0 : UART baudrate. */
Kojto 104:b9ad9a133dc7 6888 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
Kojto 104:b9ad9a133dc7 6889 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
Kojto 104:b9ad9a133dc7 6890 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
Kojto 104:b9ad9a133dc7 6891 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
Kojto 104:b9ad9a133dc7 6892 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
Kojto 104:b9ad9a133dc7 6893 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
Kojto 104:b9ad9a133dc7 6894 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
Kojto 104:b9ad9a133dc7 6895 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
Kojto 104:b9ad9a133dc7 6896 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
Kojto 104:b9ad9a133dc7 6897 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
Kojto 104:b9ad9a133dc7 6898 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
Kojto 104:b9ad9a133dc7 6899 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
Kojto 104:b9ad9a133dc7 6900 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
Kojto 104:b9ad9a133dc7 6901 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
Kojto 104:b9ad9a133dc7 6902 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
Kojto 104:b9ad9a133dc7 6903 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
Kojto 104:b9ad9a133dc7 6904 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
Kojto 104:b9ad9a133dc7 6905 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
Kojto 104:b9ad9a133dc7 6906
Kojto 104:b9ad9a133dc7 6907 /* Register: UART_CONFIG */
Kojto 104:b9ad9a133dc7 6908 /* Description: Configuration of parity and hardware flow control register. */
Kojto 104:b9ad9a133dc7 6909
Kojto 104:b9ad9a133dc7 6910 /* Bits 3..1 : Include parity bit. */
Kojto 104:b9ad9a133dc7 6911 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Kojto 104:b9ad9a133dc7 6912 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
Kojto 104:b9ad9a133dc7 6913 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
Kojto 104:b9ad9a133dc7 6914 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
Kojto 104:b9ad9a133dc7 6915
Kojto 104:b9ad9a133dc7 6916 /* Bit 0 : Hardware flow control. */
Kojto 104:b9ad9a133dc7 6917 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
Kojto 104:b9ad9a133dc7 6918 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
Kojto 104:b9ad9a133dc7 6919 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
Kojto 104:b9ad9a133dc7 6920 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
Kojto 104:b9ad9a133dc7 6921
Kojto 104:b9ad9a133dc7 6922 /* Register: UART_POWER */
Kojto 104:b9ad9a133dc7 6923 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 6924
Kojto 104:b9ad9a133dc7 6925 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 6926 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 6927 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 6928 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 6929 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 6930
Kojto 104:b9ad9a133dc7 6931
Kojto 104:b9ad9a133dc7 6932 /* Peripheral: UICR */
Kojto 104:b9ad9a133dc7 6933 /* Description: User Information Configuration. */
Kojto 104:b9ad9a133dc7 6934
Kojto 104:b9ad9a133dc7 6935 /* Register: UICR_RBPCONF */
Kojto 104:b9ad9a133dc7 6936 /* Description: Readback protection configuration. */
Kojto 104:b9ad9a133dc7 6937
Kojto 104:b9ad9a133dc7 6938 /* Bits 15..8 : Readback protect all code in the device. */
Kojto 104:b9ad9a133dc7 6939 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
Kojto 104:b9ad9a133dc7 6940 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
Kojto 104:b9ad9a133dc7 6941 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 6942 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 6943
Kojto 104:b9ad9a133dc7 6944 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
Kojto 104:b9ad9a133dc7 6945 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
Kojto 104:b9ad9a133dc7 6946 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
Kojto 104:b9ad9a133dc7 6947 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
Kojto 104:b9ad9a133dc7 6948 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
Kojto 104:b9ad9a133dc7 6949
Kojto 104:b9ad9a133dc7 6950 /* Register: UICR_XTALFREQ */
Kojto 104:b9ad9a133dc7 6951 /* Description: Reset value for CLOCK XTALFREQ register. */
Kojto 104:b9ad9a133dc7 6952
Kojto 104:b9ad9a133dc7 6953 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
Kojto 104:b9ad9a133dc7 6954 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
Kojto 104:b9ad9a133dc7 6955 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
Kojto 104:b9ad9a133dc7 6956 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
Kojto 104:b9ad9a133dc7 6957 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
Kojto 104:b9ad9a133dc7 6958
Kojto 104:b9ad9a133dc7 6959 /* Register: UICR_FWID */
Kojto 104:b9ad9a133dc7 6960 /* Description: Firmware ID. */
Kojto 104:b9ad9a133dc7 6961
Kojto 104:b9ad9a133dc7 6962 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
Kojto 104:b9ad9a133dc7 6963 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
Kojto 104:b9ad9a133dc7 6964 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
Kojto 104:b9ad9a133dc7 6965
Kojto 104:b9ad9a133dc7 6966
Kojto 104:b9ad9a133dc7 6967 /* Peripheral: WDT */
Kojto 104:b9ad9a133dc7 6968 /* Description: Watchdog Timer. */
Kojto 104:b9ad9a133dc7 6969
Kojto 104:b9ad9a133dc7 6970 /* Register: WDT_INTENSET */
Kojto 104:b9ad9a133dc7 6971 /* Description: Interrupt enable set register. */
Kojto 104:b9ad9a133dc7 6972
Kojto 104:b9ad9a133dc7 6973 /* Bit 0 : Enable interrupt on TIMEOUT event. */
Kojto 104:b9ad9a133dc7 6974 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
Kojto 104:b9ad9a133dc7 6975 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
Kojto 104:b9ad9a133dc7 6976 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6977 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6978 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 104:b9ad9a133dc7 6979
Kojto 104:b9ad9a133dc7 6980 /* Register: WDT_INTENCLR */
Kojto 104:b9ad9a133dc7 6981 /* Description: Interrupt enable clear register. */
Kojto 104:b9ad9a133dc7 6982
Kojto 104:b9ad9a133dc7 6983 /* Bit 0 : Disable interrupt on TIMEOUT event. */
Kojto 104:b9ad9a133dc7 6984 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
Kojto 104:b9ad9a133dc7 6985 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
Kojto 104:b9ad9a133dc7 6986 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 104:b9ad9a133dc7 6987 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 104:b9ad9a133dc7 6988 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 104:b9ad9a133dc7 6989
Kojto 104:b9ad9a133dc7 6990 /* Register: WDT_RUNSTATUS */
Kojto 104:b9ad9a133dc7 6991 /* Description: Watchdog running status. */
Kojto 104:b9ad9a133dc7 6992
Kojto 104:b9ad9a133dc7 6993 /* Bit 0 : Watchdog running status. */
Kojto 104:b9ad9a133dc7 6994 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
Kojto 104:b9ad9a133dc7 6995 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
Kojto 104:b9ad9a133dc7 6996 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
Kojto 104:b9ad9a133dc7 6997 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
Kojto 104:b9ad9a133dc7 6998
Kojto 104:b9ad9a133dc7 6999 /* Register: WDT_REQSTATUS */
Kojto 104:b9ad9a133dc7 7000 /* Description: Request status. */
Kojto 104:b9ad9a133dc7 7001
Kojto 104:b9ad9a133dc7 7002 /* Bit 7 : Request status for RR[7]. */
Kojto 104:b9ad9a133dc7 7003 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
Kojto 104:b9ad9a133dc7 7004 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
Kojto 104:b9ad9a133dc7 7005 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7006 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7007
Kojto 104:b9ad9a133dc7 7008 /* Bit 6 : Request status for RR[6]. */
Kojto 104:b9ad9a133dc7 7009 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
Kojto 104:b9ad9a133dc7 7010 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
Kojto 104:b9ad9a133dc7 7011 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7012 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7013
Kojto 104:b9ad9a133dc7 7014 /* Bit 5 : Request status for RR[5]. */
Kojto 104:b9ad9a133dc7 7015 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
Kojto 104:b9ad9a133dc7 7016 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
Kojto 104:b9ad9a133dc7 7017 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7018 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7019
Kojto 104:b9ad9a133dc7 7020 /* Bit 4 : Request status for RR[4]. */
Kojto 104:b9ad9a133dc7 7021 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
Kojto 104:b9ad9a133dc7 7022 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
Kojto 104:b9ad9a133dc7 7023 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7024 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7025
Kojto 104:b9ad9a133dc7 7026 /* Bit 3 : Request status for RR[3]. */
Kojto 104:b9ad9a133dc7 7027 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
Kojto 104:b9ad9a133dc7 7028 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
Kojto 104:b9ad9a133dc7 7029 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7030 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7031
Kojto 104:b9ad9a133dc7 7032 /* Bit 2 : Request status for RR[2]. */
Kojto 104:b9ad9a133dc7 7033 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
Kojto 104:b9ad9a133dc7 7034 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
Kojto 104:b9ad9a133dc7 7035 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7036 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7037
Kojto 104:b9ad9a133dc7 7038 /* Bit 1 : Request status for RR[1]. */
Kojto 104:b9ad9a133dc7 7039 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
Kojto 104:b9ad9a133dc7 7040 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
Kojto 104:b9ad9a133dc7 7041 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7042 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7043
Kojto 104:b9ad9a133dc7 7044 /* Bit 0 : Request status for RR[0]. */
Kojto 104:b9ad9a133dc7 7045 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
Kojto 104:b9ad9a133dc7 7046 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
Kojto 104:b9ad9a133dc7 7047 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
Kojto 104:b9ad9a133dc7 7048 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
Kojto 104:b9ad9a133dc7 7049
Kojto 104:b9ad9a133dc7 7050 /* Register: WDT_RREN */
Kojto 104:b9ad9a133dc7 7051 /* Description: Reload request enable. */
Kojto 104:b9ad9a133dc7 7052
Kojto 104:b9ad9a133dc7 7053 /* Bit 7 : Enable or disable RR[7] register. */
Kojto 104:b9ad9a133dc7 7054 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
Kojto 104:b9ad9a133dc7 7055 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
Kojto 104:b9ad9a133dc7 7056 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
Kojto 104:b9ad9a133dc7 7057 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
Kojto 104:b9ad9a133dc7 7058
Kojto 104:b9ad9a133dc7 7059 /* Bit 6 : Enable or disable RR[6] register. */
Kojto 104:b9ad9a133dc7 7060 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
Kojto 104:b9ad9a133dc7 7061 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
Kojto 104:b9ad9a133dc7 7062 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
Kojto 104:b9ad9a133dc7 7063 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
Kojto 104:b9ad9a133dc7 7064
Kojto 104:b9ad9a133dc7 7065 /* Bit 5 : Enable or disable RR[5] register. */
Kojto 104:b9ad9a133dc7 7066 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
Kojto 104:b9ad9a133dc7 7067 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
Kojto 104:b9ad9a133dc7 7068 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
Kojto 104:b9ad9a133dc7 7069 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
Kojto 104:b9ad9a133dc7 7070
Kojto 104:b9ad9a133dc7 7071 /* Bit 4 : Enable or disable RR[4] register. */
Kojto 104:b9ad9a133dc7 7072 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
Kojto 104:b9ad9a133dc7 7073 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
Kojto 104:b9ad9a133dc7 7074 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
Kojto 104:b9ad9a133dc7 7075 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
Kojto 104:b9ad9a133dc7 7076
Kojto 104:b9ad9a133dc7 7077 /* Bit 3 : Enable or disable RR[3] register. */
Kojto 104:b9ad9a133dc7 7078 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
Kojto 104:b9ad9a133dc7 7079 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
Kojto 104:b9ad9a133dc7 7080 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
Kojto 104:b9ad9a133dc7 7081 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
Kojto 104:b9ad9a133dc7 7082
Kojto 104:b9ad9a133dc7 7083 /* Bit 2 : Enable or disable RR[2] register. */
Kojto 104:b9ad9a133dc7 7084 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
Kojto 104:b9ad9a133dc7 7085 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
Kojto 104:b9ad9a133dc7 7086 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
Kojto 104:b9ad9a133dc7 7087 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
Kojto 104:b9ad9a133dc7 7088
Kojto 104:b9ad9a133dc7 7089 /* Bit 1 : Enable or disable RR[1] register. */
Kojto 104:b9ad9a133dc7 7090 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
Kojto 104:b9ad9a133dc7 7091 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
Kojto 104:b9ad9a133dc7 7092 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
Kojto 104:b9ad9a133dc7 7093 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
Kojto 104:b9ad9a133dc7 7094
Kojto 104:b9ad9a133dc7 7095 /* Bit 0 : Enable or disable RR[0] register. */
Kojto 104:b9ad9a133dc7 7096 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
Kojto 104:b9ad9a133dc7 7097 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
Kojto 104:b9ad9a133dc7 7098 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
Kojto 104:b9ad9a133dc7 7099 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
Kojto 104:b9ad9a133dc7 7100
Kojto 104:b9ad9a133dc7 7101 /* Register: WDT_CONFIG */
Kojto 104:b9ad9a133dc7 7102 /* Description: Configuration register. */
Kojto 104:b9ad9a133dc7 7103
Kojto 104:b9ad9a133dc7 7104 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
Kojto 104:b9ad9a133dc7 7105 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
Kojto 104:b9ad9a133dc7 7106 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
Kojto 104:b9ad9a133dc7 7107 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
Kojto 104:b9ad9a133dc7 7108 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
Kojto 104:b9ad9a133dc7 7109
Kojto 104:b9ad9a133dc7 7110 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
Kojto 104:b9ad9a133dc7 7111 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
Kojto 104:b9ad9a133dc7 7112 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
Kojto 104:b9ad9a133dc7 7113 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
Kojto 104:b9ad9a133dc7 7114 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
Kojto 104:b9ad9a133dc7 7115
Kojto 104:b9ad9a133dc7 7116 /* Register: WDT_RR */
Kojto 104:b9ad9a133dc7 7117 /* Description: Reload requests registers. */
Kojto 104:b9ad9a133dc7 7118
Kojto 104:b9ad9a133dc7 7119 /* Bits 31..0 : Reload register. */
Kojto 104:b9ad9a133dc7 7120 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
Kojto 104:b9ad9a133dc7 7121 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
Kojto 104:b9ad9a133dc7 7122 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
Kojto 104:b9ad9a133dc7 7123
Kojto 104:b9ad9a133dc7 7124 /* Register: WDT_POWER */
Kojto 104:b9ad9a133dc7 7125 /* Description: Peripheral power control. */
Kojto 104:b9ad9a133dc7 7126
Kojto 104:b9ad9a133dc7 7127 /* Bit 0 : Peripheral power control. */
Kojto 104:b9ad9a133dc7 7128 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 104:b9ad9a133dc7 7129 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 104:b9ad9a133dc7 7130 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 104:b9ad9a133dc7 7131 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 104:b9ad9a133dc7 7132
Kojto 104:b9ad9a133dc7 7133
Kojto 104:b9ad9a133dc7 7134 /*lint --flb "Leave library region" */
Kojto 104:b9ad9a133dc7 7135 #endif