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TARGET_MTS_MDOT_F411RE/stm32f411xe.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
106:ba1f97679dad 
.

Who changed what in which revision?

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Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f411xe.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V2.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
Kojto 93:e188a91d3eaa 7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
Kojto 93:e188a91d3eaa 8 *
Kojto 93:e188a91d3eaa 9 * This file contains:
Kojto 93:e188a91d3eaa 10 * - Data structures and the address mapping for all peripherals
Kojto 93:e188a91d3eaa 11 * - Peripheral's registers declarations and bits definition
Kojto 99:dbbf35b96557 12 * - Macros to access peripheral’s registers hardware
Kojto 93:e188a91d3eaa 13 *
Kojto 93:e188a91d3eaa 14 ******************************************************************************
Kojto 93:e188a91d3eaa 15 * @attention
Kojto 93:e188a91d3eaa 16 *
Kojto 99:dbbf35b96557 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 18 *
Kojto 93:e188a91d3eaa 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 20 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 22 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 24 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 25 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 27 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 28 * without specific prior written permission.
Kojto 93:e188a91d3eaa 29 *
Kojto 93:e188a91d3eaa 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 40 *
Kojto 93:e188a91d3eaa 41 ******************************************************************************
Kojto 93:e188a91d3eaa 42 */
Kojto 93:e188a91d3eaa 43
Kojto 93:e188a91d3eaa 44 /** @addtogroup CMSIS
Kojto 93:e188a91d3eaa 45 * @{
Kojto 93:e188a91d3eaa 46 */
Kojto 93:e188a91d3eaa 47
Kojto 99:dbbf35b96557 48 /** @addtogroup stm32f401xe
Kojto 93:e188a91d3eaa 49 * @{
Kojto 93:e188a91d3eaa 50 */
Kojto 93:e188a91d3eaa 51
Kojto 99:dbbf35b96557 52 #ifndef __STM32F401xE_H
Kojto 99:dbbf35b96557 53 #define __STM32F401xE_H
Kojto 93:e188a91d3eaa 54
Kojto 93:e188a91d3eaa 55 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 56 extern "C" {
Kojto 93:e188a91d3eaa 57 #endif /* __cplusplus */
Kojto 93:e188a91d3eaa 58
Kojto 93:e188a91d3eaa 59
Kojto 93:e188a91d3eaa 60 /** @addtogroup Configuration_section_for_CMSIS
Kojto 93:e188a91d3eaa 61 * @{
Kojto 93:e188a91d3eaa 62 */
Kojto 93:e188a91d3eaa 63
Kojto 93:e188a91d3eaa 64 /**
Kojto 93:e188a91d3eaa 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 93:e188a91d3eaa 66 */
Kojto 93:e188a91d3eaa 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
Kojto 93:e188a91d3eaa 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
Kojto 93:e188a91d3eaa 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 93:e188a91d3eaa 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 93:e188a91d3eaa 71 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 93:e188a91d3eaa 72
Kojto 93:e188a91d3eaa 73 /**
Kojto 93:e188a91d3eaa 74 * @}
Kojto 93:e188a91d3eaa 75 */
Kojto 93:e188a91d3eaa 76
Kojto 93:e188a91d3eaa 77 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 93:e188a91d3eaa 78 * @{
Kojto 93:e188a91d3eaa 79 */
Kojto 93:e188a91d3eaa 80
Kojto 93:e188a91d3eaa 81 /**
Kojto 93:e188a91d3eaa 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto 93:e188a91d3eaa 83 * in @ref Library_configuration_section
Kojto 93:e188a91d3eaa 84 */
Kojto 93:e188a91d3eaa 85 typedef enum
Kojto 93:e188a91d3eaa 86 {
Kojto 93:e188a91d3eaa 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 93:e188a91d3eaa 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 93:e188a91d3eaa 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 93:e188a91d3eaa 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 93:e188a91d3eaa 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 93:e188a91d3eaa 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 93:e188a91d3eaa 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 93:e188a91d3eaa 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 93:e188a91d3eaa 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 93:e188a91d3eaa 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 93:e188a91d3eaa 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 93:e188a91d3eaa 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 93:e188a91d3eaa 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 93:e188a91d3eaa 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 93:e188a91d3eaa 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 93:e188a91d3eaa 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 93:e188a91d3eaa 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 93:e188a91d3eaa 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 93:e188a91d3eaa 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 93:e188a91d3eaa 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 93:e188a91d3eaa 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 93:e188a91d3eaa 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 93:e188a91d3eaa 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 93:e188a91d3eaa 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 93:e188a91d3eaa 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 93:e188a91d3eaa 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 93:e188a91d3eaa 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 93:e188a91d3eaa 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 93:e188a91d3eaa 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 93:e188a91d3eaa 116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 93:e188a91d3eaa 117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 93:e188a91d3eaa 118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 93:e188a91d3eaa 119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 93:e188a91d3eaa 120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 93:e188a91d3eaa 121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 93:e188a91d3eaa 122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 93:e188a91d3eaa 123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 93:e188a91d3eaa 124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 93:e188a91d3eaa 125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 93:e188a91d3eaa 126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 93:e188a91d3eaa 127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 93:e188a91d3eaa 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 93:e188a91d3eaa 129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 93:e188a91d3eaa 130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 93:e188a91d3eaa 131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 93:e188a91d3eaa 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 93:e188a91d3eaa 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 93:e188a91d3eaa 134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 93:e188a91d3eaa 135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 93:e188a91d3eaa 136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
Kojto 93:e188a91d3eaa 137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 93:e188a91d3eaa 138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 93:e188a91d3eaa 139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 93:e188a91d3eaa 140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 93:e188a91d3eaa 141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 93:e188a91d3eaa 142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 93:e188a91d3eaa 143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 93:e188a91d3eaa 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 93:e188a91d3eaa 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 93:e188a91d3eaa 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 93:e188a91d3eaa 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 93:e188a91d3eaa 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 93:e188a91d3eaa 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 93:e188a91d3eaa 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 93:e188a91d3eaa 151 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 93:e188a91d3eaa 152 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 93:e188a91d3eaa 153 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
Kojto 93:e188a91d3eaa 154 } IRQn_Type;
Kojto 93:e188a91d3eaa 155
Kojto 93:e188a91d3eaa 156 /**
Kojto 93:e188a91d3eaa 157 * @}
Kojto 93:e188a91d3eaa 158 */
Kojto 93:e188a91d3eaa 159
Kojto 93:e188a91d3eaa 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 93:e188a91d3eaa 161 #include "system_stm32f4xx.h"
Kojto 93:e188a91d3eaa 162 #include <stdint.h>
Kojto 93:e188a91d3eaa 163
Kojto 93:e188a91d3eaa 164 /** @addtogroup Peripheral_registers_structures
Kojto 93:e188a91d3eaa 165 * @{
Kojto 93:e188a91d3eaa 166 */
Kojto 93:e188a91d3eaa 167
Kojto 93:e188a91d3eaa 168 /**
Kojto 93:e188a91d3eaa 169 * @brief Analog to Digital Converter
Kojto 93:e188a91d3eaa 170 */
Kojto 93:e188a91d3eaa 171
Kojto 93:e188a91d3eaa 172 typedef struct
Kojto 93:e188a91d3eaa 173 {
Kojto 93:e188a91d3eaa 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 93:e188a91d3eaa 189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 93:e188a91d3eaa 194 } ADC_TypeDef;
Kojto 93:e188a91d3eaa 195
Kojto 93:e188a91d3eaa 196 typedef struct
Kojto 93:e188a91d3eaa 197 {
Kojto 93:e188a91d3eaa 198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 93:e188a91d3eaa 199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 93:e188a91d3eaa 200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 93:e188a91d3eaa 201 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 93:e188a91d3eaa 202 } ADC_Common_TypeDef;
Kojto 93:e188a91d3eaa 203
Kojto 93:e188a91d3eaa 204 /**
Kojto 93:e188a91d3eaa 205 * @brief CRC calculation unit
Kojto 93:e188a91d3eaa 206 */
Kojto 93:e188a91d3eaa 207
Kojto 93:e188a91d3eaa 208 typedef struct
Kojto 93:e188a91d3eaa 209 {
Kojto 93:e188a91d3eaa 210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 93:e188a91d3eaa 213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 93:e188a91d3eaa 214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 215 } CRC_TypeDef;
Kojto 93:e188a91d3eaa 216
Kojto 93:e188a91d3eaa 217 /**
Kojto 93:e188a91d3eaa 218 * @brief Debug MCU
Kojto 93:e188a91d3eaa 219 */
Kojto 93:e188a91d3eaa 220
Kojto 93:e188a91d3eaa 221 typedef struct
Kojto 93:e188a91d3eaa 222 {
Kojto 93:e188a91d3eaa 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 227 }DBGMCU_TypeDef;
Kojto 93:e188a91d3eaa 228
Kojto 93:e188a91d3eaa 229
Kojto 93:e188a91d3eaa 230 /**
Kojto 93:e188a91d3eaa 231 * @brief DMA Controller
Kojto 93:e188a91d3eaa 232 */
Kojto 93:e188a91d3eaa 233
Kojto 93:e188a91d3eaa 234 typedef struct
Kojto 93:e188a91d3eaa 235 {
Kojto 93:e188a91d3eaa 236 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 93:e188a91d3eaa 237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 93:e188a91d3eaa 238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 93:e188a91d3eaa 239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 93:e188a91d3eaa 240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 93:e188a91d3eaa 241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 93:e188a91d3eaa 242 } DMA_Stream_TypeDef;
Kojto 93:e188a91d3eaa 243
Kojto 93:e188a91d3eaa 244 typedef struct
Kojto 93:e188a91d3eaa 245 {
Kojto 93:e188a91d3eaa 246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 250 } DMA_TypeDef;
Kojto 93:e188a91d3eaa 251
Kojto 93:e188a91d3eaa 252
Kojto 93:e188a91d3eaa 253 /**
Kojto 93:e188a91d3eaa 254 * @brief External Interrupt/Event Controller
Kojto 93:e188a91d3eaa 255 */
Kojto 93:e188a91d3eaa 256
Kojto 93:e188a91d3eaa 257 typedef struct
Kojto 93:e188a91d3eaa 258 {
Kojto 93:e188a91d3eaa 259 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 260 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 261 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 262 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 263 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 264 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 265 } EXTI_TypeDef;
Kojto 93:e188a91d3eaa 266
Kojto 93:e188a91d3eaa 267 /**
Kojto 93:e188a91d3eaa 268 * @brief FLASH Registers
Kojto 93:e188a91d3eaa 269 */
Kojto 93:e188a91d3eaa 270
Kojto 93:e188a91d3eaa 271 typedef struct
Kojto 93:e188a91d3eaa 272 {
Kojto 93:e188a91d3eaa 273 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 274 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 275 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 276 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 277 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 278 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 93:e188a91d3eaa 279 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 280 } FLASH_TypeDef;
Kojto 93:e188a91d3eaa 281
Kojto 93:e188a91d3eaa 282 /**
Kojto 93:e188a91d3eaa 283 * @brief General Purpose I/O
Kojto 93:e188a91d3eaa 284 */
Kojto 93:e188a91d3eaa 285
Kojto 93:e188a91d3eaa 286 typedef struct
Kojto 93:e188a91d3eaa 287 {
Kojto 93:e188a91d3eaa 288 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 289 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 290 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 291 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 292 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 293 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 294 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 295 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 296 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 93:e188a91d3eaa 297 } GPIO_TypeDef;
Kojto 93:e188a91d3eaa 298
Kojto 93:e188a91d3eaa 299 /**
Kojto 93:e188a91d3eaa 300 * @brief System configuration controller
Kojto 93:e188a91d3eaa 301 */
Kojto 93:e188a91d3eaa 302
Kojto 93:e188a91d3eaa 303 typedef struct
Kojto 93:e188a91d3eaa 304 {
Kojto 93:e188a91d3eaa 305 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 306 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 307 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 93:e188a91d3eaa 308 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 93:e188a91d3eaa 309 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 310 } SYSCFG_TypeDef;
Kojto 93:e188a91d3eaa 311
Kojto 93:e188a91d3eaa 312 /**
Kojto 93:e188a91d3eaa 313 * @brief Inter-integrated Circuit Interface
Kojto 93:e188a91d3eaa 314 */
Kojto 93:e188a91d3eaa 315
Kojto 93:e188a91d3eaa 316 typedef struct
Kojto 93:e188a91d3eaa 317 {
Kojto 93:e188a91d3eaa 318 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 319 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 320 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 321 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 322 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 323 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 324 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 325 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 326 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 327 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 328 } I2C_TypeDef;
Kojto 93:e188a91d3eaa 329
Kojto 93:e188a91d3eaa 330 /**
Kojto 93:e188a91d3eaa 331 * @brief Independent WATCHDOG
Kojto 93:e188a91d3eaa 332 */
Kojto 93:e188a91d3eaa 333
Kojto 93:e188a91d3eaa 334 typedef struct
Kojto 93:e188a91d3eaa 335 {
Kojto 93:e188a91d3eaa 336 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 337 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 338 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 339 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 340 } IWDG_TypeDef;
Kojto 93:e188a91d3eaa 341
Kojto 93:e188a91d3eaa 342 /**
Kojto 93:e188a91d3eaa 343 * @brief Power Control
Kojto 93:e188a91d3eaa 344 */
Kojto 93:e188a91d3eaa 345
Kojto 93:e188a91d3eaa 346 typedef struct
Kojto 93:e188a91d3eaa 347 {
Kojto 93:e188a91d3eaa 348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 350 } PWR_TypeDef;
Kojto 93:e188a91d3eaa 351
Kojto 93:e188a91d3eaa 352 /**
Kojto 93:e188a91d3eaa 353 * @brief Reset and Clock Control
Kojto 93:e188a91d3eaa 354 */
Kojto 93:e188a91d3eaa 355
Kojto 93:e188a91d3eaa 356 typedef struct
Kojto 93:e188a91d3eaa 357 {
Kojto 93:e188a91d3eaa 358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 93:e188a91d3eaa 366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 93:e188a91d3eaa 369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 93:e188a91d3eaa 373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 93:e188a91d3eaa 376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 93:e188a91d3eaa 378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 93:e188a91d3eaa 379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 93:e188a91d3eaa 380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 93:e188a91d3eaa 381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 93:e188a91d3eaa 382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 93:e188a91d3eaa 383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 93:e188a91d3eaa 384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 93:e188a91d3eaa 385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 93:e188a91d3eaa 386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 93:e188a91d3eaa 387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 93:e188a91d3eaa 388
Kojto 93:e188a91d3eaa 389 } RCC_TypeDef;
Kojto 93:e188a91d3eaa 390
Kojto 93:e188a91d3eaa 391 /**
Kojto 93:e188a91d3eaa 392 * @brief Real-Time Clock
Kojto 93:e188a91d3eaa 393 */
Kojto 93:e188a91d3eaa 394
Kojto 93:e188a91d3eaa 395 typedef struct
Kojto 93:e188a91d3eaa 396 {
Kojto 93:e188a91d3eaa 397 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 398 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 399 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 400 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 401 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 402 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 403 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 404 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 405 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 406 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 407 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 408 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 409 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 410 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 411 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 412 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 413 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 414 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 415 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 416 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 93:e188a91d3eaa 417 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 418 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 93:e188a91d3eaa 419 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 93:e188a91d3eaa 420 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 93:e188a91d3eaa 421 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 93:e188a91d3eaa 422 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 93:e188a91d3eaa 423 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 93:e188a91d3eaa 424 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 93:e188a91d3eaa 425 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 93:e188a91d3eaa 426 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 93:e188a91d3eaa 427 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 93:e188a91d3eaa 428 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 93:e188a91d3eaa 429 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 93:e188a91d3eaa 430 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 93:e188a91d3eaa 431 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 93:e188a91d3eaa 432 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 93:e188a91d3eaa 433 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 93:e188a91d3eaa 434 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 93:e188a91d3eaa 435 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 93:e188a91d3eaa 436 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 93:e188a91d3eaa 437 } RTC_TypeDef;
Kojto 93:e188a91d3eaa 438
Kojto 93:e188a91d3eaa 439
Kojto 93:e188a91d3eaa 440 /**
Kojto 93:e188a91d3eaa 441 * @brief SD host Interface
Kojto 93:e188a91d3eaa 442 */
Kojto 93:e188a91d3eaa 443
Kojto 93:e188a91d3eaa 444 typedef struct
Kojto 93:e188a91d3eaa 445 {
Kojto 93:e188a91d3eaa 446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 450 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 451 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 452 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 453 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 454 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 458 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 459 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 93:e188a91d3eaa 463 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 93:e188a91d3eaa 465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
Kojto 93:e188a91d3eaa 466 } SDIO_TypeDef;
Kojto 93:e188a91d3eaa 467
Kojto 93:e188a91d3eaa 468 /**
Kojto 93:e188a91d3eaa 469 * @brief Serial Peripheral Interface
Kojto 93:e188a91d3eaa 470 */
Kojto 93:e188a91d3eaa 471
Kojto 93:e188a91d3eaa 472 typedef struct
Kojto 93:e188a91d3eaa 473 {
Kojto 93:e188a91d3eaa 474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 93:e188a91d3eaa 475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 93:e188a91d3eaa 479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 93:e188a91d3eaa 480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 93:e188a91d3eaa 481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 483 } SPI_TypeDef;
Kojto 93:e188a91d3eaa 484
Kojto 93:e188a91d3eaa 485 /**
Kojto 93:e188a91d3eaa 486 * @brief TIM
Kojto 93:e188a91d3eaa 487 */
Kojto 93:e188a91d3eaa 488
Kojto 93:e188a91d3eaa 489 typedef struct
Kojto 93:e188a91d3eaa 490 {
Kojto 93:e188a91d3eaa 491 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 492 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 493 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 494 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 495 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 496 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 497 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 498 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 499 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 93:e188a91d3eaa 500 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 93:e188a91d3eaa 501 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 93:e188a91d3eaa 502 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 93:e188a91d3eaa 503 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 93:e188a91d3eaa 504 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 93:e188a91d3eaa 505 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 93:e188a91d3eaa 506 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 93:e188a91d3eaa 507 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 93:e188a91d3eaa 508 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 93:e188a91d3eaa 509 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 93:e188a91d3eaa 510 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 93:e188a91d3eaa 511 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 93:e188a91d3eaa 512 } TIM_TypeDef;
Kojto 93:e188a91d3eaa 513
Kojto 93:e188a91d3eaa 514 /**
Kojto 93:e188a91d3eaa 515 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 93:e188a91d3eaa 516 */
Kojto 93:e188a91d3eaa 517
Kojto 93:e188a91d3eaa 518 typedef struct
Kojto 93:e188a91d3eaa 519 {
Kojto 93:e188a91d3eaa 520 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 521 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 522 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 523 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 524 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 93:e188a91d3eaa 525 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 93:e188a91d3eaa 526 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 93:e188a91d3eaa 527 } USART_TypeDef;
Kojto 93:e188a91d3eaa 528
Kojto 93:e188a91d3eaa 529 /**
Kojto 93:e188a91d3eaa 530 * @brief Window WATCHDOG
Kojto 93:e188a91d3eaa 531 */
Kojto 93:e188a91d3eaa 532
Kojto 93:e188a91d3eaa 533 typedef struct
Kojto 93:e188a91d3eaa 534 {
Kojto 93:e188a91d3eaa 535 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 93:e188a91d3eaa 536 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 537 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 538 } WWDG_TypeDef;
Kojto 93:e188a91d3eaa 539
Kojto 93:e188a91d3eaa 540
Kojto 93:e188a91d3eaa 541 /**
Kojto 93:e188a91d3eaa 542 * @brief __USB_OTG_Core_register
Kojto 93:e188a91d3eaa 543 */
Kojto 93:e188a91d3eaa 544 typedef struct
Kojto 93:e188a91d3eaa 545 {
Kojto 93:e188a91d3eaa 546 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
Kojto 93:e188a91d3eaa 547 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
Kojto 93:e188a91d3eaa 548 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
Kojto 93:e188a91d3eaa 549 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
Kojto 93:e188a91d3eaa 550 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
Kojto 93:e188a91d3eaa 551 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
Kojto 93:e188a91d3eaa 552 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
Kojto 93:e188a91d3eaa 553 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
Kojto 93:e188a91d3eaa 554 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
Kojto 93:e188a91d3eaa 555 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
Kojto 93:e188a91d3eaa 556 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
Kojto 93:e188a91d3eaa 557 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
Kojto 93:e188a91d3eaa 558 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
Kojto 93:e188a91d3eaa 559 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
Kojto 93:e188a91d3eaa 560 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
Kojto 93:e188a91d3eaa 561 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
Kojto 93:e188a91d3eaa 562 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
Kojto 93:e188a91d3eaa 563 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 93:e188a91d3eaa 564 }
Kojto 93:e188a91d3eaa 565 USB_OTG_GlobalTypeDef;
Kojto 93:e188a91d3eaa 566
Kojto 93:e188a91d3eaa 567
Kojto 93:e188a91d3eaa 568
Kojto 93:e188a91d3eaa 569 /**
Kojto 93:e188a91d3eaa 570 * @brief __device_Registers
Kojto 93:e188a91d3eaa 571 */
Kojto 93:e188a91d3eaa 572 typedef struct
Kojto 93:e188a91d3eaa 573 {
Kojto 93:e188a91d3eaa 574 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
Kojto 93:e188a91d3eaa 575 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
Kojto 93:e188a91d3eaa 576 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
Kojto 93:e188a91d3eaa 577 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
Kojto 93:e188a91d3eaa 578 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
Kojto 93:e188a91d3eaa 579 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
Kojto 93:e188a91d3eaa 580 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
Kojto 93:e188a91d3eaa 581 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
Kojto 93:e188a91d3eaa 582 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
Kojto 93:e188a91d3eaa 583 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
Kojto 93:e188a91d3eaa 584 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
Kojto 93:e188a91d3eaa 585 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
Kojto 93:e188a91d3eaa 586 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
Kojto 93:e188a91d3eaa 587 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
Kojto 93:e188a91d3eaa 588 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
Kojto 93:e188a91d3eaa 589 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
Kojto 93:e188a91d3eaa 590 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
Kojto 93:e188a91d3eaa 591 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
Kojto 93:e188a91d3eaa 592 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
Kojto 93:e188a91d3eaa 593 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
Kojto 93:e188a91d3eaa 594 }
Kojto 93:e188a91d3eaa 595 USB_OTG_DeviceTypeDef;
Kojto 93:e188a91d3eaa 596
Kojto 93:e188a91d3eaa 597
Kojto 93:e188a91d3eaa 598 /**
Kojto 93:e188a91d3eaa 599 * @brief __IN_Endpoint-Specific_Register
Kojto 93:e188a91d3eaa 600 */
Kojto 93:e188a91d3eaa 601 typedef struct
Kojto 93:e188a91d3eaa 602 {
Kojto 93:e188a91d3eaa 603 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 93:e188a91d3eaa 604 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
Kojto 93:e188a91d3eaa 605 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 93:e188a91d3eaa 606 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 93:e188a91d3eaa 607 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 93:e188a91d3eaa 608 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 93:e188a91d3eaa 609 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 93:e188a91d3eaa 610 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 93:e188a91d3eaa 611 }
Kojto 93:e188a91d3eaa 612 USB_OTG_INEndpointTypeDef;
Kojto 93:e188a91d3eaa 613
Kojto 93:e188a91d3eaa 614
Kojto 93:e188a91d3eaa 615 /**
Kojto 93:e188a91d3eaa 616 * @brief __OUT_Endpoint-Specific_Registers
Kojto 93:e188a91d3eaa 617 */
Kojto 93:e188a91d3eaa 618 typedef struct
Kojto 93:e188a91d3eaa 619 {
Kojto 93:e188a91d3eaa 620 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
Kojto 93:e188a91d3eaa 621 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
Kojto 93:e188a91d3eaa 622 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
Kojto 93:e188a91d3eaa 623 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
Kojto 93:e188a91d3eaa 624 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
Kojto 93:e188a91d3eaa 625 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
Kojto 93:e188a91d3eaa 626 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
Kojto 93:e188a91d3eaa 627 }
Kojto 93:e188a91d3eaa 628 USB_OTG_OUTEndpointTypeDef;
Kojto 93:e188a91d3eaa 629
Kojto 93:e188a91d3eaa 630
Kojto 93:e188a91d3eaa 631 /**
Kojto 93:e188a91d3eaa 632 * @brief __Host_Mode_Register_Structures
Kojto 93:e188a91d3eaa 633 */
Kojto 93:e188a91d3eaa 634 typedef struct
Kojto 93:e188a91d3eaa 635 {
Kojto 93:e188a91d3eaa 636 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
Kojto 93:e188a91d3eaa 637 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
Kojto 93:e188a91d3eaa 638 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
Kojto 93:e188a91d3eaa 639 uint32_t Reserved40C; /* Reserved 40Ch*/
Kojto 93:e188a91d3eaa 640 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
Kojto 93:e188a91d3eaa 641 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
Kojto 93:e188a91d3eaa 642 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
Kojto 93:e188a91d3eaa 643 }
Kojto 93:e188a91d3eaa 644 USB_OTG_HostTypeDef;
Kojto 93:e188a91d3eaa 645
Kojto 93:e188a91d3eaa 646
Kojto 93:e188a91d3eaa 647 /**
Kojto 93:e188a91d3eaa 648 * @brief __Host_Channel_Specific_Registers
Kojto 93:e188a91d3eaa 649 */
Kojto 93:e188a91d3eaa 650 typedef struct
Kojto 93:e188a91d3eaa 651 {
Kojto 93:e188a91d3eaa 652 __IO uint32_t HCCHAR;
Kojto 93:e188a91d3eaa 653 __IO uint32_t HCSPLT;
Kojto 93:e188a91d3eaa 654 __IO uint32_t HCINT;
Kojto 93:e188a91d3eaa 655 __IO uint32_t HCINTMSK;
Kojto 93:e188a91d3eaa 656 __IO uint32_t HCTSIZ;
Kojto 93:e188a91d3eaa 657 __IO uint32_t HCDMA;
Kojto 93:e188a91d3eaa 658 uint32_t Reserved[2];
Kojto 93:e188a91d3eaa 659 }
Kojto 93:e188a91d3eaa 660 USB_OTG_HostChannelTypeDef;
Kojto 93:e188a91d3eaa 661
Kojto 93:e188a91d3eaa 662
Kojto 93:e188a91d3eaa 663 /**
Kojto 93:e188a91d3eaa 664 * @brief Peripheral_memory_map
Kojto 93:e188a91d3eaa 665 */
Kojto 93:e188a91d3eaa 666 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 93:e188a91d3eaa 667 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
Kojto 93:e188a91d3eaa 668 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
Kojto 93:e188a91d3eaa 669 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
Kojto 93:e188a91d3eaa 670 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 93:e188a91d3eaa 671 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 93:e188a91d3eaa 672 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
Kojto 106:ba1f97679dad 673 #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
Kojto 93:e188a91d3eaa 674 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
Kojto 106:ba1f97679dad 675 #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 93:e188a91d3eaa 676 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
Kojto 93:e188a91d3eaa 677
Kojto 93:e188a91d3eaa 678 /* Legacy defines */
Kojto 93:e188a91d3eaa 679 #define SRAM_BASE SRAM1_BASE
Kojto 93:e188a91d3eaa 680 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 93:e188a91d3eaa 681
Kojto 93:e188a91d3eaa 682
Kojto 93:e188a91d3eaa 683 /*!< Peripheral memory map */
Kojto 93:e188a91d3eaa 684 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 93:e188a91d3eaa 685 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto 93:e188a91d3eaa 686 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 93:e188a91d3eaa 687 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 93:e188a91d3eaa 688
Kojto 93:e188a91d3eaa 689 /*!< APB1 peripherals */
Kojto 93:e188a91d3eaa 690 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto 93:e188a91d3eaa 691 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto 93:e188a91d3eaa 692 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto 93:e188a91d3eaa 693 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Kojto 93:e188a91d3eaa 694 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto 93:e188a91d3eaa 695 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto 93:e188a91d3eaa 696 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto 93:e188a91d3eaa 697 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
Kojto 93:e188a91d3eaa 698 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto 93:e188a91d3eaa 699 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Kojto 93:e188a91d3eaa 700 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
Kojto 93:e188a91d3eaa 701 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto 93:e188a91d3eaa 702 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto 93:e188a91d3eaa 703 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto 93:e188a91d3eaa 704 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
Kojto 93:e188a91d3eaa 705 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto 93:e188a91d3eaa 706
Kojto 93:e188a91d3eaa 707 /*!< APB2 peripherals */
Kojto 93:e188a91d3eaa 708 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
Kojto 93:e188a91d3eaa 709 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
Kojto 93:e188a91d3eaa 710 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
Kojto 93:e188a91d3eaa 711 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
Kojto 93:e188a91d3eaa 712 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
Kojto 93:e188a91d3eaa 713 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto 93:e188a91d3eaa 714 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto 93:e188a91d3eaa 715 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
Kojto 93:e188a91d3eaa 716 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
Kojto 93:e188a91d3eaa 717 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
Kojto 93:e188a91d3eaa 718 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
Kojto 93:e188a91d3eaa 719 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
Kojto 93:e188a91d3eaa 720 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
Kojto 93:e188a91d3eaa 721 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
Kojto 93:e188a91d3eaa 722
Kojto 93:e188a91d3eaa 723 /*!< AHB1 peripherals */
Kojto 93:e188a91d3eaa 724 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
Kojto 93:e188a91d3eaa 725 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
Kojto 93:e188a91d3eaa 726 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
Kojto 93:e188a91d3eaa 727 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
Kojto 93:e188a91d3eaa 728 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
Kojto 93:e188a91d3eaa 729 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
Kojto 93:e188a91d3eaa 730 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
Kojto 93:e188a91d3eaa 731 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
Kojto 93:e188a91d3eaa 732 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
Kojto 93:e188a91d3eaa 733 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
Kojto 93:e188a91d3eaa 734 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
Kojto 93:e188a91d3eaa 735 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
Kojto 93:e188a91d3eaa 736 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
Kojto 93:e188a91d3eaa 737 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
Kojto 93:e188a91d3eaa 738 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
Kojto 93:e188a91d3eaa 739 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
Kojto 93:e188a91d3eaa 740 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
Kojto 93:e188a91d3eaa 741 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
Kojto 93:e188a91d3eaa 742 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
Kojto 93:e188a91d3eaa 743 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
Kojto 93:e188a91d3eaa 744 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
Kojto 93:e188a91d3eaa 745 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
Kojto 93:e188a91d3eaa 746 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
Kojto 93:e188a91d3eaa 747 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
Kojto 93:e188a91d3eaa 748 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
Kojto 93:e188a91d3eaa 749 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
Kojto 93:e188a91d3eaa 750 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
Kojto 93:e188a91d3eaa 751
Kojto 93:e188a91d3eaa 752 /* Debug MCU registers base address */
Kojto 93:e188a91d3eaa 753 #define DBGMCU_BASE ((uint32_t )0xE0042000)
Kojto 93:e188a91d3eaa 754
Kojto 93:e188a91d3eaa 755 /*!< USB registers base address */
Kojto 93:e188a91d3eaa 756 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
Kojto 93:e188a91d3eaa 757
Kojto 93:e188a91d3eaa 758 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
Kojto 93:e188a91d3eaa 759 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
Kojto 93:e188a91d3eaa 760 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
Kojto 93:e188a91d3eaa 761 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
Kojto 93:e188a91d3eaa 762 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
Kojto 93:e188a91d3eaa 763 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
Kojto 93:e188a91d3eaa 764 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
Kojto 93:e188a91d3eaa 765 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
Kojto 93:e188a91d3eaa 766 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
Kojto 93:e188a91d3eaa 767 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
Kojto 93:e188a91d3eaa 768 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
Kojto 93:e188a91d3eaa 769 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
Kojto 93:e188a91d3eaa 770
Kojto 93:e188a91d3eaa 771 /**
Kojto 93:e188a91d3eaa 772 * @}
Kojto 93:e188a91d3eaa 773 */
Kojto 93:e188a91d3eaa 774
Kojto 93:e188a91d3eaa 775 /** @addtogroup Peripheral_declaration
Kojto 93:e188a91d3eaa 776 * @{
Kojto 93:e188a91d3eaa 777 */
Kojto 93:e188a91d3eaa 778 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 93:e188a91d3eaa 779 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 93:e188a91d3eaa 780 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 93:e188a91d3eaa 781 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 93:e188a91d3eaa 782 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 93:e188a91d3eaa 783 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 93:e188a91d3eaa 784 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 93:e188a91d3eaa 785 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
Kojto 93:e188a91d3eaa 786 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 93:e188a91d3eaa 787 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 93:e188a91d3eaa 788 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
Kojto 93:e188a91d3eaa 789 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 93:e188a91d3eaa 790 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 93:e188a91d3eaa 791 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 93:e188a91d3eaa 792 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 93:e188a91d3eaa 793 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 93:e188a91d3eaa 794 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 93:e188a91d3eaa 795 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 93:e188a91d3eaa 796 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 93:e188a91d3eaa 797 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 93:e188a91d3eaa 798 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 93:e188a91d3eaa 799 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 93:e188a91d3eaa 800 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 93:e188a91d3eaa 801 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 93:e188a91d3eaa 802 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 93:e188a91d3eaa 803 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 93:e188a91d3eaa 804 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 93:e188a91d3eaa 805 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 93:e188a91d3eaa 806 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 93:e188a91d3eaa 807 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto 93:e188a91d3eaa 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 93:e188a91d3eaa 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 93:e188a91d3eaa 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 93:e188a91d3eaa 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 93:e188a91d3eaa 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 93:e188a91d3eaa 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 93:e188a91d3eaa 814 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 93:e188a91d3eaa 815 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 93:e188a91d3eaa 816 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 93:e188a91d3eaa 817 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 93:e188a91d3eaa 818 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 93:e188a91d3eaa 819 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 93:e188a91d3eaa 820 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 93:e188a91d3eaa 821 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 93:e188a91d3eaa 822 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 93:e188a91d3eaa 823 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 93:e188a91d3eaa 824 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 93:e188a91d3eaa 825 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 93:e188a91d3eaa 826 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 93:e188a91d3eaa 827 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 93:e188a91d3eaa 828 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 93:e188a91d3eaa 829 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 93:e188a91d3eaa 830 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 93:e188a91d3eaa 831 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 93:e188a91d3eaa 832 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 93:e188a91d3eaa 833 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 93:e188a91d3eaa 834 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 93:e188a91d3eaa 835
Kojto 93:e188a91d3eaa 836 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 93:e188a91d3eaa 837
Kojto 93:e188a91d3eaa 838 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 93:e188a91d3eaa 839
Kojto 93:e188a91d3eaa 840 /**
Kojto 93:e188a91d3eaa 841 * @}
Kojto 93:e188a91d3eaa 842 */
Kojto 93:e188a91d3eaa 843
Kojto 93:e188a91d3eaa 844 /** @addtogroup Exported_constants
Kojto 93:e188a91d3eaa 845 * @{
Kojto 93:e188a91d3eaa 846 */
Kojto 93:e188a91d3eaa 847
Kojto 93:e188a91d3eaa 848 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 93:e188a91d3eaa 849 * @{
Kojto 93:e188a91d3eaa 850 */
Kojto 93:e188a91d3eaa 851
Kojto 93:e188a91d3eaa 852 /******************************************************************************/
Kojto 93:e188a91d3eaa 853 /* Peripheral Registers_Bits_Definition */
Kojto 93:e188a91d3eaa 854 /******************************************************************************/
Kojto 93:e188a91d3eaa 855
Kojto 93:e188a91d3eaa 856 /******************************************************************************/
Kojto 93:e188a91d3eaa 857 /* */
Kojto 93:e188a91d3eaa 858 /* Analog to Digital Converter */
Kojto 93:e188a91d3eaa 859 /* */
Kojto 93:e188a91d3eaa 860 /******************************************************************************/
Kojto 93:e188a91d3eaa 861 /******************** Bit definition for ADC_SR register ********************/
Kojto 93:e188a91d3eaa 862 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
Kojto 93:e188a91d3eaa 863 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
Kojto 93:e188a91d3eaa 864 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
Kojto 93:e188a91d3eaa 865 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
Kojto 93:e188a91d3eaa 866 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
Kojto 93:e188a91d3eaa 867 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
Kojto 93:e188a91d3eaa 868
Kojto 93:e188a91d3eaa 869 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 93:e188a91d3eaa 870 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 93:e188a91d3eaa 871 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 872 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 873 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 874 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 875 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 876 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
Kojto 93:e188a91d3eaa 877 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
Kojto 93:e188a91d3eaa 878 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
Kojto 93:e188a91d3eaa 879 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
Kojto 93:e188a91d3eaa 880 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
Kojto 93:e188a91d3eaa 881 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
Kojto 93:e188a91d3eaa 882 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
Kojto 93:e188a91d3eaa 883 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
Kojto 93:e188a91d3eaa 884 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 93:e188a91d3eaa 885 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 886 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 887 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 888 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
Kojto 93:e188a91d3eaa 889 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
Kojto 93:e188a91d3eaa 890 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
Kojto 93:e188a91d3eaa 891 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 892 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 893 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
Kojto 93:e188a91d3eaa 894
Kojto 93:e188a91d3eaa 895 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 93:e188a91d3eaa 896 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
Kojto 93:e188a91d3eaa 897 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
Kojto 93:e188a91d3eaa 898 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
Kojto 93:e188a91d3eaa 899 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
Kojto 93:e188a91d3eaa 900 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
Kojto 93:e188a91d3eaa 901 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
Kojto 93:e188a91d3eaa 902 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 93:e188a91d3eaa 903 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 904 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 905 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 906 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 907 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 93:e188a91d3eaa 908 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 909 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 910 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
Kojto 93:e188a91d3eaa 911 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 93:e188a91d3eaa 912 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 913 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 914 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 915 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 916 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 93:e188a91d3eaa 917 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 918 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 919 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
Kojto 93:e188a91d3eaa 920
Kojto 93:e188a91d3eaa 921 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 93:e188a91d3eaa 922 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 93:e188a91d3eaa 923 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 924 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 925 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 926 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 93:e188a91d3eaa 927 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 928 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 929 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 930 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 93:e188a91d3eaa 931 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 932 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 933 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 934 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 93:e188a91d3eaa 935 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 936 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 937 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 938 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 93:e188a91d3eaa 939 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 940 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 941 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 942 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 93:e188a91d3eaa 943 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 944 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 945 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 946 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 93:e188a91d3eaa 947 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 948 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 949 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 950 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 93:e188a91d3eaa 951 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 952 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 953 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 954 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 93:e188a91d3eaa 955 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 956 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 957 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 958
Kojto 93:e188a91d3eaa 959 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 93:e188a91d3eaa 960 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 93:e188a91d3eaa 961 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 962 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 963 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 964 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 93:e188a91d3eaa 965 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 966 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 967 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 968 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 93:e188a91d3eaa 969 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 970 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 971 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 972 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 93:e188a91d3eaa 973 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 974 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 975 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 976 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 93:e188a91d3eaa 977 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 978 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 979 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 980 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 93:e188a91d3eaa 981 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 982 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 983 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 984 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 93:e188a91d3eaa 985 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 986 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 987 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 988 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 93:e188a91d3eaa 989 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 990 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 991 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 992 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 93:e188a91d3eaa 993 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 994 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 995 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 996 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 93:e188a91d3eaa 997 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 998 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 999 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1000
Kojto 93:e188a91d3eaa 1001 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 93:e188a91d3eaa 1002 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
Kojto 93:e188a91d3eaa 1003
Kojto 93:e188a91d3eaa 1004 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 93:e188a91d3eaa 1005 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
Kojto 93:e188a91d3eaa 1006
Kojto 93:e188a91d3eaa 1007 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 93:e188a91d3eaa 1008 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
Kojto 93:e188a91d3eaa 1009
Kojto 93:e188a91d3eaa 1010 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 93:e188a91d3eaa 1011 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
Kojto 93:e188a91d3eaa 1012
Kojto 93:e188a91d3eaa 1013 /******************* Bit definition for ADC_HTR register ********************/
Kojto 93:e188a91d3eaa 1014 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
Kojto 93:e188a91d3eaa 1015
Kojto 93:e188a91d3eaa 1016 /******************* Bit definition for ADC_LTR register ********************/
Kojto 93:e188a91d3eaa 1017 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
Kojto 93:e188a91d3eaa 1018
Kojto 93:e188a91d3eaa 1019 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 93:e188a91d3eaa 1020 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1021 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1022 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1023 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1024 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1025 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1026 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1027 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1028 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1029 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1030 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1031 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1032 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1033 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1034 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1035 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1036 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1037 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1038 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1039 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1040 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1041 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1042 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1043 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1044 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 93:e188a91d3eaa 1045 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1046 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1047 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1048 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1049
Kojto 93:e188a91d3eaa 1050 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 93:e188a91d3eaa 1051 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1052 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1053 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1054 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1055 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1056 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1057 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1058 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1059 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1060 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1061 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1062 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1063 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1064 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1065 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1066 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1067 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1068 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1069 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1070 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1071 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1072 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1073 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1074 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1075 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1076 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1077 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1078 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1079 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1080 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1081 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1082 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1083 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1084 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1085 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1086 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1087
Kojto 93:e188a91d3eaa 1088 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 93:e188a91d3eaa 1089 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1090 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1091 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1092 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1093 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1094 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1095 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1096 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1097 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1098 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1099 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1100 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1101 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1102 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1103 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1104 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1105 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1106 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1107 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1108 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1109 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1110 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1111 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1112 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1113 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1114 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1115 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1116 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1117 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1118 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1119 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 93:e188a91d3eaa 1120 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1121 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1122 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1123 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1124 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1125
Kojto 93:e188a91d3eaa 1126 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 93:e188a91d3eaa 1127 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 93:e188a91d3eaa 1128 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1129 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1130 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1131 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1132 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1133 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 93:e188a91d3eaa 1134 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1135 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1136 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1137 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1138 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1139 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 93:e188a91d3eaa 1140 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1141 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1142 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1143 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1144 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1145 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 93:e188a91d3eaa 1146 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1147 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1148 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1149 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1150 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1151 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 93:e188a91d3eaa 1152 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1153 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1154
Kojto 93:e188a91d3eaa 1155 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 93:e188a91d3eaa 1156 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 93:e188a91d3eaa 1157
Kojto 93:e188a91d3eaa 1158 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 93:e188a91d3eaa 1159 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 93:e188a91d3eaa 1160
Kojto 93:e188a91d3eaa 1161 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 93:e188a91d3eaa 1162 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 93:e188a91d3eaa 1163
Kojto 93:e188a91d3eaa 1164 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 93:e188a91d3eaa 1165 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 93:e188a91d3eaa 1166
Kojto 93:e188a91d3eaa 1167 /******************** Bit definition for ADC_DR register ********************/
Kojto 93:e188a91d3eaa 1168 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
Kojto 93:e188a91d3eaa 1169 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
Kojto 93:e188a91d3eaa 1170
Kojto 93:e188a91d3eaa 1171 /******************* Bit definition for ADC_CSR register ********************/
Kojto 93:e188a91d3eaa 1172 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
Kojto 93:e188a91d3eaa 1173 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
Kojto 93:e188a91d3eaa 1174 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
Kojto 93:e188a91d3eaa 1175 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
Kojto 93:e188a91d3eaa 1176 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
Kojto 93:e188a91d3eaa 1177 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
Kojto 93:e188a91d3eaa 1178 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
Kojto 93:e188a91d3eaa 1179 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
Kojto 93:e188a91d3eaa 1180 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
Kojto 93:e188a91d3eaa 1181 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
Kojto 93:e188a91d3eaa 1182 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
Kojto 93:e188a91d3eaa 1183 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
Kojto 93:e188a91d3eaa 1184 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
Kojto 93:e188a91d3eaa 1185 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
Kojto 93:e188a91d3eaa 1186 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
Kojto 93:e188a91d3eaa 1187 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
Kojto 93:e188a91d3eaa 1188 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
Kojto 93:e188a91d3eaa 1189 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
Kojto 93:e188a91d3eaa 1190
Kojto 93:e188a91d3eaa 1191 /******************* Bit definition for ADC_CCR register ********************/
Kojto 93:e188a91d3eaa 1192 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 93:e188a91d3eaa 1193 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1194 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1195 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1196 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1197 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 1198 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 93:e188a91d3eaa 1199 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1200 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1201 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 1202 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 1203 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
Kojto 93:e188a91d3eaa 1204 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 93:e188a91d3eaa 1205 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1206 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1207 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 93:e188a91d3eaa 1208 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 1209 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 1210 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
Kojto 93:e188a91d3eaa 1211 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
Kojto 93:e188a91d3eaa 1212
Kojto 93:e188a91d3eaa 1213 /******************* Bit definition for ADC_CDR register ********************/
Kojto 93:e188a91d3eaa 1214 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
Kojto 93:e188a91d3eaa 1215 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
Kojto 93:e188a91d3eaa 1216
Kojto 93:e188a91d3eaa 1217 /******************************************************************************/
Kojto 93:e188a91d3eaa 1218 /* */
Kojto 93:e188a91d3eaa 1219 /* CRC calculation unit */
Kojto 93:e188a91d3eaa 1220 /* */
Kojto 93:e188a91d3eaa 1221 /******************************************************************************/
Kojto 93:e188a91d3eaa 1222 /******************* Bit definition for CRC_DR register *********************/
Kojto 93:e188a91d3eaa 1223 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 93:e188a91d3eaa 1224
Kojto 93:e188a91d3eaa 1225
Kojto 93:e188a91d3eaa 1226 /******************* Bit definition for CRC_IDR register ********************/
Kojto 93:e188a91d3eaa 1227 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 93:e188a91d3eaa 1228
Kojto 93:e188a91d3eaa 1229
Kojto 93:e188a91d3eaa 1230 /******************** Bit definition for CRC_CR register ********************/
Kojto 93:e188a91d3eaa 1231 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
Kojto 93:e188a91d3eaa 1232
Kojto 93:e188a91d3eaa 1233 /******************************************************************************/
Kojto 93:e188a91d3eaa 1234 /* */
Kojto 93:e188a91d3eaa 1235 /* Debug MCU */
Kojto 93:e188a91d3eaa 1236 /* */
Kojto 93:e188a91d3eaa 1237 /******************************************************************************/
Kojto 93:e188a91d3eaa 1238
Kojto 93:e188a91d3eaa 1239 /******************************************************************************/
Kojto 93:e188a91d3eaa 1240 /* */
Kojto 93:e188a91d3eaa 1241 /* DMA Controller */
Kojto 93:e188a91d3eaa 1242 /* */
Kojto 93:e188a91d3eaa 1243 /******************************************************************************/
Kojto 93:e188a91d3eaa 1244 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 93:e188a91d3eaa 1245 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
Kojto 93:e188a91d3eaa 1246 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1247 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1248 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1249 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
Kojto 93:e188a91d3eaa 1250 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1251 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1252 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
Kojto 93:e188a91d3eaa 1253 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1254 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1255 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1256 #define DMA_SxCR_CT ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1257 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1258 #define DMA_SxCR_PL ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1259 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1260 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1261 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1262 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
Kojto 93:e188a91d3eaa 1263 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1264 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1265 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
Kojto 93:e188a91d3eaa 1266 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1267 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1268 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1269 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1270 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1271 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1272 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1273 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1274 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1275 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1276 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1277 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1278 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1279 #define DMA_SxCR_EN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1280
Kojto 93:e188a91d3eaa 1281 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 93:e188a91d3eaa 1282 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
Kojto 93:e188a91d3eaa 1283 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1284 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1285 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1286 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1287 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1288 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1289 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1290 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1291 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1292 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1293 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1294 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1295 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1296 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1297 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1298 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1299
Kojto 93:e188a91d3eaa 1300 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 93:e188a91d3eaa 1301 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1302 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
Kojto 93:e188a91d3eaa 1303 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1304 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1305 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1306 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1307 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1308 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1309 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1310
Kojto 93:e188a91d3eaa 1311 /******************** Bits definition for DMA_LISR register *****************/
Kojto 93:e188a91d3eaa 1312 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1313 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1314 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1315 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1316 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1317 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1318 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1319 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1320 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1321 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1322 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1323 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1324 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1325 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1326 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1327 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1328 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1329 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1330 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1331 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1332
Kojto 93:e188a91d3eaa 1333 /******************** Bits definition for DMA_HISR register *****************/
Kojto 93:e188a91d3eaa 1334 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1335 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1336 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1337 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1338 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1339 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1340 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1341 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1342 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1343 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1344 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1345 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1346 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1347 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1348 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1349 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1350 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1351 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1352 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1353 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1354
Kojto 93:e188a91d3eaa 1355 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 93:e188a91d3eaa 1356 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1357 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1358 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1359 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1360 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1361 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1362 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1363 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1364 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1365 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1366 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1367 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1368 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1369 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1370 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1371 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1372 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1373 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1374 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1375 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1376
Kojto 93:e188a91d3eaa 1377 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 93:e188a91d3eaa 1378 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1379 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1380 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1381 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1382 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1383 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1384 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1385 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1386 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1387 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1388 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1389 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1390 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1391 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1392 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1393 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1394 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1395 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1396 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1397 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1398
Kojto 93:e188a91d3eaa 1399
Kojto 93:e188a91d3eaa 1400 /******************************************************************************/
Kojto 93:e188a91d3eaa 1401 /* */
Kojto 93:e188a91d3eaa 1402 /* External Interrupt/Event Controller */
Kojto 93:e188a91d3eaa 1403 /* */
Kojto 93:e188a91d3eaa 1404 /******************************************************************************/
Kojto 93:e188a91d3eaa 1405 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 93:e188a91d3eaa 1406 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 93:e188a91d3eaa 1407 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 93:e188a91d3eaa 1408 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 93:e188a91d3eaa 1409 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 93:e188a91d3eaa 1410 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 93:e188a91d3eaa 1411 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 93:e188a91d3eaa 1412 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 93:e188a91d3eaa 1413 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 93:e188a91d3eaa 1414 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 93:e188a91d3eaa 1415 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 93:e188a91d3eaa 1416 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 93:e188a91d3eaa 1417 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 93:e188a91d3eaa 1418 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 93:e188a91d3eaa 1419 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 93:e188a91d3eaa 1420 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 93:e188a91d3eaa 1421 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 93:e188a91d3eaa 1422 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 93:e188a91d3eaa 1423 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 93:e188a91d3eaa 1424 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 93:e188a91d3eaa 1425 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 99:dbbf35b96557 1426 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 99:dbbf35b96557 1427 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 99:dbbf35b96557 1428 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 93:e188a91d3eaa 1429
Kojto 93:e188a91d3eaa 1430 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 93:e188a91d3eaa 1431 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 93:e188a91d3eaa 1432 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 93:e188a91d3eaa 1433 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 93:e188a91d3eaa 1434 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 93:e188a91d3eaa 1435 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 93:e188a91d3eaa 1436 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 93:e188a91d3eaa 1437 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 93:e188a91d3eaa 1438 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 93:e188a91d3eaa 1439 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 93:e188a91d3eaa 1440 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 93:e188a91d3eaa 1441 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 93:e188a91d3eaa 1442 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 93:e188a91d3eaa 1443 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 93:e188a91d3eaa 1444 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 93:e188a91d3eaa 1445 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 93:e188a91d3eaa 1446 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 93:e188a91d3eaa 1447 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 93:e188a91d3eaa 1448 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 93:e188a91d3eaa 1449 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 93:e188a91d3eaa 1450 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 99:dbbf35b96557 1451 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 99:dbbf35b96557 1452 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 99:dbbf35b96557 1453 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 93:e188a91d3eaa 1454
Kojto 93:e188a91d3eaa 1455 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 93:e188a91d3eaa 1456 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 93:e188a91d3eaa 1457 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 93:e188a91d3eaa 1458 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 93:e188a91d3eaa 1459 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 93:e188a91d3eaa 1460 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 93:e188a91d3eaa 1461 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 93:e188a91d3eaa 1462 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 93:e188a91d3eaa 1463 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 93:e188a91d3eaa 1464 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 93:e188a91d3eaa 1465 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 93:e188a91d3eaa 1466 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 93:e188a91d3eaa 1467 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 93:e188a91d3eaa 1468 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 93:e188a91d3eaa 1469 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 93:e188a91d3eaa 1470 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 93:e188a91d3eaa 1471 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 93:e188a91d3eaa 1472 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 93:e188a91d3eaa 1473 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 93:e188a91d3eaa 1474 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 93:e188a91d3eaa 1475 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 99:dbbf35b96557 1476 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 99:dbbf35b96557 1477 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 99:dbbf35b96557 1478 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 93:e188a91d3eaa 1479
Kojto 93:e188a91d3eaa 1480 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 93:e188a91d3eaa 1481 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 93:e188a91d3eaa 1482 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 93:e188a91d3eaa 1483 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 93:e188a91d3eaa 1484 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 93:e188a91d3eaa 1485 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 93:e188a91d3eaa 1486 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 93:e188a91d3eaa 1487 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 93:e188a91d3eaa 1488 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 93:e188a91d3eaa 1489 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 93:e188a91d3eaa 1490 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 93:e188a91d3eaa 1491 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 93:e188a91d3eaa 1492 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 93:e188a91d3eaa 1493 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 93:e188a91d3eaa 1494 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 93:e188a91d3eaa 1495 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 93:e188a91d3eaa 1496 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 93:e188a91d3eaa 1497 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 93:e188a91d3eaa 1498 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 93:e188a91d3eaa 1499 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 93:e188a91d3eaa 1500 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 99:dbbf35b96557 1501 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 99:dbbf35b96557 1502 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 99:dbbf35b96557 1503 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 93:e188a91d3eaa 1504
Kojto 93:e188a91d3eaa 1505 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 93:e188a91d3eaa 1506 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 93:e188a91d3eaa 1507 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 93:e188a91d3eaa 1508 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 93:e188a91d3eaa 1509 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 93:e188a91d3eaa 1510 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 93:e188a91d3eaa 1511 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 93:e188a91d3eaa 1512 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 93:e188a91d3eaa 1513 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 93:e188a91d3eaa 1514 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 93:e188a91d3eaa 1515 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 93:e188a91d3eaa 1516 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 93:e188a91d3eaa 1517 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 93:e188a91d3eaa 1518 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 93:e188a91d3eaa 1519 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 93:e188a91d3eaa 1520 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 93:e188a91d3eaa 1521 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 93:e188a91d3eaa 1522 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 93:e188a91d3eaa 1523 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 93:e188a91d3eaa 1524 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 93:e188a91d3eaa 1525 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 99:dbbf35b96557 1526 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 99:dbbf35b96557 1527 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 99:dbbf35b96557 1528 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 93:e188a91d3eaa 1529
Kojto 93:e188a91d3eaa 1530 /******************* Bit definition for EXTI_PR register ********************/
Kojto 93:e188a91d3eaa 1531 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 93:e188a91d3eaa 1532 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 93:e188a91d3eaa 1533 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 93:e188a91d3eaa 1534 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 93:e188a91d3eaa 1535 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 93:e188a91d3eaa 1536 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 93:e188a91d3eaa 1537 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 93:e188a91d3eaa 1538 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 93:e188a91d3eaa 1539 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 93:e188a91d3eaa 1540 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 93:e188a91d3eaa 1541 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 93:e188a91d3eaa 1542 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 93:e188a91d3eaa 1543 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 93:e188a91d3eaa 1544 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 93:e188a91d3eaa 1545 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 93:e188a91d3eaa 1546 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 93:e188a91d3eaa 1547 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 93:e188a91d3eaa 1548 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 93:e188a91d3eaa 1549 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 93:e188a91d3eaa 1550 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 99:dbbf35b96557 1551 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
Kojto 99:dbbf35b96557 1552 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
Kojto 99:dbbf35b96557 1553 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
Kojto 93:e188a91d3eaa 1554
Kojto 93:e188a91d3eaa 1555 /******************************************************************************/
Kojto 93:e188a91d3eaa 1556 /* */
Kojto 93:e188a91d3eaa 1557 /* FLASH */
Kojto 93:e188a91d3eaa 1558 /* */
Kojto 93:e188a91d3eaa 1559 /******************************************************************************/
Kojto 93:e188a91d3eaa 1560 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 93:e188a91d3eaa 1561 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 1562 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 1563 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1564 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1565 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1566 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1567 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
Kojto 93:e188a91d3eaa 1568 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
Kojto 93:e188a91d3eaa 1569 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
Kojto 93:e188a91d3eaa 1570
Kojto 93:e188a91d3eaa 1571 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1572 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1573 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1574 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1575 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1576 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
Kojto 93:e188a91d3eaa 1577 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
Kojto 93:e188a91d3eaa 1578
Kojto 93:e188a91d3eaa 1579 /******************* Bits definition for FLASH_SR register ******************/
Kojto 93:e188a91d3eaa 1580 #define FLASH_SR_EOP ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1581 #define FLASH_SR_SOP ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1582 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1583 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1584 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1585 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1586 #define FLASH_SR_BSY ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1587
Kojto 93:e188a91d3eaa 1588 /******************* Bits definition for FLASH_CR register ******************/
Kojto 93:e188a91d3eaa 1589 #define FLASH_CR_PG ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1590 #define FLASH_CR_SER ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1591 #define FLASH_CR_MER ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1592 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
Kojto 93:e188a91d3eaa 1593 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1594 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1595 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1596 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1597 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1598 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1599 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1600 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1601 #define FLASH_CR_STRT ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1602 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1603 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1604
Kojto 93:e188a91d3eaa 1605 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 93:e188a91d3eaa 1606 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1607 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1608 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1609 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1610 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1611
Kojto 93:e188a91d3eaa 1612 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1613 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1614 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1615 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
Kojto 93:e188a91d3eaa 1616 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1617 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1618 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1619 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1620 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1621 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1622 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1623 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1624 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
Kojto 93:e188a91d3eaa 1625 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1626 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1627 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1628 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1629 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1630 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1631 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1632 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1633 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1634 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1635 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1636 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1637
Kojto 93:e188a91d3eaa 1638 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 93:e188a91d3eaa 1639 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
Kojto 93:e188a91d3eaa 1640 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1641 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1642 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1643 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1644 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1645 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1646 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1647 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1648 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1649 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1650 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1651 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1652
Kojto 93:e188a91d3eaa 1653 /******************************************************************************/
Kojto 93:e188a91d3eaa 1654 /* */
Kojto 93:e188a91d3eaa 1655 /* General Purpose I/O */
Kojto 93:e188a91d3eaa 1656 /* */
Kojto 93:e188a91d3eaa 1657 /******************************************************************************/
Kojto 93:e188a91d3eaa 1658 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 93:e188a91d3eaa 1659 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1660 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1661 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1662
Kojto 93:e188a91d3eaa 1663 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1664 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1665 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1666
Kojto 93:e188a91d3eaa 1667 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 1668 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1669 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1670
Kojto 93:e188a91d3eaa 1671 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1672 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1673 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1674
Kojto 93:e188a91d3eaa 1675 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1676 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1677 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1678
Kojto 93:e188a91d3eaa 1679 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 1680 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1681 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1682
Kojto 93:e188a91d3eaa 1683 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 93:e188a91d3eaa 1684 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1685 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1686
Kojto 93:e188a91d3eaa 1687 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 93:e188a91d3eaa 1688 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1689 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1690
Kojto 93:e188a91d3eaa 1691 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1692 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1693 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1694
Kojto 93:e188a91d3eaa 1695 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 93:e188a91d3eaa 1696 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1697 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1698
Kojto 93:e188a91d3eaa 1699 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1700 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1701 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1702
Kojto 93:e188a91d3eaa 1703 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 93:e188a91d3eaa 1704 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1705 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1706
Kojto 93:e188a91d3eaa 1707 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 93:e188a91d3eaa 1708 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1709 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1710
Kojto 93:e188a91d3eaa 1711 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 93:e188a91d3eaa 1712 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1713 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1714
Kojto 93:e188a91d3eaa 1715 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 1716 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1717 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1718
Kojto 93:e188a91d3eaa 1719 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 1720 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1721 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1722
Kojto 93:e188a91d3eaa 1723 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 93:e188a91d3eaa 1724 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1725 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1726 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1727 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1728 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1729 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1730 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1731 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1732 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1733 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1734 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1735 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1736 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1737 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1738 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1739 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1740
Kojto 93:e188a91d3eaa 1741 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 93:e188a91d3eaa 1742 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1743 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1744 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1745
Kojto 93:e188a91d3eaa 1746 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1747 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1748 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1749
Kojto 93:e188a91d3eaa 1750 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 1751 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1752 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1753
Kojto 93:e188a91d3eaa 1754 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1755 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1756 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1757
Kojto 93:e188a91d3eaa 1758 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1759 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1760 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1761
Kojto 93:e188a91d3eaa 1762 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 1763 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1764 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1765
Kojto 93:e188a91d3eaa 1766 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 93:e188a91d3eaa 1767 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1768 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1769
Kojto 93:e188a91d3eaa 1770 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 93:e188a91d3eaa 1771 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1772 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1773
Kojto 93:e188a91d3eaa 1774 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1775 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1776 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1777
Kojto 93:e188a91d3eaa 1778 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 93:e188a91d3eaa 1779 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1780 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1781
Kojto 93:e188a91d3eaa 1782 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1783 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1784 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1785
Kojto 93:e188a91d3eaa 1786 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 93:e188a91d3eaa 1787 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1788 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1789
Kojto 93:e188a91d3eaa 1790 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 93:e188a91d3eaa 1791 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1792 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1793
Kojto 93:e188a91d3eaa 1794 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 93:e188a91d3eaa 1795 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1796 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1797
Kojto 93:e188a91d3eaa 1798 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 1799 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1800 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1801
Kojto 93:e188a91d3eaa 1802 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 1803 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1804 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1805
Kojto 93:e188a91d3eaa 1806 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 93:e188a91d3eaa 1807 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 1808 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1809 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1810
Kojto 93:e188a91d3eaa 1811 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 93:e188a91d3eaa 1812 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1813 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1814
Kojto 93:e188a91d3eaa 1815 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 1816 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1817 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1818
Kojto 93:e188a91d3eaa 1819 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 1820 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1821 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1822
Kojto 93:e188a91d3eaa 1823 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 1824 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1825 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1826
Kojto 93:e188a91d3eaa 1827 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 1828 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1829 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1830
Kojto 93:e188a91d3eaa 1831 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 93:e188a91d3eaa 1832 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1833 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1834
Kojto 93:e188a91d3eaa 1835 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 93:e188a91d3eaa 1836 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1837 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1838
Kojto 93:e188a91d3eaa 1839 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 1840 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1841 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1842
Kojto 93:e188a91d3eaa 1843 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 93:e188a91d3eaa 1844 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1845 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1846
Kojto 93:e188a91d3eaa 1847 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 1848 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1849 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1850
Kojto 93:e188a91d3eaa 1851 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 93:e188a91d3eaa 1852 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1853 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1854
Kojto 93:e188a91d3eaa 1855 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 93:e188a91d3eaa 1856 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1857 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1858
Kojto 93:e188a91d3eaa 1859 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 93:e188a91d3eaa 1860 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1861 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1862
Kojto 93:e188a91d3eaa 1863 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 1864 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1865 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1866
Kojto 93:e188a91d3eaa 1867 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 1868 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1869 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1870
Kojto 93:e188a91d3eaa 1871 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 93:e188a91d3eaa 1872 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1873 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1874 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1875 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1876 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1877 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1878 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1879 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1880 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1881 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1882 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1883 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1884 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1885 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1886 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1887 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1888 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1889 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto 93:e188a91d3eaa 1890 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto 93:e188a91d3eaa 1891 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto 93:e188a91d3eaa 1892 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto 93:e188a91d3eaa 1893 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto 93:e188a91d3eaa 1894 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto 93:e188a91d3eaa 1895 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto 93:e188a91d3eaa 1896 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto 93:e188a91d3eaa 1897 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto 93:e188a91d3eaa 1898 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto 93:e188a91d3eaa 1899 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto 93:e188a91d3eaa 1900 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto 93:e188a91d3eaa 1901 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto 93:e188a91d3eaa 1902 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto 93:e188a91d3eaa 1903 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto 93:e188a91d3eaa 1904 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto 93:e188a91d3eaa 1905
Kojto 93:e188a91d3eaa 1906 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 93:e188a91d3eaa 1907 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1908 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1909 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1910 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1911 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1912 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1913 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1914 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1915 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1916 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1917 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1918 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1919 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1920 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1921 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1922 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1923 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 1924 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto 93:e188a91d3eaa 1925 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto 93:e188a91d3eaa 1926 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto 93:e188a91d3eaa 1927 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto 93:e188a91d3eaa 1928 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto 93:e188a91d3eaa 1929 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto 93:e188a91d3eaa 1930 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto 93:e188a91d3eaa 1931 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto 93:e188a91d3eaa 1932 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto 93:e188a91d3eaa 1933 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto 93:e188a91d3eaa 1934 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto 93:e188a91d3eaa 1935 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto 93:e188a91d3eaa 1936 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto 93:e188a91d3eaa 1937 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto 93:e188a91d3eaa 1938 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto 93:e188a91d3eaa 1939 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto 93:e188a91d3eaa 1940
Kojto 93:e188a91d3eaa 1941 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 93:e188a91d3eaa 1942 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1943 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1944 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1945 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1946 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1947 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1948 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1949 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1950 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1951 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1952 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1953 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1954 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1955 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1956 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1957 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1958 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1959 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 1960 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 1961 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 1962 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 1963 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 1964 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 1965 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 1966 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 1967 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 1968 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 1969 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 1970 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 1971 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 1972 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 1973 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 1974
Kojto 93:e188a91d3eaa 1975 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 93:e188a91d3eaa 1976 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 1977 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 1978 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 1979 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 1980 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 1981 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 1982 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 1983 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 1984 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 1985 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 1986 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 1987 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 1988 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 1989 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 1990 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 1991 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 1992 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 1993
Kojto 93:e188a91d3eaa 1994 /******************************************************************************/
Kojto 93:e188a91d3eaa 1995 /* */
Kojto 93:e188a91d3eaa 1996 /* Inter-integrated Circuit Interface */
Kojto 93:e188a91d3eaa 1997 /* */
Kojto 93:e188a91d3eaa 1998 /******************************************************************************/
Kojto 93:e188a91d3eaa 1999 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 93:e188a91d3eaa 2000 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
Kojto 93:e188a91d3eaa 2001 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
Kojto 93:e188a91d3eaa 2002 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
Kojto 93:e188a91d3eaa 2003 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
Kojto 93:e188a91d3eaa 2004 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
Kojto 93:e188a91d3eaa 2005 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
Kojto 93:e188a91d3eaa 2006 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
Kojto 93:e188a91d3eaa 2007 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
Kojto 93:e188a91d3eaa 2008 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
Kojto 93:e188a91d3eaa 2009 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
Kojto 93:e188a91d3eaa 2010 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
Kojto 93:e188a91d3eaa 2011 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
Kojto 93:e188a91d3eaa 2012 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
Kojto 93:e188a91d3eaa 2013 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
Kojto 93:e188a91d3eaa 2014
Kojto 93:e188a91d3eaa 2015 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 93:e188a91d3eaa 2016 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 93:e188a91d3eaa 2017 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2018 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2019 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2020 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2021 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 2022 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 2023
Kojto 93:e188a91d3eaa 2024 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
Kojto 93:e188a91d3eaa 2025 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
Kojto 93:e188a91d3eaa 2026 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
Kojto 93:e188a91d3eaa 2027 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
Kojto 93:e188a91d3eaa 2028 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
Kojto 93:e188a91d3eaa 2029
Kojto 93:e188a91d3eaa 2030 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 93:e188a91d3eaa 2031 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
Kojto 93:e188a91d3eaa 2032 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
Kojto 93:e188a91d3eaa 2033
Kojto 93:e188a91d3eaa 2034 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2035 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2036 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2037 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 2038 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 2039 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 2040 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 2041 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 2042 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
Kojto 93:e188a91d3eaa 2043 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
Kojto 93:e188a91d3eaa 2044
Kojto 93:e188a91d3eaa 2045 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
Kojto 93:e188a91d3eaa 2046
Kojto 93:e188a91d3eaa 2047 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 93:e188a91d3eaa 2048 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
Kojto 93:e188a91d3eaa 2049 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
Kojto 93:e188a91d3eaa 2050
Kojto 93:e188a91d3eaa 2051 /******************** Bit definition for I2C_DR register ********************/
Kojto 93:e188a91d3eaa 2052 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
Kojto 93:e188a91d3eaa 2053
Kojto 93:e188a91d3eaa 2054 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 93:e188a91d3eaa 2055 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
Kojto 93:e188a91d3eaa 2056 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
Kojto 93:e188a91d3eaa 2057 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
Kojto 93:e188a91d3eaa 2058 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
Kojto 93:e188a91d3eaa 2059 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
Kojto 93:e188a91d3eaa 2060 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
Kojto 93:e188a91d3eaa 2061 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
Kojto 93:e188a91d3eaa 2062 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
Kojto 93:e188a91d3eaa 2063 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
Kojto 93:e188a91d3eaa 2064 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
Kojto 93:e188a91d3eaa 2065 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
Kojto 93:e188a91d3eaa 2066 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
Kojto 93:e188a91d3eaa 2067 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
Kojto 93:e188a91d3eaa 2068 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
Kojto 93:e188a91d3eaa 2069
Kojto 93:e188a91d3eaa 2070 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 93:e188a91d3eaa 2071 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
Kojto 93:e188a91d3eaa 2072 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
Kojto 93:e188a91d3eaa 2073 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
Kojto 93:e188a91d3eaa 2074 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
Kojto 93:e188a91d3eaa 2075 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
Kojto 93:e188a91d3eaa 2076 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
Kojto 93:e188a91d3eaa 2077 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
Kojto 93:e188a91d3eaa 2078 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
Kojto 93:e188a91d3eaa 2079
Kojto 93:e188a91d3eaa 2080 /******************* Bit definition for I2C_CCR register ********************/
Kojto 93:e188a91d3eaa 2081 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 93:e188a91d3eaa 2082 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
Kojto 93:e188a91d3eaa 2083 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
Kojto 93:e188a91d3eaa 2084
Kojto 93:e188a91d3eaa 2085 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 93:e188a91d3eaa 2086 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 93:e188a91d3eaa 2087
Kojto 93:e188a91d3eaa 2088 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 93:e188a91d3eaa 2089 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
Kojto 93:e188a91d3eaa 2090 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
Kojto 93:e188a91d3eaa 2091
Kojto 93:e188a91d3eaa 2092 /******************************************************************************/
Kojto 93:e188a91d3eaa 2093 /* */
Kojto 93:e188a91d3eaa 2094 /* Independent WATCHDOG */
Kojto 93:e188a91d3eaa 2095 /* */
Kojto 93:e188a91d3eaa 2096 /******************************************************************************/
Kojto 93:e188a91d3eaa 2097 /******************* Bit definition for IWDG_KR register ********************/
Kojto 93:e188a91d3eaa 2098 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
Kojto 93:e188a91d3eaa 2099
Kojto 93:e188a91d3eaa 2100 /******************* Bit definition for IWDG_PR register ********************/
Kojto 93:e188a91d3eaa 2101 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
Kojto 93:e188a91d3eaa 2102 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2103 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2104 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 2105
Kojto 93:e188a91d3eaa 2106 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 93:e188a91d3eaa 2107 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
Kojto 93:e188a91d3eaa 2108
Kojto 93:e188a91d3eaa 2109 /******************* Bit definition for IWDG_SR register ********************/
Kojto 93:e188a91d3eaa 2110 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
Kojto 93:e188a91d3eaa 2111 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
Kojto 93:e188a91d3eaa 2112
Kojto 93:e188a91d3eaa 2113
Kojto 93:e188a91d3eaa 2114 /******************************************************************************/
Kojto 93:e188a91d3eaa 2115 /* */
Kojto 93:e188a91d3eaa 2116 /* Power Control */
Kojto 93:e188a91d3eaa 2117 /* */
Kojto 93:e188a91d3eaa 2118 /******************************************************************************/
Kojto 93:e188a91d3eaa 2119 /******************** Bit definition for PWR_CR register ********************/
Kojto 93:e188a91d3eaa 2120 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
Kojto 93:e188a91d3eaa 2121 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 93:e188a91d3eaa 2122 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 93:e188a91d3eaa 2123 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 93:e188a91d3eaa 2124 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 93:e188a91d3eaa 2125
Kojto 93:e188a91d3eaa 2126 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 93:e188a91d3eaa 2127 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2128 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2129 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2130
Kojto 93:e188a91d3eaa 2131 /*!< PVD level configuration */
Kojto 93:e188a91d3eaa 2132 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 93:e188a91d3eaa 2133 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 93:e188a91d3eaa 2134 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 93:e188a91d3eaa 2135 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 93:e188a91d3eaa 2136 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 93:e188a91d3eaa 2137 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 93:e188a91d3eaa 2138 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 93:e188a91d3eaa 2139 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 93:e188a91d3eaa 2140
Kojto 93:e188a91d3eaa 2141 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 93:e188a91d3eaa 2142 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
Kojto 93:e188a91d3eaa 2143 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
Kojto 93:e188a91d3eaa 2144 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
Kojto 93:e188a91d3eaa 2145 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
Kojto 93:e188a91d3eaa 2146
Kojto 93:e188a91d3eaa 2147 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 93:e188a91d3eaa 2148 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2149 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2150
Kojto 93:e188a91d3eaa 2151 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
Kojto 93:e188a91d3eaa 2152 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
Kojto 93:e188a91d3eaa 2153 /* Legacy define */
Kojto 93:e188a91d3eaa 2154 #define PWR_CR_PMODE PWR_CR_VOS
Kojto 93:e188a91d3eaa 2155
Kojto 93:e188a91d3eaa 2156 /******************* Bit definition for PWR_CSR register ********************/
Kojto 93:e188a91d3eaa 2157 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 93:e188a91d3eaa 2158 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 93:e188a91d3eaa 2159 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 93:e188a91d3eaa 2160 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
Kojto 93:e188a91d3eaa 2161 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
Kojto 93:e188a91d3eaa 2162 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
Kojto 93:e188a91d3eaa 2163 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
Kojto 93:e188a91d3eaa 2164
Kojto 93:e188a91d3eaa 2165 /* Legacy define */
Kojto 93:e188a91d3eaa 2166 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto 93:e188a91d3eaa 2167
Kojto 93:e188a91d3eaa 2168 /******************************************************************************/
Kojto 93:e188a91d3eaa 2169 /* */
Kojto 93:e188a91d3eaa 2170 /* Reset and Clock Control */
Kojto 93:e188a91d3eaa 2171 /* */
Kojto 93:e188a91d3eaa 2172 /******************************************************************************/
Kojto 93:e188a91d3eaa 2173 /******************** Bit definition for RCC_CR register ********************/
Kojto 93:e188a91d3eaa 2174 #define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2175 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2176
Kojto 93:e188a91d3eaa 2177 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto 93:e188a91d3eaa 2178 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
Kojto 93:e188a91d3eaa 2179 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
Kojto 93:e188a91d3eaa 2180 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
Kojto 93:e188a91d3eaa 2181 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
Kojto 93:e188a91d3eaa 2182 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
Kojto 93:e188a91d3eaa 2183
Kojto 93:e188a91d3eaa 2184 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto 93:e188a91d3eaa 2185 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
Kojto 93:e188a91d3eaa 2186 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
Kojto 93:e188a91d3eaa 2187 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
Kojto 93:e188a91d3eaa 2188 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
Kojto 93:e188a91d3eaa 2189 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
Kojto 93:e188a91d3eaa 2190 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
Kojto 93:e188a91d3eaa 2191 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
Kojto 93:e188a91d3eaa 2192 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
Kojto 93:e188a91d3eaa 2193
Kojto 93:e188a91d3eaa 2194 #define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2195 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2196 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2197 #define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2198 #define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2199 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2200 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2201 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2202
Kojto 93:e188a91d3eaa 2203 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 93:e188a91d3eaa 2204 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
Kojto 93:e188a91d3eaa 2205 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2206 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2207 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2208 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2209 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2210 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2211
Kojto 93:e188a91d3eaa 2212 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
Kojto 93:e188a91d3eaa 2213 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2214 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2215 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2216 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2217 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2218 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2219 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2220 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2221 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2222
Kojto 93:e188a91d3eaa 2223 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 2224 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2225 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2226
Kojto 93:e188a91d3eaa 2227 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2228 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2229 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 2230
Kojto 93:e188a91d3eaa 2231 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2232 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2233 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2234 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2235 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2236
Kojto 93:e188a91d3eaa 2237 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 93:e188a91d3eaa 2238 /*!< SW configuration */
Kojto 93:e188a91d3eaa 2239 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 93:e188a91d3eaa 2240 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2241 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2242
Kojto 93:e188a91d3eaa 2243 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 93:e188a91d3eaa 2244 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 93:e188a91d3eaa 2245 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 93:e188a91d3eaa 2246
Kojto 93:e188a91d3eaa 2247 /*!< SWS configuration */
Kojto 93:e188a91d3eaa 2248 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 93:e188a91d3eaa 2249 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2250 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2251
Kojto 93:e188a91d3eaa 2252 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 93:e188a91d3eaa 2253 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 93:e188a91d3eaa 2254 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 93:e188a91d3eaa 2255
Kojto 93:e188a91d3eaa 2256 /*!< HPRE configuration */
Kojto 93:e188a91d3eaa 2257 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 93:e188a91d3eaa 2258 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2259 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2260 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2261 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 93:e188a91d3eaa 2262
Kojto 93:e188a91d3eaa 2263 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 93:e188a91d3eaa 2264 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 93:e188a91d3eaa 2265 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 93:e188a91d3eaa 2266 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 93:e188a91d3eaa 2267 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 93:e188a91d3eaa 2268 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 93:e188a91d3eaa 2269 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 93:e188a91d3eaa 2270 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 93:e188a91d3eaa 2271 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 93:e188a91d3eaa 2272
Kojto 93:e188a91d3eaa 2273 /*!< PPRE1 configuration */
Kojto 93:e188a91d3eaa 2274 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 93:e188a91d3eaa 2275 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2276 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2277 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2278
Kojto 93:e188a91d3eaa 2279 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 93:e188a91d3eaa 2280 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
Kojto 93:e188a91d3eaa 2281 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
Kojto 93:e188a91d3eaa 2282 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
Kojto 93:e188a91d3eaa 2283 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
Kojto 93:e188a91d3eaa 2284
Kojto 93:e188a91d3eaa 2285 /*!< PPRE2 configuration */
Kojto 93:e188a91d3eaa 2286 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 93:e188a91d3eaa 2287 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2288 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2289 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 93:e188a91d3eaa 2290
Kojto 93:e188a91d3eaa 2291 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 93:e188a91d3eaa 2292 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
Kojto 93:e188a91d3eaa 2293 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
Kojto 93:e188a91d3eaa 2294 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
Kojto 93:e188a91d3eaa 2295 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
Kojto 93:e188a91d3eaa 2296
Kojto 93:e188a91d3eaa 2297 /*!< RTCPRE configuration */
Kojto 93:e188a91d3eaa 2298 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
Kojto 93:e188a91d3eaa 2299 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2300 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2301 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2302 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2303 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2304
Kojto 93:e188a91d3eaa 2305 /*!< MCO1 configuration */
Kojto 93:e188a91d3eaa 2306 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
Kojto 93:e188a91d3eaa 2307 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2308 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2309
Kojto 93:e188a91d3eaa 2310 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2311
Kojto 93:e188a91d3eaa 2312 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
Kojto 93:e188a91d3eaa 2313 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2314 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2315 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2316
Kojto 93:e188a91d3eaa 2317 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
Kojto 93:e188a91d3eaa 2318 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2319 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2320 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2321
Kojto 93:e188a91d3eaa 2322 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
Kojto 93:e188a91d3eaa 2323 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2324 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2325
Kojto 93:e188a91d3eaa 2326 /******************** Bit definition for RCC_CIR register *******************/
Kojto 93:e188a91d3eaa 2327 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2328 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2329 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2330 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2331 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2332 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2333
Kojto 93:e188a91d3eaa 2334 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2335 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2336 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2337 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2338 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2339 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2340 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2341
Kojto 93:e188a91d3eaa 2342 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2343 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2344 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2345 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2346 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2347 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2348
Kojto 93:e188a91d3eaa 2349 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2350
Kojto 93:e188a91d3eaa 2351 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 93:e188a91d3eaa 2352 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2353 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2354 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2355 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2356 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2357 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2358 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2359 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2360 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2361
Kojto 93:e188a91d3eaa 2362 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 93:e188a91d3eaa 2363 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2364
Kojto 93:e188a91d3eaa 2365 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 93:e188a91d3eaa 2366
Kojto 93:e188a91d3eaa 2367 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 93:e188a91d3eaa 2368 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2369 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2370 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2371 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2372 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2373 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2374 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2375 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2376 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2377 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2378 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2379 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2380
Kojto 93:e188a91d3eaa 2381 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 93:e188a91d3eaa 2382 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2383 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2384 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2385 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2386 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2387 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2388 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2389 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2390 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2391 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2392 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2393 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2394
Kojto 93:e188a91d3eaa 2395 /* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 2396 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto 93:e188a91d3eaa 2397
Kojto 93:e188a91d3eaa 2398 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 93:e188a91d3eaa 2399 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2400 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2401 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2402 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2403 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2404 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2405 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2406 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2407 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2408 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2409 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2410
Kojto 93:e188a91d3eaa 2411 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 93:e188a91d3eaa 2412 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2413
Kojto 93:e188a91d3eaa 2414 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 93:e188a91d3eaa 2415
Kojto 93:e188a91d3eaa 2416 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 93:e188a91d3eaa 2417 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2418 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2419 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2420 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2421 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2422 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2423 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2424 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2425 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2426 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2427 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2428 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2429
Kojto 93:e188a91d3eaa 2430 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 93:e188a91d3eaa 2431 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2432 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2433 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2434 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2435 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2436 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2437 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2438 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2439 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2440 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2441 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2442 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2443
Kojto 93:e188a91d3eaa 2444 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 93:e188a91d3eaa 2445 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2446 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2447 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2448 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2449 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2450 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2451 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2452 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2453 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2454 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2455 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2456 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2457 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2458
Kojto 93:e188a91d3eaa 2459 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 93:e188a91d3eaa 2460 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2461
Kojto 93:e188a91d3eaa 2462 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 93:e188a91d3eaa 2463
Kojto 93:e188a91d3eaa 2464 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 93:e188a91d3eaa 2465 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2466 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2467 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2468 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2469 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2470 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2471 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2472 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2473 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2474 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2475 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2476 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2477 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2478
Kojto 93:e188a91d3eaa 2479 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 93:e188a91d3eaa 2480 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2481 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2482 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2483 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2484 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2485 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2486 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2487 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2488 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2489 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2490 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2491 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2492
Kojto 93:e188a91d3eaa 2493 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 93:e188a91d3eaa 2494 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2495 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2496 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2497 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2498
Kojto 93:e188a91d3eaa 2499 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
Kojto 93:e188a91d3eaa 2500 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2501 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2502
Kojto 93:e188a91d3eaa 2503 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2504 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2505
Kojto 93:e188a91d3eaa 2506 /******************** Bit definition for RCC_CSR register *******************/
Kojto 93:e188a91d3eaa 2507 #define RCC_CSR_LSION ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2508 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2509 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2510 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2511 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2512 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2513 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2514 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2515 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2516 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2517
Kojto 93:e188a91d3eaa 2518 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 93:e188a91d3eaa 2519 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
Kojto 93:e188a91d3eaa 2520 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
Kojto 93:e188a91d3eaa 2521 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2522 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2523
Kojto 93:e188a91d3eaa 2524 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 93:e188a91d3eaa 2525 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
Kojto 93:e188a91d3eaa 2526 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2527 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2528 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2529 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2530 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2531 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2532
Kojto 93:e188a91d3eaa 2533 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
Kojto 93:e188a91d3eaa 2534 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2535 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2536 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2537 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2538 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2539 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2540 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2541 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2542 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2543
Kojto 93:e188a91d3eaa 2544 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
Kojto 93:e188a91d3eaa 2545 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2546 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2547 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2548
Kojto 93:e188a91d3eaa 2549
Kojto 93:e188a91d3eaa 2550 /******************************************************************************/
Kojto 93:e188a91d3eaa 2551 /* */
Kojto 93:e188a91d3eaa 2552 /* Real-Time Clock (RTC) */
Kojto 93:e188a91d3eaa 2553 /* */
Kojto 93:e188a91d3eaa 2554 /******************************************************************************/
Kojto 93:e188a91d3eaa 2555 /******************** Bits definition for RTC_TR register *******************/
Kojto 93:e188a91d3eaa 2556 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2557 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 2558 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2559 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2560 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2561 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2562 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2563 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2564 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2565 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 2566 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2567 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2568 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2569 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2570 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2571 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2572 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2573 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2574 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2575 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2576 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2577 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2578 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2579 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2580 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2581 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2582 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2583
Kojto 93:e188a91d3eaa 2584 /******************** Bits definition for RTC_DR register *******************/
Kojto 93:e188a91d3eaa 2585 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 93:e188a91d3eaa 2586 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2587 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2588 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2589 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2590 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2591 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2592 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2593 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2594 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2595 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 93:e188a91d3eaa 2596 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2597 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2598 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2599 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2600 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2601 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2602 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2603 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2604 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2605 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 2606 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2607 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2608 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2609 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2610 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2611 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2612 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2613
Kojto 93:e188a91d3eaa 2614 /******************** Bits definition for RTC_CR register *******************/
Kojto 93:e188a91d3eaa 2615 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2616 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 93:e188a91d3eaa 2617 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2618 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2619 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2620 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2621 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2622 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2623 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2624 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2625 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2626 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2627 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2628 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2629 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2630 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2631 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2632 #define RTC_CR_DCE ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2633 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2634 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2635 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2636 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2637 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 93:e188a91d3eaa 2638 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2639 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2640 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2641
Kojto 93:e188a91d3eaa 2642 /******************** Bits definition for RTC_ISR register ******************/
Kojto 93:e188a91d3eaa 2643 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2644 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2645 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2646 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2647 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2648 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2649 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2650 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2651 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2652 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2653 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2654 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2655 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2656 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2657 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2658 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2659
Kojto 93:e188a91d3eaa 2660 /******************** Bits definition for RTC_PRER register *****************/
Kojto 93:e188a91d3eaa 2661 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 106:ba1f97679dad 2662 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2663
Kojto 93:e188a91d3eaa 2664 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 93:e188a91d3eaa 2665 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 93:e188a91d3eaa 2666
Kojto 93:e188a91d3eaa 2667 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 93:e188a91d3eaa 2668 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2669 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
Kojto 93:e188a91d3eaa 2670
Kojto 93:e188a91d3eaa 2671 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 93:e188a91d3eaa 2672 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2673 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2674 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 2675 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2676 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2677 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2678 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2679 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2680 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2681 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2682 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2683 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2684 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 2685 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2686 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2687 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2688 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2689 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2690 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2691 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2692 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2693 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 2694 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2695 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2696 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2697 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2698 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2699 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2700 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2701 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2702 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2703 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2704 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2705 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2706 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2707 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2708 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2709 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2710 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2711 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2712
Kojto 93:e188a91d3eaa 2713 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 93:e188a91d3eaa 2714 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2715 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 2716 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 2717 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 2718 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 2719 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2720 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2721 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2722 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2723 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2724 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 2725 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2726 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 2727 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2728 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2729 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2730 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2731 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2732 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2733 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2734 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2735 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 2736 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2737 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2738 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2739 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2740 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2741 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2742 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2743 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2744 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2745 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2746 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2747 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2748 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2749 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2750 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2751 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2752 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2753 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2754
Kojto 93:e188a91d3eaa 2755 /******************** Bits definition for RTC_WPR register ******************/
Kojto 93:e188a91d3eaa 2756 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 93:e188a91d3eaa 2757
Kojto 93:e188a91d3eaa 2758 /******************** Bits definition for RTC_SSR register ******************/
Kojto 93:e188a91d3eaa 2759 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 93:e188a91d3eaa 2760
Kojto 93:e188a91d3eaa 2761 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 93:e188a91d3eaa 2762 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2763 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 93:e188a91d3eaa 2764
Kojto 93:e188a91d3eaa 2765 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 93:e188a91d3eaa 2766 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 2767 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 93:e188a91d3eaa 2768 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 2769 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 2770 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 93:e188a91d3eaa 2771 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2772 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2773 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2774 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 2775 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 93:e188a91d3eaa 2776 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2777 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2778 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2779 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2780 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2781 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2782 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2783 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2784 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 93:e188a91d3eaa 2785 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2786 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2787 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2788 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2789 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2790 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2791 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2792 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2793
Kojto 93:e188a91d3eaa 2794 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 93:e188a91d3eaa 2795 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 93:e188a91d3eaa 2796 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2797 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2798 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2799 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2800 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 93:e188a91d3eaa 2801 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2802 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2803 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2804 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2805 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 93:e188a91d3eaa 2806 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2807 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2808 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 93:e188a91d3eaa 2809 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2810 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2811 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2812 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2813
Kojto 93:e188a91d3eaa 2814 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 93:e188a91d3eaa 2815 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 93:e188a91d3eaa 2816
Kojto 93:e188a91d3eaa 2817 /******************** Bits definition for RTC_CAL register *****************/
Kojto 93:e188a91d3eaa 2818 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2819 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2820 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2821 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 93:e188a91d3eaa 2822 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2823 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2824 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2825 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2826 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2827 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 2828 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 2829 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2830 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2831
Kojto 93:e188a91d3eaa 2832 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 93:e188a91d3eaa 2833 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 2834 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 2835 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 2836 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 2837 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 93:e188a91d3eaa 2838 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 2839 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 2840 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 93:e188a91d3eaa 2841 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 2842 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 2843 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 93:e188a91d3eaa 2844 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 2845 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 2846 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 2847 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 2848 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 2849 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 2850 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 2851 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 2852 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 2853
Kojto 93:e188a91d3eaa 2854 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 93:e188a91d3eaa 2855 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2856 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2857 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2858 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2859 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2860 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2861
Kojto 93:e188a91d3eaa 2862 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 93:e188a91d3eaa 2863 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto 93:e188a91d3eaa 2864 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 93:e188a91d3eaa 2865 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 2866 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 2867 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 93:e188a91d3eaa 2868 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto 93:e188a91d3eaa 2869
Kojto 93:e188a91d3eaa 2870 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 93:e188a91d3eaa 2871 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2872
Kojto 93:e188a91d3eaa 2873 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 93:e188a91d3eaa 2874 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2875
Kojto 93:e188a91d3eaa 2876 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 93:e188a91d3eaa 2877 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2878
Kojto 93:e188a91d3eaa 2879 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 93:e188a91d3eaa 2880 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2881
Kojto 93:e188a91d3eaa 2882 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 93:e188a91d3eaa 2883 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2884
Kojto 93:e188a91d3eaa 2885 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 93:e188a91d3eaa 2886 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2887
Kojto 93:e188a91d3eaa 2888 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 93:e188a91d3eaa 2889 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2890
Kojto 93:e188a91d3eaa 2891 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 93:e188a91d3eaa 2892 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2893
Kojto 93:e188a91d3eaa 2894 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 93:e188a91d3eaa 2895 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2896
Kojto 93:e188a91d3eaa 2897 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 93:e188a91d3eaa 2898 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2899
Kojto 93:e188a91d3eaa 2900 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 93:e188a91d3eaa 2901 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2902
Kojto 93:e188a91d3eaa 2903 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 93:e188a91d3eaa 2904 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2905
Kojto 93:e188a91d3eaa 2906 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 93:e188a91d3eaa 2907 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2908
Kojto 93:e188a91d3eaa 2909 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 93:e188a91d3eaa 2910 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2911
Kojto 93:e188a91d3eaa 2912 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 93:e188a91d3eaa 2913 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2914
Kojto 93:e188a91d3eaa 2915 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 93:e188a91d3eaa 2916 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2917
Kojto 93:e188a91d3eaa 2918 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 93:e188a91d3eaa 2919 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2920
Kojto 93:e188a91d3eaa 2921 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 93:e188a91d3eaa 2922 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2923
Kojto 93:e188a91d3eaa 2924 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 93:e188a91d3eaa 2925 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2926
Kojto 93:e188a91d3eaa 2927 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 93:e188a91d3eaa 2928 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto 93:e188a91d3eaa 2929
Kojto 93:e188a91d3eaa 2930
Kojto 93:e188a91d3eaa 2931
Kojto 93:e188a91d3eaa 2932 /******************************************************************************/
Kojto 93:e188a91d3eaa 2933 /* */
Kojto 93:e188a91d3eaa 2934 /* SD host Interface */
Kojto 93:e188a91d3eaa 2935 /* */
Kojto 93:e188a91d3eaa 2936 /******************************************************************************/
Kojto 93:e188a91d3eaa 2937 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 93:e188a91d3eaa 2938 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 93:e188a91d3eaa 2939 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2940 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2941
Kojto 93:e188a91d3eaa 2942 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 93:e188a91d3eaa 2943 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
Kojto 93:e188a91d3eaa 2944 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
Kojto 93:e188a91d3eaa 2945 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
Kojto 93:e188a91d3eaa 2946 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
Kojto 93:e188a91d3eaa 2947
Kojto 93:e188a91d3eaa 2948 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 93:e188a91d3eaa 2949 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 2950 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 2951
Kojto 93:e188a91d3eaa 2952 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
Kojto 93:e188a91d3eaa 2953 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
Kojto 93:e188a91d3eaa 2954
Kojto 93:e188a91d3eaa 2955 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 93:e188a91d3eaa 2956 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
Kojto 93:e188a91d3eaa 2957
Kojto 93:e188a91d3eaa 2958 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 93:e188a91d3eaa 2959 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
Kojto 93:e188a91d3eaa 2960
Kojto 93:e188a91d3eaa 2961 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 93:e188a91d3eaa 2962 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
Kojto 93:e188a91d3eaa 2963 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
Kojto 93:e188a91d3eaa 2964
Kojto 93:e188a91d3eaa 2965 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
Kojto 93:e188a91d3eaa 2966 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 93:e188a91d3eaa 2967 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
Kojto 93:e188a91d3eaa 2968 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
Kojto 93:e188a91d3eaa 2969 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
Kojto 93:e188a91d3eaa 2970 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
Kojto 93:e188a91d3eaa 2971 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
Kojto 93:e188a91d3eaa 2972
Kojto 93:e188a91d3eaa 2973 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 93:e188a91d3eaa 2974 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
Kojto 93:e188a91d3eaa 2975
Kojto 93:e188a91d3eaa 2976 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 93:e188a91d3eaa 2977 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 93:e188a91d3eaa 2978
Kojto 93:e188a91d3eaa 2979 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 93:e188a91d3eaa 2980 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 93:e188a91d3eaa 2981
Kojto 93:e188a91d3eaa 2982 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 93:e188a91d3eaa 2983 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 93:e188a91d3eaa 2984
Kojto 93:e188a91d3eaa 2985 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 93:e188a91d3eaa 2986 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 93:e188a91d3eaa 2987
Kojto 93:e188a91d3eaa 2988 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 93:e188a91d3eaa 2989 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 93:e188a91d3eaa 2990
Kojto 93:e188a91d3eaa 2991 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 93:e188a91d3eaa 2992 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
Kojto 93:e188a91d3eaa 2993
Kojto 93:e188a91d3eaa 2994 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 93:e188a91d3eaa 2995 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
Kojto 93:e188a91d3eaa 2996
Kojto 93:e188a91d3eaa 2997 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 93:e188a91d3eaa 2998 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
Kojto 93:e188a91d3eaa 2999 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
Kojto 93:e188a91d3eaa 3000 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
Kojto 93:e188a91d3eaa 3001 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
Kojto 93:e188a91d3eaa 3002
Kojto 93:e188a91d3eaa 3003 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 93:e188a91d3eaa 3004 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3005 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3006 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3007 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3008
Kojto 93:e188a91d3eaa 3009 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
Kojto 93:e188a91d3eaa 3010 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
Kojto 93:e188a91d3eaa 3011 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
Kojto 93:e188a91d3eaa 3012 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
Kojto 93:e188a91d3eaa 3013
Kojto 93:e188a91d3eaa 3014 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 93:e188a91d3eaa 3015 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
Kojto 93:e188a91d3eaa 3016
Kojto 93:e188a91d3eaa 3017 /****************** Bit definition for SDIO_STA register ********************/
Kojto 93:e188a91d3eaa 3018 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
Kojto 93:e188a91d3eaa 3019 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
Kojto 93:e188a91d3eaa 3020 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
Kojto 93:e188a91d3eaa 3021 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
Kojto 93:e188a91d3eaa 3022 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
Kojto 93:e188a91d3eaa 3023 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
Kojto 93:e188a91d3eaa 3024 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
Kojto 93:e188a91d3eaa 3025 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
Kojto 93:e188a91d3eaa 3026 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 93:e188a91d3eaa 3027 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
Kojto 93:e188a91d3eaa 3028 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
Kojto 93:e188a91d3eaa 3029 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
Kojto 93:e188a91d3eaa 3030 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
Kojto 93:e188a91d3eaa 3031 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
Kojto 93:e188a91d3eaa 3032 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 93:e188a91d3eaa 3033 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 93:e188a91d3eaa 3034 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
Kojto 93:e188a91d3eaa 3035 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
Kojto 93:e188a91d3eaa 3036 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
Kojto 93:e188a91d3eaa 3037 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
Kojto 93:e188a91d3eaa 3038 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
Kojto 93:e188a91d3eaa 3039 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
Kojto 93:e188a91d3eaa 3040 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
Kojto 93:e188a91d3eaa 3041 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
Kojto 93:e188a91d3eaa 3042
Kojto 93:e188a91d3eaa 3043 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 93:e188a91d3eaa 3044 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
Kojto 93:e188a91d3eaa 3045 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
Kojto 93:e188a91d3eaa 3046 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
Kojto 93:e188a91d3eaa 3047 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
Kojto 93:e188a91d3eaa 3048 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
Kojto 93:e188a91d3eaa 3049 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
Kojto 93:e188a91d3eaa 3050 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
Kojto 93:e188a91d3eaa 3051 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
Kojto 93:e188a91d3eaa 3052 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
Kojto 93:e188a91d3eaa 3053 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
Kojto 93:e188a91d3eaa 3054 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
Kojto 93:e188a91d3eaa 3055 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
Kojto 93:e188a91d3eaa 3056 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
Kojto 93:e188a91d3eaa 3057
Kojto 93:e188a91d3eaa 3058 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 93:e188a91d3eaa 3059 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
Kojto 93:e188a91d3eaa 3060 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
Kojto 93:e188a91d3eaa 3061 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
Kojto 93:e188a91d3eaa 3062 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
Kojto 93:e188a91d3eaa 3063 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 93:e188a91d3eaa 3064 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 93:e188a91d3eaa 3065 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
Kojto 93:e188a91d3eaa 3066 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
Kojto 93:e188a91d3eaa 3067 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
Kojto 93:e188a91d3eaa 3068 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
Kojto 93:e188a91d3eaa 3069 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
Kojto 93:e188a91d3eaa 3070 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
Kojto 93:e188a91d3eaa 3071 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
Kojto 93:e188a91d3eaa 3072 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
Kojto 93:e188a91d3eaa 3073 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 93:e188a91d3eaa 3074 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
Kojto 93:e188a91d3eaa 3075 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
Kojto 93:e188a91d3eaa 3076 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
Kojto 93:e188a91d3eaa 3077 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
Kojto 93:e188a91d3eaa 3078 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
Kojto 93:e188a91d3eaa 3079 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
Kojto 93:e188a91d3eaa 3080 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
Kojto 93:e188a91d3eaa 3081 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 93:e188a91d3eaa 3082 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
Kojto 93:e188a91d3eaa 3083
Kojto 93:e188a91d3eaa 3084 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 93:e188a91d3eaa 3085 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 93:e188a91d3eaa 3086
Kojto 93:e188a91d3eaa 3087 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 93:e188a91d3eaa 3088 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
Kojto 93:e188a91d3eaa 3089
Kojto 93:e188a91d3eaa 3090 /******************************************************************************/
Kojto 93:e188a91d3eaa 3091 /* */
Kojto 93:e188a91d3eaa 3092 /* Serial Peripheral Interface */
Kojto 93:e188a91d3eaa 3093 /* */
Kojto 93:e188a91d3eaa 3094 /******************************************************************************/
Kojto 93:e188a91d3eaa 3095 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 93:e188a91d3eaa 3096 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
Kojto 93:e188a91d3eaa 3097 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
Kojto 93:e188a91d3eaa 3098 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
Kojto 93:e188a91d3eaa 3099
Kojto 93:e188a91d3eaa 3100 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 93:e188a91d3eaa 3101 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3102 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3103 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3104
Kojto 93:e188a91d3eaa 3105 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
Kojto 93:e188a91d3eaa 3106 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
Kojto 93:e188a91d3eaa 3107 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
Kojto 93:e188a91d3eaa 3108 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
Kojto 93:e188a91d3eaa 3109 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
Kojto 93:e188a91d3eaa 3110 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
Kojto 93:e188a91d3eaa 3111 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
Kojto 93:e188a91d3eaa 3112 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
Kojto 93:e188a91d3eaa 3113 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
Kojto 93:e188a91d3eaa 3114 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
Kojto 93:e188a91d3eaa 3115
Kojto 93:e188a91d3eaa 3116 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 93:e188a91d3eaa 3117 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
Kojto 93:e188a91d3eaa 3118 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
Kojto 93:e188a91d3eaa 3119 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
Kojto 93:e188a91d3eaa 3120 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
Kojto 93:e188a91d3eaa 3121 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
Kojto 93:e188a91d3eaa 3122 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
Kojto 93:e188a91d3eaa 3123 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
Kojto 93:e188a91d3eaa 3124
Kojto 93:e188a91d3eaa 3125 /******************** Bit definition for SPI_SR register ********************/
Kojto 93:e188a91d3eaa 3126 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
Kojto 93:e188a91d3eaa 3127 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
Kojto 93:e188a91d3eaa 3128 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
Kojto 93:e188a91d3eaa 3129 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
Kojto 93:e188a91d3eaa 3130 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
Kojto 93:e188a91d3eaa 3131 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
Kojto 93:e188a91d3eaa 3132 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
Kojto 93:e188a91d3eaa 3133 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
Kojto 93:e188a91d3eaa 3134 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
Kojto 93:e188a91d3eaa 3135
Kojto 93:e188a91d3eaa 3136 /******************** Bit definition for SPI_DR register ********************/
Kojto 93:e188a91d3eaa 3137 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
Kojto 93:e188a91d3eaa 3138
Kojto 93:e188a91d3eaa 3139 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 93:e188a91d3eaa 3140 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
Kojto 93:e188a91d3eaa 3141
Kojto 93:e188a91d3eaa 3142 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 93:e188a91d3eaa 3143 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
Kojto 93:e188a91d3eaa 3144
Kojto 93:e188a91d3eaa 3145 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 93:e188a91d3eaa 3146 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
Kojto 93:e188a91d3eaa 3147
Kojto 93:e188a91d3eaa 3148 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 93:e188a91d3eaa 3149 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 93:e188a91d3eaa 3150
Kojto 93:e188a91d3eaa 3151 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 93:e188a91d3eaa 3152 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3153 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3154
Kojto 93:e188a91d3eaa 3155 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 93:e188a91d3eaa 3156
Kojto 93:e188a91d3eaa 3157 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 93:e188a91d3eaa 3158 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3159 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3160
Kojto 93:e188a91d3eaa 3161 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 93:e188a91d3eaa 3162
Kojto 93:e188a91d3eaa 3163 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 93:e188a91d3eaa 3164 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3165 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3166
Kojto 93:e188a91d3eaa 3167 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 93:e188a91d3eaa 3168 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 93:e188a91d3eaa 3169
Kojto 93:e188a91d3eaa 3170 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 93:e188a91d3eaa 3171 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 93:e188a91d3eaa 3172 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 93:e188a91d3eaa 3173 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 93:e188a91d3eaa 3174
Kojto 93:e188a91d3eaa 3175 /******************************************************************************/
Kojto 93:e188a91d3eaa 3176 /* */
Kojto 93:e188a91d3eaa 3177 /* SYSCFG */
Kojto 93:e188a91d3eaa 3178 /* */
Kojto 93:e188a91d3eaa 3179 /******************************************************************************/
Kojto 93:e188a91d3eaa 3180 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 93:e188a91d3eaa 3181 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
Kojto 93:e188a91d3eaa 3182 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 3183 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 3184 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 3185
Kojto 93:e188a91d3eaa 3186 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 93:e188a91d3eaa 3187 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
Kojto 93:e188a91d3eaa 3188
Kojto 93:e188a91d3eaa 3189 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 93:e188a91d3eaa 3190 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
Kojto 93:e188a91d3eaa 3191 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
Kojto 93:e188a91d3eaa 3192 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
Kojto 93:e188a91d3eaa 3193 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
Kojto 93:e188a91d3eaa 3194 /**
Kojto 93:e188a91d3eaa 3195 * @brief EXTI0 configuration
Kojto 93:e188a91d3eaa 3196 */
Kojto 93:e188a91d3eaa 3197 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
Kojto 93:e188a91d3eaa 3198 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
Kojto 93:e188a91d3eaa 3199 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
Kojto 93:e188a91d3eaa 3200 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
Kojto 93:e188a91d3eaa 3201 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
Kojto 93:e188a91d3eaa 3202 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
Kojto 93:e188a91d3eaa 3203
Kojto 93:e188a91d3eaa 3204 /**
Kojto 93:e188a91d3eaa 3205 * @brief EXTI1 configuration
Kojto 93:e188a91d3eaa 3206 */
Kojto 93:e188a91d3eaa 3207 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
Kojto 93:e188a91d3eaa 3208 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
Kojto 93:e188a91d3eaa 3209 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
Kojto 93:e188a91d3eaa 3210 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
Kojto 93:e188a91d3eaa 3211 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
Kojto 93:e188a91d3eaa 3212 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
Kojto 93:e188a91d3eaa 3213
Kojto 93:e188a91d3eaa 3214 /**
Kojto 93:e188a91d3eaa 3215 * @brief EXTI2 configuration
Kojto 93:e188a91d3eaa 3216 */
Kojto 93:e188a91d3eaa 3217 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
Kojto 93:e188a91d3eaa 3218 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
Kojto 93:e188a91d3eaa 3219 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
Kojto 93:e188a91d3eaa 3220 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
Kojto 93:e188a91d3eaa 3221 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
Kojto 93:e188a91d3eaa 3222 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
Kojto 93:e188a91d3eaa 3223
Kojto 93:e188a91d3eaa 3224 /**
Kojto 93:e188a91d3eaa 3225 * @brief EXTI3 configuration
Kojto 93:e188a91d3eaa 3226 */
Kojto 93:e188a91d3eaa 3227 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
Kojto 93:e188a91d3eaa 3228 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
Kojto 93:e188a91d3eaa 3229 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
Kojto 93:e188a91d3eaa 3230 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
Kojto 93:e188a91d3eaa 3231 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
Kojto 93:e188a91d3eaa 3232 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
Kojto 93:e188a91d3eaa 3233
Kojto 93:e188a91d3eaa 3234 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 93:e188a91d3eaa 3235 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
Kojto 93:e188a91d3eaa 3236 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
Kojto 93:e188a91d3eaa 3237 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
Kojto 93:e188a91d3eaa 3238 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
Kojto 93:e188a91d3eaa 3239 /**
Kojto 93:e188a91d3eaa 3240 * @brief EXTI4 configuration
Kojto 93:e188a91d3eaa 3241 */
Kojto 93:e188a91d3eaa 3242 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
Kojto 93:e188a91d3eaa 3243 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
Kojto 93:e188a91d3eaa 3244 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
Kojto 93:e188a91d3eaa 3245 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
Kojto 93:e188a91d3eaa 3246 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
Kojto 93:e188a91d3eaa 3247 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
Kojto 93:e188a91d3eaa 3248
Kojto 93:e188a91d3eaa 3249 /**
Kojto 93:e188a91d3eaa 3250 * @brief EXTI5 configuration
Kojto 93:e188a91d3eaa 3251 */
Kojto 93:e188a91d3eaa 3252 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
Kojto 93:e188a91d3eaa 3253 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
Kojto 93:e188a91d3eaa 3254 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
Kojto 93:e188a91d3eaa 3255 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
Kojto 93:e188a91d3eaa 3256 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
Kojto 93:e188a91d3eaa 3257 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
Kojto 93:e188a91d3eaa 3258
Kojto 93:e188a91d3eaa 3259 /**
Kojto 93:e188a91d3eaa 3260 * @brief EXTI6 configuration
Kojto 93:e188a91d3eaa 3261 */
Kojto 93:e188a91d3eaa 3262 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
Kojto 93:e188a91d3eaa 3263 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
Kojto 93:e188a91d3eaa 3264 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
Kojto 93:e188a91d3eaa 3265 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
Kojto 93:e188a91d3eaa 3266 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
Kojto 93:e188a91d3eaa 3267 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
Kojto 93:e188a91d3eaa 3268
Kojto 93:e188a91d3eaa 3269 /**
Kojto 93:e188a91d3eaa 3270 * @brief EXTI7 configuration
Kojto 93:e188a91d3eaa 3271 */
Kojto 93:e188a91d3eaa 3272 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
Kojto 93:e188a91d3eaa 3273 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
Kojto 93:e188a91d3eaa 3274 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
Kojto 93:e188a91d3eaa 3275 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
Kojto 93:e188a91d3eaa 3276 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
Kojto 93:e188a91d3eaa 3277 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
Kojto 93:e188a91d3eaa 3278
Kojto 93:e188a91d3eaa 3279
Kojto 93:e188a91d3eaa 3280 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 93:e188a91d3eaa 3281 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
Kojto 93:e188a91d3eaa 3282 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
Kojto 93:e188a91d3eaa 3283 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
Kojto 93:e188a91d3eaa 3284 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
Kojto 93:e188a91d3eaa 3285
Kojto 93:e188a91d3eaa 3286 /**
Kojto 93:e188a91d3eaa 3287 * @brief EXTI8 configuration
Kojto 93:e188a91d3eaa 3288 */
Kojto 93:e188a91d3eaa 3289 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
Kojto 93:e188a91d3eaa 3290 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
Kojto 93:e188a91d3eaa 3291 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
Kojto 93:e188a91d3eaa 3292 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
Kojto 93:e188a91d3eaa 3293 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
Kojto 93:e188a91d3eaa 3294 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
Kojto 93:e188a91d3eaa 3295
Kojto 93:e188a91d3eaa 3296 /**
Kojto 93:e188a91d3eaa 3297 * @brief EXTI9 configuration
Kojto 93:e188a91d3eaa 3298 */
Kojto 93:e188a91d3eaa 3299 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
Kojto 93:e188a91d3eaa 3300 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
Kojto 93:e188a91d3eaa 3301 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
Kojto 93:e188a91d3eaa 3302 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
Kojto 93:e188a91d3eaa 3303 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
Kojto 93:e188a91d3eaa 3304 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
Kojto 93:e188a91d3eaa 3305
Kojto 93:e188a91d3eaa 3306 /**
Kojto 93:e188a91d3eaa 3307 * @brief EXTI10 configuration
Kojto 93:e188a91d3eaa 3308 */
Kojto 93:e188a91d3eaa 3309 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
Kojto 93:e188a91d3eaa 3310 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
Kojto 93:e188a91d3eaa 3311 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
Kojto 93:e188a91d3eaa 3312 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
Kojto 93:e188a91d3eaa 3313 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
Kojto 93:e188a91d3eaa 3314 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
Kojto 93:e188a91d3eaa 3315
Kojto 93:e188a91d3eaa 3316 /**
Kojto 93:e188a91d3eaa 3317 * @brief EXTI11 configuration
Kojto 93:e188a91d3eaa 3318 */
Kojto 93:e188a91d3eaa 3319 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
Kojto 93:e188a91d3eaa 3320 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
Kojto 93:e188a91d3eaa 3321 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
Kojto 93:e188a91d3eaa 3322 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
Kojto 93:e188a91d3eaa 3323 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
Kojto 93:e188a91d3eaa 3324 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
Kojto 93:e188a91d3eaa 3325
Kojto 93:e188a91d3eaa 3326 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 93:e188a91d3eaa 3327 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
Kojto 93:e188a91d3eaa 3328 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
Kojto 93:e188a91d3eaa 3329 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
Kojto 93:e188a91d3eaa 3330 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
Kojto 93:e188a91d3eaa 3331 /**
Kojto 93:e188a91d3eaa 3332 * @brief EXTI12 configuration
Kojto 93:e188a91d3eaa 3333 */
Kojto 93:e188a91d3eaa 3334 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
Kojto 93:e188a91d3eaa 3335 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
Kojto 93:e188a91d3eaa 3336 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
Kojto 93:e188a91d3eaa 3337 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
Kojto 93:e188a91d3eaa 3338 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
Kojto 93:e188a91d3eaa 3339 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
Kojto 93:e188a91d3eaa 3340
Kojto 93:e188a91d3eaa 3341 /**
Kojto 93:e188a91d3eaa 3342 * @brief EXTI13 configuration
Kojto 93:e188a91d3eaa 3343 */
Kojto 93:e188a91d3eaa 3344 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
Kojto 93:e188a91d3eaa 3345 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
Kojto 93:e188a91d3eaa 3346 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
Kojto 93:e188a91d3eaa 3347 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
Kojto 93:e188a91d3eaa 3348 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
Kojto 93:e188a91d3eaa 3349 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
Kojto 93:e188a91d3eaa 3350
Kojto 93:e188a91d3eaa 3351 /**
Kojto 93:e188a91d3eaa 3352 * @brief EXTI14 configuration
Kojto 93:e188a91d3eaa 3353 */
Kojto 93:e188a91d3eaa 3354 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
Kojto 93:e188a91d3eaa 3355 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
Kojto 93:e188a91d3eaa 3356 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
Kojto 93:e188a91d3eaa 3357 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
Kojto 93:e188a91d3eaa 3358 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
Kojto 93:e188a91d3eaa 3359 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
Kojto 93:e188a91d3eaa 3360
Kojto 93:e188a91d3eaa 3361 /**
Kojto 93:e188a91d3eaa 3362 * @brief EXTI15 configuration
Kojto 93:e188a91d3eaa 3363 */
Kojto 93:e188a91d3eaa 3364 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
Kojto 93:e188a91d3eaa 3365 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
Kojto 93:e188a91d3eaa 3366 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
Kojto 93:e188a91d3eaa 3367 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
Kojto 93:e188a91d3eaa 3368 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
Kojto 93:e188a91d3eaa 3369 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
Kojto 93:e188a91d3eaa 3370
Kojto 93:e188a91d3eaa 3371 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 93:e188a91d3eaa 3372 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
Kojto 93:e188a91d3eaa 3373 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
Kojto 93:e188a91d3eaa 3374
Kojto 93:e188a91d3eaa 3375 /******************************************************************************/
Kojto 93:e188a91d3eaa 3376 /* */
Kojto 93:e188a91d3eaa 3377 /* TIM */
Kojto 93:e188a91d3eaa 3378 /* */
Kojto 93:e188a91d3eaa 3379 /******************************************************************************/
Kojto 93:e188a91d3eaa 3380 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 93:e188a91d3eaa 3381 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
Kojto 93:e188a91d3eaa 3382 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
Kojto 93:e188a91d3eaa 3383 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
Kojto 93:e188a91d3eaa 3384 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
Kojto 93:e188a91d3eaa 3385 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
Kojto 93:e188a91d3eaa 3386
Kojto 93:e188a91d3eaa 3387 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 93:e188a91d3eaa 3388 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3389 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3390
Kojto 93:e188a91d3eaa 3391 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
Kojto 93:e188a91d3eaa 3392
Kojto 93:e188a91d3eaa 3393 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
Kojto 93:e188a91d3eaa 3394 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3395 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3396
Kojto 93:e188a91d3eaa 3397 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 93:e188a91d3eaa 3398 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
Kojto 93:e188a91d3eaa 3399 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
Kojto 93:e188a91d3eaa 3400 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
Kojto 93:e188a91d3eaa 3401
Kojto 93:e188a91d3eaa 3402 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 93:e188a91d3eaa 3403 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3404 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3405 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3406
Kojto 93:e188a91d3eaa 3407 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
Kojto 93:e188a91d3eaa 3408 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
Kojto 93:e188a91d3eaa 3409 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
Kojto 93:e188a91d3eaa 3410 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
Kojto 93:e188a91d3eaa 3411 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
Kojto 93:e188a91d3eaa 3412 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
Kojto 93:e188a91d3eaa 3413 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
Kojto 93:e188a91d3eaa 3414 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
Kojto 93:e188a91d3eaa 3415
Kojto 93:e188a91d3eaa 3416 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 93:e188a91d3eaa 3417 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 93:e188a91d3eaa 3418 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3419 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3420 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3421
Kojto 93:e188a91d3eaa 3422 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 93:e188a91d3eaa 3423 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3424 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3425 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3426
Kojto 93:e188a91d3eaa 3427 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
Kojto 93:e188a91d3eaa 3428
Kojto 93:e188a91d3eaa 3429 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 93:e188a91d3eaa 3430 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3431 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3432 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3433 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3434
Kojto 93:e188a91d3eaa 3435 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 93:e188a91d3eaa 3436 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3437 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3438
Kojto 93:e188a91d3eaa 3439 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
Kojto 93:e188a91d3eaa 3440 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
Kojto 93:e188a91d3eaa 3441
Kojto 93:e188a91d3eaa 3442 /******************* Bit definition for TIM_DIER register *******************/
Kojto 93:e188a91d3eaa 3443 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
Kojto 93:e188a91d3eaa 3444 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
Kojto 93:e188a91d3eaa 3445 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
Kojto 93:e188a91d3eaa 3446 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
Kojto 93:e188a91d3eaa 3447 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
Kojto 93:e188a91d3eaa 3448 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
Kojto 93:e188a91d3eaa 3449 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
Kojto 93:e188a91d3eaa 3450 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
Kojto 93:e188a91d3eaa 3451 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
Kojto 93:e188a91d3eaa 3452 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
Kojto 93:e188a91d3eaa 3453 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
Kojto 93:e188a91d3eaa 3454 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
Kojto 93:e188a91d3eaa 3455 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
Kojto 93:e188a91d3eaa 3456 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
Kojto 93:e188a91d3eaa 3457 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
Kojto 93:e188a91d3eaa 3458
Kojto 93:e188a91d3eaa 3459 /******************** Bit definition for TIM_SR register ********************/
Kojto 93:e188a91d3eaa 3460 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
Kojto 93:e188a91d3eaa 3461 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 93:e188a91d3eaa 3462 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 93:e188a91d3eaa 3463 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 93:e188a91d3eaa 3464 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 93:e188a91d3eaa 3465 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
Kojto 93:e188a91d3eaa 3466 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
Kojto 93:e188a91d3eaa 3467 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
Kojto 93:e188a91d3eaa 3468 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 93:e188a91d3eaa 3469 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 93:e188a91d3eaa 3470 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 93:e188a91d3eaa 3471 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 93:e188a91d3eaa 3472
Kojto 93:e188a91d3eaa 3473 /******************* Bit definition for TIM_EGR register ********************/
Kojto 93:e188a91d3eaa 3474 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
Kojto 93:e188a91d3eaa 3475 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
Kojto 93:e188a91d3eaa 3476 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
Kojto 93:e188a91d3eaa 3477 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
Kojto 93:e188a91d3eaa 3478 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
Kojto 93:e188a91d3eaa 3479 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
Kojto 93:e188a91d3eaa 3480 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
Kojto 93:e188a91d3eaa 3481 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
Kojto 93:e188a91d3eaa 3482
Kojto 93:e188a91d3eaa 3483 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 93:e188a91d3eaa 3484 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 93:e188a91d3eaa 3485 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3486 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3487
Kojto 93:e188a91d3eaa 3488 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
Kojto 93:e188a91d3eaa 3489 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
Kojto 93:e188a91d3eaa 3490
Kojto 93:e188a91d3eaa 3491 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 93:e188a91d3eaa 3492 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3493 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3494 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3495
Kojto 93:e188a91d3eaa 3496 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
Kojto 93:e188a91d3eaa 3497
Kojto 93:e188a91d3eaa 3498 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 93:e188a91d3eaa 3499 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3500 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3501
Kojto 93:e188a91d3eaa 3502 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
Kojto 93:e188a91d3eaa 3503 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
Kojto 93:e188a91d3eaa 3504
Kojto 93:e188a91d3eaa 3505 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 93:e188a91d3eaa 3506 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3507 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3508 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3509
Kojto 93:e188a91d3eaa 3510 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
Kojto 93:e188a91d3eaa 3511
Kojto 93:e188a91d3eaa 3512 /*----------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 3513
Kojto 93:e188a91d3eaa 3514 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 93:e188a91d3eaa 3515 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3516 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3517
Kojto 93:e188a91d3eaa 3518 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 93:e188a91d3eaa 3519 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3520 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3521 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3522 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3523
Kojto 93:e188a91d3eaa 3524 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 93:e188a91d3eaa 3525 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3526 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3527
Kojto 93:e188a91d3eaa 3528 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 93:e188a91d3eaa 3529 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3530 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3531 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3532 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3533
Kojto 93:e188a91d3eaa 3534 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 93:e188a91d3eaa 3535 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 93:e188a91d3eaa 3536 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3537 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3538
Kojto 93:e188a91d3eaa 3539 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
Kojto 93:e188a91d3eaa 3540 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
Kojto 93:e188a91d3eaa 3541
Kojto 93:e188a91d3eaa 3542 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 93:e188a91d3eaa 3543 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3544 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3545 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3546
Kojto 93:e188a91d3eaa 3547 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
Kojto 93:e188a91d3eaa 3548
Kojto 93:e188a91d3eaa 3549 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 93:e188a91d3eaa 3550 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3551 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3552
Kojto 93:e188a91d3eaa 3553 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
Kojto 93:e188a91d3eaa 3554 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
Kojto 93:e188a91d3eaa 3555
Kojto 93:e188a91d3eaa 3556 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 93:e188a91d3eaa 3557 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3558 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3559 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3560
Kojto 93:e188a91d3eaa 3561 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
Kojto 93:e188a91d3eaa 3562
Kojto 93:e188a91d3eaa 3563 /*----------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 3564
Kojto 93:e188a91d3eaa 3565 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 93:e188a91d3eaa 3566 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3567 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3568
Kojto 93:e188a91d3eaa 3569 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 93:e188a91d3eaa 3570 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3571 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3572 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3573 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3574
Kojto 93:e188a91d3eaa 3575 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 93:e188a91d3eaa 3576 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3577 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3578
Kojto 93:e188a91d3eaa 3579 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 93:e188a91d3eaa 3580 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3581 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3582 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3583 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3584
Kojto 93:e188a91d3eaa 3585 /******************* Bit definition for TIM_CCER register *******************/
Kojto 93:e188a91d3eaa 3586 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
Kojto 93:e188a91d3eaa 3587 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
Kojto 93:e188a91d3eaa 3588 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 93:e188a91d3eaa 3589 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 93:e188a91d3eaa 3590 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
Kojto 93:e188a91d3eaa 3591 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
Kojto 93:e188a91d3eaa 3592 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 93:e188a91d3eaa 3593 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 93:e188a91d3eaa 3594 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
Kojto 93:e188a91d3eaa 3595 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
Kojto 93:e188a91d3eaa 3596 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 93:e188a91d3eaa 3597 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 93:e188a91d3eaa 3598 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
Kojto 93:e188a91d3eaa 3599 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
Kojto 93:e188a91d3eaa 3600 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 93:e188a91d3eaa 3601
Kojto 93:e188a91d3eaa 3602 /******************* Bit definition for TIM_CNT register ********************/
Kojto 93:e188a91d3eaa 3603 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
Kojto 93:e188a91d3eaa 3604
Kojto 93:e188a91d3eaa 3605 /******************* Bit definition for TIM_PSC register ********************/
Kojto 93:e188a91d3eaa 3606 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
Kojto 93:e188a91d3eaa 3607
Kojto 93:e188a91d3eaa 3608 /******************* Bit definition for TIM_ARR register ********************/
Kojto 93:e188a91d3eaa 3609 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
Kojto 93:e188a91d3eaa 3610
Kojto 93:e188a91d3eaa 3611 /******************* Bit definition for TIM_RCR register ********************/
Kojto 93:e188a91d3eaa 3612 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
Kojto 93:e188a91d3eaa 3613
Kojto 93:e188a91d3eaa 3614 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 93:e188a91d3eaa 3615 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
Kojto 93:e188a91d3eaa 3616
Kojto 93:e188a91d3eaa 3617 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 93:e188a91d3eaa 3618 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
Kojto 93:e188a91d3eaa 3619
Kojto 93:e188a91d3eaa 3620 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 93:e188a91d3eaa 3621 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
Kojto 93:e188a91d3eaa 3622
Kojto 93:e188a91d3eaa 3623 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 93:e188a91d3eaa 3624 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
Kojto 93:e188a91d3eaa 3625
Kojto 93:e188a91d3eaa 3626 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 93:e188a91d3eaa 3627 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 93:e188a91d3eaa 3628 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3629 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3630 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3631 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3632 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3633 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3634 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3635 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 3636
Kojto 93:e188a91d3eaa 3637 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 93:e188a91d3eaa 3638 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3639 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3640
Kojto 93:e188a91d3eaa 3641 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
Kojto 93:e188a91d3eaa 3642 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
Kojto 93:e188a91d3eaa 3643 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
Kojto 93:e188a91d3eaa 3644 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
Kojto 93:e188a91d3eaa 3645 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
Kojto 93:e188a91d3eaa 3646 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
Kojto 93:e188a91d3eaa 3647
Kojto 93:e188a91d3eaa 3648 /******************* Bit definition for TIM_DCR register ********************/
Kojto 93:e188a91d3eaa 3649 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 93:e188a91d3eaa 3650 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3651 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3652 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3653 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3654 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3655
Kojto 93:e188a91d3eaa 3656 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 93:e188a91d3eaa 3657 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3658 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3659 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3660 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3661 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3662
Kojto 93:e188a91d3eaa 3663 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 93:e188a91d3eaa 3664 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
Kojto 93:e188a91d3eaa 3665
Kojto 93:e188a91d3eaa 3666 /******************* Bit definition for TIM_OR register *********************/
Kojto 93:e188a91d3eaa 3667 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 93:e188a91d3eaa 3668 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3669 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3670 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 93:e188a91d3eaa 3671 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3672 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3673
Kojto 93:e188a91d3eaa 3674
Kojto 93:e188a91d3eaa 3675 /******************************************************************************/
Kojto 93:e188a91d3eaa 3676 /* */
Kojto 93:e188a91d3eaa 3677 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 93:e188a91d3eaa 3678 /* */
Kojto 93:e188a91d3eaa 3679 /******************************************************************************/
Kojto 93:e188a91d3eaa 3680 /******************* Bit definition for USART_SR register *******************/
Kojto 93:e188a91d3eaa 3681 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
Kojto 93:e188a91d3eaa 3682 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
Kojto 93:e188a91d3eaa 3683 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
Kojto 93:e188a91d3eaa 3684 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
Kojto 93:e188a91d3eaa 3685 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
Kojto 93:e188a91d3eaa 3686 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
Kojto 93:e188a91d3eaa 3687 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
Kojto 93:e188a91d3eaa 3688 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
Kojto 93:e188a91d3eaa 3689 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
Kojto 93:e188a91d3eaa 3690 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
Kojto 93:e188a91d3eaa 3691
Kojto 93:e188a91d3eaa 3692 /******************* Bit definition for USART_DR register *******************/
Kojto 93:e188a91d3eaa 3693 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
Kojto 93:e188a91d3eaa 3694
Kojto 93:e188a91d3eaa 3695 /****************** Bit definition for USART_BRR register *******************/
Kojto 93:e188a91d3eaa 3696 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
Kojto 93:e188a91d3eaa 3697 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
Kojto 93:e188a91d3eaa 3698
Kojto 93:e188a91d3eaa 3699 /****************** Bit definition for USART_CR1 register *******************/
Kojto 93:e188a91d3eaa 3700 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
Kojto 93:e188a91d3eaa 3701 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
Kojto 93:e188a91d3eaa 3702 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
Kojto 93:e188a91d3eaa 3703 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
Kojto 93:e188a91d3eaa 3704 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
Kojto 93:e188a91d3eaa 3705 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
Kojto 93:e188a91d3eaa 3706 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
Kojto 93:e188a91d3eaa 3707 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
Kojto 93:e188a91d3eaa 3708 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
Kojto 93:e188a91d3eaa 3709 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
Kojto 93:e188a91d3eaa 3710 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
Kojto 93:e188a91d3eaa 3711 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
Kojto 93:e188a91d3eaa 3712 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
Kojto 93:e188a91d3eaa 3713 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
Kojto 93:e188a91d3eaa 3714 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
Kojto 93:e188a91d3eaa 3715
Kojto 93:e188a91d3eaa 3716 /****************** Bit definition for USART_CR2 register *******************/
Kojto 93:e188a91d3eaa 3717 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
Kojto 93:e188a91d3eaa 3718 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
Kojto 93:e188a91d3eaa 3719 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
Kojto 93:e188a91d3eaa 3720 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
Kojto 93:e188a91d3eaa 3721 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
Kojto 93:e188a91d3eaa 3722 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
Kojto 93:e188a91d3eaa 3723 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
Kojto 93:e188a91d3eaa 3724
Kojto 93:e188a91d3eaa 3725 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
Kojto 93:e188a91d3eaa 3726 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3727 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3728
Kojto 93:e188a91d3eaa 3729 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
Kojto 93:e188a91d3eaa 3730
Kojto 93:e188a91d3eaa 3731 /****************** Bit definition for USART_CR3 register *******************/
Kojto 93:e188a91d3eaa 3732 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
Kojto 93:e188a91d3eaa 3733 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
Kojto 93:e188a91d3eaa 3734 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
Kojto 93:e188a91d3eaa 3735 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
Kojto 93:e188a91d3eaa 3736 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
Kojto 93:e188a91d3eaa 3737 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
Kojto 93:e188a91d3eaa 3738 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
Kojto 93:e188a91d3eaa 3739 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
Kojto 93:e188a91d3eaa 3740 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
Kojto 93:e188a91d3eaa 3741 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
Kojto 93:e188a91d3eaa 3742 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
Kojto 93:e188a91d3eaa 3743 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
Kojto 93:e188a91d3eaa 3744
Kojto 93:e188a91d3eaa 3745 /****************** Bit definition for USART_GTPR register ******************/
Kojto 93:e188a91d3eaa 3746 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
Kojto 93:e188a91d3eaa 3747 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3748 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3749 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3750 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3751 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3752 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3753 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3754 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 3755
Kojto 93:e188a91d3eaa 3756 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
Kojto 93:e188a91d3eaa 3757
Kojto 93:e188a91d3eaa 3758 /******************************************************************************/
Kojto 93:e188a91d3eaa 3759 /* */
Kojto 93:e188a91d3eaa 3760 /* Window WATCHDOG */
Kojto 93:e188a91d3eaa 3761 /* */
Kojto 93:e188a91d3eaa 3762 /******************************************************************************/
Kojto 93:e188a91d3eaa 3763 /******************* Bit definition for WWDG_CR register ********************/
Kojto 93:e188a91d3eaa 3764 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 93:e188a91d3eaa 3765 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3766 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3767 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3768 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3769 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3770 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3771 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3772
Kojto 93:e188a91d3eaa 3773 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 93:e188a91d3eaa 3774
Kojto 93:e188a91d3eaa 3775 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 93:e188a91d3eaa 3776 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 93:e188a91d3eaa 3777 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3778 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3779 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3780 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3781 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3782 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3783 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3784
Kojto 93:e188a91d3eaa 3785 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 93:e188a91d3eaa 3786 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3787 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3788
Kojto 93:e188a91d3eaa 3789 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 93:e188a91d3eaa 3790
Kojto 93:e188a91d3eaa 3791 /******************* Bit definition for WWDG_SR register ********************/
Kojto 93:e188a91d3eaa 3792 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 93:e188a91d3eaa 3793
Kojto 93:e188a91d3eaa 3794
Kojto 93:e188a91d3eaa 3795 /******************************************************************************/
Kojto 93:e188a91d3eaa 3796 /* */
Kojto 93:e188a91d3eaa 3797 /* DBG */
Kojto 93:e188a91d3eaa 3798 /* */
Kojto 93:e188a91d3eaa 3799 /******************************************************************************/
Kojto 93:e188a91d3eaa 3800 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 93:e188a91d3eaa 3801 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto 93:e188a91d3eaa 3802 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto 93:e188a91d3eaa 3803
Kojto 93:e188a91d3eaa 3804 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 93:e188a91d3eaa 3805 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 3806 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 3807 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 3808 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 3809
Kojto 93:e188a91d3eaa 3810 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto 93:e188a91d3eaa 3811 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
Kojto 93:e188a91d3eaa 3812 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
Kojto 93:e188a91d3eaa 3813
Kojto 93:e188a91d3eaa 3814 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 93:e188a91d3eaa 3815 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 3816 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 3817 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 3818 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 3819 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 3820 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 3821 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 3822 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 3823 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 3824 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 3825 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 3826 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 3827 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 3828 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 3829 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 3830 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
Kojto 93:e188a91d3eaa 3831 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
Kojto 93:e188a91d3eaa 3832 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto 93:e188a91d3eaa 3833 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto 93:e188a91d3eaa 3834
Kojto 93:e188a91d3eaa 3835 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 93:e188a91d3eaa 3836 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 3837 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 3838 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 3839 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 3840 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 3841
Kojto 93:e188a91d3eaa 3842 /******************************************************************************/
Kojto 93:e188a91d3eaa 3843 /* */
Kojto 93:e188a91d3eaa 3844 /* USB_OTG */
Kojto 93:e188a91d3eaa 3845 /* */
Kojto 93:e188a91d3eaa 3846 /******************************************************************************/
Kojto 93:e188a91d3eaa 3847 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
Kojto 93:e188a91d3eaa 3848 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
Kojto 93:e188a91d3eaa 3849 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
Kojto 93:e188a91d3eaa 3850 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
Kojto 93:e188a91d3eaa 3851 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
Kojto 93:e188a91d3eaa 3852 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
Kojto 93:e188a91d3eaa 3853 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
Kojto 93:e188a91d3eaa 3854 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
Kojto 93:e188a91d3eaa 3855 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
Kojto 93:e188a91d3eaa 3856 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
Kojto 93:e188a91d3eaa 3857 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
Kojto 93:e188a91d3eaa 3858
Kojto 93:e188a91d3eaa 3859 /******************** Bit definition forUSB_OTG_HCFG register ********************/
Kojto 93:e188a91d3eaa 3860
Kojto 93:e188a91d3eaa 3861 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
Kojto 93:e188a91d3eaa 3862 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3863 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3864 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
Kojto 93:e188a91d3eaa 3865
Kojto 93:e188a91d3eaa 3866 /******************** Bit definition forUSB_OTG_DCFG register ********************/
Kojto 93:e188a91d3eaa 3867
Kojto 93:e188a91d3eaa 3868 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
Kojto 93:e188a91d3eaa 3869 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3870 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3871 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
Kojto 93:e188a91d3eaa 3872
Kojto 93:e188a91d3eaa 3873 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
Kojto 93:e188a91d3eaa 3874 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3875 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3876 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3877 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3878 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3879 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 3880 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 3881
Kojto 93:e188a91d3eaa 3882 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
Kojto 93:e188a91d3eaa 3883 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3884 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3885
Kojto 93:e188a91d3eaa 3886 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
Kojto 93:e188a91d3eaa 3887 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3888 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3889
Kojto 93:e188a91d3eaa 3890 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
Kojto 93:e188a91d3eaa 3891 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
Kojto 93:e188a91d3eaa 3892 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
Kojto 93:e188a91d3eaa 3893 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
Kojto 93:e188a91d3eaa 3894
Kojto 93:e188a91d3eaa 3895 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
Kojto 93:e188a91d3eaa 3896 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
Kojto 93:e188a91d3eaa 3897 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
Kojto 93:e188a91d3eaa 3898 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
Kojto 93:e188a91d3eaa 3899 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
Kojto 93:e188a91d3eaa 3900 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
Kojto 93:e188a91d3eaa 3901 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
Kojto 93:e188a91d3eaa 3902
Kojto 93:e188a91d3eaa 3903 /******************** Bit definition forUSB_OTG_DCTL register ********************/
Kojto 93:e188a91d3eaa 3904 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
Kojto 93:e188a91d3eaa 3905 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
Kojto 93:e188a91d3eaa 3906 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
Kojto 93:e188a91d3eaa 3907 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
Kojto 93:e188a91d3eaa 3908
Kojto 93:e188a91d3eaa 3909 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
Kojto 93:e188a91d3eaa 3910 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3911 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3912 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3913 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
Kojto 93:e188a91d3eaa 3914 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
Kojto 93:e188a91d3eaa 3915 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
Kojto 93:e188a91d3eaa 3916 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
Kojto 93:e188a91d3eaa 3917 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
Kojto 93:e188a91d3eaa 3918
Kojto 93:e188a91d3eaa 3919 /******************** Bit definition forUSB_OTG_HFIR register ********************/
Kojto 93:e188a91d3eaa 3920 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
Kojto 93:e188a91d3eaa 3921
Kojto 93:e188a91d3eaa 3922 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
Kojto 93:e188a91d3eaa 3923 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
Kojto 93:e188a91d3eaa 3924 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
Kojto 93:e188a91d3eaa 3925
Kojto 93:e188a91d3eaa 3926 /******************** Bit definition forUSB_OTG_DSTS register ********************/
Kojto 93:e188a91d3eaa 3927 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
Kojto 93:e188a91d3eaa 3928
Kojto 93:e188a91d3eaa 3929 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
Kojto 93:e188a91d3eaa 3930 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3931 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3932 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
Kojto 93:e188a91d3eaa 3933 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
Kojto 93:e188a91d3eaa 3934
Kojto 93:e188a91d3eaa 3935 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
Kojto 93:e188a91d3eaa 3936 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
Kojto 93:e188a91d3eaa 3937
Kojto 93:e188a91d3eaa 3938 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
Kojto 93:e188a91d3eaa 3939 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3940 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3941 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3942 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3943 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
Kojto 93:e188a91d3eaa 3944 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
Kojto 93:e188a91d3eaa 3945 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
Kojto 93:e188a91d3eaa 3946
Kojto 93:e188a91d3eaa 3947 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
Kojto 93:e188a91d3eaa 3948
Kojto 93:e188a91d3eaa 3949 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
Kojto 93:e188a91d3eaa 3950 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3951 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3952 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3953 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 93:e188a91d3eaa 3954 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
Kojto 93:e188a91d3eaa 3955 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
Kojto 93:e188a91d3eaa 3956
Kojto 93:e188a91d3eaa 3957 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
Kojto 93:e188a91d3eaa 3958 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3959 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3960 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3961 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3962 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
Kojto 93:e188a91d3eaa 3963 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
Kojto 93:e188a91d3eaa 3964 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
Kojto 93:e188a91d3eaa 3965 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
Kojto 93:e188a91d3eaa 3966 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
Kojto 93:e188a91d3eaa 3967 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
Kojto 93:e188a91d3eaa 3968 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
Kojto 93:e188a91d3eaa 3969 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
Kojto 93:e188a91d3eaa 3970 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
Kojto 93:e188a91d3eaa 3971 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
Kojto 93:e188a91d3eaa 3972 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
Kojto 93:e188a91d3eaa 3973 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
Kojto 93:e188a91d3eaa 3974 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
Kojto 93:e188a91d3eaa 3975
Kojto 93:e188a91d3eaa 3976 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
Kojto 93:e188a91d3eaa 3977 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
Kojto 93:e188a91d3eaa 3978 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
Kojto 93:e188a91d3eaa 3979 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
Kojto 93:e188a91d3eaa 3980 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
Kojto 93:e188a91d3eaa 3981 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
Kojto 93:e188a91d3eaa 3982
Kojto 93:e188a91d3eaa 3983 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
Kojto 93:e188a91d3eaa 3984 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 3985 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 3986 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 3987 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 3988 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 3989 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
Kojto 93:e188a91d3eaa 3990 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
Kojto 93:e188a91d3eaa 3991
Kojto 93:e188a91d3eaa 3992 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
Kojto 93:e188a91d3eaa 3993 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 93:e188a91d3eaa 3994 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 93:e188a91d3eaa 3995 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 93:e188a91d3eaa 3996 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 93:e188a91d3eaa 3997 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 93:e188a91d3eaa 3998 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 93:e188a91d3eaa 3999 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 93:e188a91d3eaa 4000 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 93:e188a91d3eaa 4001
Kojto 93:e188a91d3eaa 4002 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
Kojto 93:e188a91d3eaa 4003 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
Kojto 93:e188a91d3eaa 4004
Kojto 93:e188a91d3eaa 4005 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
Kojto 93:e188a91d3eaa 4006 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4007 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4008 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4009 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4010 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4011 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4012 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4013 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 4014
Kojto 93:e188a91d3eaa 4015 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
Kojto 93:e188a91d3eaa 4016 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4017 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4018 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4019 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4020 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4021 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4022 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4023 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 4024
Kojto 93:e188a91d3eaa 4025 /******************** Bit definition forUSB_OTG_HAINT register ********************/
Kojto 93:e188a91d3eaa 4026 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
Kojto 93:e188a91d3eaa 4027
Kojto 93:e188a91d3eaa 4028 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
Kojto 93:e188a91d3eaa 4029 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 93:e188a91d3eaa 4030 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 93:e188a91d3eaa 4031 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
Kojto 93:e188a91d3eaa 4032 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
Kojto 93:e188a91d3eaa 4033 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
Kojto 93:e188a91d3eaa 4034 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 93:e188a91d3eaa 4035 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 93:e188a91d3eaa 4036
Kojto 93:e188a91d3eaa 4037 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
Kojto 93:e188a91d3eaa 4038 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
Kojto 93:e188a91d3eaa 4039 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
Kojto 93:e188a91d3eaa 4040 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
Kojto 93:e188a91d3eaa 4041 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
Kojto 93:e188a91d3eaa 4042 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
Kojto 93:e188a91d3eaa 4043 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
Kojto 93:e188a91d3eaa 4044 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
Kojto 93:e188a91d3eaa 4045 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
Kojto 93:e188a91d3eaa 4046 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
Kojto 93:e188a91d3eaa 4047 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
Kojto 93:e188a91d3eaa 4048 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
Kojto 93:e188a91d3eaa 4049 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
Kojto 93:e188a91d3eaa 4050 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
Kojto 93:e188a91d3eaa 4051 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
Kojto 93:e188a91d3eaa 4052 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
Kojto 93:e188a91d3eaa 4053 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
Kojto 93:e188a91d3eaa 4054 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
Kojto 93:e188a91d3eaa 4055 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
Kojto 93:e188a91d3eaa 4056 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
Kojto 93:e188a91d3eaa 4057 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
Kojto 93:e188a91d3eaa 4058 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
Kojto 93:e188a91d3eaa 4059 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
Kojto 93:e188a91d3eaa 4060 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
Kojto 93:e188a91d3eaa 4061 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
Kojto 93:e188a91d3eaa 4062 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
Kojto 93:e188a91d3eaa 4063 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
Kojto 93:e188a91d3eaa 4064
Kojto 93:e188a91d3eaa 4065 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
Kojto 93:e188a91d3eaa 4066 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
Kojto 93:e188a91d3eaa 4067 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
Kojto 93:e188a91d3eaa 4068 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
Kojto 93:e188a91d3eaa 4069 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
Kojto 93:e188a91d3eaa 4070 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
Kojto 93:e188a91d3eaa 4071 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
Kojto 93:e188a91d3eaa 4072 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
Kojto 93:e188a91d3eaa 4073 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
Kojto 93:e188a91d3eaa 4074 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
Kojto 93:e188a91d3eaa 4075 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
Kojto 93:e188a91d3eaa 4076 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
Kojto 93:e188a91d3eaa 4077 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 93:e188a91d3eaa 4078 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
Kojto 93:e188a91d3eaa 4079 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
Kojto 93:e188a91d3eaa 4080 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
Kojto 93:e188a91d3eaa 4081 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
Kojto 93:e188a91d3eaa 4082 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
Kojto 93:e188a91d3eaa 4083 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
Kojto 93:e188a91d3eaa 4084 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
Kojto 93:e188a91d3eaa 4085 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
Kojto 93:e188a91d3eaa 4086 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
Kojto 93:e188a91d3eaa 4087 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
Kojto 93:e188a91d3eaa 4088 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
Kojto 93:e188a91d3eaa 4089 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
Kojto 93:e188a91d3eaa 4090 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
Kojto 93:e188a91d3eaa 4091 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
Kojto 93:e188a91d3eaa 4092
Kojto 93:e188a91d3eaa 4093 /******************** Bit definition forUSB_OTG_DAINT register ********************/
Kojto 93:e188a91d3eaa 4094 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
Kojto 93:e188a91d3eaa 4095 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
Kojto 93:e188a91d3eaa 4096
Kojto 93:e188a91d3eaa 4097 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
Kojto 93:e188a91d3eaa 4098 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
Kojto 93:e188a91d3eaa 4099
Kojto 93:e188a91d3eaa 4100 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 93:e188a91d3eaa 4101 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4102 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4103 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4104 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4105
Kojto 93:e188a91d3eaa 4106 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
Kojto 93:e188a91d3eaa 4107 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4108 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
Kojto 93:e188a91d3eaa 4109
Kojto 93:e188a91d3eaa 4110 /******************** Bit definition for OTG register ********************/
Kojto 93:e188a91d3eaa 4111
Kojto 93:e188a91d3eaa 4112 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 93:e188a91d3eaa 4113 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4114 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4115 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4116 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4117 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 93:e188a91d3eaa 4118
Kojto 93:e188a91d3eaa 4119 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 93:e188a91d3eaa 4120 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4121 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4122
Kojto 93:e188a91d3eaa 4123 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 93:e188a91d3eaa 4124 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4125 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4126 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4127 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4128
Kojto 93:e188a91d3eaa 4129 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 93:e188a91d3eaa 4130 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4131 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4132 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4133 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4134
Kojto 93:e188a91d3eaa 4135 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 93:e188a91d3eaa 4136 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4137 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4138 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4139 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4140
Kojto 93:e188a91d3eaa 4141 /******************** Bit definition for OTG register ********************/
Kojto 93:e188a91d3eaa 4142
Kojto 93:e188a91d3eaa 4143 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 93:e188a91d3eaa 4144 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4145 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4146 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4147 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4148 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 93:e188a91d3eaa 4149
Kojto 93:e188a91d3eaa 4150 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 93:e188a91d3eaa 4151 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4152 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4153
Kojto 93:e188a91d3eaa 4154 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 93:e188a91d3eaa 4155 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4156 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4157 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4158 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4159
Kojto 93:e188a91d3eaa 4160 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 93:e188a91d3eaa 4161 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4162 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4163 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4164 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4165
Kojto 93:e188a91d3eaa 4166 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 93:e188a91d3eaa 4167 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4168 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4169 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4170 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4171
Kojto 93:e188a91d3eaa 4172 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
Kojto 93:e188a91d3eaa 4173 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
Kojto 93:e188a91d3eaa 4174
Kojto 93:e188a91d3eaa 4175 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
Kojto 93:e188a91d3eaa 4176 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
Kojto 93:e188a91d3eaa 4177
Kojto 93:e188a91d3eaa 4178 /******************** Bit definition for OTG register ********************/
Kojto 93:e188a91d3eaa 4179 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
Kojto 93:e188a91d3eaa 4180 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
Kojto 93:e188a91d3eaa 4181 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
Kojto 93:e188a91d3eaa 4182 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
Kojto 93:e188a91d3eaa 4183
Kojto 93:e188a91d3eaa 4184 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
Kojto 93:e188a91d3eaa 4185 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
Kojto 93:e188a91d3eaa 4186
Kojto 93:e188a91d3eaa 4187 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
Kojto 93:e188a91d3eaa 4188 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
Kojto 93:e188a91d3eaa 4189
Kojto 93:e188a91d3eaa 4190 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
Kojto 93:e188a91d3eaa 4191 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4192 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4193 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4194 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4195 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4196 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4197 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4198 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 4199
Kojto 93:e188a91d3eaa 4200 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
Kojto 93:e188a91d3eaa 4201 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4202 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4203 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4204 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4205 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4206 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4207 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4208
Kojto 93:e188a91d3eaa 4209 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
Kojto 93:e188a91d3eaa 4210 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
Kojto 93:e188a91d3eaa 4211 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
Kojto 93:e188a91d3eaa 4212
Kojto 93:e188a91d3eaa 4213 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
Kojto 93:e188a91d3eaa 4214 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4215 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4216 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4217 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4218 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4219 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4220 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4221 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 4222 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
Kojto 93:e188a91d3eaa 4223 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
Kojto 93:e188a91d3eaa 4224
Kojto 93:e188a91d3eaa 4225 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
Kojto 93:e188a91d3eaa 4226 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4227 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4228 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4229 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4230 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4231 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4232 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4233 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
Kojto 93:e188a91d3eaa 4234 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
Kojto 93:e188a91d3eaa 4235 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
Kojto 93:e188a91d3eaa 4236
Kojto 93:e188a91d3eaa 4237 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
Kojto 93:e188a91d3eaa 4238 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 93:e188a91d3eaa 4239
Kojto 93:e188a91d3eaa 4240 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
Kojto 93:e188a91d3eaa 4241 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
Kojto 93:e188a91d3eaa 4242 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
Kojto 93:e188a91d3eaa 4243
Kojto 93:e188a91d3eaa 4244 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
Kojto 93:e188a91d3eaa 4245 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
Kojto 93:e188a91d3eaa 4246 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
Kojto 93:e188a91d3eaa 4247 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
Kojto 93:e188a91d3eaa 4248 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
Kojto 93:e188a91d3eaa 4249 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
Kojto 93:e188a91d3eaa 4250 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
Kojto 93:e188a91d3eaa 4251
Kojto 93:e188a91d3eaa 4252 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
Kojto 93:e188a91d3eaa 4253 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
Kojto 93:e188a91d3eaa 4254 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 93:e188a91d3eaa 4255
Kojto 93:e188a91d3eaa 4256 /******************** Bit definition forUSB_OTG_CID register ********************/
Kojto 93:e188a91d3eaa 4257 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
Kojto 93:e188a91d3eaa 4258
Kojto 93:e188a91d3eaa 4259 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
Kojto 93:e188a91d3eaa 4260 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 93:e188a91d3eaa 4261 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 93:e188a91d3eaa 4262 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 93:e188a91d3eaa 4263 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 93:e188a91d3eaa 4264 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 93:e188a91d3eaa 4265 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 93:e188a91d3eaa 4266 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 93:e188a91d3eaa 4267 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 93:e188a91d3eaa 4268 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 93:e188a91d3eaa 4269
Kojto 93:e188a91d3eaa 4270 /******************** Bit definition forUSB_OTG_HPRT register ********************/
Kojto 93:e188a91d3eaa 4271 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
Kojto 93:e188a91d3eaa 4272 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
Kojto 93:e188a91d3eaa 4273 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
Kojto 93:e188a91d3eaa 4274 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
Kojto 93:e188a91d3eaa 4275 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
Kojto 93:e188a91d3eaa 4276 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
Kojto 93:e188a91d3eaa 4277 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
Kojto 93:e188a91d3eaa 4278 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
Kojto 93:e188a91d3eaa 4279 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
Kojto 93:e188a91d3eaa 4280
Kojto 93:e188a91d3eaa 4281 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
Kojto 93:e188a91d3eaa 4282 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4283 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4284 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
Kojto 93:e188a91d3eaa 4285
Kojto 93:e188a91d3eaa 4286 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
Kojto 93:e188a91d3eaa 4287 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4288 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4289 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4290 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4291
Kojto 93:e188a91d3eaa 4292 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
Kojto 93:e188a91d3eaa 4293 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4294 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4295
Kojto 93:e188a91d3eaa 4296 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
Kojto 93:e188a91d3eaa 4297 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 93:e188a91d3eaa 4298 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 93:e188a91d3eaa 4299 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
Kojto 93:e188a91d3eaa 4300 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 93:e188a91d3eaa 4301 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 93:e188a91d3eaa 4302 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 93:e188a91d3eaa 4303 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 93:e188a91d3eaa 4304 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 93:e188a91d3eaa 4305 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
Kojto 93:e188a91d3eaa 4306 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 93:e188a91d3eaa 4307 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
Kojto 93:e188a91d3eaa 4308
Kojto 93:e188a91d3eaa 4309 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
Kojto 93:e188a91d3eaa 4310 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
Kojto 93:e188a91d3eaa 4311 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
Kojto 93:e188a91d3eaa 4312
Kojto 93:e188a91d3eaa 4313 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
Kojto 93:e188a91d3eaa 4314 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 93:e188a91d3eaa 4315 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 93:e188a91d3eaa 4316 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
Kojto 93:e188a91d3eaa 4317 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 93:e188a91d3eaa 4318
Kojto 93:e188a91d3eaa 4319 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 93:e188a91d3eaa 4320 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4321 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4322 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 93:e188a91d3eaa 4323
Kojto 93:e188a91d3eaa 4324 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
Kojto 93:e188a91d3eaa 4325 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4326 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4327 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4328 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4329 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 93:e188a91d3eaa 4330 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 93:e188a91d3eaa 4331 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 93:e188a91d3eaa 4332 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 93:e188a91d3eaa 4333 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 93:e188a91d3eaa 4334 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 93:e188a91d3eaa 4335
Kojto 93:e188a91d3eaa 4336 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
Kojto 93:e188a91d3eaa 4337 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 93:e188a91d3eaa 4338
Kojto 93:e188a91d3eaa 4339 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
Kojto 93:e188a91d3eaa 4340 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4341 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4342 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4343 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4344 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
Kojto 93:e188a91d3eaa 4345 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
Kojto 93:e188a91d3eaa 4346
Kojto 93:e188a91d3eaa 4347 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 93:e188a91d3eaa 4348 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4349 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4350
Kojto 93:e188a91d3eaa 4351 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
Kojto 93:e188a91d3eaa 4352 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4353 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4354
Kojto 93:e188a91d3eaa 4355 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
Kojto 93:e188a91d3eaa 4356 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4357 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4358 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4359 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4360 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4361 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4362 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4363 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
Kojto 93:e188a91d3eaa 4364 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
Kojto 93:e188a91d3eaa 4365 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
Kojto 93:e188a91d3eaa 4366
Kojto 93:e188a91d3eaa 4367 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
Kojto 93:e188a91d3eaa 4368
Kojto 93:e188a91d3eaa 4369 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
Kojto 93:e188a91d3eaa 4370 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4371 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4372 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4373 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4374 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4375 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4376 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4377
Kojto 93:e188a91d3eaa 4378 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
Kojto 93:e188a91d3eaa 4379 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4380 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4381 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 93:e188a91d3eaa 4382 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 93:e188a91d3eaa 4383 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 93:e188a91d3eaa 4384 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 93:e188a91d3eaa 4385 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
Kojto 93:e188a91d3eaa 4386
Kojto 93:e188a91d3eaa 4387 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
Kojto 93:e188a91d3eaa 4388 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4389 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4390 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
Kojto 93:e188a91d3eaa 4391 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
Kojto 93:e188a91d3eaa 4392
Kojto 93:e188a91d3eaa 4393 /******************** Bit definition forUSB_OTG_HCINT register ********************/
Kojto 93:e188a91d3eaa 4394 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
Kojto 93:e188a91d3eaa 4395 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
Kojto 93:e188a91d3eaa 4396 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 93:e188a91d3eaa 4397 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
Kojto 93:e188a91d3eaa 4398 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
Kojto 93:e188a91d3eaa 4399 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
Kojto 93:e188a91d3eaa 4400 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
Kojto 93:e188a91d3eaa 4401 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
Kojto 93:e188a91d3eaa 4402 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
Kojto 93:e188a91d3eaa 4403 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
Kojto 93:e188a91d3eaa 4404 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
Kojto 93:e188a91d3eaa 4405
Kojto 93:e188a91d3eaa 4406 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
Kojto 93:e188a91d3eaa 4407 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 93:e188a91d3eaa 4408 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 93:e188a91d3eaa 4409 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
Kojto 93:e188a91d3eaa 4410 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
Kojto 93:e188a91d3eaa 4411 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
Kojto 93:e188a91d3eaa 4412 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
Kojto 93:e188a91d3eaa 4413 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
Kojto 93:e188a91d3eaa 4414 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
Kojto 93:e188a91d3eaa 4415 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
Kojto 93:e188a91d3eaa 4416 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
Kojto 93:e188a91d3eaa 4417 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
Kojto 93:e188a91d3eaa 4418
Kojto 93:e188a91d3eaa 4419 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
Kojto 93:e188a91d3eaa 4420 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
Kojto 93:e188a91d3eaa 4421 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
Kojto 93:e188a91d3eaa 4422 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 93:e188a91d3eaa 4423 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
Kojto 93:e188a91d3eaa 4424 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
Kojto 93:e188a91d3eaa 4425 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
Kojto 93:e188a91d3eaa 4426 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
Kojto 93:e188a91d3eaa 4427 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
Kojto 93:e188a91d3eaa 4428 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
Kojto 93:e188a91d3eaa 4429 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
Kojto 93:e188a91d3eaa 4430 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
Kojto 93:e188a91d3eaa 4431
Kojto 93:e188a91d3eaa 4432 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 93:e188a91d3eaa 4433
Kojto 93:e188a91d3eaa 4434 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 93:e188a91d3eaa 4435 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 93:e188a91d3eaa 4436 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
Kojto 93:e188a91d3eaa 4437 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
Kojto 93:e188a91d3eaa 4438 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 93:e188a91d3eaa 4439 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 93:e188a91d3eaa 4440 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
Kojto 93:e188a91d3eaa 4441 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
Kojto 93:e188a91d3eaa 4442 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4443 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4444
Kojto 93:e188a91d3eaa 4445 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
Kojto 93:e188a91d3eaa 4446 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 93:e188a91d3eaa 4447
Kojto 93:e188a91d3eaa 4448 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
Kojto 93:e188a91d3eaa 4449 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 93:e188a91d3eaa 4450
Kojto 93:e188a91d3eaa 4451 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
Kojto 93:e188a91d3eaa 4452 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
Kojto 93:e188a91d3eaa 4453
Kojto 93:e188a91d3eaa 4454 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
Kojto 93:e188a91d3eaa 4455 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 93:e188a91d3eaa 4456 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
Kojto 93:e188a91d3eaa 4457
Kojto 93:e188a91d3eaa 4458 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
Kojto 93:e188a91d3eaa 4459
Kojto 93:e188a91d3eaa 4460 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4461 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 93:e188a91d3eaa 4462 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 93:e188a91d3eaa 4463 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 93:e188a91d3eaa 4464 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 93:e188a91d3eaa 4465 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 93:e188a91d3eaa 4466 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4467 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4468 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
Kojto 93:e188a91d3eaa 4469 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 93:e188a91d3eaa 4470 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 93:e188a91d3eaa 4471 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 93:e188a91d3eaa 4472 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 93:e188a91d3eaa 4473 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 93:e188a91d3eaa 4474
Kojto 93:e188a91d3eaa 4475 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
Kojto 93:e188a91d3eaa 4476 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 93:e188a91d3eaa 4477 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 93:e188a91d3eaa 4478 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
Kojto 93:e188a91d3eaa 4479 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
Kojto 93:e188a91d3eaa 4480 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
Kojto 93:e188a91d3eaa 4481 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
Kojto 93:e188a91d3eaa 4482
Kojto 93:e188a91d3eaa 4483 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
Kojto 93:e188a91d3eaa 4484
Kojto 93:e188a91d3eaa 4485 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 93:e188a91d3eaa 4486 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 93:e188a91d3eaa 4487
Kojto 93:e188a91d3eaa 4488 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
Kojto 93:e188a91d3eaa 4489 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4490 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4491
Kojto 93:e188a91d3eaa 4492 /******************** Bit definition for PCGCCTL register ********************/
Kojto 93:e188a91d3eaa 4493 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
Kojto 93:e188a91d3eaa 4494 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 93:e188a91d3eaa 4495 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 93:e188a91d3eaa 4496
Kojto 93:e188a91d3eaa 4497 /**
Kojto 93:e188a91d3eaa 4498 * @}
Kojto 93:e188a91d3eaa 4499 */
Kojto 93:e188a91d3eaa 4500
Kojto 93:e188a91d3eaa 4501 /**
Kojto 93:e188a91d3eaa 4502 * @}
Kojto 93:e188a91d3eaa 4503 */
Kojto 93:e188a91d3eaa 4504
Kojto 93:e188a91d3eaa 4505 /** @addtogroup Exported_macros
Kojto 93:e188a91d3eaa 4506 * @{
Kojto 93:e188a91d3eaa 4507 */
Kojto 93:e188a91d3eaa 4508
Kojto 93:e188a91d3eaa 4509 /******************************* ADC Instances ********************************/
Kojto 93:e188a91d3eaa 4510 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 93:e188a91d3eaa 4511
Kojto 93:e188a91d3eaa 4512 /******************************* CRC Instances ********************************/
Kojto 93:e188a91d3eaa 4513 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 93:e188a91d3eaa 4514
Kojto 93:e188a91d3eaa 4515 /******************************** DMA Instances *******************************/
Kojto 93:e188a91d3eaa 4516 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 93:e188a91d3eaa 4517 ((INSTANCE) == DMA1_Stream1) || \
Kojto 93:e188a91d3eaa 4518 ((INSTANCE) == DMA1_Stream2) || \
Kojto 93:e188a91d3eaa 4519 ((INSTANCE) == DMA1_Stream3) || \
Kojto 93:e188a91d3eaa 4520 ((INSTANCE) == DMA1_Stream4) || \
Kojto 93:e188a91d3eaa 4521 ((INSTANCE) == DMA1_Stream5) || \
Kojto 93:e188a91d3eaa 4522 ((INSTANCE) == DMA1_Stream6) || \
Kojto 93:e188a91d3eaa 4523 ((INSTANCE) == DMA1_Stream7) || \
Kojto 93:e188a91d3eaa 4524 ((INSTANCE) == DMA2_Stream0) || \
Kojto 93:e188a91d3eaa 4525 ((INSTANCE) == DMA2_Stream1) || \
Kojto 93:e188a91d3eaa 4526 ((INSTANCE) == DMA2_Stream2) || \
Kojto 93:e188a91d3eaa 4527 ((INSTANCE) == DMA2_Stream3) || \
Kojto 93:e188a91d3eaa 4528 ((INSTANCE) == DMA2_Stream4) || \
Kojto 93:e188a91d3eaa 4529 ((INSTANCE) == DMA2_Stream5) || \
Kojto 93:e188a91d3eaa 4530 ((INSTANCE) == DMA2_Stream6) || \
Kojto 93:e188a91d3eaa 4531 ((INSTANCE) == DMA2_Stream7))
Kojto 93:e188a91d3eaa 4532
Kojto 93:e188a91d3eaa 4533 /******************************* GPIO Instances *******************************/
Kojto 93:e188a91d3eaa 4534 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 4535 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 4536 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 4537 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 4538 ((INSTANCE) == GPIOE) || \
Kojto 93:e188a91d3eaa 4539 ((INSTANCE) == GPIOH))
Kojto 93:e188a91d3eaa 4540
Kojto 93:e188a91d3eaa 4541 /******************************** I2C Instances *******************************/
Kojto 93:e188a91d3eaa 4542 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 93:e188a91d3eaa 4543 ((INSTANCE) == I2C2) || \
Kojto 93:e188a91d3eaa 4544 ((INSTANCE) == I2C3))
Kojto 93:e188a91d3eaa 4545
Kojto 93:e188a91d3eaa 4546 /******************************** I2S Instances *******************************/
Kojto 99:dbbf35b96557 4547 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 4548 ((INSTANCE) == SPI2) || \
Kojto 93:e188a91d3eaa 4549 ((INSTANCE) == SPI3) || \
Kojto 93:e188a91d3eaa 4550 ((INSTANCE) == SPI4) || \
Kojto 93:e188a91d3eaa 4551 ((INSTANCE) == SPI5))
Kojto 93:e188a91d3eaa 4552
Kojto 93:e188a91d3eaa 4553 /*************************** I2S Extended Instances ***************************/
Kojto 99:dbbf35b96557 4554 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
Kojto 99:dbbf35b96557 4555 ((INSTANCE) == SPI3) || \
Kojto 99:dbbf35b96557 4556 ((INSTANCE) == I2S2ext) || \
Kojto 99:dbbf35b96557 4557 ((INSTANCE) == I2S3ext))
Kojto 93:e188a91d3eaa 4558
Kojto 93:e188a91d3eaa 4559
Kojto 93:e188a91d3eaa 4560 /****************************** RTC Instances *********************************/
Kojto 93:e188a91d3eaa 4561 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 93:e188a91d3eaa 4562
Kojto 93:e188a91d3eaa 4563 /******************************** SPI Instances *******************************/
Kojto 93:e188a91d3eaa 4564 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 4565 ((INSTANCE) == SPI2) || \
Kojto 93:e188a91d3eaa 4566 ((INSTANCE) == SPI3) || \
Kojto 93:e188a91d3eaa 4567 ((INSTANCE) == SPI4) || \
Kojto 93:e188a91d3eaa 4568 ((INSTANCE) == SPI5))
Kojto 93:e188a91d3eaa 4569 /*************************** SPI Extended Instances ***************************/
Kojto 93:e188a91d3eaa 4570 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 93:e188a91d3eaa 4571 ((INSTANCE) == SPI2) || \
Kojto 93:e188a91d3eaa 4572 ((INSTANCE) == SPI3) || \
Kojto 93:e188a91d3eaa 4573 ((INSTANCE) == SPI4) || \
Kojto 93:e188a91d3eaa 4574 ((INSTANCE) == SPI5) || \
Kojto 93:e188a91d3eaa 4575 ((INSTANCE) == I2S2ext) || \
Kojto 93:e188a91d3eaa 4576 ((INSTANCE) == I2S3ext))
Kojto 93:e188a91d3eaa 4577
Kojto 93:e188a91d3eaa 4578 /****************** TIM Instances : All supported instances *******************/
Kojto 93:e188a91d3eaa 4579 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4580 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4581 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4582 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4583 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4584 ((INSTANCE) == TIM9) || \
Kojto 93:e188a91d3eaa 4585 ((INSTANCE) == TIM10) || \
Kojto 93:e188a91d3eaa 4586 ((INSTANCE) == TIM11))
Kojto 93:e188a91d3eaa 4587
Kojto 93:e188a91d3eaa 4588 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 93:e188a91d3eaa 4589 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4590 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4591 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4592 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4593 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4594 ((INSTANCE) == TIM9) || \
Kojto 93:e188a91d3eaa 4595 ((INSTANCE) == TIM10) || \
Kojto 93:e188a91d3eaa 4596 ((INSTANCE) == TIM11))
Kojto 93:e188a91d3eaa 4597
Kojto 93:e188a91d3eaa 4598 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 93:e188a91d3eaa 4599 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4600 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4601 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4602 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4603 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4604 ((INSTANCE) == TIM9))
Kojto 93:e188a91d3eaa 4605
Kojto 93:e188a91d3eaa 4606 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 93:e188a91d3eaa 4607 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4608 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4609 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4610 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4611 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4612
Kojto 93:e188a91d3eaa 4613 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 93:e188a91d3eaa 4614 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4615 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4616 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4617 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4618 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4619
Kojto 93:e188a91d3eaa 4620 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 93:e188a91d3eaa 4621 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 93:e188a91d3eaa 4622
Kojto 93:e188a91d3eaa 4623 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 93:e188a91d3eaa 4624 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4625 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4626 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4627 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4628 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4629
Kojto 93:e188a91d3eaa 4630 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 93:e188a91d3eaa 4631 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4632 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4633 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4634 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4635 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4636
Kojto 93:e188a91d3eaa 4637 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 93:e188a91d3eaa 4638 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4639 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4640 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4641 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4642 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4643
Kojto 93:e188a91d3eaa 4644 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 93:e188a91d3eaa 4645 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4646 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4647 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4648 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4649 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4650
Kojto 93:e188a91d3eaa 4651 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 93:e188a91d3eaa 4652 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4653 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4654 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4655 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4656 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4657
Kojto 93:e188a91d3eaa 4658 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 93:e188a91d3eaa 4659 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4660 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4661 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4662 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4663 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4664 ((INSTANCE) == TIM9))
Kojto 93:e188a91d3eaa 4665
Kojto 93:e188a91d3eaa 4666 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 93:e188a91d3eaa 4667 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4668 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4669 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4670 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4671 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4672 ((INSTANCE) == TIM9))
Kojto 93:e188a91d3eaa 4673
Kojto 93:e188a91d3eaa 4674 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 93:e188a91d3eaa 4675 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4676 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4677
Kojto 93:e188a91d3eaa 4678 /***************** TIM Instances : external trigger input availabe ************/
Kojto 93:e188a91d3eaa 4679 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 93:e188a91d3eaa 4680 ((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4681 ((INSTANCE) == TIM3) || \
Kojto 93:e188a91d3eaa 4682 ((INSTANCE) == TIM4) || \
Kojto 93:e188a91d3eaa 4683 ((INSTANCE) == TIM5))
Kojto 93:e188a91d3eaa 4684
Kojto 93:e188a91d3eaa 4685 /****************** TIM Instances : remapping capability **********************/
Kojto 93:e188a91d3eaa 4686 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 93:e188a91d3eaa 4687 ((INSTANCE) == TIM5) || \
Kojto 93:e188a91d3eaa 4688 ((INSTANCE) == TIM11))
Kojto 93:e188a91d3eaa 4689
Kojto 93:e188a91d3eaa 4690 /******************* TIM Instances : output(s) available **********************/
Kojto 93:e188a91d3eaa 4691 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 93:e188a91d3eaa 4692 ((((INSTANCE) == TIM1) && \
Kojto 93:e188a91d3eaa 4693 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4694 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4695 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4696 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4697 || \
Kojto 93:e188a91d3eaa 4698 (((INSTANCE) == TIM2) && \
Kojto 93:e188a91d3eaa 4699 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4700 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4701 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4702 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4703 || \
Kojto 93:e188a91d3eaa 4704 (((INSTANCE) == TIM3) && \
Kojto 93:e188a91d3eaa 4705 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4706 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4707 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4708 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4709 || \
Kojto 93:e188a91d3eaa 4710 (((INSTANCE) == TIM4) && \
Kojto 93:e188a91d3eaa 4711 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4712 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4713 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4714 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4715 || \
Kojto 93:e188a91d3eaa 4716 (((INSTANCE) == TIM5) && \
Kojto 93:e188a91d3eaa 4717 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4718 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4719 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 93:e188a91d3eaa 4720 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 93:e188a91d3eaa 4721 || \
Kojto 93:e188a91d3eaa 4722 (((INSTANCE) == TIM9) && \
Kojto 93:e188a91d3eaa 4723 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4724 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 93:e188a91d3eaa 4725 || \
Kojto 93:e188a91d3eaa 4726 (((INSTANCE) == TIM10) && \
Kojto 93:e188a91d3eaa 4727 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 93:e188a91d3eaa 4728 || \
Kojto 93:e188a91d3eaa 4729 (((INSTANCE) == TIM11) && \
Kojto 93:e188a91d3eaa 4730 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 93:e188a91d3eaa 4731
Kojto 93:e188a91d3eaa 4732 /************ TIM Instances : complementary output(s) available ***************/
Kojto 93:e188a91d3eaa 4733 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 93:e188a91d3eaa 4734 ((((INSTANCE) == TIM1) && \
Kojto 93:e188a91d3eaa 4735 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 93:e188a91d3eaa 4736 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 93:e188a91d3eaa 4737 ((CHANNEL) == TIM_CHANNEL_3))))
Kojto 93:e188a91d3eaa 4738
Kojto 93:e188a91d3eaa 4739 /******************** USART Instances : Synchronous mode **********************/
Kojto 93:e188a91d3eaa 4740 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4741 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4742 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4743
Kojto 93:e188a91d3eaa 4744 /******************** UART Instances : Asynchronous mode **********************/
Kojto 93:e188a91d3eaa 4745 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4746 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4747 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4748
Kojto 93:e188a91d3eaa 4749 /****************** UART Instances : Hardware Flow control ********************/
Kojto 93:e188a91d3eaa 4750 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4751 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4752 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4753
Kojto 93:e188a91d3eaa 4754 /********************* UART Instances : Smard card mode ***********************/
Kojto 93:e188a91d3eaa 4755 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4756 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4757 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4758
Kojto 93:e188a91d3eaa 4759 /*********************** UART Instances : IRDA mode ***************************/
Kojto 93:e188a91d3eaa 4760 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 93:e188a91d3eaa 4761 ((INSTANCE) == USART2) || \
Kojto 93:e188a91d3eaa 4762 ((INSTANCE) == USART6))
Kojto 93:e188a91d3eaa 4763
Kojto 93:e188a91d3eaa 4764 /****************************** IWDG Instances ********************************/
Kojto 93:e188a91d3eaa 4765 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 93:e188a91d3eaa 4766
Kojto 93:e188a91d3eaa 4767 /****************************** WWDG Instances ********************************/
Kojto 93:e188a91d3eaa 4768 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 93:e188a91d3eaa 4769
Kojto 99:dbbf35b96557 4770 /****************************** SDIO Instances ********************************/
Kojto 99:dbbf35b96557 4771 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 99:dbbf35b96557 4772
Kojto 99:dbbf35b96557 4773 /****************************** USB Exported Constants ************************/
Kojto 99:dbbf35b96557 4774 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
Kojto 99:dbbf35b96557 4775 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
Kojto 99:dbbf35b96557 4776 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
Kojto 99:dbbf35b96557 4777 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
Kojto 93:e188a91d3eaa 4778
Kojto 93:e188a91d3eaa 4779 /**
Kojto 93:e188a91d3eaa 4780 * @}
Kojto 93:e188a91d3eaa 4781 */
Kojto 93:e188a91d3eaa 4782
Kojto 93:e188a91d3eaa 4783 /**
Kojto 93:e188a91d3eaa 4784 * @}
Kojto 93:e188a91d3eaa 4785 */
Kojto 93:e188a91d3eaa 4786
Kojto 93:e188a91d3eaa 4787 /**
Kojto 93:e188a91d3eaa 4788 * @}
Kojto 93:e188a91d3eaa 4789 */
Kojto 93:e188a91d3eaa 4790
Kojto 93:e188a91d3eaa 4791 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 4792 }
Kojto 93:e188a91d3eaa 4793 #endif /* __cplusplus */
Kojto 93:e188a91d3eaa 4794
Kojto 93:e188a91d3eaa 4795 #endif /* __STM32F411xE_H */
Kojto 93:e188a91d3eaa 4796
Kojto 93:e188a91d3eaa 4797
Kojto 93:e188a91d3eaa 4798
Kojto 93:e188a91d3eaa 4799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/