Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MAXWSNENV/max32610.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
99:dbbf35b96557 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /*******************************************************************************
Kojto 99:dbbf35b96557 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 99:dbbf35b96557 3 *
Kojto 99:dbbf35b96557 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 99:dbbf35b96557 5 * copy of this software and associated documentation files (the "Software"),
Kojto 99:dbbf35b96557 6 * to deal in the Software without restriction, including without limitation
Kojto 99:dbbf35b96557 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 99:dbbf35b96557 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 99:dbbf35b96557 9 * Software is furnished to do so, subject to the following conditions:
Kojto 99:dbbf35b96557 10 *
Kojto 99:dbbf35b96557 11 * The above copyright notice and this permission notice shall be included
Kojto 99:dbbf35b96557 12 * in all copies or substantial portions of the Software.
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 99:dbbf35b96557 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 99:dbbf35b96557 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 99:dbbf35b96557 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 99:dbbf35b96557 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 99:dbbf35b96557 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 99:dbbf35b96557 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 99:dbbf35b96557 21 *
Kojto 99:dbbf35b96557 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 99:dbbf35b96557 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 99:dbbf35b96557 24 * Products, Inc. Branding Policy.
Kojto 99:dbbf35b96557 25 *
Kojto 99:dbbf35b96557 26 * The mere transfer of this software does not imply any licenses
Kojto 99:dbbf35b96557 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 99:dbbf35b96557 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 99:dbbf35b96557 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 99:dbbf35b96557 30 * ownership rights.
Kojto 99:dbbf35b96557 31 *******************************************************************************
Kojto 99:dbbf35b96557 32 */
Kojto 99:dbbf35b96557 33
Kojto 99:dbbf35b96557 34 #ifndef _MAX32610_H_
Kojto 99:dbbf35b96557 35 #define _MAX32610_H_
Kojto 99:dbbf35b96557 36
Kojto 99:dbbf35b96557 37 #include <stdint.h>
Kojto 99:dbbf35b96557 38
Kojto 99:dbbf35b96557 39 typedef enum IRQn_Type {
Kojto 99:dbbf35b96557 40 NonMaskableInt_IRQn = -14,
Kojto 99:dbbf35b96557 41 HardFault_IRQn = -13,
Kojto 99:dbbf35b96557 42 MemoryManagement_IRQn = -12,
Kojto 99:dbbf35b96557 43 BusFault_IRQn = -11,
Kojto 99:dbbf35b96557 44 UsageFault_IRQn = -10,
Kojto 99:dbbf35b96557 45 SVCall_IRQn = -5,
Kojto 99:dbbf35b96557 46 DebugMonitor_IRQn = -4,
Kojto 99:dbbf35b96557 47 PendSV_IRQn = -2,
Kojto 99:dbbf35b96557 48 SysTick_IRQn = -1,
Kojto 99:dbbf35b96557 49
Kojto 99:dbbf35b96557 50 /* Externals interrupts */
Kojto 99:dbbf35b96557 51 UART0_IRQn = 0, /* 16:01 UART0 */
Kojto 99:dbbf35b96557 52 UART1_IRQn, /* 17: 2 UART1 */
Kojto 99:dbbf35b96557 53 I2CM0_IRQn, /* 18: 3 I2C Master 0 */
Kojto 99:dbbf35b96557 54 I2CS_IRQn, /* 19: 4 I2C Slave */
Kojto 99:dbbf35b96557 55 USB_IRQn, /* 20: 5 USB */
Kojto 99:dbbf35b96557 56 PMU_IRQn, /* 21: 6 DMA */
Kojto 99:dbbf35b96557 57 AFE_IRQn, /* 22: 7 AFE */
Kojto 99:dbbf35b96557 58 MAA_IRQn, /* 23: 8 MAA */
Kojto 99:dbbf35b96557 59 AES_IRQn, /* 24: 9 AES */
Kojto 99:dbbf35b96557 60 SPI0_IRQn, /* 25:10 SPI0 */
Kojto 99:dbbf35b96557 61 SPI1_IRQn, /* 26:11 SPI1 */
Kojto 99:dbbf35b96557 62 SPI2_IRQn, /* 27:12 SPI2 */
Kojto 99:dbbf35b96557 63 TMR0_IRQn, /* 28:13 Timer32-0 */
Kojto 99:dbbf35b96557 64 TMR1_IRQn, /* 29:14 Timer32-1 */
Kojto 99:dbbf35b96557 65 TMR2_IRQn, /* 30:15 Timer32-1 */
Kojto 99:dbbf35b96557 66 TMR3_IRQn, /* 31:16 Timer32-2 */
Kojto 99:dbbf35b96557 67 RSVD0_IRQn, /* 32:17 RSVD */
Kojto 99:dbbf35b96557 68 RSVD1_IRQn, /* 33:18 RSVD */
Kojto 99:dbbf35b96557 69 DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
Kojto 99:dbbf35b96557 70 DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
Kojto 99:dbbf35b96557 71 DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
Kojto 99:dbbf35b96557 72 DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
Kojto 99:dbbf35b96557 73 ADC_IRQn, /* 38:23 ADC */
Kojto 99:dbbf35b96557 74 FLC_IRQn, /* 39:24 Flash Controller */
Kojto 99:dbbf35b96557 75 PWRMAN_IRQn, /* 40:25 PWRMAN */
Kojto 99:dbbf35b96557 76 CLKMAN_IRQn, /* 41:26 CLKMAN */
Kojto 99:dbbf35b96557 77 RTC0_IRQn, /* 42:27 RTC INT0 */
Kojto 99:dbbf35b96557 78 RTC1_IRQn, /* 43:28 RTC INT1 */
Kojto 99:dbbf35b96557 79 RTC2_IRQn, /* 44:29 RTC INT2 */
Kojto 99:dbbf35b96557 80 RTC3_IRQn, /* 45:30 RTC INT3 */
Kojto 99:dbbf35b96557 81 WDT0_IRQn, /* 46:31 WATCHDOG0 */
Kojto 99:dbbf35b96557 82 WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
Kojto 99:dbbf35b96557 83 WDT1_IRQn, /* 48:33 WATCHDOG1 */
Kojto 99:dbbf35b96557 84 WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
Kojto 99:dbbf35b96557 85 GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
Kojto 99:dbbf35b96557 86 GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
Kojto 99:dbbf35b96557 87 GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
Kojto 99:dbbf35b96557 88 GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
Kojto 99:dbbf35b96557 89 GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
Kojto 99:dbbf35b96557 90 GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
Kojto 99:dbbf35b96557 91 GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
Kojto 99:dbbf35b96557 92 GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
Kojto 99:dbbf35b96557 93 TMR16_0_IRQn, /* 58:43 Timer16-s0 */
Kojto 99:dbbf35b96557 94 TMR16_1_IRQn, /* 59:44 Timer16-s1 */
Kojto 99:dbbf35b96557 95 TMR16_2_IRQn, /* 60:45 Timer16-s2 */
Kojto 99:dbbf35b96557 96 TMR16_3_IRQn, /* 61:46 Timer16-s3 */
Kojto 99:dbbf35b96557 97 I2CM1_IRQn, /* 62:47 I2C Master 1 */
Kojto 99:dbbf35b96557 98 MXC_IRQ_EXT_COUNT,
Kojto 99:dbbf35b96557 99 } IRQn_Type;
Kojto 99:dbbf35b96557 100
Kojto 99:dbbf35b96557 101 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
Kojto 99:dbbf35b96557 102
Kojto 99:dbbf35b96557 103 /* ================================================================================ */
Kojto 99:dbbf35b96557 104 /* ================ Processor and Core Peripheral Section ================ */
Kojto 99:dbbf35b96557 105 /* ================================================================================ */
Kojto 99:dbbf35b96557 106
Kojto 99:dbbf35b96557 107 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
Kojto 99:dbbf35b96557 108
Kojto 99:dbbf35b96557 109 #include <core_cm3.h> /* Processor and core peripherals */
Kojto 99:dbbf35b96557 110 #include "system_max32610.h" /* System Header */
Kojto 99:dbbf35b96557 111
Kojto 99:dbbf35b96557 112
Kojto 99:dbbf35b96557 113 /* ================================================================================ */
Kojto 99:dbbf35b96557 114 /* ================== Device Specific Memory Section ================== */
Kojto 99:dbbf35b96557 115 /* ================================================================================ */
Kojto 99:dbbf35b96557 116
Kojto 99:dbbf35b96557 117 #define MXC_FLASH_MEM_BASE 0x00000000UL
Kojto 99:dbbf35b96557 118 #define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB
Kojto 99:dbbf35b96557 119 #define MXC_FLASH_MEM_SIZE 0x00040000UL
Kojto 99:dbbf35b96557 120 #define MXC_SYS_MEM_BASE 0x20000000UL
Kojto 99:dbbf35b96557 121
Kojto 99:dbbf35b96557 122 /* ================================================================================ */
Kojto 99:dbbf35b96557 123 /* ================ Device Specific Peripheral Section ================ */
Kojto 99:dbbf35b96557 124 /* ================================================================================ */
Kojto 99:dbbf35b96557 125
Kojto 99:dbbf35b96557 126 /*******************************************************************************/
Kojto 99:dbbf35b96557 127 /* General Purpose I/O Ports (GPIO) */
Kojto 99:dbbf35b96557 128
Kojto 99:dbbf35b96557 129
Kojto 99:dbbf35b96557 130 #define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
Kojto 99:dbbf35b96557 131 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
Kojto 99:dbbf35b96557 132 #define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
Kojto 99:dbbf35b96557 133
Kojto 99:dbbf35b96557 134 #define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn)
Kojto 99:dbbf35b96557 135
Kojto 99:dbbf35b96557 136
Kojto 99:dbbf35b96557 137 /*******************************************************************************/
Kojto 99:dbbf35b96557 138 /* Pulse Train Generation */
Kojto 99:dbbf35b96557 139
Kojto 99:dbbf35b96557 140 #define MXC_CFG_PT_INSTANCES (13)
Kojto 99:dbbf35b96557 141
Kojto 99:dbbf35b96557 142 #define MXC_BASE_PTG ((uint32_t)0x40001000UL)
Kojto 99:dbbf35b96557 143 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
Kojto 99:dbbf35b96557 144 #define MXC_BASE_PT ((uint32_t)0x40001008UL)
Kojto 99:dbbf35b96557 145 #define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
Kojto 99:dbbf35b96557 146 #define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
Kojto 99:dbbf35b96557 147 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
Kojto 99:dbbf35b96557 148 #define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
Kojto 99:dbbf35b96557 149 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
Kojto 99:dbbf35b96557 150 #define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
Kojto 99:dbbf35b96557 151 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
Kojto 99:dbbf35b96557 152 #define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
Kojto 99:dbbf35b96557 153 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
Kojto 99:dbbf35b96557 154 #define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
Kojto 99:dbbf35b96557 155 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
Kojto 99:dbbf35b96557 156 #define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
Kojto 99:dbbf35b96557 157 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
Kojto 99:dbbf35b96557 158 #define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
Kojto 99:dbbf35b96557 159 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
Kojto 99:dbbf35b96557 160 #define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
Kojto 99:dbbf35b96557 161 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
Kojto 99:dbbf35b96557 162
Kojto 99:dbbf35b96557 163 /* PT12, PT13, PT14 are not used */
Kojto 99:dbbf35b96557 164
Kojto 99:dbbf35b96557 165 /*******************************************************************************/
Kojto 99:dbbf35b96557 166 /* CRC-16/CRC-32 Engine */
Kojto 99:dbbf35b96557 167
Kojto 99:dbbf35b96557 168 #define MXC_BASE_CRC ((uint32_t)0x40010000UL)
Kojto 99:dbbf35b96557 169 #define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
Kojto 99:dbbf35b96557 170
Kojto 99:dbbf35b96557 171 #define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
Kojto 99:dbbf35b96557 172 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
Kojto 99:dbbf35b96557 173
Kojto 99:dbbf35b96557 174 /*******************************************************************************/
Kojto 99:dbbf35b96557 175 /* Trust Protection Unit (TPU) */
Kojto 99:dbbf35b96557 176
Kojto 99:dbbf35b96557 177 #define MXC_BASE_TPU ((uint32_t)0x40011000UL)
Kojto 99:dbbf35b96557 178 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
Kojto 99:dbbf35b96557 179
Kojto 99:dbbf35b96557 180 #define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
Kojto 99:dbbf35b96557 181 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
Kojto 99:dbbf35b96557 182
Kojto 99:dbbf35b96557 183 /*******************************************************************************/
Kojto 99:dbbf35b96557 184 /* AES Cryptographic Engine */
Kojto 99:dbbf35b96557 185
Kojto 99:dbbf35b96557 186 #define MXC_BASE_AES ((uint32_t)0x40011400UL)
Kojto 99:dbbf35b96557 187 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
Kojto 99:dbbf35b96557 188
Kojto 99:dbbf35b96557 189 #define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
Kojto 99:dbbf35b96557 190 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
Kojto 99:dbbf35b96557 191
Kojto 99:dbbf35b96557 192
Kojto 99:dbbf35b96557 193 /*******************************************************************************/
Kojto 99:dbbf35b96557 194 /* MAA Cryptographic Engine */
Kojto 99:dbbf35b96557 195
Kojto 99:dbbf35b96557 196 #define MXC_BASE_MAA ((uint32_t)0x40011800UL)
Kojto 99:dbbf35b96557 197 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
Kojto 99:dbbf35b96557 198
Kojto 99:dbbf35b96557 199 #define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
Kojto 99:dbbf35b96557 200 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
Kojto 99:dbbf35b96557 201
Kojto 99:dbbf35b96557 202 /*******************************************************************************/
Kojto 99:dbbf35b96557 203 /* 32-Bit PWM Timer/Counter */
Kojto 99:dbbf35b96557 204
Kojto 99:dbbf35b96557 205 #define MXC_CFG_TMR_INSTANCES (4)
Kojto 99:dbbf35b96557 206
Kojto 99:dbbf35b96557 207 #define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
Kojto 99:dbbf35b96557 208 #define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
Kojto 99:dbbf35b96557 209 #define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
Kojto 99:dbbf35b96557 210
Kojto 99:dbbf35b96557 211 #define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
Kojto 99:dbbf35b96557 212 #define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
Kojto 99:dbbf35b96557 213 #define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
Kojto 99:dbbf35b96557 214
Kojto 99:dbbf35b96557 215 #define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
Kojto 99:dbbf35b96557 216 #define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
Kojto 99:dbbf35b96557 217 #define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
Kojto 99:dbbf35b96557 218
Kojto 99:dbbf35b96557 219 #define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
Kojto 99:dbbf35b96557 220 #define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
Kojto 99:dbbf35b96557 221 #define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
Kojto 99:dbbf35b96557 222
Kojto 99:dbbf35b96557 223
Kojto 99:dbbf35b96557 224 #define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
Kojto 99:dbbf35b96557 225 (i) == 1 ? TMR1_IRQn : \
Kojto 99:dbbf35b96557 226 (i) == 2 ? TMR2_IRQn : \
Kojto 99:dbbf35b96557 227 (i) == 3 ? TMR3_IRQn : 0)
Kojto 99:dbbf35b96557 228
Kojto 99:dbbf35b96557 229 #define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
Kojto 99:dbbf35b96557 230 (i) == 1 ? TMR1_IRQn : \
Kojto 99:dbbf35b96557 231 (i) == 2 ? TMR2_IRQn : \
Kojto 99:dbbf35b96557 232 (i) == 3 ? TMR3_IRQn : \
Kojto 99:dbbf35b96557 233 (i) == 4 ? TMR16_0_IRQn : \
Kojto 99:dbbf35b96557 234 (i) == 5 ? TMR16_1_IRQn : \
Kojto 99:dbbf35b96557 235 (i) == 6 ? TMR16_2_IRQn : \
Kojto 99:dbbf35b96557 236 (i) == 7 ? TMR16_3_IRQn : 0)
Kojto 99:dbbf35b96557 237
Kojto 99:dbbf35b96557 238 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
Kojto 99:dbbf35b96557 239 (i) == 1 ? MXC_BASE_TMR1 : \
Kojto 99:dbbf35b96557 240 (i) == 2 ? MXC_BASE_TMR2 : \
Kojto 99:dbbf35b96557 241 (i) == 3 ? MXC_BASE_TMR3 : 0)
Kojto 99:dbbf35b96557 242
Kojto 99:dbbf35b96557 243 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
Kojto 99:dbbf35b96557 244 (i) == 1 ? MXC_TMR1 : \
Kojto 99:dbbf35b96557 245 (i) == 2 ? MXC_TMR2 : \
Kojto 99:dbbf35b96557 246 (i) == 3 ? MXC_TMR3 : 0)
Kojto 99:dbbf35b96557 247 /*******************************************************************************/
Kojto 99:dbbf35b96557 248 /* Watchdog Timer */
Kojto 99:dbbf35b96557 249
Kojto 99:dbbf35b96557 250 #define MXC_CFG_WDT_INSTANCES (2)
Kojto 99:dbbf35b96557 251
Kojto 99:dbbf35b96557 252 #define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
Kojto 99:dbbf35b96557 253 #define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
Kojto 99:dbbf35b96557 254 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
Kojto 99:dbbf35b96557 255
Kojto 99:dbbf35b96557 256 #define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
Kojto 99:dbbf35b96557 257 #define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
Kojto 99:dbbf35b96557 258 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
Kojto 99:dbbf35b96557 259
Kojto 99:dbbf35b96557 260 #define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
Kojto 99:dbbf35b96557 261 (i) == 1 ? WDT1_IRQn : 0)
Kojto 99:dbbf35b96557 262
Kojto 99:dbbf35b96557 263 #define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
Kojto 99:dbbf35b96557 264 (i) == 1 ? WDT1_P_IRQn : 0)
Kojto 99:dbbf35b96557 265
Kojto 99:dbbf35b96557 266 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
Kojto 99:dbbf35b96557 267 (i) == 1 ? MXC_BASE_WDT1 : 0)
Kojto 99:dbbf35b96557 268
Kojto 99:dbbf35b96557 269 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
Kojto 99:dbbf35b96557 270 (i) == 1 ? MXC_WDT1 : 0)
Kojto 99:dbbf35b96557 271
Kojto 99:dbbf35b96557 272 /*******************************************************************************/
Kojto 99:dbbf35b96557 273 /* SPI Interface */
Kojto 99:dbbf35b96557 274
Kojto 99:dbbf35b96557 275 #define MXC_CFG_SPI_INSTANCES (3)
Kojto 99:dbbf35b96557 276 #define MXC_CFG_SPI_FIFO_DEPTH (16)
Kojto 99:dbbf35b96557 277
Kojto 99:dbbf35b96557 278 #define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
Kojto 99:dbbf35b96557 279 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
Kojto 99:dbbf35b96557 280
Kojto 99:dbbf35b96557 281 #define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL)
Kojto 99:dbbf35b96557 282 #define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
Kojto 99:dbbf35b96557 283 #define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL)
Kojto 99:dbbf35b96557 284 #define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
Kojto 99:dbbf35b96557 285
Kojto 99:dbbf35b96557 286 #define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
Kojto 99:dbbf35b96557 287 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
Kojto 99:dbbf35b96557 288
Kojto 99:dbbf35b96557 289 #define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL)
Kojto 99:dbbf35b96557 290 #define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
Kojto 99:dbbf35b96557 291 #define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL)
Kojto 99:dbbf35b96557 292 #define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
Kojto 99:dbbf35b96557 293
Kojto 99:dbbf35b96557 294 #define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
Kojto 99:dbbf35b96557 295 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
Kojto 99:dbbf35b96557 296
Kojto 99:dbbf35b96557 297 #define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL)
Kojto 99:dbbf35b96557 298 #define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
Kojto 99:dbbf35b96557 299 #define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL)
Kojto 99:dbbf35b96557 300 #define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
Kojto 99:dbbf35b96557 301
Kojto 99:dbbf35b96557 302
Kojto 99:dbbf35b96557 303 #define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
Kojto 99:dbbf35b96557 304 (i) == 1 ? SPI1_IRQn : \
Kojto 99:dbbf35b96557 305 (i) == 2 ? SPI2_IRQn : 0)
Kojto 99:dbbf35b96557 306
Kojto 99:dbbf35b96557 307 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
Kojto 99:dbbf35b96557 308 (i) == 1 ? MXC_BASE_SPI1 : \
Kojto 99:dbbf35b96557 309 (i) == 2 ? MXC_BASE_SPI2 : 0)
Kojto 99:dbbf35b96557 310
Kojto 99:dbbf35b96557 311 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
Kojto 99:dbbf35b96557 312 (i) == 1 ? MXC_SPI1 : \
Kojto 99:dbbf35b96557 313 (i) == 2 ? MXC_SPI2 : 0)
Kojto 99:dbbf35b96557 314
Kojto 99:dbbf35b96557 315 #define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \
Kojto 99:dbbf35b96557 316 (i) == 1 ? MXC_SPI1_RXFIFO : \
Kojto 99:dbbf35b96557 317 (i) == 2 ? MXC_SPI2_RXFIFO : 0)
Kojto 99:dbbf35b96557 318
Kojto 99:dbbf35b96557 319 #define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \
Kojto 99:dbbf35b96557 320 (i) == 1 ? MXC_SPI1_TXFIFO : \
Kojto 99:dbbf35b96557 321 (i) == 2 ? MXC_SPI2_TXFIFO : 0)
Kojto 99:dbbf35b96557 322
Kojto 99:dbbf35b96557 323 #define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
Kojto 99:dbbf35b96557 324 #define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12)
Kojto 99:dbbf35b96557 325
Kojto 99:dbbf35b96557 326
Kojto 99:dbbf35b96557 327 /*******************************************************************************/
Kojto 99:dbbf35b96557 328 /* UART Interface */
Kojto 99:dbbf35b96557 329
Kojto 99:dbbf35b96557 330 #define MXC_CFG_UART_INSTANCES (2)
Kojto 99:dbbf35b96557 331
Kojto 99:dbbf35b96557 332 #define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
Kojto 99:dbbf35b96557 333 #define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
Kojto 99:dbbf35b96557 334 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
Kojto 99:dbbf35b96557 335
Kojto 99:dbbf35b96557 336 #define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
Kojto 99:dbbf35b96557 337 #define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
Kojto 99:dbbf35b96557 338 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
Kojto 99:dbbf35b96557 339
Kojto 99:dbbf35b96557 340
Kojto 99:dbbf35b96557 341 #define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
Kojto 99:dbbf35b96557 342 (i) == 1 ? UART1_IRQn : 0)
Kojto 99:dbbf35b96557 343
Kojto 99:dbbf35b96557 344 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
Kojto 99:dbbf35b96557 345 (i) == 1 ? MXC_BASE_UART1 : 0)
Kojto 99:dbbf35b96557 346
Kojto 99:dbbf35b96557 347 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
Kojto 99:dbbf35b96557 348 (i) == 1 ? MXC_UART1 : 0)
Kojto 99:dbbf35b96557 349
Kojto 99:dbbf35b96557 350 #define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
Kojto 99:dbbf35b96557 351 #define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12)
Kojto 99:dbbf35b96557 352
Kojto 99:dbbf35b96557 353
Kojto 99:dbbf35b96557 354 /*******************************************************************************/
Kojto 99:dbbf35b96557 355 /* I2C Master Interface */
Kojto 99:dbbf35b96557 356
Kojto 99:dbbf35b96557 357 #define MXC_CFG_I2CM_INSTANCES (2)
Kojto 99:dbbf35b96557 358
Kojto 99:dbbf35b96557 359 #define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
Kojto 99:dbbf35b96557 360 #define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
Kojto 99:dbbf35b96557 361 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
Kojto 99:dbbf35b96557 362 #define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL)
Kojto 99:dbbf35b96557 363 #define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL)
Kojto 99:dbbf35b96557 364
Kojto 99:dbbf35b96557 365 #define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
Kojto 99:dbbf35b96557 366 #define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
Kojto 99:dbbf35b96557 367 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
Kojto 99:dbbf35b96557 368 #define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL)
Kojto 99:dbbf35b96557 369 #define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL)
Kojto 99:dbbf35b96557 370
Kojto 99:dbbf35b96557 371 #define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
Kojto 99:dbbf35b96557 372 (i) == 1 ? I2CM1_IRQn : 0)
Kojto 99:dbbf35b96557 373
Kojto 99:dbbf35b96557 374 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
Kojto 99:dbbf35b96557 375 (i) == 1 ? MXC_BASE_I2CM1 : 0)
Kojto 99:dbbf35b96557 376
Kojto 99:dbbf35b96557 377 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
Kojto 99:dbbf35b96557 378 (i) == 1 ? MXC_I2CM1 : 0)
Kojto 99:dbbf35b96557 379
Kojto 99:dbbf35b96557 380 #define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \
Kojto 99:dbbf35b96557 381 (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
Kojto 99:dbbf35b96557 382
Kojto 99:dbbf35b96557 383 #define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \
Kojto 99:dbbf35b96557 384 (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
Kojto 99:dbbf35b96557 385
Kojto 99:dbbf35b96557 386 #define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
Kojto 99:dbbf35b96557 387 #define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13)
Kojto 99:dbbf35b96557 388
Kojto 99:dbbf35b96557 389
Kojto 99:dbbf35b96557 390 /*******************************************************************************/
Kojto 99:dbbf35b96557 391 /* I2C Slave Interface */
Kojto 99:dbbf35b96557 392
Kojto 99:dbbf35b96557 393 #define MXC_CFG_I2CS_INSTANCES (1)
Kojto 99:dbbf35b96557 394
Kojto 99:dbbf35b96557 395 #define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
Kojto 99:dbbf35b96557 396 #define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
Kojto 99:dbbf35b96557 397 #define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
Kojto 99:dbbf35b96557 398
Kojto 99:dbbf35b96557 399 #define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
Kojto 99:dbbf35b96557 400 #define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
Kojto 99:dbbf35b96557 401
Kojto 99:dbbf35b96557 402
Kojto 99:dbbf35b96557 403
Kojto 99:dbbf35b96557 404 /*******************************************************************************/
Kojto 99:dbbf35b96557 405 /* DACs */
Kojto 99:dbbf35b96557 406
Kojto 99:dbbf35b96557 407 #define MXC_CFG_DAC_INSTANCES (4)
Kojto 99:dbbf35b96557 408 #define MXC_CFG_DAC_FIFO_DEPTH (32)
Kojto 99:dbbf35b96557 409
Kojto 99:dbbf35b96557 410 #define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
Kojto 99:dbbf35b96557 411 #define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
Kojto 99:dbbf35b96557 412 #define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
Kojto 99:dbbf35b96557 413 #define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
Kojto 99:dbbf35b96557 414 #define MXC_DAC0_WIDTH ((uint8_t)(2))
Kojto 99:dbbf35b96557 415
Kojto 99:dbbf35b96557 416 #define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
Kojto 99:dbbf35b96557 417 #define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
Kojto 99:dbbf35b96557 418 #define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
Kojto 99:dbbf35b96557 419 #define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
Kojto 99:dbbf35b96557 420 #define MXC_DAC1_WIDTH ((uint8_t)(2))
Kojto 99:dbbf35b96557 421
Kojto 99:dbbf35b96557 422 #define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
Kojto 99:dbbf35b96557 423 #define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
Kojto 99:dbbf35b96557 424 #define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
Kojto 99:dbbf35b96557 425 #define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
Kojto 99:dbbf35b96557 426 #define MXC_DAC2_WIDTH ((uint8_t)(1))
Kojto 99:dbbf35b96557 427
Kojto 99:dbbf35b96557 428 #define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
Kojto 99:dbbf35b96557 429 #define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
Kojto 99:dbbf35b96557 430 #define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
Kojto 99:dbbf35b96557 431 #define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
Kojto 99:dbbf35b96557 432 #define MXC_DAC3_WIDTH ((uint8_t)(1))
Kojto 99:dbbf35b96557 433
Kojto 99:dbbf35b96557 434
Kojto 99:dbbf35b96557 435 #define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
Kojto 99:dbbf35b96557 436 (i) == 1 ? DAC1_IRQn : \
Kojto 99:dbbf35b96557 437 (i) == 2 ? DAC2_IRQn : \
Kojto 99:dbbf35b96557 438 (i) == 3 ? DAC3_IRQn : 0)
Kojto 99:dbbf35b96557 439
Kojto 99:dbbf35b96557 440
Kojto 99:dbbf35b96557 441 #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
Kojto 99:dbbf35b96557 442 i == 1 ? MXC_BASE_DAC1 : \
Kojto 99:dbbf35b96557 443 i == 2 ? MXC_BASE_DAC2 : \
Kojto 99:dbbf35b96557 444 i == 3 ? MXC_BASE_DAC3 : 0)
Kojto 99:dbbf35b96557 445
Kojto 99:dbbf35b96557 446 #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
Kojto 99:dbbf35b96557 447 i == 1 ? MXC_BASE_DAC1_FIFO : \
Kojto 99:dbbf35b96557 448 i == 2 ? MXC_BASE_DAC2_FIFO : \
Kojto 99:dbbf35b96557 449 i == 3 ? MXC_BASE_DAC3_FIFO : 0)
Kojto 99:dbbf35b96557 450
Kojto 99:dbbf35b96557 451 #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
Kojto 99:dbbf35b96557 452 i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
Kojto 99:dbbf35b96557 453 i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
Kojto 99:dbbf35b96557 454 i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
Kojto 99:dbbf35b96557 455
Kojto 99:dbbf35b96557 456 #define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
Kojto 99:dbbf35b96557 457 i == 1 ? MXC_DAC1 : \
Kojto 99:dbbf35b96557 458 i == 2 ? MXC_DAC2 : \
Kojto 99:dbbf35b96557 459 i == 3 ? MXC_DAC3 : 0)
Kojto 99:dbbf35b96557 460
Kojto 99:dbbf35b96557 461 #define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
Kojto 99:dbbf35b96557 462 i == 1 ? MXC_DAC1_WIDTH : \
Kojto 99:dbbf35b96557 463 i == 2 ? MXC_DAC2_WIDTH : \
Kojto 99:dbbf35b96557 464 i == 3 ? MXC_DAC3_WIDTH : 0)
Kojto 99:dbbf35b96557 465
Kojto 99:dbbf35b96557 466
Kojto 99:dbbf35b96557 467 /*******************************************************************************/
Kojto 99:dbbf35b96557 468 /* Analog Front End */
Kojto 99:dbbf35b96557 469
Kojto 99:dbbf35b96557 470 #define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
Kojto 99:dbbf35b96557 471 #define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
Kojto 99:dbbf35b96557 472
Kojto 99:dbbf35b96557 473
Kojto 99:dbbf35b96557 474
Kojto 99:dbbf35b96557 475 /*******************************************************************************/
Kojto 99:dbbf35b96557 476 /* ADC */
Kojto 99:dbbf35b96557 477
Kojto 99:dbbf35b96557 478 #define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
Kojto 99:dbbf35b96557 479
Kojto 99:dbbf35b96557 480 #define MXC_BASE_ADC ((uint32_t)0x40054000UL)
Kojto 99:dbbf35b96557 481 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
Kojto 99:dbbf35b96557 482
Kojto 99:dbbf35b96557 483 #define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
Kojto 99:dbbf35b96557 484 #define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
Kojto 99:dbbf35b96557 485
Kojto 99:dbbf35b96557 486 #define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
Kojto 99:dbbf35b96557 487 #define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
Kojto 99:dbbf35b96557 488
Kojto 99:dbbf35b96557 489
Kojto 99:dbbf35b96557 490
Kojto 99:dbbf35b96557 491 /*******************************************************************************/
Kojto 99:dbbf35b96557 492 /* Peripheral Management Unit (PMU) - formerly DMA Controller */
Kojto 99:dbbf35b96557 493
Kojto 99:dbbf35b96557 494 #define MXC_CFG_PMU_CHANNELS (6)
Kojto 99:dbbf35b96557 495
Kojto 99:dbbf35b96557 496 #define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
Kojto 99:dbbf35b96557 497 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
Kojto 99:dbbf35b96557 498 #define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
Kojto 99:dbbf35b96557 499 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
Kojto 99:dbbf35b96557 500 #define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
Kojto 99:dbbf35b96557 501 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
Kojto 99:dbbf35b96557 502 #define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
Kojto 99:dbbf35b96557 503 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
Kojto 99:dbbf35b96557 504 #define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
Kojto 99:dbbf35b96557 505 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
Kojto 99:dbbf35b96557 506 #define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
Kojto 99:dbbf35b96557 507 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
Kojto 99:dbbf35b96557 508
Kojto 99:dbbf35b96557 509 #define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
Kojto 99:dbbf35b96557 510 #define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
Kojto 99:dbbf35b96557 511 /*******************************************************************************/
Kojto 99:dbbf35b96557 512
Kojto 99:dbbf35b96557 513 typedef enum {
Kojto 99:dbbf35b96557 514 PMU_IRQ_DAC0_FIFO_AE,
Kojto 99:dbbf35b96557 515 PMU_IRQ_DAC1_FIFO_AE,
Kojto 99:dbbf35b96557 516 PMU_IRQ_DAC2_FIFO_AE,
Kojto 99:dbbf35b96557 517 PMU_IRQ_DAC3_FIFO_AE,
Kojto 99:dbbf35b96557 518 PMU_IRQ_DAC0_DONE,
Kojto 99:dbbf35b96557 519 PMU_IRQ_DAC1_DONE,
Kojto 99:dbbf35b96557 520 PMU_IRQ_DAC2_DONE,
Kojto 99:dbbf35b96557 521 PMU_IRQ_DAC3_DONE,
Kojto 99:dbbf35b96557 522 PMU_IRQ_ADC_FIFO_AF,
Kojto 99:dbbf35b96557 523 PMU_IRQ_ADC_DONE,
Kojto 99:dbbf35b96557 524 PMU_IRQ_I2C_MST0_DONE,
Kojto 99:dbbf35b96557 525 PMU_IRQ_I2C_MST1_DONE,
Kojto 99:dbbf35b96557 526 PMU_IRQ_SPI0_RSLTS_DONE,
Kojto 99:dbbf35b96557 527 PMU_IRQ_SPI1_RSLTS_DONE,
Kojto 99:dbbf35b96557 528 PMU_IRQ_SPI2_RSLTS_DONE,
Kojto 99:dbbf35b96557 529 PMU_IRQ_MAA_DONE,
Kojto 99:dbbf35b96557 530 PMU_IRQ_SPI0_TX_FIFO_AE,
Kojto 99:dbbf35b96557 531 PMU_IRQ_SPI0_RSLTS_FIFO_AF,
Kojto 99:dbbf35b96557 532 PMU_IRQ_SPI1_TX_FIFO_AE,
Kojto 99:dbbf35b96557 533 PMU_IRQ_SPI1_RSLTS_FIFO_AF,
Kojto 99:dbbf35b96557 534 PMU_IRQ_SPI2_TX_FIFO_AE,
Kojto 99:dbbf35b96557 535 PMU_IRQ_SPI3_RSLTS_FIFO_AF,
Kojto 99:dbbf35b96557 536 PMU_IRQ_I2C_MST0_TRANS_FIFO,
Kojto 99:dbbf35b96557 537 PMU_IRQ_I2C_MST0_RSLT_FIFO,
Kojto 99:dbbf35b96557 538 PMU_IRQ_I2C_MST1_TRANS_FIFO,
Kojto 99:dbbf35b96557 539 PMU_IRQ_I2C_MST2_RSLT_FIFO,
Kojto 99:dbbf35b96557 540 PMU_IRQ_I2C_SLV_TRANS_FIFO,
Kojto 99:dbbf35b96557 541 PMU_IRQ_I2C_SLV_RSLT_FIFO,
Kojto 99:dbbf35b96557 542 PMU_IRQ_UART0_TX_FIFO,
Kojto 99:dbbf35b96557 543 PMU_IRQ_UART0_RX_FIFO,
Kojto 99:dbbf35b96557 544 PMU_IRQ_UART1_TX_FIFO,
Kojto 99:dbbf35b96557 545 PMU_IRQ_UART1_RX_FIFO,
Kojto 99:dbbf35b96557 546 PMU_IRQ_SPI0_EXCP,
Kojto 99:dbbf35b96557 547 PMU_IRQ_SPI1_EXCP,
Kojto 99:dbbf35b96557 548 PMU_IRQ_SPI2_EXCP,
Kojto 99:dbbf35b96557 549 PMU_IRQ_RSVD0,
Kojto 99:dbbf35b96557 550 PMU_IRQ_I2C_MST0_EXCP,
Kojto 99:dbbf35b96557 551 PMU_IRQ_I2C_MST1_EXCP,
Kojto 99:dbbf35b96557 552 PMU_IRQ_I2C_SLV_EXCP,
Kojto 99:dbbf35b96557 553 PMU_IRQ_RSVD1,
Kojto 99:dbbf35b96557 554 PMU_IRQ_GPIO0,
Kojto 99:dbbf35b96557 555 PMU_IRQ_GPIO1,
Kojto 99:dbbf35b96557 556 PMU_IRQ_GPIO2,
Kojto 99:dbbf35b96557 557 PMU_IRQ_GPIO3,
Kojto 99:dbbf35b96557 558 PMU_IRQ_GPIO4,
Kojto 99:dbbf35b96557 559 PMU_IRQ_GPIO5,
Kojto 99:dbbf35b96557 560 PMU_IRQ_GPIO6,
Kojto 99:dbbf35b96557 561 PMU_IRQ_GPIO7,
Kojto 99:dbbf35b96557 562 PMU_IRQ_GPIO8,
Kojto 99:dbbf35b96557 563 PMU_IRQ_AFE_COMP_NMI,
Kojto 99:dbbf35b96557 564 PMU_IRQ_AES_ENGINE,
Kojto 99:dbbf35b96557 565 } pmu_int_mask_t;
Kojto 99:dbbf35b96557 566
Kojto 99:dbbf35b96557 567 /*******************************************************************************/
Kojto 99:dbbf35b96557 568 /* USB */
Kojto 99:dbbf35b96557 569
Kojto 99:dbbf35b96557 570 #define MXC_BASE_USB ((uint32_t)0x4010C000UL)
Kojto 99:dbbf35b96557 571 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
Kojto 99:dbbf35b96557 572
Kojto 99:dbbf35b96557 573 #define MXC_USB_MAX_PACKET (64)
Kojto 99:dbbf35b96557 574 #define MXC_USB_NUM_EP (8)
Kojto 99:dbbf35b96557 575
Kojto 99:dbbf35b96557 576
Kojto 99:dbbf35b96557 577 /*******************************************************************************/
Kojto 99:dbbf35b96557 578 /* Instruction Cache Controller */
Kojto 99:dbbf35b96557 579
Kojto 99:dbbf35b96557 580 #define MXC_BASE_ICC ((uint32_t)0x40080000UL)
Kojto 99:dbbf35b96557 581 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
Kojto 99:dbbf35b96557 582
Kojto 99:dbbf35b96557 583 /* System Manager */
Kojto 99:dbbf35b96557 584
Kojto 99:dbbf35b96557 585 #define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
Kojto 99:dbbf35b96557 586
Kojto 99:dbbf35b96557 587 /*******************************************************************************/
Kojto 99:dbbf35b96557 588 /* Clock Manager */
Kojto 99:dbbf35b96557 589
Kojto 99:dbbf35b96557 590 #define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
Kojto 99:dbbf35b96557 591 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
Kojto 99:dbbf35b96557 592
Kojto 99:dbbf35b96557 593
Kojto 99:dbbf35b96557 594 /*******************************************************************************/
Kojto 99:dbbf35b96557 595 /* Power Manager */
Kojto 99:dbbf35b96557 596
Kojto 99:dbbf35b96557 597 #define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
Kojto 99:dbbf35b96557 598 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
Kojto 99:dbbf35b96557 599
Kojto 99:dbbf35b96557 600 /*******************************************************************************/
Kojto 99:dbbf35b96557 601 /* I/O Manager */
Kojto 99:dbbf35b96557 602
Kojto 99:dbbf35b96557 603 #define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
Kojto 99:dbbf35b96557 604 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
Kojto 99:dbbf35b96557 605
Kojto 99:dbbf35b96557 606
Kojto 99:dbbf35b96557 607 /*******************************************************************************/
Kojto 99:dbbf35b96557 608 /* RTC: Timer/Alarms */
Kojto 99:dbbf35b96557 609
Kojto 99:dbbf35b96557 610 #define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
Kojto 99:dbbf35b96557 611 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
Kojto 99:dbbf35b96557 612
Kojto 99:dbbf35b96557 613 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
Kojto 99:dbbf35b96557 614 i == 1 ? RTC1_IRQn : \
Kojto 99:dbbf35b96557 615 i == 2 ? RTC2_IRQn : \
Kojto 99:dbbf35b96557 616 i == 3 ? RTC3_IRQn : 0)
Kojto 99:dbbf35b96557 617
Kojto 99:dbbf35b96557 618 #define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
Kojto 99:dbbf35b96557 619 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
Kojto 99:dbbf35b96557 620 /*******************************************************************************/
Kojto 99:dbbf35b96557 621 /* RTC: Power Sequencer */
Kojto 99:dbbf35b96557 622
Kojto 99:dbbf35b96557 623 #define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
Kojto 99:dbbf35b96557 624 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
Kojto 99:dbbf35b96557 625
Kojto 99:dbbf35b96557 626 /*******************************************************************************/
Kojto 99:dbbf35b96557 627 /* Trim Shadow Registers */
Kojto 99:dbbf35b96557 628
Kojto 99:dbbf35b96557 629 #define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
Kojto 99:dbbf35b96557 630 #define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
Kojto 99:dbbf35b96557 631
Kojto 99:dbbf35b96557 632 /*******************************************************************************/
Kojto 99:dbbf35b96557 633 /* Flash Memory Controller / Security */
Kojto 99:dbbf35b96557 634
Kojto 99:dbbf35b96557 635 #define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
Kojto 99:dbbf35b96557 636 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
Kojto 99:dbbf35b96557 637 #define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
Kojto 99:dbbf35b96557 638 #define MXC_FLC_PAGE_SIZE_SHIFT 11
Kojto 99:dbbf35b96557 639 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
Kojto 99:dbbf35b96557 640 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
Kojto 99:dbbf35b96557 641
Kojto 99:dbbf35b96557 642 /*******************************************************************************/
Kojto 99:dbbf35b96557 643
Kojto 99:dbbf35b96557 644 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
Kojto 99:dbbf35b96557 645
Kojto 99:dbbf35b96557 646 /*******************************************************************************/
Kojto 99:dbbf35b96557 647
Kojto 99:dbbf35b96557 648 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
Kojto 99:dbbf35b96557 649 #define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0
Kojto 99:dbbf35b96557 650 #define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1
Kojto 99:dbbf35b96557 651 #define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
Kojto 99:dbbf35b96557 652
Kojto 99:dbbf35b96557 653 /*******************************************************************************/
Kojto 99:dbbf35b96557 654
Kojto 99:dbbf35b96557 655 #endif /* _MAX32610_H_ */