Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MAXWSNENV/ioman_regs.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
99:dbbf35b96557 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /*******************************************************************************
Kojto 99:dbbf35b96557 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 99:dbbf35b96557 3 *
Kojto 99:dbbf35b96557 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 99:dbbf35b96557 5 * copy of this software and associated documentation files (the "Software"),
Kojto 99:dbbf35b96557 6 * to deal in the Software without restriction, including without limitation
Kojto 99:dbbf35b96557 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 99:dbbf35b96557 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 99:dbbf35b96557 9 * Software is furnished to do so, subject to the following conditions:
Kojto 99:dbbf35b96557 10 *
Kojto 99:dbbf35b96557 11 * The above copyright notice and this permission notice shall be included
Kojto 99:dbbf35b96557 12 * in all copies or substantial portions of the Software.
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 99:dbbf35b96557 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 99:dbbf35b96557 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 99:dbbf35b96557 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 99:dbbf35b96557 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 99:dbbf35b96557 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 99:dbbf35b96557 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 99:dbbf35b96557 21 *
Kojto 99:dbbf35b96557 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 99:dbbf35b96557 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 99:dbbf35b96557 24 * Products, Inc. Branding Policy.
Kojto 99:dbbf35b96557 25 *
Kojto 99:dbbf35b96557 26 * The mere transfer of this software does not imply any licenses
Kojto 99:dbbf35b96557 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 99:dbbf35b96557 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 99:dbbf35b96557 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 99:dbbf35b96557 30 * ownership rights.
Kojto 99:dbbf35b96557 31 *******************************************************************************
Kojto 99:dbbf35b96557 32 */
Kojto 99:dbbf35b96557 33
Kojto 99:dbbf35b96557 34 #ifndef _MXC_IOMAN_REGS_H_
Kojto 99:dbbf35b96557 35 #define _MXC_IOMAN_REGS_H_
Kojto 99:dbbf35b96557 36
Kojto 99:dbbf35b96557 37 #ifdef __cplusplus
Kojto 99:dbbf35b96557 38 extern "C" {
Kojto 99:dbbf35b96557 39 #endif
Kojto 99:dbbf35b96557 40
Kojto 99:dbbf35b96557 41 #include <stdint.h>
Kojto 99:dbbf35b96557 42
Kojto 99:dbbf35b96557 43 /**
Kojto 99:dbbf35b96557 44 * @file ioman_regs.h
Kojto 99:dbbf35b96557 45 * @addtogroup ioman IO MUX Manager
Kojto 99:dbbf35b96557 46 * @{
Kojto 99:dbbf35b96557 47 */
Kojto 99:dbbf35b96557 48
Kojto 99:dbbf35b96557 49 typedef enum {
Kojto 99:dbbf35b96557 50 /** Pin Mapping 'A' */
Kojto 99:dbbf35b96557 51 MXC_E_IOMAN_MAPPING_A = 0,
Kojto 99:dbbf35b96557 52 /** Pin Mapping 'B' */
Kojto 99:dbbf35b96557 53 MXC_E_IOMAN_MAPPING_B,
Kojto 99:dbbf35b96557 54 /** Pin Mapping 'C' */
Kojto 99:dbbf35b96557 55 MXC_E_IOMAN_MAPPING_C,
Kojto 99:dbbf35b96557 56 /** Pin Mapping 'D' */
Kojto 99:dbbf35b96557 57 MXC_E_IOMAN_MAPPING_D,
Kojto 99:dbbf35b96557 58 /** Pin Mapping 'E' */
Kojto 99:dbbf35b96557 59 MXC_E_IOMAN_MAPPING_E,
Kojto 99:dbbf35b96557 60 /** Pin Mapping 'F' */
Kojto 99:dbbf35b96557 61 MXC_E_IOMAN_MAPPING_F,
Kojto 99:dbbf35b96557 62 /** Pin Mapping 'G' */
Kojto 99:dbbf35b96557 63 MXC_E_IOMAN_MAPPING_G,
Kojto 99:dbbf35b96557 64 /** Pin Mapping 'H' */
Kojto 99:dbbf35b96557 65 MXC_E_IOMAN_MAPPING_H,
Kojto 99:dbbf35b96557 66 } ioman_mapping_t;
Kojto 99:dbbf35b96557 67
Kojto 99:dbbf35b96557 68 /* Offset Register Description
Kojto 99:dbbf35b96557 69 ====== ========================================== */
Kojto 99:dbbf35b96557 70 typedef struct {
Kojto 99:dbbf35b96557 71 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
Kojto 99:dbbf35b96557 72 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
Kojto 99:dbbf35b96557 73 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
Kojto 99:dbbf35b96557 74 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
Kojto 99:dbbf35b96557 75 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
Kojto 99:dbbf35b96557 76 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
Kojto 99:dbbf35b96557 77 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
Kojto 99:dbbf35b96557 78 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
Kojto 99:dbbf35b96557 79 __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
Kojto 99:dbbf35b96557 80 __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
Kojto 99:dbbf35b96557 81 __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
Kojto 99:dbbf35b96557 82 __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
Kojto 99:dbbf35b96557 83 __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
Kojto 99:dbbf35b96557 84 __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
Kojto 99:dbbf35b96557 85 __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
Kojto 99:dbbf35b96557 86 __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
Kojto 99:dbbf35b96557 87 __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
Kojto 99:dbbf35b96557 88 __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
Kojto 99:dbbf35b96557 89 __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
Kojto 99:dbbf35b96557 90 __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
Kojto 99:dbbf35b96557 91 __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
Kojto 99:dbbf35b96557 92 __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
Kojto 99:dbbf35b96557 93 __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
Kojto 99:dbbf35b96557 94 __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
Kojto 99:dbbf35b96557 95 __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
Kojto 99:dbbf35b96557 96 __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
Kojto 99:dbbf35b96557 97 __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
Kojto 99:dbbf35b96557 98 __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
Kojto 99:dbbf35b96557 99 __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
Kojto 99:dbbf35b96557 100 __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
Kojto 99:dbbf35b96557 101 __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
Kojto 99:dbbf35b96557 102 __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
Kojto 99:dbbf35b96557 103 __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
Kojto 99:dbbf35b96557 104 __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
Kojto 99:dbbf35b96557 105 __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
Kojto 99:dbbf35b96557 106 __IO uint32_t padx_control; /* 0x008C PADX Control */
Kojto 99:dbbf35b96557 107 } mxc_ioman_regs_t;
Kojto 99:dbbf35b96557 108
Kojto 99:dbbf35b96557 109
Kojto 99:dbbf35b96557 110 /*
Kojto 99:dbbf35b96557 111 Register offsets for module IOMAN.
Kojto 99:dbbf35b96557 112 */
Kojto 99:dbbf35b96557 113 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
Kojto 99:dbbf35b96557 114 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
Kojto 99:dbbf35b96557 115 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
Kojto 99:dbbf35b96557 116 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
Kojto 99:dbbf35b96557 117 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
Kojto 99:dbbf35b96557 118 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
Kojto 99:dbbf35b96557 119 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
Kojto 99:dbbf35b96557 120 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
Kojto 99:dbbf35b96557 121 #define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
Kojto 99:dbbf35b96557 122 #define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
Kojto 99:dbbf35b96557 123 #define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
Kojto 99:dbbf35b96557 124 #define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
Kojto 99:dbbf35b96557 125 #define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
Kojto 99:dbbf35b96557 126 #define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
Kojto 99:dbbf35b96557 127 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
Kojto 99:dbbf35b96557 128 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
Kojto 99:dbbf35b96557 129 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
Kojto 99:dbbf35b96557 130 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
Kojto 99:dbbf35b96557 131 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
Kojto 99:dbbf35b96557 132 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
Kojto 99:dbbf35b96557 133 #define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
Kojto 99:dbbf35b96557 134 #define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
Kojto 99:dbbf35b96557 135 #define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
Kojto 99:dbbf35b96557 136 #define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
Kojto 99:dbbf35b96557 137 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
Kojto 99:dbbf35b96557 138 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
Kojto 99:dbbf35b96557 139 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
Kojto 99:dbbf35b96557 140 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
Kojto 99:dbbf35b96557 141 #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
Kojto 99:dbbf35b96557 142 #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
Kojto 99:dbbf35b96557 143 #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
Kojto 99:dbbf35b96557 144 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
Kojto 99:dbbf35b96557 145 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
Kojto 99:dbbf35b96557 146 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
Kojto 99:dbbf35b96557 147 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
Kojto 99:dbbf35b96557 148 #define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
Kojto 99:dbbf35b96557 149
Kojto 99:dbbf35b96557 150
Kojto 99:dbbf35b96557 151 /*
Kojto 99:dbbf35b96557 152 Field positions and masks for module IOMAN.
Kojto 99:dbbf35b96557 153 */
Kojto 99:dbbf35b96557 154 #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
Kojto 99:dbbf35b96557 155 #define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
Kojto 99:dbbf35b96557 156 #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
Kojto 99:dbbf35b96557 157 #define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
Kojto 99:dbbf35b96557 158 #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
Kojto 99:dbbf35b96557 159 #define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
Kojto 99:dbbf35b96557 160 #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
Kojto 99:dbbf35b96557 161 #define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
Kojto 99:dbbf35b96557 162
Kojto 99:dbbf35b96557 163 #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
Kojto 99:dbbf35b96557 164 #define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
Kojto 99:dbbf35b96557 165 #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
Kojto 99:dbbf35b96557 166 #define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
Kojto 99:dbbf35b96557 167 #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
Kojto 99:dbbf35b96557 168 #define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
Kojto 99:dbbf35b96557 169 #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
Kojto 99:dbbf35b96557 170 #define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
Kojto 99:dbbf35b96557 171
Kojto 99:dbbf35b96557 172 #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
Kojto 99:dbbf35b96557 173 #define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
Kojto 99:dbbf35b96557 174 #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
Kojto 99:dbbf35b96557 175 #define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
Kojto 99:dbbf35b96557 176 #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
Kojto 99:dbbf35b96557 177 #define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
Kojto 99:dbbf35b96557 178 #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
Kojto 99:dbbf35b96557 179 #define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
Kojto 99:dbbf35b96557 180
Kojto 99:dbbf35b96557 181 #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
Kojto 99:dbbf35b96557 182 #define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
Kojto 99:dbbf35b96557 183 #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
Kojto 99:dbbf35b96557 184 #define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
Kojto 99:dbbf35b96557 185 #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
Kojto 99:dbbf35b96557 186 #define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
Kojto 99:dbbf35b96557 187 #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
Kojto 99:dbbf35b96557 188 #define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
Kojto 99:dbbf35b96557 189
Kojto 99:dbbf35b96557 190 #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
Kojto 99:dbbf35b96557 191 #define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
Kojto 99:dbbf35b96557 192 #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
Kojto 99:dbbf35b96557 193 #define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
Kojto 99:dbbf35b96557 194 #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
Kojto 99:dbbf35b96557 195 #define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
Kojto 99:dbbf35b96557 196 #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
Kojto 99:dbbf35b96557 197 #define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
Kojto 99:dbbf35b96557 198
Kojto 99:dbbf35b96557 199 #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
Kojto 99:dbbf35b96557 200 #define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
Kojto 99:dbbf35b96557 201 #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
Kojto 99:dbbf35b96557 202 #define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
Kojto 99:dbbf35b96557 203 #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
Kojto 99:dbbf35b96557 204 #define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
Kojto 99:dbbf35b96557 205 #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
Kojto 99:dbbf35b96557 206 #define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
Kojto 99:dbbf35b96557 207
Kojto 99:dbbf35b96557 208 #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
Kojto 99:dbbf35b96557 209 #define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
Kojto 99:dbbf35b96557 210 #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
Kojto 99:dbbf35b96557 211 #define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
Kojto 99:dbbf35b96557 212 #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
Kojto 99:dbbf35b96557 213 #define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
Kojto 99:dbbf35b96557 214 #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
Kojto 99:dbbf35b96557 215 #define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
Kojto 99:dbbf35b96557 216
Kojto 99:dbbf35b96557 217 #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
Kojto 99:dbbf35b96557 218 #define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
Kojto 99:dbbf35b96557 219 #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
Kojto 99:dbbf35b96557 220 #define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
Kojto 99:dbbf35b96557 221 #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
Kojto 99:dbbf35b96557 222 #define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
Kojto 99:dbbf35b96557 223 #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
Kojto 99:dbbf35b96557 224 #define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
Kojto 99:dbbf35b96557 225
Kojto 99:dbbf35b96557 226 #define MXC_F_IOMAN_SPI_MAPPING_POS 0
Kojto 99:dbbf35b96557 227 #define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
Kojto 99:dbbf35b96557 228 #define MXC_F_IOMAN_SPI_CORE_IO_POS 4
Kojto 99:dbbf35b96557 229 #define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
Kojto 99:dbbf35b96557 230 #define MXC_F_IOMAN_SPI_SS0_IO_POS 8
Kojto 99:dbbf35b96557 231 #define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
Kojto 99:dbbf35b96557 232 #define MXC_F_IOMAN_SPI_SS1_IO_POS 9
Kojto 99:dbbf35b96557 233 #define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
Kojto 99:dbbf35b96557 234 #define MXC_F_IOMAN_SPI_SS2_IO_POS 10
Kojto 99:dbbf35b96557 235 #define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
Kojto 99:dbbf35b96557 236 #define MXC_F_IOMAN_SPI_SS3_IO_POS 11
Kojto 99:dbbf35b96557 237 #define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
Kojto 99:dbbf35b96557 238 #define MXC_F_IOMAN_SPI_SS4_IO_POS 12
Kojto 99:dbbf35b96557 239 #define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
Kojto 99:dbbf35b96557 240 #define MXC_F_IOMAN_SPI_SR0_IO_POS 16
Kojto 99:dbbf35b96557 241 #define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
Kojto 99:dbbf35b96557 242 #define MXC_F_IOMAN_SPI_SR1_IO_POS 17
Kojto 99:dbbf35b96557 243 #define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
Kojto 99:dbbf35b96557 244 #define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
Kojto 99:dbbf35b96557 245 #define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
Kojto 99:dbbf35b96557 246 #define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
Kojto 99:dbbf35b96557 247 #define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
Kojto 99:dbbf35b96557 248
Kojto 99:dbbf35b96557 249 #define MXC_F_IOMAN_UART_MAPPING_POS 0
Kojto 99:dbbf35b96557 250 #define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
Kojto 99:dbbf35b96557 251 #define MXC_F_IOMAN_UART_CORE_IO_POS 4
Kojto 99:dbbf35b96557 252 #define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
Kojto 99:dbbf35b96557 253 #define MXC_F_IOMAN_UART_CTS_IO_POS 5
Kojto 99:dbbf35b96557 254 #define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
Kojto 99:dbbf35b96557 255 #define MXC_F_IOMAN_UART_RTS_IO_POS 6
Kojto 99:dbbf35b96557 256 #define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
Kojto 99:dbbf35b96557 257
Kojto 99:dbbf35b96557 258 #define MXC_F_IOMAN_I2CM_MAPPING_POS 0
Kojto 99:dbbf35b96557 259 #define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
Kojto 99:dbbf35b96557 260 #define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
Kojto 99:dbbf35b96557 261 #define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
Kojto 99:dbbf35b96557 262
Kojto 99:dbbf35b96557 263 #define MXC_F_IOMAN_I2CS_MAPPING_POS 0
Kojto 99:dbbf35b96557 264 #define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
Kojto 99:dbbf35b96557 265 #define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
Kojto 99:dbbf35b96557 266 #define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
Kojto 99:dbbf35b96557 267
Kojto 99:dbbf35b96557 268 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
Kojto 99:dbbf35b96557 269 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
Kojto 99:dbbf35b96557 270
Kojto 99:dbbf35b96557 271 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
Kojto 99:dbbf35b96557 272 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
Kojto 99:dbbf35b96557 273
Kojto 99:dbbf35b96557 274 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
Kojto 99:dbbf35b96557 275 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
Kojto 99:dbbf35b96557 276 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
Kojto 99:dbbf35b96557 277 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
Kojto 99:dbbf35b96557 278 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
Kojto 99:dbbf35b96557 279 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
Kojto 99:dbbf35b96557 280 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
Kojto 99:dbbf35b96557 281 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
Kojto 99:dbbf35b96557 282 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
Kojto 99:dbbf35b96557 283 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
Kojto 99:dbbf35b96557 284 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
Kojto 99:dbbf35b96557 285 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
Kojto 99:dbbf35b96557 286 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
Kojto 99:dbbf35b96557 287 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
Kojto 99:dbbf35b96557 288 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
Kojto 99:dbbf35b96557 289 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
Kojto 99:dbbf35b96557 290 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
Kojto 99:dbbf35b96557 291 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
Kojto 99:dbbf35b96557 292 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
Kojto 99:dbbf35b96557 293 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
Kojto 99:dbbf35b96557 294 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
Kojto 99:dbbf35b96557 295 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
Kojto 99:dbbf35b96557 296 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
Kojto 99:dbbf35b96557 297 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
Kojto 99:dbbf35b96557 298 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
Kojto 99:dbbf35b96557 299 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
Kojto 99:dbbf35b96557 300 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
Kojto 99:dbbf35b96557 301 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
Kojto 99:dbbf35b96557 302 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
Kojto 99:dbbf35b96557 303 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
Kojto 99:dbbf35b96557 304 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
Kojto 99:dbbf35b96557 305 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
Kojto 99:dbbf35b96557 306 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
Kojto 99:dbbf35b96557 307 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
Kojto 99:dbbf35b96557 308 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
Kojto 99:dbbf35b96557 309 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
Kojto 99:dbbf35b96557 310 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
Kojto 99:dbbf35b96557 311 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
Kojto 99:dbbf35b96557 312 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
Kojto 99:dbbf35b96557 313 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
Kojto 99:dbbf35b96557 314 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
Kojto 99:dbbf35b96557 315 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
Kojto 99:dbbf35b96557 316 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
Kojto 99:dbbf35b96557 317 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
Kojto 99:dbbf35b96557 318 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
Kojto 99:dbbf35b96557 319 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
Kojto 99:dbbf35b96557 320 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
Kojto 99:dbbf35b96557 321 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
Kojto 99:dbbf35b96557 322 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
Kojto 99:dbbf35b96557 323 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
Kojto 99:dbbf35b96557 324 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
Kojto 99:dbbf35b96557 325 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
Kojto 99:dbbf35b96557 326 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
Kojto 99:dbbf35b96557 327 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
Kojto 99:dbbf35b96557 328 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
Kojto 99:dbbf35b96557 329 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
Kojto 99:dbbf35b96557 330 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
Kojto 99:dbbf35b96557 331 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
Kojto 99:dbbf35b96557 332 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
Kojto 99:dbbf35b96557 333 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
Kojto 99:dbbf35b96557 334 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
Kojto 99:dbbf35b96557 335 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
Kojto 99:dbbf35b96557 336 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
Kojto 99:dbbf35b96557 337 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
Kojto 99:dbbf35b96557 338
Kojto 99:dbbf35b96557 339 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
Kojto 99:dbbf35b96557 340 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
Kojto 99:dbbf35b96557 341 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
Kojto 99:dbbf35b96557 342 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
Kojto 99:dbbf35b96557 343 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
Kojto 99:dbbf35b96557 344 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
Kojto 99:dbbf35b96557 345 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
Kojto 99:dbbf35b96557 346 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
Kojto 99:dbbf35b96557 347 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
Kojto 99:dbbf35b96557 348 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
Kojto 99:dbbf35b96557 349 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
Kojto 99:dbbf35b96557 350 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
Kojto 99:dbbf35b96557 351 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
Kojto 99:dbbf35b96557 352 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
Kojto 99:dbbf35b96557 353 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
Kojto 99:dbbf35b96557 354 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
Kojto 99:dbbf35b96557 355
Kojto 99:dbbf35b96557 356 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
Kojto 99:dbbf35b96557 357 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
Kojto 99:dbbf35b96557 358 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
Kojto 99:dbbf35b96557 359 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
Kojto 99:dbbf35b96557 360 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
Kojto 99:dbbf35b96557 361 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
Kojto 99:dbbf35b96557 362 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
Kojto 99:dbbf35b96557 363 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
Kojto 99:dbbf35b96557 364 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
Kojto 99:dbbf35b96557 365 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
Kojto 99:dbbf35b96557 366 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
Kojto 99:dbbf35b96557 367 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
Kojto 99:dbbf35b96557 368 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
Kojto 99:dbbf35b96557 369 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
Kojto 99:dbbf35b96557 370 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
Kojto 99:dbbf35b96557 371 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
Kojto 99:dbbf35b96557 372 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
Kojto 99:dbbf35b96557 373 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
Kojto 99:dbbf35b96557 374 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
Kojto 99:dbbf35b96557 375 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
Kojto 99:dbbf35b96557 376 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
Kojto 99:dbbf35b96557 377 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
Kojto 99:dbbf35b96557 378 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
Kojto 99:dbbf35b96557 379 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
Kojto 99:dbbf35b96557 380 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
Kojto 99:dbbf35b96557 381 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
Kojto 99:dbbf35b96557 382 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
Kojto 99:dbbf35b96557 383 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
Kojto 99:dbbf35b96557 384 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
Kojto 99:dbbf35b96557 385 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
Kojto 99:dbbf35b96557 386 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
Kojto 99:dbbf35b96557 387 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
Kojto 99:dbbf35b96557 388 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
Kojto 99:dbbf35b96557 389 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
Kojto 99:dbbf35b96557 390 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
Kojto 99:dbbf35b96557 391 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
Kojto 99:dbbf35b96557 392 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
Kojto 99:dbbf35b96557 393 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
Kojto 99:dbbf35b96557 394 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
Kojto 99:dbbf35b96557 395 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
Kojto 99:dbbf35b96557 396 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
Kojto 99:dbbf35b96557 397 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
Kojto 99:dbbf35b96557 398 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
Kojto 99:dbbf35b96557 399 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
Kojto 99:dbbf35b96557 400 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
Kojto 99:dbbf35b96557 401 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
Kojto 99:dbbf35b96557 402 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
Kojto 99:dbbf35b96557 403 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
Kojto 99:dbbf35b96557 404 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
Kojto 99:dbbf35b96557 405 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
Kojto 99:dbbf35b96557 406 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
Kojto 99:dbbf35b96557 407 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
Kojto 99:dbbf35b96557 408 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
Kojto 99:dbbf35b96557 409 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
Kojto 99:dbbf35b96557 410 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
Kojto 99:dbbf35b96557 411 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
Kojto 99:dbbf35b96557 412 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
Kojto 99:dbbf35b96557 413 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
Kojto 99:dbbf35b96557 414 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
Kojto 99:dbbf35b96557 415 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
Kojto 99:dbbf35b96557 416 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
Kojto 99:dbbf35b96557 417 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
Kojto 99:dbbf35b96557 418 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
Kojto 99:dbbf35b96557 419 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
Kojto 99:dbbf35b96557 420
Kojto 99:dbbf35b96557 421 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
Kojto 99:dbbf35b96557 422 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
Kojto 99:dbbf35b96557 423 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
Kojto 99:dbbf35b96557 424 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
Kojto 99:dbbf35b96557 425 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
Kojto 99:dbbf35b96557 426 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
Kojto 99:dbbf35b96557 427 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
Kojto 99:dbbf35b96557 428 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
Kojto 99:dbbf35b96557 429 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
Kojto 99:dbbf35b96557 430 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
Kojto 99:dbbf35b96557 431 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
Kojto 99:dbbf35b96557 432 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
Kojto 99:dbbf35b96557 433 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
Kojto 99:dbbf35b96557 434 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
Kojto 99:dbbf35b96557 435 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
Kojto 99:dbbf35b96557 436 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
Kojto 99:dbbf35b96557 437
Kojto 99:dbbf35b96557 438 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
Kojto 99:dbbf35b96557 439 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
Kojto 99:dbbf35b96557 440 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
Kojto 99:dbbf35b96557 441 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
Kojto 99:dbbf35b96557 442 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
Kojto 99:dbbf35b96557 443 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
Kojto 99:dbbf35b96557 444 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
Kojto 99:dbbf35b96557 445 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
Kojto 99:dbbf35b96557 446 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
Kojto 99:dbbf35b96557 447 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
Kojto 99:dbbf35b96557 448 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
Kojto 99:dbbf35b96557 449 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
Kojto 99:dbbf35b96557 450 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
Kojto 99:dbbf35b96557 451 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
Kojto 99:dbbf35b96557 452 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
Kojto 99:dbbf35b96557 453 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
Kojto 99:dbbf35b96557 454
Kojto 99:dbbf35b96557 455 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
Kojto 99:dbbf35b96557 456 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
Kojto 99:dbbf35b96557 457 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
Kojto 99:dbbf35b96557 458 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
Kojto 99:dbbf35b96557 459 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
Kojto 99:dbbf35b96557 460 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
Kojto 99:dbbf35b96557 461 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
Kojto 99:dbbf35b96557 462 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
Kojto 99:dbbf35b96557 463 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
Kojto 99:dbbf35b96557 464 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
Kojto 99:dbbf35b96557 465 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
Kojto 99:dbbf35b96557 466 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
Kojto 99:dbbf35b96557 467 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
Kojto 99:dbbf35b96557 468 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
Kojto 99:dbbf35b96557 469 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
Kojto 99:dbbf35b96557 470 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
Kojto 99:dbbf35b96557 471
Kojto 99:dbbf35b96557 472 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
Kojto 99:dbbf35b96557 473 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
Kojto 99:dbbf35b96557 474 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
Kojto 99:dbbf35b96557 475 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
Kojto 99:dbbf35b96557 476 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
Kojto 99:dbbf35b96557 477 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
Kojto 99:dbbf35b96557 478 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
Kojto 99:dbbf35b96557 479 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
Kojto 99:dbbf35b96557 480 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
Kojto 99:dbbf35b96557 481 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
Kojto 99:dbbf35b96557 482 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
Kojto 99:dbbf35b96557 483 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
Kojto 99:dbbf35b96557 484 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
Kojto 99:dbbf35b96557 485 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
Kojto 99:dbbf35b96557 486 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
Kojto 99:dbbf35b96557 487 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
Kojto 99:dbbf35b96557 488
Kojto 99:dbbf35b96557 489 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
Kojto 99:dbbf35b96557 490 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
Kojto 99:dbbf35b96557 491 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
Kojto 99:dbbf35b96557 492 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
Kojto 99:dbbf35b96557 493 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
Kojto 99:dbbf35b96557 494 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
Kojto 99:dbbf35b96557 495 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
Kojto 99:dbbf35b96557 496 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
Kojto 99:dbbf35b96557 497 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
Kojto 99:dbbf35b96557 498 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
Kojto 99:dbbf35b96557 499
Kojto 99:dbbf35b96557 500 #ifdef __cplusplus
Kojto 99:dbbf35b96557 501 }
Kojto 99:dbbf35b96557 502 #endif
Kojto 99:dbbf35b96557 503
Kojto 99:dbbf35b96557 504 /**
Kojto 99:dbbf35b96557 505 * @}
Kojto 99:dbbf35b96557 506 */
Kojto 99:dbbf35b96557 507
Kojto 99:dbbf35b96557 508 #endif /* _MXC_IOMAN_REGS_H_ */