Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MAXWSNENV/clkman_regs.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
99:dbbf35b96557 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /*******************************************************************************
Kojto 99:dbbf35b96557 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 99:dbbf35b96557 3 *
Kojto 99:dbbf35b96557 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 99:dbbf35b96557 5 * copy of this software and associated documentation files (the "Software"),
Kojto 99:dbbf35b96557 6 * to deal in the Software without restriction, including without limitation
Kojto 99:dbbf35b96557 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 99:dbbf35b96557 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 99:dbbf35b96557 9 * Software is furnished to do so, subject to the following conditions:
Kojto 99:dbbf35b96557 10 *
Kojto 99:dbbf35b96557 11 * The above copyright notice and this permission notice shall be included
Kojto 99:dbbf35b96557 12 * in all copies or substantial portions of the Software.
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 99:dbbf35b96557 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 99:dbbf35b96557 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 99:dbbf35b96557 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 99:dbbf35b96557 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 99:dbbf35b96557 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 99:dbbf35b96557 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 99:dbbf35b96557 21 *
Kojto 99:dbbf35b96557 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 99:dbbf35b96557 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 99:dbbf35b96557 24 * Products, Inc. Branding Policy.
Kojto 99:dbbf35b96557 25 *
Kojto 99:dbbf35b96557 26 * The mere transfer of this software does not imply any licenses
Kojto 99:dbbf35b96557 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 99:dbbf35b96557 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 99:dbbf35b96557 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 99:dbbf35b96557 30 * ownership rights.
Kojto 99:dbbf35b96557 31 *******************************************************************************
Kojto 99:dbbf35b96557 32 */
Kojto 99:dbbf35b96557 33
Kojto 99:dbbf35b96557 34 #ifndef _MXC_CLKMAN_REGS_H_
Kojto 99:dbbf35b96557 35 #define _MXC_CLKMAN_REGS_H_
Kojto 99:dbbf35b96557 36
Kojto 99:dbbf35b96557 37 #ifdef __cplusplus
Kojto 99:dbbf35b96557 38 extern "C" {
Kojto 99:dbbf35b96557 39 #endif
Kojto 99:dbbf35b96557 40
Kojto 99:dbbf35b96557 41 #include <stdint.h>
Kojto 99:dbbf35b96557 42
Kojto 99:dbbf35b96557 43 /**
Kojto 99:dbbf35b96557 44 * @file clkman_regs.h
Kojto 99:dbbf35b96557 45 * @addtogroup clkman CLKMAN
Kojto 99:dbbf35b96557 46 * @{
Kojto 99:dbbf35b96557 47 */
Kojto 99:dbbf35b96557 48
Kojto 99:dbbf35b96557 49 /**
Kojto 99:dbbf35b96557 50 * @brief Defines clock input selections for the phase locked loop.
Kojto 99:dbbf35b96557 51 */
Kojto 99:dbbf35b96557 52 typedef enum {
Kojto 99:dbbf35b96557 53 /** Input select for high frequency crystal oscillator */
Kojto 99:dbbf35b96557 54 MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
Kojto 99:dbbf35b96557 55 /** Input select for 24MHz ring oscillator */
Kojto 99:dbbf35b96557 56 MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
Kojto 99:dbbf35b96557 57 } mxc_clkman_pll_input_select_t;
Kojto 99:dbbf35b96557 58
Kojto 99:dbbf35b96557 59 /**
Kojto 99:dbbf35b96557 60 * @brief Defines clock input frequency for the phase locked loop.
Kojto 99:dbbf35b96557 61 */
Kojto 99:dbbf35b96557 62 typedef enum {
Kojto 99:dbbf35b96557 63 /** Input frequency of 24MHz */
Kojto 99:dbbf35b96557 64 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
Kojto 99:dbbf35b96557 65 /** Input frequency of 12MHz */
Kojto 99:dbbf35b96557 66 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
Kojto 99:dbbf35b96557 67 /** Input frequency of 8MHz */
Kojto 99:dbbf35b96557 68 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
Kojto 99:dbbf35b96557 69 } mxc_clkman_pll_divisor_select_t;
Kojto 99:dbbf35b96557 70
Kojto 99:dbbf35b96557 71 /**
Kojto 99:dbbf35b96557 72 * @brief Defines terminal count for PLL stable.
Kojto 99:dbbf35b96557 73 */
Kojto 99:dbbf35b96557 74 typedef enum {
Kojto 99:dbbf35b96557 75 /** Clock stable after 2^8 = 256 clock cycles */
Kojto 99:dbbf35b96557 76 MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
Kojto 99:dbbf35b96557 77 /** Clock stable after 2^9 = 512 clock cycles */
Kojto 99:dbbf35b96557 78 MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
Kojto 99:dbbf35b96557 79 /** Clock stable after 2^10 = 1024 clock cycles */
Kojto 99:dbbf35b96557 80 MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
Kojto 99:dbbf35b96557 81 /** Clock stable after 2^11 = 2048 clock cycles */
Kojto 99:dbbf35b96557 82 MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
Kojto 99:dbbf35b96557 83 /** Clock stable after 2^12 = 4096 clock cycles */
Kojto 99:dbbf35b96557 84 MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
Kojto 99:dbbf35b96557 85 /** Clock stable after 2^13 = 8192 clock cycles */
Kojto 99:dbbf35b96557 86 MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
Kojto 99:dbbf35b96557 87 /** Clock stable after 2^14 = 16384 clock cycles */
Kojto 99:dbbf35b96557 88 MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
Kojto 99:dbbf35b96557 89 /** Clock stable after 2^15 = 32768 clock cycles */
Kojto 99:dbbf35b96557 90 MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
Kojto 99:dbbf35b96557 91 /** Clock stable after 2^16 = 65536 clock cycles */
Kojto 99:dbbf35b96557 92 MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
Kojto 99:dbbf35b96557 93 /** Clock stable after 2^17 = 131072 clock cycles */
Kojto 99:dbbf35b96557 94 MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
Kojto 99:dbbf35b96557 95 /** Clock stable after 2^18 = 262144 clock cycles */
Kojto 99:dbbf35b96557 96 MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
Kojto 99:dbbf35b96557 97 /** Clock stable after 2^19 = 524288 clock cycles */
Kojto 99:dbbf35b96557 98 MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
Kojto 99:dbbf35b96557 99 /** Clock stable after 2^20 = 1048576 clock cycles */
Kojto 99:dbbf35b96557 100 MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
Kojto 99:dbbf35b96557 101 /** Clock stable after 2^21 = 2097152 clock cycles */
Kojto 99:dbbf35b96557 102 MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
Kojto 99:dbbf35b96557 103 /** Clock stable after 2^22 = 4194304 clock cycles */
Kojto 99:dbbf35b96557 104 MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
Kojto 99:dbbf35b96557 105 /** Clock stable after 2^23 = 8388608 clock cycles */
Kojto 99:dbbf35b96557 106 MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
Kojto 99:dbbf35b96557 107 } mxc_clkman_stability_count_t;
Kojto 99:dbbf35b96557 108
Kojto 99:dbbf35b96557 109 /**
Kojto 99:dbbf35b96557 110 * @brief Defines clock source selections for system clock.
Kojto 99:dbbf35b96557 111 */
Kojto 99:dbbf35b96557 112 typedef enum {
Kojto 99:dbbf35b96557 113 /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
Kojto 99:dbbf35b96557 114 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
Kojto 99:dbbf35b96557 115 /** Clock select for 24MHz ring oscillator */
Kojto 99:dbbf35b96557 116 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
Kojto 99:dbbf35b96557 117 /** Clock select for high frequency crystal oscillator */
Kojto 99:dbbf35b96557 118 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
Kojto 99:dbbf35b96557 119 /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
Kojto 99:dbbf35b96557 120 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
Kojto 99:dbbf35b96557 121 } mxc_clkman_system_source_select_t;
Kojto 99:dbbf35b96557 122
Kojto 99:dbbf35b96557 123 /**
Kojto 99:dbbf35b96557 124 * @brief Defines clock source selections for analog to digital converter clock.
Kojto 99:dbbf35b96557 125 */
Kojto 99:dbbf35b96557 126 typedef enum {
Kojto 99:dbbf35b96557 127 /** Clock select for system clock frequency */
Kojto 99:dbbf35b96557 128 MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
Kojto 99:dbbf35b96557 129 /** Clock select for 8MHz phase locked loop output */
Kojto 99:dbbf35b96557 130 MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
Kojto 99:dbbf35b96557 131 /** Clock select for high frequency crystal oscillator */
Kojto 99:dbbf35b96557 132 MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
Kojto 99:dbbf35b96557 133 /** Clock select for 24MHz ring oscillator */
Kojto 99:dbbf35b96557 134 MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
Kojto 99:dbbf35b96557 135 } mxc_clkman_adc_source_select_t;
Kojto 99:dbbf35b96557 136
Kojto 99:dbbf35b96557 137 /**
Kojto 99:dbbf35b96557 138 * @brief Defines clock source selections for watchdog timer clock.
Kojto 99:dbbf35b96557 139 */
Kojto 99:dbbf35b96557 140 typedef enum {
Kojto 99:dbbf35b96557 141 /** Clock select for system clock frequency */
Kojto 99:dbbf35b96557 142 MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
Kojto 99:dbbf35b96557 143 /** Clock select for 8MHz phase locked loop output */
Kojto 99:dbbf35b96557 144 MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
Kojto 99:dbbf35b96557 145 /** Clock select for high frequency crystal oscillator */
Kojto 99:dbbf35b96557 146 MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
Kojto 99:dbbf35b96557 147 /** Clock select for 24MHz ring oscillator */
Kojto 99:dbbf35b96557 148 MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
Kojto 99:dbbf35b96557 149 } mxc_clkman_wdt_source_select_t;
Kojto 99:dbbf35b96557 150
Kojto 99:dbbf35b96557 151 /**
Kojto 99:dbbf35b96557 152 * @brief Defines clock scales for various clocks.
Kojto 99:dbbf35b96557 153 */
Kojto 99:dbbf35b96557 154 typedef enum {
Kojto 99:dbbf35b96557 155 /** Clock disabled */
Kojto 99:dbbf35b96557 156 MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
Kojto 99:dbbf35b96557 157 /** Clock enabled */
Kojto 99:dbbf35b96557 158 MXC_E_CLKMAN_CLK_SCALE_ENABLED,
Kojto 99:dbbf35b96557 159 /** Clock scale for dividing by 2 */
Kojto 99:dbbf35b96557 160 MXC_E_CLKMAN_CLK_SCALE_DIV_2,
Kojto 99:dbbf35b96557 161 /** Clock scale for dividing by 4 */
Kojto 99:dbbf35b96557 162 MXC_E_CLKMAN_CLK_SCALE_DIV_4,
Kojto 99:dbbf35b96557 163 /** Clock scale for dividing by 8 */
Kojto 99:dbbf35b96557 164 MXC_E_CLKMAN_CLK_SCALE_DIV_8,
Kojto 99:dbbf35b96557 165 /** Clock scale for dividing by 16 */
Kojto 99:dbbf35b96557 166 MXC_E_CLKMAN_CLK_SCALE_DIV_16,
Kojto 99:dbbf35b96557 167 /** Clock scale for dividing by 32 */
Kojto 99:dbbf35b96557 168 MXC_E_CLKMAN_CLK_SCALE_DIV_32,
Kojto 99:dbbf35b96557 169 /** Clock scale for dividing by 64 */
Kojto 99:dbbf35b96557 170 MXC_E_CLKMAN_CLK_SCALE_DIV_64,
Kojto 99:dbbf35b96557 171 /** Clock scale for dividing by 128 */
Kojto 99:dbbf35b96557 172 MXC_E_CLKMAN_CLK_SCALE_DIV_128,
Kojto 99:dbbf35b96557 173 /** Clock scale for dividing by 256 */
Kojto 99:dbbf35b96557 174 MXC_E_CLKMAN_CLK_SCALE_DIV_256
Kojto 99:dbbf35b96557 175 } mxc_clkman_clk_scale_t;
Kojto 99:dbbf35b96557 176
Kojto 99:dbbf35b96557 177 /**
Kojto 99:dbbf35b96557 178 * @brief Defines Setting of the Clock Gates .
Kojto 99:dbbf35b96557 179 */
Kojto 99:dbbf35b96557 180 typedef enum {
Kojto 99:dbbf35b96557 181 /** Clock Gater is Off */
Kojto 99:dbbf35b96557 182 MXC_E_CLKMAN_CLK_GATE_OFF = 0,
Kojto 99:dbbf35b96557 183 /** Clock Gater is Dynamic */
Kojto 99:dbbf35b96557 184 MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
Kojto 99:dbbf35b96557 185 /** Clock Gater is On */
Kojto 99:dbbf35b96557 186 MXC_E_CLKMAN_CLK_GATE_ON
Kojto 99:dbbf35b96557 187 } mxc_clkman_clk_gate_t;
Kojto 99:dbbf35b96557 188
Kojto 99:dbbf35b96557 189 /* Offset Register Description
Kojto 99:dbbf35b96557 190 ====== ===================================================================== */
Kojto 99:dbbf35b96557 191 typedef struct {
Kojto 99:dbbf35b96557 192 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
Kojto 99:dbbf35b96557 193 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
Kojto 99:dbbf35b96557 194 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
Kojto 99:dbbf35b96557 195 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
Kojto 99:dbbf35b96557 196 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
Kojto 99:dbbf35b96557 197 __I uint32_t rsv0014[4]; /* 0x0014 */
Kojto 99:dbbf35b96557 198 __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
Kojto 99:dbbf35b96557 199 __I uint32_t rsv0028[6]; /* 0x0028 */
Kojto 99:dbbf35b96557 200 __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
Kojto 99:dbbf35b96557 201 __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
Kojto 99:dbbf35b96557 202 __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
Kojto 99:dbbf35b96557 203 __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
Kojto 99:dbbf35b96557 204 __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
Kojto 99:dbbf35b96557 205 __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
Kojto 99:dbbf35b96557 206 __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
Kojto 99:dbbf35b96557 207 __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
Kojto 99:dbbf35b96557 208 __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
Kojto 99:dbbf35b96557 209 __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
Kojto 99:dbbf35b96557 210 __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
Kojto 99:dbbf35b96557 211 __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
Kojto 99:dbbf35b96557 212 __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
Kojto 99:dbbf35b96557 213 __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
Kojto 99:dbbf35b96557 214 __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
Kojto 99:dbbf35b96557 215 __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
Kojto 99:dbbf35b96557 216 __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
Kojto 99:dbbf35b96557 217 __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
Kojto 99:dbbf35b96557 218 __I uint32_t rsv0088[30]; /* 0x0088 */
Kojto 99:dbbf35b96557 219 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
Kojto 99:dbbf35b96557 220 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
Kojto 99:dbbf35b96557 221 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
Kojto 99:dbbf35b96557 222 __I uint32_t rsv010C[13]; /* 0x010C */
Kojto 99:dbbf35b96557 223 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
Kojto 99:dbbf35b96557 224 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
Kojto 99:dbbf35b96557 225 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
Kojto 99:dbbf35b96557 226 } mxc_clkman_regs_t;
Kojto 99:dbbf35b96557 227
Kojto 99:dbbf35b96557 228 /*
Kojto 99:dbbf35b96557 229 Register offsets for module CLKMAN.
Kojto 99:dbbf35b96557 230 */
Kojto 99:dbbf35b96557 231 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
Kojto 99:dbbf35b96557 232 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
Kojto 99:dbbf35b96557 233 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
Kojto 99:dbbf35b96557 234 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
Kojto 99:dbbf35b96557 235 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
Kojto 99:dbbf35b96557 236 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
Kojto 99:dbbf35b96557 237 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
Kojto 99:dbbf35b96557 238 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
Kojto 99:dbbf35b96557 239 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
Kojto 99:dbbf35b96557 240 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
Kojto 99:dbbf35b96557 241 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
Kojto 99:dbbf35b96557 242 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
Kojto 99:dbbf35b96557 243 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
Kojto 99:dbbf35b96557 244 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
Kojto 99:dbbf35b96557 245 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
Kojto 99:dbbf35b96557 246 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
Kojto 99:dbbf35b96557 247 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
Kojto 99:dbbf35b96557 248 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
Kojto 99:dbbf35b96557 249 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
Kojto 99:dbbf35b96557 250 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
Kojto 99:dbbf35b96557 251 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
Kojto 99:dbbf35b96557 252 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
Kojto 99:dbbf35b96557 253 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
Kojto 99:dbbf35b96557 254 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
Kojto 99:dbbf35b96557 255 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
Kojto 99:dbbf35b96557 256 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
Kojto 99:dbbf35b96557 257 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
Kojto 99:dbbf35b96557 258 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
Kojto 99:dbbf35b96557 259 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
Kojto 99:dbbf35b96557 260 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
Kojto 99:dbbf35b96557 261
Kojto 99:dbbf35b96557 262 /*
Kojto 99:dbbf35b96557 263 Field positions and masks for module CLKMAN.
Kojto 99:dbbf35b96557 264 */
Kojto 99:dbbf35b96557 265 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
Kojto 99:dbbf35b96557 266 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
Kojto 99:dbbf35b96557 267 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
Kojto 99:dbbf35b96557 268 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
Kojto 99:dbbf35b96557 269 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
Kojto 99:dbbf35b96557 270 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
Kojto 99:dbbf35b96557 271 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
Kojto 99:dbbf35b96557 272 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
Kojto 99:dbbf35b96557 273 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
Kojto 99:dbbf35b96557 274 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
Kojto 99:dbbf35b96557 275 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
Kojto 99:dbbf35b96557 276 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
Kojto 99:dbbf35b96557 277 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
Kojto 99:dbbf35b96557 278 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
Kojto 99:dbbf35b96557 279 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
Kojto 99:dbbf35b96557 280 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
Kojto 99:dbbf35b96557 281 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
Kojto 99:dbbf35b96557 282 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
Kojto 99:dbbf35b96557 283 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
Kojto 99:dbbf35b96557 284 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
Kojto 99:dbbf35b96557 285 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
Kojto 99:dbbf35b96557 286 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
Kojto 99:dbbf35b96557 287 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
Kojto 99:dbbf35b96557 288 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
Kojto 99:dbbf35b96557 289 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
Kojto 99:dbbf35b96557 290 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
Kojto 99:dbbf35b96557 291 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
Kojto 99:dbbf35b96557 292 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
Kojto 99:dbbf35b96557 293 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
Kojto 99:dbbf35b96557 294 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Kojto 99:dbbf35b96557 295
Kojto 99:dbbf35b96557 296 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
Kojto 99:dbbf35b96557 297 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
Kojto 99:dbbf35b96557 298 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
Kojto 99:dbbf35b96557 299 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
Kojto 99:dbbf35b96557 300 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
Kojto 99:dbbf35b96557 301 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
Kojto 99:dbbf35b96557 302 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
Kojto 99:dbbf35b96557 303 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
Kojto 99:dbbf35b96557 304 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
Kojto 99:dbbf35b96557 305 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
Kojto 99:dbbf35b96557 306 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
Kojto 99:dbbf35b96557 307 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
Kojto 99:dbbf35b96557 308 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
Kojto 99:dbbf35b96557 309 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
Kojto 99:dbbf35b96557 310 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
Kojto 99:dbbf35b96557 311 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
Kojto 99:dbbf35b96557 312 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
Kojto 99:dbbf35b96557 313 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
Kojto 99:dbbf35b96557 314 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
Kojto 99:dbbf35b96557 315 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
Kojto 99:dbbf35b96557 316 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
Kojto 99:dbbf35b96557 317 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
Kojto 99:dbbf35b96557 318
Kojto 99:dbbf35b96557 319 #define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
Kojto 99:dbbf35b96557 320 #define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
Kojto 99:dbbf35b96557 321 #define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
Kojto 99:dbbf35b96557 322 #define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
Kojto 99:dbbf35b96557 323 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
Kojto 99:dbbf35b96557 324 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
Kojto 99:dbbf35b96557 325
Kojto 99:dbbf35b96557 326 #define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
Kojto 99:dbbf35b96557 327 #define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
Kojto 99:dbbf35b96557 328 #define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
Kojto 99:dbbf35b96557 329 #define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
Kojto 99:dbbf35b96557 330 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
Kojto 99:dbbf35b96557 331 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
Kojto 99:dbbf35b96557 332
Kojto 99:dbbf35b96557 333 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
Kojto 99:dbbf35b96557 334 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
Kojto 99:dbbf35b96557 335 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
Kojto 99:dbbf35b96557 336 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
Kojto 99:dbbf35b96557 337 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
Kojto 99:dbbf35b96557 338 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
Kojto 99:dbbf35b96557 339 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
Kojto 99:dbbf35b96557 340 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
Kojto 99:dbbf35b96557 341 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
Kojto 99:dbbf35b96557 342 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
Kojto 99:dbbf35b96557 343
Kojto 99:dbbf35b96557 344 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
Kojto 99:dbbf35b96557 345 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
Kojto 99:dbbf35b96557 346
Kojto 99:dbbf35b96557 347 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 348 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 349
Kojto 99:dbbf35b96557 350 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 351 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 352
Kojto 99:dbbf35b96557 353 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 354 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 355
Kojto 99:dbbf35b96557 356 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 357 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 358
Kojto 99:dbbf35b96557 359 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 360 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 361
Kojto 99:dbbf35b96557 362 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 363 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 364
Kojto 99:dbbf35b96557 365 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 366 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 367
Kojto 99:dbbf35b96557 368 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 369 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 370
Kojto 99:dbbf35b96557 371 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 372 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 373
Kojto 99:dbbf35b96557 374 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 375 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 376
Kojto 99:dbbf35b96557 377 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 378 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 379
Kojto 99:dbbf35b96557 380 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 381 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 382
Kojto 99:dbbf35b96557 383 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 384 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 385
Kojto 99:dbbf35b96557 386 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 387 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 388
Kojto 99:dbbf35b96557 389 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 390 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 391
Kojto 99:dbbf35b96557 392 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 393 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 394
Kojto 99:dbbf35b96557 395 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 396 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 397
Kojto 99:dbbf35b96557 398 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 399 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 400
Kojto 99:dbbf35b96557 401 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 402 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 403
Kojto 99:dbbf35b96557 404 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 405 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 406
Kojto 99:dbbf35b96557 407 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
Kojto 99:dbbf35b96557 408 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
Kojto 99:dbbf35b96557 409
Kojto 99:dbbf35b96557 410 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
Kojto 99:dbbf35b96557 411 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
Kojto 99:dbbf35b96557 412 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
Kojto 99:dbbf35b96557 413 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
Kojto 99:dbbf35b96557 414 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
Kojto 99:dbbf35b96557 415 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
Kojto 99:dbbf35b96557 416 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
Kojto 99:dbbf35b96557 417 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
Kojto 99:dbbf35b96557 418 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
Kojto 99:dbbf35b96557 419 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
Kojto 99:dbbf35b96557 420 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
Kojto 99:dbbf35b96557 421 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
Kojto 99:dbbf35b96557 422 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
Kojto 99:dbbf35b96557 423 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
Kojto 99:dbbf35b96557 424 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
Kojto 99:dbbf35b96557 425 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 426 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
Kojto 99:dbbf35b96557 427 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 428 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
Kojto 99:dbbf35b96557 429 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 430 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
Kojto 99:dbbf35b96557 431 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 432 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
Kojto 99:dbbf35b96557 433 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
Kojto 99:dbbf35b96557 434 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
Kojto 99:dbbf35b96557 435 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
Kojto 99:dbbf35b96557 436 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
Kojto 99:dbbf35b96557 437 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 438 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
Kojto 99:dbbf35b96557 439 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 440 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
Kojto 99:dbbf35b96557 441 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
Kojto 99:dbbf35b96557 442
Kojto 99:dbbf35b96557 443 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
Kojto 99:dbbf35b96557 444 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
Kojto 99:dbbf35b96557 445 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
Kojto 99:dbbf35b96557 446 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
Kojto 99:dbbf35b96557 447 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
Kojto 99:dbbf35b96557 448 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 449 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
Kojto 99:dbbf35b96557 450 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 451 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
Kojto 99:dbbf35b96557 452 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 453 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
Kojto 99:dbbf35b96557 454 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 455 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
Kojto 99:dbbf35b96557 456 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
Kojto 99:dbbf35b96557 457 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
Kojto 99:dbbf35b96557 458 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
Kojto 99:dbbf35b96557 459 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
Kojto 99:dbbf35b96557 460 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
Kojto 99:dbbf35b96557 461 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
Kojto 99:dbbf35b96557 462 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
Kojto 99:dbbf35b96557 463 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
Kojto 99:dbbf35b96557 464 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 465 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
Kojto 99:dbbf35b96557 466 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 467 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
Kojto 99:dbbf35b96557 468 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
Kojto 99:dbbf35b96557 469 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
Kojto 99:dbbf35b96557 470 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
Kojto 99:dbbf35b96557 471 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
Kojto 99:dbbf35b96557 472 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
Kojto 99:dbbf35b96557 473 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
Kojto 99:dbbf35b96557 474 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
Kojto 99:dbbf35b96557 475
Kojto 99:dbbf35b96557 476 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
Kojto 99:dbbf35b96557 477 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
Kojto 99:dbbf35b96557 478 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
Kojto 99:dbbf35b96557 479 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
Kojto 99:dbbf35b96557 480 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
Kojto 99:dbbf35b96557 481 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
Kojto 99:dbbf35b96557 482 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
Kojto 99:dbbf35b96557 483 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
Kojto 99:dbbf35b96557 484
Kojto 99:dbbf35b96557 485 #ifdef __cplusplus
Kojto 99:dbbf35b96557 486 }
Kojto 99:dbbf35b96557 487 #endif
Kojto 99:dbbf35b96557 488
Kojto 99:dbbf35b96557 489 /**
Kojto 99:dbbf35b96557 490 * @}
Kojto 99:dbbf35b96557 491 */
Kojto 99:dbbf35b96557 492
Kojto 99:dbbf35b96557 493 #endif /* _MXC_CLKMAN_REGS_H_ */