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TARGET_DISCO_L476VG/stm32l4xx_hal_rcc.h@107:4f6c30876dfa, 2015-09-16 (annotated)

Committer:: Kojto
Date:: Wed Sep 16 15:32:31 2015 +0100
Revision:: 107:4f6c30876dfa
Child:: 111:4336505e4b1c

Release 107  of the mbed library



Changes:

- new platforms - DISCO_F746NG, DISCO_L476VG, NUCLEO_L476RG

- KL43Z - bugfix RTC init function

- K20 - SPI mode fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	107:4f6c30876dfa	1	/**
Kojto	107:4f6c30876dfa	2	******************************************************************************
Kojto	107:4f6c30876dfa	3	* @file stm32l4xx_hal_rcc.h
Kojto	107:4f6c30876dfa	4	* @author MCD Application Team
Kojto	107:4f6c30876dfa	5	* @version V1.0.0
Kojto	107:4f6c30876dfa	6	* @date 26-June-2015
Kojto	107:4f6c30876dfa	7	* @brief Header file of RCC HAL module.
Kojto	107:4f6c30876dfa	8	******************************************************************************
Kojto	107:4f6c30876dfa	9	* @attention
Kojto	107:4f6c30876dfa	10	*
Kojto	107:4f6c30876dfa	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	107:4f6c30876dfa	12	*
Kojto	107:4f6c30876dfa	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	107:4f6c30876dfa	14	* are permitted provided that the following conditions are met:
Kojto	107:4f6c30876dfa	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	107:4f6c30876dfa	16	* this list of conditions and the following disclaimer.
Kojto	107:4f6c30876dfa	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	107:4f6c30876dfa	18	* this list of conditions and the following disclaimer in the documentation
Kojto	107:4f6c30876dfa	19	* and/or other materials provided with the distribution.
Kojto	107:4f6c30876dfa	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	107:4f6c30876dfa	21	* may be used to endorse or promote products derived from this software
Kojto	107:4f6c30876dfa	22	* without specific prior written permission.
Kojto	107:4f6c30876dfa	23	*
Kojto	107:4f6c30876dfa	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	107:4f6c30876dfa	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	107:4f6c30876dfa	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	107:4f6c30876dfa	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	107:4f6c30876dfa	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	107:4f6c30876dfa	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	107:4f6c30876dfa	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	107:4f6c30876dfa	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	107:4f6c30876dfa	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	107:4f6c30876dfa	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	107:4f6c30876dfa	34	*
Kojto	107:4f6c30876dfa	35	******************************************************************************
Kojto	107:4f6c30876dfa	36	*/
Kojto	107:4f6c30876dfa	37
Kojto	107:4f6c30876dfa	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	107:4f6c30876dfa	39	#ifndef __STM32L4xx_HAL_RCC_H
Kojto	107:4f6c30876dfa	40	#define __STM32L4xx_HAL_RCC_H
Kojto	107:4f6c30876dfa	41
Kojto	107:4f6c30876dfa	42	#ifdef __cplusplus
Kojto	107:4f6c30876dfa	43	extern "C" {
Kojto	107:4f6c30876dfa	44	#endif
Kojto	107:4f6c30876dfa	45
Kojto	107:4f6c30876dfa	46	/* Includes ------------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	47	#include "stm32l4xx_hal_def.h"
Kojto	107:4f6c30876dfa	48
Kojto	107:4f6c30876dfa	49	/** @addtogroup STM32L4xx_HAL_Driver
Kojto	107:4f6c30876dfa	50	* @{
Kojto	107:4f6c30876dfa	51	*/
Kojto	107:4f6c30876dfa	52
Kojto	107:4f6c30876dfa	53	/** @addtogroup RCC
Kojto	107:4f6c30876dfa	54	* @{
Kojto	107:4f6c30876dfa	55	*/
Kojto	107:4f6c30876dfa	56
Kojto	107:4f6c30876dfa	57	/* Exported types ------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	58	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	107:4f6c30876dfa	59	* @{
Kojto	107:4f6c30876dfa	60	*/
Kojto	107:4f6c30876dfa	61
Kojto	107:4f6c30876dfa	62	/**
Kojto	107:4f6c30876dfa	63	* @brief RCC PLL configuration structure definition
Kojto	107:4f6c30876dfa	64	*/
Kojto	107:4f6c30876dfa	65	typedef struct
Kojto	107:4f6c30876dfa	66	{
Kojto	107:4f6c30876dfa	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	107:4f6c30876dfa	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	107:4f6c30876dfa	69
Kojto	107:4f6c30876dfa	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	107:4f6c30876dfa	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	107:4f6c30876dfa	72
Kojto	107:4f6c30876dfa	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	107:4f6c30876dfa	74	This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
Kojto	107:4f6c30876dfa	75
Kojto	107:4f6c30876dfa	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	107:4f6c30876dfa	77	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
Kojto	107:4f6c30876dfa	78
Kojto	107:4f6c30876dfa	79	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
Kojto	107:4f6c30876dfa	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	107:4f6c30876dfa	81
Kojto	107:4f6c30876dfa	82	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
Kojto	107:4f6c30876dfa	83	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
Kojto	107:4f6c30876dfa	84
Kojto	107:4f6c30876dfa	85	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
Kojto	107:4f6c30876dfa	86	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
Kojto	107:4f6c30876dfa	87	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto	107:4f6c30876dfa	88
Kojto	107:4f6c30876dfa	89	}RCC_PLLInitTypeDef;
Kojto	107:4f6c30876dfa	90
Kojto	107:4f6c30876dfa	91	/**
Kojto	107:4f6c30876dfa	92	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
Kojto	107:4f6c30876dfa	93	*/
Kojto	107:4f6c30876dfa	94	typedef struct
Kojto	107:4f6c30876dfa	95	{
Kojto	107:4f6c30876dfa	96	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	107:4f6c30876dfa	97	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	107:4f6c30876dfa	98
Kojto	107:4f6c30876dfa	99	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	107:4f6c30876dfa	100	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	107:4f6c30876dfa	101
Kojto	107:4f6c30876dfa	102	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	107:4f6c30876dfa	103	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	107:4f6c30876dfa	104
Kojto	107:4f6c30876dfa	105	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	107:4f6c30876dfa	106	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	107:4f6c30876dfa	107
Kojto	107:4f6c30876dfa	108	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	107:4f6c30876dfa	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	107:4f6c30876dfa	110
Kojto	107:4f6c30876dfa	111	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	107:4f6c30876dfa	112	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	107:4f6c30876dfa	113
Kojto	107:4f6c30876dfa	114	uint32_t MSIState; /*!< The new state of the MSI.
Kojto	107:4f6c30876dfa	115	This parameter can be a value of @ref RCC_MSI_Config */
Kojto	107:4f6c30876dfa	116
Kojto	107:4f6c30876dfa	117	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
Kojto	107:4f6c30876dfa	118	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto	107:4f6c30876dfa	119
Kojto	107:4f6c30876dfa	120	uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto	107:4f6c30876dfa	121	This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto	107:4f6c30876dfa	122
Kojto	107:4f6c30876dfa	123	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
Kojto	107:4f6c30876dfa	124
Kojto	107:4f6c30876dfa	125	}RCC_OscInitTypeDef;
Kojto	107:4f6c30876dfa	126
Kojto	107:4f6c30876dfa	127	/**
Kojto	107:4f6c30876dfa	128	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	107:4f6c30876dfa	129	*/
Kojto	107:4f6c30876dfa	130	typedef struct
Kojto	107:4f6c30876dfa	131	{
Kojto	107:4f6c30876dfa	132	uint32_t ClockType; /*!< The clock to be configured.
Kojto	107:4f6c30876dfa	133	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	107:4f6c30876dfa	134
Kojto	107:4f6c30876dfa	135	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
Kojto	107:4f6c30876dfa	136	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	107:4f6c30876dfa	137
Kojto	107:4f6c30876dfa	138	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	107:4f6c30876dfa	139	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	107:4f6c30876dfa	140
Kojto	107:4f6c30876dfa	141	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	107:4f6c30876dfa	142	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	107:4f6c30876dfa	143
Kojto	107:4f6c30876dfa	144	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	107:4f6c30876dfa	145	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	107:4f6c30876dfa	146
Kojto	107:4f6c30876dfa	147	}RCC_ClkInitTypeDef;
Kojto	107:4f6c30876dfa	148
Kojto	107:4f6c30876dfa	149	/**
Kojto	107:4f6c30876dfa	150	* @}
Kojto	107:4f6c30876dfa	151	*/
Kojto	107:4f6c30876dfa	152
Kojto	107:4f6c30876dfa	153	/* Exported constants --------------------------------------------------------*/
Kojto	107:4f6c30876dfa	154	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	107:4f6c30876dfa	155	* @{
Kojto	107:4f6c30876dfa	156	*/
Kojto	107:4f6c30876dfa	157
Kojto	107:4f6c30876dfa	158	/** @defgroup RCC_Timeout_Value Timeout Values
Kojto	107:4f6c30876dfa	159	* @{
Kojto	107:4f6c30876dfa	160	*/
Kojto	107:4f6c30876dfa	161	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	107:4f6c30876dfa	162	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
Kojto	107:4f6c30876dfa	163	/**
Kojto	107:4f6c30876dfa	164	* @}
Kojto	107:4f6c30876dfa	165	*/
Kojto	107:4f6c30876dfa	166
Kojto	107:4f6c30876dfa	167	/** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto	107:4f6c30876dfa	168	* @{
Kojto	107:4f6c30876dfa	169	*/
Kojto	107:4f6c30876dfa	170	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /!< Oscillator configuration unchanged /
Kojto	107:4f6c30876dfa	171	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /!< HSE to configure /
Kojto	107:4f6c30876dfa	172	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /!< HSI to configure /
Kojto	107:4f6c30876dfa	173	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /!< LSE to configure /
Kojto	107:4f6c30876dfa	174	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /!< LSI to configure /
Kojto	107:4f6c30876dfa	175	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /!< MSI to configure /
Kojto	107:4f6c30876dfa	176	/**
Kojto	107:4f6c30876dfa	177	* @}
Kojto	107:4f6c30876dfa	178	*/
Kojto	107:4f6c30876dfa	179
Kojto	107:4f6c30876dfa	180	/** @defgroup RCC_HSE_Config HSE Config
Kojto	107:4f6c30876dfa	181	* @{
Kojto	107:4f6c30876dfa	182	*/
Kojto	107:4f6c30876dfa	183	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
Kojto	107:4f6c30876dfa	184	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
Kojto	107:4f6c30876dfa	185	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
Kojto	107:4f6c30876dfa	186	/**
Kojto	107:4f6c30876dfa	187	* @}
Kojto	107:4f6c30876dfa	188	*/
Kojto	107:4f6c30876dfa	189
Kojto	107:4f6c30876dfa	190	/** @defgroup RCC_LSE_Config LSE Config
Kojto	107:4f6c30876dfa	191	* @{
Kojto	107:4f6c30876dfa	192	*/
Kojto	107:4f6c30876dfa	193	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
Kojto	107:4f6c30876dfa	194	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
Kojto	107:4f6c30876dfa	195	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
Kojto	107:4f6c30876dfa	196	/**
Kojto	107:4f6c30876dfa	197	* @}
Kojto	107:4f6c30876dfa	198	*/
Kojto	107:4f6c30876dfa	199
Kojto	107:4f6c30876dfa	200	/** @defgroup RCC_HSI_Config HSI Config
Kojto	107:4f6c30876dfa	201	* @{
Kojto	107:4f6c30876dfa	202	*/
Kojto	107:4f6c30876dfa	203	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
Kojto	107:4f6c30876dfa	204	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
Kojto	107:4f6c30876dfa	205
Kojto	107:4f6c30876dfa	206	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /!< Default HSI calibration trimming value /
Kojto	107:4f6c30876dfa	207	/**
Kojto	107:4f6c30876dfa	208	* @}
Kojto	107:4f6c30876dfa	209	*/
Kojto	107:4f6c30876dfa	210
Kojto	107:4f6c30876dfa	211	/** @defgroup RCC_LSI_Config LSI Config
Kojto	107:4f6c30876dfa	212	* @{
Kojto	107:4f6c30876dfa	213	*/
Kojto	107:4f6c30876dfa	214	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
Kojto	107:4f6c30876dfa	215	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
Kojto	107:4f6c30876dfa	216	/**
Kojto	107:4f6c30876dfa	217	* @}
Kojto	107:4f6c30876dfa	218	*/
Kojto	107:4f6c30876dfa	219
Kojto	107:4f6c30876dfa	220	/** @defgroup RCC_MSI_Config MSI Config
Kojto	107:4f6c30876dfa	221	* @{
Kojto	107:4f6c30876dfa	222	*/
Kojto	107:4f6c30876dfa	223	#define RCC_MSI_OFF ((uint32_t)0x00000000) /!< MSI clock deactivation /
Kojto	107:4f6c30876dfa	224	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
Kojto	107:4f6c30876dfa	225
Kojto	107:4f6c30876dfa	226	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /!< Default MSI calibration trimming value /
Kojto	107:4f6c30876dfa	227	/**
Kojto	107:4f6c30876dfa	228	* @}
Kojto	107:4f6c30876dfa	229	*/
Kojto	107:4f6c30876dfa	230
Kojto	107:4f6c30876dfa	231	/** @defgroup RCC_PLL_Config PLL Config
Kojto	107:4f6c30876dfa	232	* @{
Kojto	107:4f6c30876dfa	233	*/
Kojto	107:4f6c30876dfa	234	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL configuration unchanged /
Kojto	107:4f6c30876dfa	235	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
Kojto	107:4f6c30876dfa	236	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
Kojto	107:4f6c30876dfa	237	/**
Kojto	107:4f6c30876dfa	238	* @}
Kojto	107:4f6c30876dfa	239	*/
Kojto	107:4f6c30876dfa	240
Kojto	107:4f6c30876dfa	241	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto	107:4f6c30876dfa	242	* @{
Kojto	107:4f6c30876dfa	243	*/
Kojto	107:4f6c30876dfa	244	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007) /!< PLLP division factor = 7 /
Kojto	107:4f6c30876dfa	245	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011) /!< PLLP division factor = 17 /
Kojto	107:4f6c30876dfa	246	/**
Kojto	107:4f6c30876dfa	247	* @}
Kojto	107:4f6c30876dfa	248	*/
Kojto	107:4f6c30876dfa	249
Kojto	107:4f6c30876dfa	250	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
Kojto	107:4f6c30876dfa	251	* @{
Kojto	107:4f6c30876dfa	252	*/
Kojto	107:4f6c30876dfa	253	#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002) /!< PLLQ division factor = 2 /
Kojto	107:4f6c30876dfa	254	#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004) /!< PLLQ division factor = 4 /
Kojto	107:4f6c30876dfa	255	#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006) /!< PLLQ division factor = 6 /
Kojto	107:4f6c30876dfa	256	#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008) /!< PLLQ division factor = 8 /
Kojto	107:4f6c30876dfa	257	/**
Kojto	107:4f6c30876dfa	258	* @}
Kojto	107:4f6c30876dfa	259	*/
Kojto	107:4f6c30876dfa	260
Kojto	107:4f6c30876dfa	261	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
Kojto	107:4f6c30876dfa	262	* @{
Kojto	107:4f6c30876dfa	263	*/
Kojto	107:4f6c30876dfa	264	#define RCC_PLLR_DIV2 ((uint32_t)0x00000002) /!< PLLR division factor = 2 /
Kojto	107:4f6c30876dfa	265	#define RCC_PLLR_DIV4 ((uint32_t)0x00000004) /!< PLLR division factor = 4 /
Kojto	107:4f6c30876dfa	266	#define RCC_PLLR_DIV6 ((uint32_t)0x00000006) /!< PLLR division factor = 6 /
Kojto	107:4f6c30876dfa	267	#define RCC_PLLR_DIV8 ((uint32_t)0x00000008) /!< PLLR division factor = 8 /
Kojto	107:4f6c30876dfa	268	/**
Kojto	107:4f6c30876dfa	269	* @}
Kojto	107:4f6c30876dfa	270	*/
Kojto	107:4f6c30876dfa	271
Kojto	107:4f6c30876dfa	272	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto	107:4f6c30876dfa	273	* @{
Kojto	107:4f6c30876dfa	274	*/
Kojto	107:4f6c30876dfa	275	#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000) /!< No clock selected as PLL entry clock source /
Kojto	107:4f6c30876dfa	276	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
Kojto	107:4f6c30876dfa	277	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
Kojto	107:4f6c30876dfa	278	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
Kojto	107:4f6c30876dfa	279	/**
Kojto	107:4f6c30876dfa	280	* @}
Kojto	107:4f6c30876dfa	281	*/
Kojto	107:4f6c30876dfa	282
Kojto	107:4f6c30876dfa	283	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
Kojto	107:4f6c30876dfa	284	* @{
Kojto	107:4f6c30876dfa	285	*/
Kojto	107:4f6c30876dfa	286	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL /
Kojto	107:4f6c30876dfa	287	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
Kojto	107:4f6c30876dfa	288	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
Kojto	107:4f6c30876dfa	289	/**
Kojto	107:4f6c30876dfa	290	* @}
Kojto	107:4f6c30876dfa	291	*/
Kojto	107:4f6c30876dfa	292
Kojto	107:4f6c30876dfa	293	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
Kojto	107:4f6c30876dfa	294	* @{
Kojto	107:4f6c30876dfa	295	*/
Kojto	107:4f6c30876dfa	296	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
Kojto	107:4f6c30876dfa	297	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
Kojto	107:4f6c30876dfa	298	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
Kojto	107:4f6c30876dfa	299	/**
Kojto	107:4f6c30876dfa	300	* @}
Kojto	107:4f6c30876dfa	301	*/
Kojto	107:4f6c30876dfa	302
Kojto	107:4f6c30876dfa	303	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
Kojto	107:4f6c30876dfa	304	* @{
Kojto	107:4f6c30876dfa	305	*/
Kojto	107:4f6c30876dfa	306	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
Kojto	107:4f6c30876dfa	307	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
Kojto	107:4f6c30876dfa	308	/**
Kojto	107:4f6c30876dfa	309	* @}
Kojto	107:4f6c30876dfa	310	*/
Kojto	107:4f6c30876dfa	311
Kojto	107:4f6c30876dfa	312	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
Kojto	107:4f6c30876dfa	313	* @{
Kojto	107:4f6c30876dfa	314	*/
Kojto	107:4f6c30876dfa	315	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
Kojto	107:4f6c30876dfa	316	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
Kojto	107:4f6c30876dfa	317	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
Kojto	107:4f6c30876dfa	318	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
Kojto	107:4f6c30876dfa	319	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
Kojto	107:4f6c30876dfa	320	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
Kojto	107:4f6c30876dfa	321	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
Kojto	107:4f6c30876dfa	322	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
Kojto	107:4f6c30876dfa	323	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
Kojto	107:4f6c30876dfa	324	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
Kojto	107:4f6c30876dfa	325	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
Kojto	107:4f6c30876dfa	326	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
Kojto	107:4f6c30876dfa	327	/**
Kojto	107:4f6c30876dfa	328	* @}
Kojto	107:4f6c30876dfa	329	*/
Kojto	107:4f6c30876dfa	330
Kojto	107:4f6c30876dfa	331	/** @defgroup RCC_System_Clock_Type System Clock Type
Kojto	107:4f6c30876dfa	332	* @{
Kojto	107:4f6c30876dfa	333	*/
Kojto	107:4f6c30876dfa	334	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
Kojto	107:4f6c30876dfa	335	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
Kojto	107:4f6c30876dfa	336	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
Kojto	107:4f6c30876dfa	337	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
Kojto	107:4f6c30876dfa	338	/**
Kojto	107:4f6c30876dfa	339	* @}
Kojto	107:4f6c30876dfa	340	*/
Kojto	107:4f6c30876dfa	341
Kojto	107:4f6c30876dfa	342	/** @defgroup RCC_System_Clock_Source System Clock Source
Kojto	107:4f6c30876dfa	343	* @{
Kojto	107:4f6c30876dfa	344	*/
Kojto	107:4f6c30876dfa	345	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
Kojto	107:4f6c30876dfa	346	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
Kojto	107:4f6c30876dfa	347	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
Kojto	107:4f6c30876dfa	348	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
Kojto	107:4f6c30876dfa	349	/**
Kojto	107:4f6c30876dfa	350	* @}
Kojto	107:4f6c30876dfa	351	*/
Kojto	107:4f6c30876dfa	352
Kojto	107:4f6c30876dfa	353	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	107:4f6c30876dfa	354	* @{
Kojto	107:4f6c30876dfa	355	*/
Kojto	107:4f6c30876dfa	356	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
Kojto	107:4f6c30876dfa	357	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	107:4f6c30876dfa	358	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	107:4f6c30876dfa	359	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	107:4f6c30876dfa	360	/**
Kojto	107:4f6c30876dfa	361	* @}
Kojto	107:4f6c30876dfa	362	*/
Kojto	107:4f6c30876dfa	363
Kojto	107:4f6c30876dfa	364	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto	107:4f6c30876dfa	365	* @{
Kojto	107:4f6c30876dfa	366	*/
Kojto	107:4f6c30876dfa	367	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
Kojto	107:4f6c30876dfa	368	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
Kojto	107:4f6c30876dfa	369	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
Kojto	107:4f6c30876dfa	370	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
Kojto	107:4f6c30876dfa	371	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
Kojto	107:4f6c30876dfa	372	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
Kojto	107:4f6c30876dfa	373	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
Kojto	107:4f6c30876dfa	374	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
Kojto	107:4f6c30876dfa	375	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
Kojto	107:4f6c30876dfa	376	/**
Kojto	107:4f6c30876dfa	377	* @}
Kojto	107:4f6c30876dfa	378	*/
Kojto	107:4f6c30876dfa	379
Kojto	107:4f6c30876dfa	380	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
Kojto	107:4f6c30876dfa	381	* @{
Kojto	107:4f6c30876dfa	382	*/
Kojto	107:4f6c30876dfa	383	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
Kojto	107:4f6c30876dfa	384	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
Kojto	107:4f6c30876dfa	385	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
Kojto	107:4f6c30876dfa	386	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
Kojto	107:4f6c30876dfa	387	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
Kojto	107:4f6c30876dfa	388	/**
Kojto	107:4f6c30876dfa	389	* @}
Kojto	107:4f6c30876dfa	390	*/
Kojto	107:4f6c30876dfa	391
Kojto	107:4f6c30876dfa	392	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto	107:4f6c30876dfa	393	* @{
Kojto	107:4f6c30876dfa	394	*/
Kojto	107:4f6c30876dfa	395	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
Kojto	107:4f6c30876dfa	396	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
Kojto	107:4f6c30876dfa	397	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
Kojto	107:4f6c30876dfa	398	/**
Kojto	107:4f6c30876dfa	399	* @}
Kojto	107:4f6c30876dfa	400	*/
Kojto	107:4f6c30876dfa	401
Kojto	107:4f6c30876dfa	402	/** @defgroup RCC_MCO_Index MCO Index
Kojto	107:4f6c30876dfa	403	* @{
Kojto	107:4f6c30876dfa	404	*/
Kojto	107:4f6c30876dfa	405	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	406	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
Kojto	107:4f6c30876dfa	407	/**
Kojto	107:4f6c30876dfa	408	* @}
Kojto	107:4f6c30876dfa	409	*/
Kojto	107:4f6c30876dfa	410
Kojto	107:4f6c30876dfa	411	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto	107:4f6c30876dfa	412	* @{
Kojto	107:4f6c30876dfa	413	*/
Kojto	107:4f6c30876dfa	414	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
Kojto	107:4f6c30876dfa	415	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
Kojto	107:4f6c30876dfa	416	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
Kojto	107:4f6c30876dfa	417	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
Kojto	107:4f6c30876dfa	418	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
Kojto	107:4f6c30876dfa	419	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
Kojto	107:4f6c30876dfa	420	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL /!< LSE selection as MCO1 source /
Kojto	107:4f6c30876dfa	421	/**
Kojto	107:4f6c30876dfa	422	* @}
Kojto	107:4f6c30876dfa	423	*/
Kojto	107:4f6c30876dfa	424
Kojto	107:4f6c30876dfa	425	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
Kojto	107:4f6c30876dfa	426	* @{
Kojto	107:4f6c30876dfa	427	*/
Kojto	107:4f6c30876dfa	428	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1 /!< MCO not divided /
Kojto	107:4f6c30876dfa	429	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2 /!< MCO divided by 2 /
Kojto	107:4f6c30876dfa	430	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4 /!< MCO divided by 4 /
Kojto	107:4f6c30876dfa	431	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 /!< MCO divided by 8 /
Kojto	107:4f6c30876dfa	432	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 /!< MCO divided by 16 /
Kojto	107:4f6c30876dfa	433	/**
Kojto	107:4f6c30876dfa	434	* @}
Kojto	107:4f6c30876dfa	435	*/
Kojto	107:4f6c30876dfa	436
Kojto	107:4f6c30876dfa	437	/** @defgroup RCC_Interrupt Interrupts
Kojto	107:4f6c30876dfa	438	* @{
Kojto	107:4f6c30876dfa	439	*/
Kojto	107:4f6c30876dfa	440	#define RCC_IT_LSIRDY ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
Kojto	107:4f6c30876dfa	441	#define RCC_IT_LSERDY ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
Kojto	107:4f6c30876dfa	442	#define RCC_IT_MSIRDY ((uint32_t)0x00000004) /!< MSI Ready Interrupt flag /
Kojto	107:4f6c30876dfa	443	#define RCC_IT_HSIRDY ((uint32_t)0x00000008) /!< HSI Ready Interrupt flag /
Kojto	107:4f6c30876dfa	444	#define RCC_IT_HSERDY ((uint32_t)0x00000010) /!< HSE Ready Interrupt flag /
Kojto	107:4f6c30876dfa	445	#define RCC_IT_PLLRDY ((uint32_t)0x00000020) /!< PLL Ready Interrupt flag /
Kojto	107:4f6c30876dfa	446	#define RCC_IT_PLLSAI1RDY ((uint32_t)0x00000040) /!< PLLSAI1 Ready Interrupt flag /
Kojto	107:4f6c30876dfa	447	#define RCC_IT_PLLSAI2RDY ((uint32_t)0x00000080) /!< PLLSAI2 Ready Interrupt flag /
Kojto	107:4f6c30876dfa	448	#define RCC_IT_CSS ((uint32_t)0x00000100) /!< Clock Security System Interrupt flag /
Kojto	107:4f6c30876dfa	449	#define RCC_IT_LSECSS ((uint32_t)0x00000200) /!< LSE Clock Security System Interrupt flag /
Kojto	107:4f6c30876dfa	450	/**
Kojto	107:4f6c30876dfa	451	* @}
Kojto	107:4f6c30876dfa	452	*/
Kojto	107:4f6c30876dfa	453
Kojto	107:4f6c30876dfa	454	/** @defgroup RCC_Flag Flags
Kojto	107:4f6c30876dfa	455	* Elements values convention: 0XXYYYYYb
Kojto	107:4f6c30876dfa	456	* - YYYYY : Flag position in the register
Kojto	107:4f6c30876dfa	457	* - 0XX : Register index
Kojto	107:4f6c30876dfa	458	* - 01: CR register
Kojto	107:4f6c30876dfa	459	* - 10: BDCR register
Kojto	107:4f6c30876dfa	460	* - 11: CSR register
Kojto	107:4f6c30876dfa	461	* @{
Kojto	107:4f6c30876dfa	462	*/
Kojto	107:4f6c30876dfa	463	/* Flags in the CR register */
Kojto	107:4f6c30876dfa	464	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI Ready flag /
Kojto	107:4f6c30876dfa	465	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< HSI Ready flag /
Kojto	107:4f6c30876dfa	466	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< HSE Ready flag /
Kojto	107:4f6c30876dfa	467	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL Ready flag /
Kojto	107:4f6c30876dfa	468	#define RCC_FLAG_PLLSAI1RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI1RDY))) /!< PLLSAI1 Ready flag /
Kojto	107:4f6c30876dfa	469	#define RCC_FLAG_PLLSAI2RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI2RDY))) /!< PLLSAI2 Ready flag /
Kojto	107:4f6c30876dfa	470
Kojto	107:4f6c30876dfa	471	/* Flags in the BDCR register */
Kojto	107:4f6c30876dfa	472	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< LSE Ready flag /
Kojto	107:4f6c30876dfa	473	#define RCC_FLAG_LSECSSD ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSECSSD))) /!< LSE Clock Security System Interrupt flag /
Kojto	107:4f6c30876dfa	474
Kojto	107:4f6c30876dfa	475	/* Flags in the CSR register */
Kojto	107:4f6c30876dfa	476	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< LSI Ready flag /
Kojto	107:4f6c30876dfa	477	#define RCC_FLAG_RMVF ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
Kojto	107:4f6c30876dfa	478	#define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_FWRSTF))) /!< Firewall reset flag /
Kojto	107:4f6c30876dfa	479	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Option Byte Loader reset flag /
Kojto	107:4f6c30876dfa	480	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
Kojto	107:4f6c30876dfa	481	#define RCC_FLAG_BORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_BORRSTF))) /!< BOR reset flag /
Kojto	107:4f6c30876dfa	482	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
Kojto	107:4f6c30876dfa	483	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
Kojto	107:4f6c30876dfa	484	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
Kojto	107:4f6c30876dfa	485	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
Kojto	107:4f6c30876dfa	486	/**
Kojto	107:4f6c30876dfa	487	* @}
Kojto	107:4f6c30876dfa	488	*/
Kojto	107:4f6c30876dfa	489
Kojto	107:4f6c30876dfa	490	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
Kojto	107:4f6c30876dfa	491	* @{
Kojto	107:4f6c30876dfa	492	*/
Kojto	107:4f6c30876dfa	493	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /!< LSE low drive capability /
Kojto	107:4f6c30876dfa	494	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< LSE medium low drive capability /
Kojto	107:4f6c30876dfa	495	/* Workaround implementation on medium low */
Kojto	107:4f6c30876dfa	496	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< LSE medium high drive capability /
Kojto	107:4f6c30876dfa	497	/* Workaround implementation on medium high */
Kojto	107:4f6c30876dfa	498	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
Kojto	107:4f6c30876dfa	499	/**
Kojto	107:4f6c30876dfa	500	* @}
Kojto	107:4f6c30876dfa	501	*/
Kojto	107:4f6c30876dfa	502
Kojto	107:4f6c30876dfa	503	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
Kojto	107:4f6c30876dfa	504	* @{
Kojto	107:4f6c30876dfa	505	*/
Kojto	107:4f6c30876dfa	506	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /!< MSI selection after wake-up from STOP /
Kojto	107:4f6c30876dfa	507	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
Kojto	107:4f6c30876dfa	508	/**
Kojto	107:4f6c30876dfa	509	* @}
Kojto	107:4f6c30876dfa	510	*/
Kojto	107:4f6c30876dfa	511
Kojto	107:4f6c30876dfa	512	/**
Kojto	107:4f6c30876dfa	513	* @}
Kojto	107:4f6c30876dfa	514	*/
Kojto	107:4f6c30876dfa	515
Kojto	107:4f6c30876dfa	516	/* Exported macros -----------------------------------------------------------*/
Kojto	107:4f6c30876dfa	517
Kojto	107:4f6c30876dfa	518	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	107:4f6c30876dfa	519	* @{
Kojto	107:4f6c30876dfa	520	*/
Kojto	107:4f6c30876dfa	521
Kojto	107:4f6c30876dfa	522	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	523	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	107:4f6c30876dfa	524	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	525	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	526	* using it.
Kojto	107:4f6c30876dfa	527	* @{
Kojto	107:4f6c30876dfa	528	*/
Kojto	107:4f6c30876dfa	529
Kojto	107:4f6c30876dfa	530	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	531	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	532	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
Kojto	107:4f6c30876dfa	533	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	534	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
Kojto	107:4f6c30876dfa	535	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	536	} while(0)
Kojto	107:4f6c30876dfa	537
Kojto	107:4f6c30876dfa	538	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	539	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	540	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
Kojto	107:4f6c30876dfa	541	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	542	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
Kojto	107:4f6c30876dfa	543	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	544	} while(0)
Kojto	107:4f6c30876dfa	545
Kojto	107:4f6c30876dfa	546	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	547	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
Kojto	107:4f6c30876dfa	549	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
Kojto	107:4f6c30876dfa	551	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	552	} while(0)
Kojto	107:4f6c30876dfa	553
Kojto	107:4f6c30876dfa	554	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	555	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	556	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
Kojto	107:4f6c30876dfa	557	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	558	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
Kojto	107:4f6c30876dfa	559	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	560	} while(0)
Kojto	107:4f6c30876dfa	561
Kojto	107:4f6c30876dfa	562	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	563	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	564	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
Kojto	107:4f6c30876dfa	565	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	566	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
Kojto	107:4f6c30876dfa	567	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	568	} while(0)
Kojto	107:4f6c30876dfa	569
Kojto	107:4f6c30876dfa	570	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
Kojto	107:4f6c30876dfa	571
Kojto	107:4f6c30876dfa	572	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
Kojto	107:4f6c30876dfa	573
Kojto	107:4f6c30876dfa	574	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
Kojto	107:4f6c30876dfa	575
Kojto	107:4f6c30876dfa	576	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
Kojto	107:4f6c30876dfa	577
Kojto	107:4f6c30876dfa	578	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
Kojto	107:4f6c30876dfa	579
Kojto	107:4f6c30876dfa	580	/**
Kojto	107:4f6c30876dfa	581	* @}
Kojto	107:4f6c30876dfa	582	*/
Kojto	107:4f6c30876dfa	583
Kojto	107:4f6c30876dfa	584	/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	585	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	107:4f6c30876dfa	586	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	587	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	588	* using it.
Kojto	107:4f6c30876dfa	589	* @{
Kojto	107:4f6c30876dfa	590	*/
Kojto	107:4f6c30876dfa	591
Kojto	107:4f6c30876dfa	592	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	593	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	594	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
Kojto	107:4f6c30876dfa	595	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	596	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
Kojto	107:4f6c30876dfa	597	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	598	} while(0)
Kojto	107:4f6c30876dfa	599
Kojto	107:4f6c30876dfa	600	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	601	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	602	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
Kojto	107:4f6c30876dfa	603	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	604	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
Kojto	107:4f6c30876dfa	605	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	606	} while(0)
Kojto	107:4f6c30876dfa	607
Kojto	107:4f6c30876dfa	608	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	609	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	610	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
Kojto	107:4f6c30876dfa	611	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	612	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
Kojto	107:4f6c30876dfa	613	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	614	} while(0)
Kojto	107:4f6c30876dfa	615
Kojto	107:4f6c30876dfa	616	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	617	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	618	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
Kojto	107:4f6c30876dfa	619	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	620	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
Kojto	107:4f6c30876dfa	621	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	622	} while(0)
Kojto	107:4f6c30876dfa	623
Kojto	107:4f6c30876dfa	624	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	625	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	626	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
Kojto	107:4f6c30876dfa	627	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	628	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
Kojto	107:4f6c30876dfa	629	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	630	} while(0)
Kojto	107:4f6c30876dfa	631
Kojto	107:4f6c30876dfa	632	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	633	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	634	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
Kojto	107:4f6c30876dfa	635	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	636	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
Kojto	107:4f6c30876dfa	637	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	638	} while(0)
Kojto	107:4f6c30876dfa	639
Kojto	107:4f6c30876dfa	640	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	641	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	642	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
Kojto	107:4f6c30876dfa	643	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	644	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
Kojto	107:4f6c30876dfa	645	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	646	} while(0)
Kojto	107:4f6c30876dfa	647
Kojto	107:4f6c30876dfa	648	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	649	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	650	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
Kojto	107:4f6c30876dfa	651	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	652	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
Kojto	107:4f6c30876dfa	653	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	654	} while(0)
Kojto	107:4f6c30876dfa	655
Kojto	107:4f6c30876dfa	656	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	657	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	658	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
Kojto	107:4f6c30876dfa	659	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	660	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
Kojto	107:4f6c30876dfa	661	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	662	} while(0)
Kojto	107:4f6c30876dfa	663
Kojto	107:4f6c30876dfa	664	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	665	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	666	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
Kojto	107:4f6c30876dfa	667	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	668	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
Kojto	107:4f6c30876dfa	669	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	670	} while(0)
Kojto	107:4f6c30876dfa	671
Kojto	107:4f6c30876dfa	672	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
Kojto	107:4f6c30876dfa	673
Kojto	107:4f6c30876dfa	674	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
Kojto	107:4f6c30876dfa	675
Kojto	107:4f6c30876dfa	676	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
Kojto	107:4f6c30876dfa	677
Kojto	107:4f6c30876dfa	678	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
Kojto	107:4f6c30876dfa	679
Kojto	107:4f6c30876dfa	680	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
Kojto	107:4f6c30876dfa	681
Kojto	107:4f6c30876dfa	682	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
Kojto	107:4f6c30876dfa	683
Kojto	107:4f6c30876dfa	684	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
Kojto	107:4f6c30876dfa	685
Kojto	107:4f6c30876dfa	686	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
Kojto	107:4f6c30876dfa	687
Kojto	107:4f6c30876dfa	688	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
Kojto	107:4f6c30876dfa	689
Kojto	107:4f6c30876dfa	690	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
Kojto	107:4f6c30876dfa	691
Kojto	107:4f6c30876dfa	692	/**
Kojto	107:4f6c30876dfa	693	* @}
Kojto	107:4f6c30876dfa	694	*/
Kojto	107:4f6c30876dfa	695
Kojto	107:4f6c30876dfa	696	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	697	* @brief Enable or disable the AHB3 peripheral clock.
Kojto	107:4f6c30876dfa	698	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	699	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	700	* using it.
Kojto	107:4f6c30876dfa	701	* @{
Kojto	107:4f6c30876dfa	702	*/
Kojto	107:4f6c30876dfa	703
Kojto	107:4f6c30876dfa	704	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	705	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	706	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
Kojto	107:4f6c30876dfa	707	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	708	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
Kojto	107:4f6c30876dfa	709	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	710	} while(0)
Kojto	107:4f6c30876dfa	711
Kojto	107:4f6c30876dfa	712	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	713	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	714	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
Kojto	107:4f6c30876dfa	715	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	716	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
Kojto	107:4f6c30876dfa	717	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	718	} while(0)
Kojto	107:4f6c30876dfa	719
Kojto	107:4f6c30876dfa	720	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
Kojto	107:4f6c30876dfa	721
Kojto	107:4f6c30876dfa	722	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
Kojto	107:4f6c30876dfa	723
Kojto	107:4f6c30876dfa	724	/**
Kojto	107:4f6c30876dfa	725	* @}
Kojto	107:4f6c30876dfa	726	*/
Kojto	107:4f6c30876dfa	727
Kojto	107:4f6c30876dfa	728	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	729	* @brief Enable or disable the APB1 peripheral clock.
Kojto	107:4f6c30876dfa	730	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	731	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	732	* using it.
Kojto	107:4f6c30876dfa	733	* @{
Kojto	107:4f6c30876dfa	734	*/
Kojto	107:4f6c30876dfa	735
Kojto	107:4f6c30876dfa	736	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	737	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	738	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
Kojto	107:4f6c30876dfa	739	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	740	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
Kojto	107:4f6c30876dfa	741	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	742	} while(0)
Kojto	107:4f6c30876dfa	743
Kojto	107:4f6c30876dfa	744	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	745	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	746	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
Kojto	107:4f6c30876dfa	747	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	748	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
Kojto	107:4f6c30876dfa	749	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	750	} while(0)
Kojto	107:4f6c30876dfa	751
Kojto	107:4f6c30876dfa	752	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	753	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	754	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
Kojto	107:4f6c30876dfa	755	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	756	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
Kojto	107:4f6c30876dfa	757	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	758	} while(0)
Kojto	107:4f6c30876dfa	759
Kojto	107:4f6c30876dfa	760	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	761	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	762	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
Kojto	107:4f6c30876dfa	763	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	764	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
Kojto	107:4f6c30876dfa	765	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	766	} while(0)
Kojto	107:4f6c30876dfa	767
Kojto	107:4f6c30876dfa	768	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	769	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	770	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
Kojto	107:4f6c30876dfa	771	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	772	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
Kojto	107:4f6c30876dfa	773	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	774	} while(0)
Kojto	107:4f6c30876dfa	775
Kojto	107:4f6c30876dfa	776	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	777	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	778	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
Kojto	107:4f6c30876dfa	779	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	780	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
Kojto	107:4f6c30876dfa	781	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	782	} while(0)
Kojto	107:4f6c30876dfa	783
Kojto	107:4f6c30876dfa	784	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	785	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	786	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
Kojto	107:4f6c30876dfa	787	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	788	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
Kojto	107:4f6c30876dfa	789	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	790	} while(0)
Kojto	107:4f6c30876dfa	791
Kojto	107:4f6c30876dfa	792	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	793	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	794	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
Kojto	107:4f6c30876dfa	795	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	796	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
Kojto	107:4f6c30876dfa	797	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	798	} while(0)
Kojto	107:4f6c30876dfa	799
Kojto	107:4f6c30876dfa	800	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	801	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	802	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
Kojto	107:4f6c30876dfa	803	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	804	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
Kojto	107:4f6c30876dfa	805	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	806	} while(0)
Kojto	107:4f6c30876dfa	807
Kojto	107:4f6c30876dfa	808	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	809	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	810	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
Kojto	107:4f6c30876dfa	811	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	812	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
Kojto	107:4f6c30876dfa	813	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	814	} while(0)
Kojto	107:4f6c30876dfa	815
Kojto	107:4f6c30876dfa	816	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	817	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	818	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
Kojto	107:4f6c30876dfa	819	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	820	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
Kojto	107:4f6c30876dfa	821	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	822	} while(0)
Kojto	107:4f6c30876dfa	823
Kojto	107:4f6c30876dfa	824	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	825	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	826	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
Kojto	107:4f6c30876dfa	827	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	828	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
Kojto	107:4f6c30876dfa	829	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	830	} while(0)
Kojto	107:4f6c30876dfa	831
Kojto	107:4f6c30876dfa	832	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	833	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	834	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
Kojto	107:4f6c30876dfa	835	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	836	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
Kojto	107:4f6c30876dfa	837	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	838	} while(0)
Kojto	107:4f6c30876dfa	839
Kojto	107:4f6c30876dfa	840	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	841	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	842	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
Kojto	107:4f6c30876dfa	843	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	844	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
Kojto	107:4f6c30876dfa	845	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	846	} while(0)
Kojto	107:4f6c30876dfa	847
Kojto	107:4f6c30876dfa	848	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	849	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	850	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
Kojto	107:4f6c30876dfa	851	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	852	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
Kojto	107:4f6c30876dfa	853	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	854	} while(0)
Kojto	107:4f6c30876dfa	855
Kojto	107:4f6c30876dfa	856	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	857	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	858	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
Kojto	107:4f6c30876dfa	859	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	860	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
Kojto	107:4f6c30876dfa	861	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	862	} while(0)
Kojto	107:4f6c30876dfa	863
Kojto	107:4f6c30876dfa	864	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	865	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	866	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
Kojto	107:4f6c30876dfa	867	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	868	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
Kojto	107:4f6c30876dfa	869	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	870	} while(0)
Kojto	107:4f6c30876dfa	871
Kojto	107:4f6c30876dfa	872	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	873	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	874	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
Kojto	107:4f6c30876dfa	875	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	876	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
Kojto	107:4f6c30876dfa	877	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	878	} while(0)
Kojto	107:4f6c30876dfa	879
Kojto	107:4f6c30876dfa	880	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	881	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	882	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
Kojto	107:4f6c30876dfa	883	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	884	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
Kojto	107:4f6c30876dfa	885	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	886	} while(0)
Kojto	107:4f6c30876dfa	887
Kojto	107:4f6c30876dfa	888	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	889	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	890	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
Kojto	107:4f6c30876dfa	891	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	892	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
Kojto	107:4f6c30876dfa	893	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	894	} while(0)
Kojto	107:4f6c30876dfa	895
Kojto	107:4f6c30876dfa	896	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	897	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	898	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
Kojto	107:4f6c30876dfa	899	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	900	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
Kojto	107:4f6c30876dfa	901	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	902	} while(0)
Kojto	107:4f6c30876dfa	903
Kojto	107:4f6c30876dfa	904	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	905	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	906	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
Kojto	107:4f6c30876dfa	907	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	908	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
Kojto	107:4f6c30876dfa	909	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	910	} while(0)
Kojto	107:4f6c30876dfa	911
Kojto	107:4f6c30876dfa	912	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	913	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	914	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
Kojto	107:4f6c30876dfa	915	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	916	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
Kojto	107:4f6c30876dfa	917	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	918	} while(0)
Kojto	107:4f6c30876dfa	919
Kojto	107:4f6c30876dfa	920	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	921	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	922	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
Kojto	107:4f6c30876dfa	923	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	924	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
Kojto	107:4f6c30876dfa	925	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	926	} while(0)
Kojto	107:4f6c30876dfa	927
Kojto	107:4f6c30876dfa	928	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
Kojto	107:4f6c30876dfa	929
Kojto	107:4f6c30876dfa	930	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
Kojto	107:4f6c30876dfa	931
Kojto	107:4f6c30876dfa	932	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
Kojto	107:4f6c30876dfa	933
Kojto	107:4f6c30876dfa	934	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
Kojto	107:4f6c30876dfa	935
Kojto	107:4f6c30876dfa	936	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
Kojto	107:4f6c30876dfa	937
Kojto	107:4f6c30876dfa	938	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
Kojto	107:4f6c30876dfa	939
Kojto	107:4f6c30876dfa	940	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
Kojto	107:4f6c30876dfa	941
Kojto	107:4f6c30876dfa	942	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
Kojto	107:4f6c30876dfa	943
Kojto	107:4f6c30876dfa	944	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
Kojto	107:4f6c30876dfa	945
Kojto	107:4f6c30876dfa	946	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
Kojto	107:4f6c30876dfa	947
Kojto	107:4f6c30876dfa	948	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
Kojto	107:4f6c30876dfa	949
Kojto	107:4f6c30876dfa	950	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
Kojto	107:4f6c30876dfa	951
Kojto	107:4f6c30876dfa	952	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
Kojto	107:4f6c30876dfa	953
Kojto	107:4f6c30876dfa	954	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
Kojto	107:4f6c30876dfa	955
Kojto	107:4f6c30876dfa	956	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
Kojto	107:4f6c30876dfa	957
Kojto	107:4f6c30876dfa	958	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
Kojto	107:4f6c30876dfa	959
Kojto	107:4f6c30876dfa	960	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
Kojto	107:4f6c30876dfa	961
Kojto	107:4f6c30876dfa	962	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
Kojto	107:4f6c30876dfa	963
Kojto	107:4f6c30876dfa	964	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
Kojto	107:4f6c30876dfa	965
Kojto	107:4f6c30876dfa	966	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
Kojto	107:4f6c30876dfa	967
Kojto	107:4f6c30876dfa	968	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
Kojto	107:4f6c30876dfa	969
Kojto	107:4f6c30876dfa	970	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
Kojto	107:4f6c30876dfa	971
Kojto	107:4f6c30876dfa	972	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
Kojto	107:4f6c30876dfa	973
Kojto	107:4f6c30876dfa	974	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
Kojto	107:4f6c30876dfa	975
Kojto	107:4f6c30876dfa	976	/**
Kojto	107:4f6c30876dfa	977	* @}
Kojto	107:4f6c30876dfa	978	*/
Kojto	107:4f6c30876dfa	979
Kojto	107:4f6c30876dfa	980	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	981	* @brief Enable or disable the APB2 peripheral clock.
Kojto	107:4f6c30876dfa	982	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	983	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	984	* using it.
Kojto	107:4f6c30876dfa	985	* @{
Kojto	107:4f6c30876dfa	986	*/
Kojto	107:4f6c30876dfa	987
Kojto	107:4f6c30876dfa	988	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	989	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	990	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Kojto	107:4f6c30876dfa	991	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	992	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Kojto	107:4f6c30876dfa	993	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	994	} while(0)
Kojto	107:4f6c30876dfa	995
Kojto	107:4f6c30876dfa	996	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	997	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	998	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
Kojto	107:4f6c30876dfa	999	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1000	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
Kojto	107:4f6c30876dfa	1001	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1002	} while(0)
Kojto	107:4f6c30876dfa	1003
Kojto	107:4f6c30876dfa	1004	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1005	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1006	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
Kojto	107:4f6c30876dfa	1007	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1008	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
Kojto	107:4f6c30876dfa	1009	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1010	} while(0)
Kojto	107:4f6c30876dfa	1011
Kojto	107:4f6c30876dfa	1012	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1013	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1014	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
Kojto	107:4f6c30876dfa	1015	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1016	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
Kojto	107:4f6c30876dfa	1017	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1018	} while(0)
Kojto	107:4f6c30876dfa	1019
Kojto	107:4f6c30876dfa	1020	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1021	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1022	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
Kojto	107:4f6c30876dfa	1023	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1024	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
Kojto	107:4f6c30876dfa	1025	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1026	} while(0)
Kojto	107:4f6c30876dfa	1027
Kojto	107:4f6c30876dfa	1028	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1029	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1030	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
Kojto	107:4f6c30876dfa	1031	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1032	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
Kojto	107:4f6c30876dfa	1033	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1034	} while(0)
Kojto	107:4f6c30876dfa	1035
Kojto	107:4f6c30876dfa	1036	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1037	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1038	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
Kojto	107:4f6c30876dfa	1039	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1040	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
Kojto	107:4f6c30876dfa	1041	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1042	} while(0)
Kojto	107:4f6c30876dfa	1043
Kojto	107:4f6c30876dfa	1044
Kojto	107:4f6c30876dfa	1045	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1046	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1047	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
Kojto	107:4f6c30876dfa	1048	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1049	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
Kojto	107:4f6c30876dfa	1050	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1051	} while(0)
Kojto	107:4f6c30876dfa	1052
Kojto	107:4f6c30876dfa	1053	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1054	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1055	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
Kojto	107:4f6c30876dfa	1056	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1057	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
Kojto	107:4f6c30876dfa	1058	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1059	} while(0)
Kojto	107:4f6c30876dfa	1060
Kojto	107:4f6c30876dfa	1061	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1062	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1063	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
Kojto	107:4f6c30876dfa	1064	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1065	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
Kojto	107:4f6c30876dfa	1066	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1067	} while(0)
Kojto	107:4f6c30876dfa	1068
Kojto	107:4f6c30876dfa	1069	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1070	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1071	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
Kojto	107:4f6c30876dfa	1072	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1073	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
Kojto	107:4f6c30876dfa	1074	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1075	} while(0)
Kojto	107:4f6c30876dfa	1076
Kojto	107:4f6c30876dfa	1077	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1078	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1079	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
Kojto	107:4f6c30876dfa	1080	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1081	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
Kojto	107:4f6c30876dfa	1082	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1083	} while(0)
Kojto	107:4f6c30876dfa	1084
Kojto	107:4f6c30876dfa	1085	#define __HAL_RCC_DFSDM_CLK_ENABLE() do { \
Kojto	107:4f6c30876dfa	1086	__IO uint32_t tmpreg; \
Kojto	107:4f6c30876dfa	1087	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
Kojto	107:4f6c30876dfa	1088	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	1089	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
Kojto	107:4f6c30876dfa	1090	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	1091	} while(0)
Kojto	107:4f6c30876dfa	1092
Kojto	107:4f6c30876dfa	1093	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
Kojto	107:4f6c30876dfa	1094
Kojto	107:4f6c30876dfa	1095	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
Kojto	107:4f6c30876dfa	1096
Kojto	107:4f6c30876dfa	1097	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
Kojto	107:4f6c30876dfa	1098
Kojto	107:4f6c30876dfa	1099	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
Kojto	107:4f6c30876dfa	1100
Kojto	107:4f6c30876dfa	1101	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
Kojto	107:4f6c30876dfa	1102
Kojto	107:4f6c30876dfa	1103	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
Kojto	107:4f6c30876dfa	1104
Kojto	107:4f6c30876dfa	1105	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
Kojto	107:4f6c30876dfa	1106
Kojto	107:4f6c30876dfa	1107	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
Kojto	107:4f6c30876dfa	1108
Kojto	107:4f6c30876dfa	1109	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
Kojto	107:4f6c30876dfa	1110
Kojto	107:4f6c30876dfa	1111	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
Kojto	107:4f6c30876dfa	1112
Kojto	107:4f6c30876dfa	1113	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
Kojto	107:4f6c30876dfa	1114
Kojto	107:4f6c30876dfa	1115	#define __HAL_RCC_DFSDM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN)
Kojto	107:4f6c30876dfa	1116
Kojto	107:4f6c30876dfa	1117	/**
Kojto	107:4f6c30876dfa	1118	* @}
Kojto	107:4f6c30876dfa	1119	*/
Kojto	107:4f6c30876dfa	1120
Kojto	107:4f6c30876dfa	1121	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1122	* @brief Check whether the AHB1 peripheral clock is enabled or not.
Kojto	107:4f6c30876dfa	1123	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	1124	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	1125	* using it.
Kojto	107:4f6c30876dfa	1126	* @{
Kojto	107:4f6c30876dfa	1127	*/
Kojto	107:4f6c30876dfa	1128
Kojto	107:4f6c30876dfa	1129	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
Kojto	107:4f6c30876dfa	1130
Kojto	107:4f6c30876dfa	1131	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
Kojto	107:4f6c30876dfa	1132
Kojto	107:4f6c30876dfa	1133	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
Kojto	107:4f6c30876dfa	1134
Kojto	107:4f6c30876dfa	1135	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
Kojto	107:4f6c30876dfa	1136
Kojto	107:4f6c30876dfa	1137	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
Kojto	107:4f6c30876dfa	1138
Kojto	107:4f6c30876dfa	1139	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
Kojto	107:4f6c30876dfa	1140
Kojto	107:4f6c30876dfa	1141	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
Kojto	107:4f6c30876dfa	1142
Kojto	107:4f6c30876dfa	1143	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
Kojto	107:4f6c30876dfa	1144
Kojto	107:4f6c30876dfa	1145	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
Kojto	107:4f6c30876dfa	1146
Kojto	107:4f6c30876dfa	1147	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
Kojto	107:4f6c30876dfa	1148
Kojto	107:4f6c30876dfa	1149	/**
Kojto	107:4f6c30876dfa	1150	* @}
Kojto	107:4f6c30876dfa	1151	*/
Kojto	107:4f6c30876dfa	1152
Kojto	107:4f6c30876dfa	1153	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1154	* @brief Check whether the AHB2 peripheral clock is enabled or not.
Kojto	107:4f6c30876dfa	1155	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	1156	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	1157	* using it.
Kojto	107:4f6c30876dfa	1158	* @{
Kojto	107:4f6c30876dfa	1159	*/
Kojto	107:4f6c30876dfa	1160
Kojto	107:4f6c30876dfa	1161	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
Kojto	107:4f6c30876dfa	1162
Kojto	107:4f6c30876dfa	1163	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
Kojto	107:4f6c30876dfa	1164
Kojto	107:4f6c30876dfa	1165	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
Kojto	107:4f6c30876dfa	1166
Kojto	107:4f6c30876dfa	1167	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
Kojto	107:4f6c30876dfa	1168
Kojto	107:4f6c30876dfa	1169	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
Kojto	107:4f6c30876dfa	1170
Kojto	107:4f6c30876dfa	1171	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
Kojto	107:4f6c30876dfa	1172
Kojto	107:4f6c30876dfa	1173	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
Kojto	107:4f6c30876dfa	1174
Kojto	107:4f6c30876dfa	1175	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
Kojto	107:4f6c30876dfa	1176
Kojto	107:4f6c30876dfa	1177	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
Kojto	107:4f6c30876dfa	1178
Kojto	107:4f6c30876dfa	1179	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
Kojto	107:4f6c30876dfa	1180
Kojto	107:4f6c30876dfa	1181	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
Kojto	107:4f6c30876dfa	1182
Kojto	107:4f6c30876dfa	1183	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
Kojto	107:4f6c30876dfa	1184
Kojto	107:4f6c30876dfa	1185	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
Kojto	107:4f6c30876dfa	1186
Kojto	107:4f6c30876dfa	1187	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
Kojto	107:4f6c30876dfa	1188
Kojto	107:4f6c30876dfa	1189	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
Kojto	107:4f6c30876dfa	1190
Kojto	107:4f6c30876dfa	1191	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
Kojto	107:4f6c30876dfa	1192
Kojto	107:4f6c30876dfa	1193	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
Kojto	107:4f6c30876dfa	1194
Kojto	107:4f6c30876dfa	1195	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
Kojto	107:4f6c30876dfa	1196
Kojto	107:4f6c30876dfa	1197	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
Kojto	107:4f6c30876dfa	1198
Kojto	107:4f6c30876dfa	1199	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
Kojto	107:4f6c30876dfa	1200
Kojto	107:4f6c30876dfa	1201	/**
Kojto	107:4f6c30876dfa	1202	* @}
Kojto	107:4f6c30876dfa	1203	*/
Kojto	107:4f6c30876dfa	1204
Kojto	107:4f6c30876dfa	1205	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1206	* @brief Check whether the AHB3 peripheral clock is enabled or not.
Kojto	107:4f6c30876dfa	1207	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	1208	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	1209	* using it.
Kojto	107:4f6c30876dfa	1210	* @{
Kojto	107:4f6c30876dfa	1211	*/
Kojto	107:4f6c30876dfa	1212
Kojto	107:4f6c30876dfa	1213	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
Kojto	107:4f6c30876dfa	1214
Kojto	107:4f6c30876dfa	1215	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
Kojto	107:4f6c30876dfa	1216
Kojto	107:4f6c30876dfa	1217	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
Kojto	107:4f6c30876dfa	1218
Kojto	107:4f6c30876dfa	1219	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
Kojto	107:4f6c30876dfa	1220
Kojto	107:4f6c30876dfa	1221	/**
Kojto	107:4f6c30876dfa	1222	* @}
Kojto	107:4f6c30876dfa	1223	*/
Kojto	107:4f6c30876dfa	1224
Kojto	107:4f6c30876dfa	1225	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1226	* @brief Check whether the APB1 peripheral clock is enabled or not.
Kojto	107:4f6c30876dfa	1227	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	1228	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	1229	* using it.
Kojto	107:4f6c30876dfa	1230	* @{
Kojto	107:4f6c30876dfa	1231	*/
Kojto	107:4f6c30876dfa	1232
Kojto	107:4f6c30876dfa	1233	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
Kojto	107:4f6c30876dfa	1234
Kojto	107:4f6c30876dfa	1235	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
Kojto	107:4f6c30876dfa	1236
Kojto	107:4f6c30876dfa	1237	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
Kojto	107:4f6c30876dfa	1238
Kojto	107:4f6c30876dfa	1239	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
Kojto	107:4f6c30876dfa	1240
Kojto	107:4f6c30876dfa	1241	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
Kojto	107:4f6c30876dfa	1242
Kojto	107:4f6c30876dfa	1243	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
Kojto	107:4f6c30876dfa	1244
Kojto	107:4f6c30876dfa	1245	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
Kojto	107:4f6c30876dfa	1246
Kojto	107:4f6c30876dfa	1247	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
Kojto	107:4f6c30876dfa	1248
Kojto	107:4f6c30876dfa	1249	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
Kojto	107:4f6c30876dfa	1250
Kojto	107:4f6c30876dfa	1251	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
Kojto	107:4f6c30876dfa	1252
Kojto	107:4f6c30876dfa	1253	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
Kojto	107:4f6c30876dfa	1254
Kojto	107:4f6c30876dfa	1255	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
Kojto	107:4f6c30876dfa	1256
Kojto	107:4f6c30876dfa	1257	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
Kojto	107:4f6c30876dfa	1258
Kojto	107:4f6c30876dfa	1259	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
Kojto	107:4f6c30876dfa	1260
Kojto	107:4f6c30876dfa	1261	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
Kojto	107:4f6c30876dfa	1262
Kojto	107:4f6c30876dfa	1263	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
Kojto	107:4f6c30876dfa	1264
Kojto	107:4f6c30876dfa	1265	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
Kojto	107:4f6c30876dfa	1266
Kojto	107:4f6c30876dfa	1267	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
Kojto	107:4f6c30876dfa	1268
Kojto	107:4f6c30876dfa	1269	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
Kojto	107:4f6c30876dfa	1270
Kojto	107:4f6c30876dfa	1271	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
Kojto	107:4f6c30876dfa	1272
Kojto	107:4f6c30876dfa	1273	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
Kojto	107:4f6c30876dfa	1274
Kojto	107:4f6c30876dfa	1275	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
Kojto	107:4f6c30876dfa	1276
Kojto	107:4f6c30876dfa	1277	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
Kojto	107:4f6c30876dfa	1278
Kojto	107:4f6c30876dfa	1279	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
Kojto	107:4f6c30876dfa	1280
Kojto	107:4f6c30876dfa	1281	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
Kojto	107:4f6c30876dfa	1282
Kojto	107:4f6c30876dfa	1283	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
Kojto	107:4f6c30876dfa	1284
Kojto	107:4f6c30876dfa	1285	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
Kojto	107:4f6c30876dfa	1286
Kojto	107:4f6c30876dfa	1287	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
Kojto	107:4f6c30876dfa	1288
Kojto	107:4f6c30876dfa	1289	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
Kojto	107:4f6c30876dfa	1290
Kojto	107:4f6c30876dfa	1291	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
Kojto	107:4f6c30876dfa	1292
Kojto	107:4f6c30876dfa	1293	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
Kojto	107:4f6c30876dfa	1294
Kojto	107:4f6c30876dfa	1295	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
Kojto	107:4f6c30876dfa	1296
Kojto	107:4f6c30876dfa	1297	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
Kojto	107:4f6c30876dfa	1298
Kojto	107:4f6c30876dfa	1299	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
Kojto	107:4f6c30876dfa	1300
Kojto	107:4f6c30876dfa	1301	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
Kojto	107:4f6c30876dfa	1302
Kojto	107:4f6c30876dfa	1303	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
Kojto	107:4f6c30876dfa	1304
Kojto	107:4f6c30876dfa	1305	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
Kojto	107:4f6c30876dfa	1306
Kojto	107:4f6c30876dfa	1307	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
Kojto	107:4f6c30876dfa	1308
Kojto	107:4f6c30876dfa	1309	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
Kojto	107:4f6c30876dfa	1310
Kojto	107:4f6c30876dfa	1311	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
Kojto	107:4f6c30876dfa	1312
Kojto	107:4f6c30876dfa	1313	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
Kojto	107:4f6c30876dfa	1314
Kojto	107:4f6c30876dfa	1315	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
Kojto	107:4f6c30876dfa	1316
Kojto	107:4f6c30876dfa	1317	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
Kojto	107:4f6c30876dfa	1318
Kojto	107:4f6c30876dfa	1319	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
Kojto	107:4f6c30876dfa	1320
Kojto	107:4f6c30876dfa	1321	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
Kojto	107:4f6c30876dfa	1322
Kojto	107:4f6c30876dfa	1323	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
Kojto	107:4f6c30876dfa	1324
Kojto	107:4f6c30876dfa	1325	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
Kojto	107:4f6c30876dfa	1326
Kojto	107:4f6c30876dfa	1327	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
Kojto	107:4f6c30876dfa	1328
Kojto	107:4f6c30876dfa	1329	/**
Kojto	107:4f6c30876dfa	1330	* @}
Kojto	107:4f6c30876dfa	1331	*/
Kojto	107:4f6c30876dfa	1332
Kojto	107:4f6c30876dfa	1333	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1334	* @brief Check whether the APB2 peripheral clock is enabled or not.
Kojto	107:4f6c30876dfa	1335	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	1336	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	1337	* using it.
Kojto	107:4f6c30876dfa	1338	* @{
Kojto	107:4f6c30876dfa	1339	*/
Kojto	107:4f6c30876dfa	1340
Kojto	107:4f6c30876dfa	1341	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
Kojto	107:4f6c30876dfa	1342
Kojto	107:4f6c30876dfa	1343	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
Kojto	107:4f6c30876dfa	1344
Kojto	107:4f6c30876dfa	1345	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
Kojto	107:4f6c30876dfa	1346
Kojto	107:4f6c30876dfa	1347	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
Kojto	107:4f6c30876dfa	1348
Kojto	107:4f6c30876dfa	1349	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
Kojto	107:4f6c30876dfa	1350
Kojto	107:4f6c30876dfa	1351	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
Kojto	107:4f6c30876dfa	1352
Kojto	107:4f6c30876dfa	1353	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
Kojto	107:4f6c30876dfa	1354
Kojto	107:4f6c30876dfa	1355	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
Kojto	107:4f6c30876dfa	1356
Kojto	107:4f6c30876dfa	1357	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
Kojto	107:4f6c30876dfa	1358
Kojto	107:4f6c30876dfa	1359	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
Kojto	107:4f6c30876dfa	1360
Kojto	107:4f6c30876dfa	1361	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
Kojto	107:4f6c30876dfa	1362
Kojto	107:4f6c30876dfa	1363	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
Kojto	107:4f6c30876dfa	1364
Kojto	107:4f6c30876dfa	1365	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) != RESET)
Kojto	107:4f6c30876dfa	1366
Kojto	107:4f6c30876dfa	1367	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
Kojto	107:4f6c30876dfa	1368
Kojto	107:4f6c30876dfa	1369	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
Kojto	107:4f6c30876dfa	1370
Kojto	107:4f6c30876dfa	1371	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
Kojto	107:4f6c30876dfa	1372
Kojto	107:4f6c30876dfa	1373	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
Kojto	107:4f6c30876dfa	1374
Kojto	107:4f6c30876dfa	1375	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
Kojto	107:4f6c30876dfa	1376
Kojto	107:4f6c30876dfa	1377	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
Kojto	107:4f6c30876dfa	1378
Kojto	107:4f6c30876dfa	1379	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
Kojto	107:4f6c30876dfa	1380
Kojto	107:4f6c30876dfa	1381	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
Kojto	107:4f6c30876dfa	1382
Kojto	107:4f6c30876dfa	1383	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
Kojto	107:4f6c30876dfa	1384
Kojto	107:4f6c30876dfa	1385	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
Kojto	107:4f6c30876dfa	1386
Kojto	107:4f6c30876dfa	1387	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
Kojto	107:4f6c30876dfa	1388
Kojto	107:4f6c30876dfa	1389	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) == RESET)
Kojto	107:4f6c30876dfa	1390
Kojto	107:4f6c30876dfa	1391	/**
Kojto	107:4f6c30876dfa	1392	* @}
Kojto	107:4f6c30876dfa	1393	*/
Kojto	107:4f6c30876dfa	1394
Kojto	107:4f6c30876dfa	1395	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
Kojto	107:4f6c30876dfa	1396	* @brief Force or release AHB1 peripheral reset.
Kojto	107:4f6c30876dfa	1397	* @{
Kojto	107:4f6c30876dfa	1398	*/
Kojto	107:4f6c30876dfa	1399	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	1400
Kojto	107:4f6c30876dfa	1401	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
Kojto	107:4f6c30876dfa	1402
Kojto	107:4f6c30876dfa	1403	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
Kojto	107:4f6c30876dfa	1404
Kojto	107:4f6c30876dfa	1405	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
Kojto	107:4f6c30876dfa	1406
Kojto	107:4f6c30876dfa	1407	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
Kojto	107:4f6c30876dfa	1408
Kojto	107:4f6c30876dfa	1409	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
Kojto	107:4f6c30876dfa	1410
Kojto	107:4f6c30876dfa	1411	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000)
Kojto	107:4f6c30876dfa	1412
Kojto	107:4f6c30876dfa	1413	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
Kojto	107:4f6c30876dfa	1414
Kojto	107:4f6c30876dfa	1415	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
Kojto	107:4f6c30876dfa	1416
Kojto	107:4f6c30876dfa	1417	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
Kojto	107:4f6c30876dfa	1418
Kojto	107:4f6c30876dfa	1419	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
Kojto	107:4f6c30876dfa	1420
Kojto	107:4f6c30876dfa	1421	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
Kojto	107:4f6c30876dfa	1422
Kojto	107:4f6c30876dfa	1423	/**
Kojto	107:4f6c30876dfa	1424	* @}
Kojto	107:4f6c30876dfa	1425	*/
Kojto	107:4f6c30876dfa	1426
Kojto	107:4f6c30876dfa	1427	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
Kojto	107:4f6c30876dfa	1428	* @brief Force or release AHB2 peripheral reset.
Kojto	107:4f6c30876dfa	1429	* @{
Kojto	107:4f6c30876dfa	1430	*/
Kojto	107:4f6c30876dfa	1431	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	1432
Kojto	107:4f6c30876dfa	1433	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
Kojto	107:4f6c30876dfa	1434
Kojto	107:4f6c30876dfa	1435	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
Kojto	107:4f6c30876dfa	1436
Kojto	107:4f6c30876dfa	1437	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
Kojto	107:4f6c30876dfa	1438
Kojto	107:4f6c30876dfa	1439	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
Kojto	107:4f6c30876dfa	1440
Kojto	107:4f6c30876dfa	1441	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
Kojto	107:4f6c30876dfa	1442
Kojto	107:4f6c30876dfa	1443	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
Kojto	107:4f6c30876dfa	1444
Kojto	107:4f6c30876dfa	1445	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
Kojto	107:4f6c30876dfa	1446
Kojto	107:4f6c30876dfa	1447	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
Kojto	107:4f6c30876dfa	1448
Kojto	107:4f6c30876dfa	1449	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
Kojto	107:4f6c30876dfa	1450
Kojto	107:4f6c30876dfa	1451	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
Kojto	107:4f6c30876dfa	1452
Kojto	107:4f6c30876dfa	1453	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000)
Kojto	107:4f6c30876dfa	1454
Kojto	107:4f6c30876dfa	1455	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
Kojto	107:4f6c30876dfa	1456
Kojto	107:4f6c30876dfa	1457	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
Kojto	107:4f6c30876dfa	1458
Kojto	107:4f6c30876dfa	1459	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
Kojto	107:4f6c30876dfa	1460
Kojto	107:4f6c30876dfa	1461	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
Kojto	107:4f6c30876dfa	1462
Kojto	107:4f6c30876dfa	1463	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
Kojto	107:4f6c30876dfa	1464
Kojto	107:4f6c30876dfa	1465	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
Kojto	107:4f6c30876dfa	1466
Kojto	107:4f6c30876dfa	1467	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
Kojto	107:4f6c30876dfa	1468
Kojto	107:4f6c30876dfa	1469	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
Kojto	107:4f6c30876dfa	1470
Kojto	107:4f6c30876dfa	1471	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
Kojto	107:4f6c30876dfa	1472
Kojto	107:4f6c30876dfa	1473	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
Kojto	107:4f6c30876dfa	1474
Kojto	107:4f6c30876dfa	1475	/**
Kojto	107:4f6c30876dfa	1476	* @}
Kojto	107:4f6c30876dfa	1477	*/
Kojto	107:4f6c30876dfa	1478
Kojto	107:4f6c30876dfa	1479	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
Kojto	107:4f6c30876dfa	1480	* @brief Force or release AHB3 peripheral reset.
Kojto	107:4f6c30876dfa	1481	* @{
Kojto	107:4f6c30876dfa	1482	*/
Kojto	107:4f6c30876dfa	1483	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	1484
Kojto	107:4f6c30876dfa	1485	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
Kojto	107:4f6c30876dfa	1486
Kojto	107:4f6c30876dfa	1487	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
Kojto	107:4f6c30876dfa	1488
Kojto	107:4f6c30876dfa	1489	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000)
Kojto	107:4f6c30876dfa	1490
Kojto	107:4f6c30876dfa	1491	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
Kojto	107:4f6c30876dfa	1492
Kojto	107:4f6c30876dfa	1493	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
Kojto	107:4f6c30876dfa	1494
Kojto	107:4f6c30876dfa	1495	/**
Kojto	107:4f6c30876dfa	1496	* @}
Kojto	107:4f6c30876dfa	1497	*/
Kojto	107:4f6c30876dfa	1498
Kojto	107:4f6c30876dfa	1499	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
Kojto	107:4f6c30876dfa	1500	* @brief Force or release APB1 peripheral reset.
Kojto	107:4f6c30876dfa	1501	* @{
Kojto	107:4f6c30876dfa	1502	*/
Kojto	107:4f6c30876dfa	1503	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	1504
Kojto	107:4f6c30876dfa	1505	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
Kojto	107:4f6c30876dfa	1506
Kojto	107:4f6c30876dfa	1507	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
Kojto	107:4f6c30876dfa	1508
Kojto	107:4f6c30876dfa	1509	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
Kojto	107:4f6c30876dfa	1510
Kojto	107:4f6c30876dfa	1511	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
Kojto	107:4f6c30876dfa	1512
Kojto	107:4f6c30876dfa	1513	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
Kojto	107:4f6c30876dfa	1514
Kojto	107:4f6c30876dfa	1515	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
Kojto	107:4f6c30876dfa	1516
Kojto	107:4f6c30876dfa	1517	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
Kojto	107:4f6c30876dfa	1518
Kojto	107:4f6c30876dfa	1519	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
Kojto	107:4f6c30876dfa	1520
Kojto	107:4f6c30876dfa	1521	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
Kojto	107:4f6c30876dfa	1522
Kojto	107:4f6c30876dfa	1523	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
Kojto	107:4f6c30876dfa	1524
Kojto	107:4f6c30876dfa	1525	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
Kojto	107:4f6c30876dfa	1526
Kojto	107:4f6c30876dfa	1527	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
Kojto	107:4f6c30876dfa	1528
Kojto	107:4f6c30876dfa	1529	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Kojto	107:4f6c30876dfa	1530
Kojto	107:4f6c30876dfa	1531	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
Kojto	107:4f6c30876dfa	1532
Kojto	107:4f6c30876dfa	1533	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
Kojto	107:4f6c30876dfa	1534
Kojto	107:4f6c30876dfa	1535	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
Kojto	107:4f6c30876dfa	1536
Kojto	107:4f6c30876dfa	1537	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
Kojto	107:4f6c30876dfa	1538
Kojto	107:4f6c30876dfa	1539	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
Kojto	107:4f6c30876dfa	1540
Kojto	107:4f6c30876dfa	1541	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
Kojto	107:4f6c30876dfa	1542
Kojto	107:4f6c30876dfa	1543	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
Kojto	107:4f6c30876dfa	1544
Kojto	107:4f6c30876dfa	1545	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
Kojto	107:4f6c30876dfa	1546
Kojto	107:4f6c30876dfa	1547	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
Kojto	107:4f6c30876dfa	1548
Kojto	107:4f6c30876dfa	1549	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
Kojto	107:4f6c30876dfa	1550
Kojto	107:4f6c30876dfa	1551	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000)
Kojto	107:4f6c30876dfa	1552
Kojto	107:4f6c30876dfa	1553	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
Kojto	107:4f6c30876dfa	1554
Kojto	107:4f6c30876dfa	1555	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
Kojto	107:4f6c30876dfa	1556
Kojto	107:4f6c30876dfa	1557	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
Kojto	107:4f6c30876dfa	1558
Kojto	107:4f6c30876dfa	1559	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
Kojto	107:4f6c30876dfa	1560
Kojto	107:4f6c30876dfa	1561	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
Kojto	107:4f6c30876dfa	1562
Kojto	107:4f6c30876dfa	1563	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
Kojto	107:4f6c30876dfa	1564
Kojto	107:4f6c30876dfa	1565	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
Kojto	107:4f6c30876dfa	1566
Kojto	107:4f6c30876dfa	1567	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
Kojto	107:4f6c30876dfa	1568
Kojto	107:4f6c30876dfa	1569	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
Kojto	107:4f6c30876dfa	1570
Kojto	107:4f6c30876dfa	1571	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
Kojto	107:4f6c30876dfa	1572
Kojto	107:4f6c30876dfa	1573	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
Kojto	107:4f6c30876dfa	1574
Kojto	107:4f6c30876dfa	1575	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
Kojto	107:4f6c30876dfa	1576
Kojto	107:4f6c30876dfa	1577	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Kojto	107:4f6c30876dfa	1578
Kojto	107:4f6c30876dfa	1579	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
Kojto	107:4f6c30876dfa	1580
Kojto	107:4f6c30876dfa	1581	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
Kojto	107:4f6c30876dfa	1582
Kojto	107:4f6c30876dfa	1583	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
Kojto	107:4f6c30876dfa	1584
Kojto	107:4f6c30876dfa	1585	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
Kojto	107:4f6c30876dfa	1586
Kojto	107:4f6c30876dfa	1587	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
Kojto	107:4f6c30876dfa	1588
Kojto	107:4f6c30876dfa	1589	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
Kojto	107:4f6c30876dfa	1590
Kojto	107:4f6c30876dfa	1591	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
Kojto	107:4f6c30876dfa	1592
Kojto	107:4f6c30876dfa	1593	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
Kojto	107:4f6c30876dfa	1594
Kojto	107:4f6c30876dfa	1595	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
Kojto	107:4f6c30876dfa	1596
Kojto	107:4f6c30876dfa	1597	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
Kojto	107:4f6c30876dfa	1598
Kojto	107:4f6c30876dfa	1599	/**
Kojto	107:4f6c30876dfa	1600	* @}
Kojto	107:4f6c30876dfa	1601	*/
Kojto	107:4f6c30876dfa	1602
Kojto	107:4f6c30876dfa	1603	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
Kojto	107:4f6c30876dfa	1604	* @brief Force or release APB2 peripheral reset.
Kojto	107:4f6c30876dfa	1605	* @{
Kojto	107:4f6c30876dfa	1606	*/
Kojto	107:4f6c30876dfa	1607	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	1608
Kojto	107:4f6c30876dfa	1609	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
Kojto	107:4f6c30876dfa	1610
Kojto	107:4f6c30876dfa	1611	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
Kojto	107:4f6c30876dfa	1612
Kojto	107:4f6c30876dfa	1613	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
Kojto	107:4f6c30876dfa	1614
Kojto	107:4f6c30876dfa	1615	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
Kojto	107:4f6c30876dfa	1616
Kojto	107:4f6c30876dfa	1617	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
Kojto	107:4f6c30876dfa	1618
Kojto	107:4f6c30876dfa	1619	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
Kojto	107:4f6c30876dfa	1620
Kojto	107:4f6c30876dfa	1621	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
Kojto	107:4f6c30876dfa	1622
Kojto	107:4f6c30876dfa	1623	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
Kojto	107:4f6c30876dfa	1624
Kojto	107:4f6c30876dfa	1625	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
Kojto	107:4f6c30876dfa	1626
Kojto	107:4f6c30876dfa	1627	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
Kojto	107:4f6c30876dfa	1628
Kojto	107:4f6c30876dfa	1629	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
Kojto	107:4f6c30876dfa	1630
Kojto	107:4f6c30876dfa	1631	#define __HAL_RCC_DFSDM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
Kojto	107:4f6c30876dfa	1632
Kojto	107:4f6c30876dfa	1633	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000)
Kojto	107:4f6c30876dfa	1634
Kojto	107:4f6c30876dfa	1635	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
Kojto	107:4f6c30876dfa	1636
Kojto	107:4f6c30876dfa	1637	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
Kojto	107:4f6c30876dfa	1638
Kojto	107:4f6c30876dfa	1639	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
Kojto	107:4f6c30876dfa	1640
Kojto	107:4f6c30876dfa	1641	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
Kojto	107:4f6c30876dfa	1642
Kojto	107:4f6c30876dfa	1643	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
Kojto	107:4f6c30876dfa	1644
Kojto	107:4f6c30876dfa	1645	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
Kojto	107:4f6c30876dfa	1646
Kojto	107:4f6c30876dfa	1647	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
Kojto	107:4f6c30876dfa	1648
Kojto	107:4f6c30876dfa	1649	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
Kojto	107:4f6c30876dfa	1650
Kojto	107:4f6c30876dfa	1651	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
Kojto	107:4f6c30876dfa	1652
Kojto	107:4f6c30876dfa	1653	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
Kojto	107:4f6c30876dfa	1654
Kojto	107:4f6c30876dfa	1655	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
Kojto	107:4f6c30876dfa	1656
Kojto	107:4f6c30876dfa	1657	#define __HAL_RCC_DFSDM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
Kojto	107:4f6c30876dfa	1658
Kojto	107:4f6c30876dfa	1659	/**
Kojto	107:4f6c30876dfa	1660	* @}
Kojto	107:4f6c30876dfa	1661	*/
Kojto	107:4f6c30876dfa	1662
Kojto	107:4f6c30876dfa	1663	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
Kojto	107:4f6c30876dfa	1664	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	1665	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1666	* power consumption.
Kojto	107:4f6c30876dfa	1667	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1668	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1669	* @{
Kojto	107:4f6c30876dfa	1670	*/
Kojto	107:4f6c30876dfa	1671
Kojto	107:4f6c30876dfa	1672	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
Kojto	107:4f6c30876dfa	1673
Kojto	107:4f6c30876dfa	1674	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
Kojto	107:4f6c30876dfa	1675
Kojto	107:4f6c30876dfa	1676	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
Kojto	107:4f6c30876dfa	1677
Kojto	107:4f6c30876dfa	1678	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
Kojto	107:4f6c30876dfa	1679
Kojto	107:4f6c30876dfa	1680	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
Kojto	107:4f6c30876dfa	1681
Kojto	107:4f6c30876dfa	1682	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
Kojto	107:4f6c30876dfa	1683
Kojto	107:4f6c30876dfa	1684	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
Kojto	107:4f6c30876dfa	1685
Kojto	107:4f6c30876dfa	1686	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
Kojto	107:4f6c30876dfa	1687
Kojto	107:4f6c30876dfa	1688	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
Kojto	107:4f6c30876dfa	1689
Kojto	107:4f6c30876dfa	1690	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
Kojto	107:4f6c30876dfa	1691
Kojto	107:4f6c30876dfa	1692	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
Kojto	107:4f6c30876dfa	1693
Kojto	107:4f6c30876dfa	1694	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
Kojto	107:4f6c30876dfa	1695
Kojto	107:4f6c30876dfa	1696	/**
Kojto	107:4f6c30876dfa	1697	* @}
Kojto	107:4f6c30876dfa	1698	*/
Kojto	107:4f6c30876dfa	1699
Kojto	107:4f6c30876dfa	1700	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
Kojto	107:4f6c30876dfa	1701	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	1702	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1703	* power consumption.
Kojto	107:4f6c30876dfa	1704	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1705	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1706	* @{
Kojto	107:4f6c30876dfa	1707	*/
Kojto	107:4f6c30876dfa	1708
Kojto	107:4f6c30876dfa	1709	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
Kojto	107:4f6c30876dfa	1710
Kojto	107:4f6c30876dfa	1711	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
Kojto	107:4f6c30876dfa	1712
Kojto	107:4f6c30876dfa	1713	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
Kojto	107:4f6c30876dfa	1714
Kojto	107:4f6c30876dfa	1715	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
Kojto	107:4f6c30876dfa	1716
Kojto	107:4f6c30876dfa	1717	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
Kojto	107:4f6c30876dfa	1718
Kojto	107:4f6c30876dfa	1719	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
Kojto	107:4f6c30876dfa	1720
Kojto	107:4f6c30876dfa	1721	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
Kojto	107:4f6c30876dfa	1722
Kojto	107:4f6c30876dfa	1723	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
Kojto	107:4f6c30876dfa	1724
Kojto	107:4f6c30876dfa	1725	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
Kojto	107:4f6c30876dfa	1726
Kojto	107:4f6c30876dfa	1727	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
Kojto	107:4f6c30876dfa	1728
Kojto	107:4f6c30876dfa	1729	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
Kojto	107:4f6c30876dfa	1730
Kojto	107:4f6c30876dfa	1731	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
Kojto	107:4f6c30876dfa	1732
Kojto	107:4f6c30876dfa	1733	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
Kojto	107:4f6c30876dfa	1734
Kojto	107:4f6c30876dfa	1735	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
Kojto	107:4f6c30876dfa	1736
Kojto	107:4f6c30876dfa	1737	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
Kojto	107:4f6c30876dfa	1738
Kojto	107:4f6c30876dfa	1739	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
Kojto	107:4f6c30876dfa	1740
Kojto	107:4f6c30876dfa	1741	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
Kojto	107:4f6c30876dfa	1742
Kojto	107:4f6c30876dfa	1743	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
Kojto	107:4f6c30876dfa	1744
Kojto	107:4f6c30876dfa	1745	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
Kojto	107:4f6c30876dfa	1746
Kojto	107:4f6c30876dfa	1747	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
Kojto	107:4f6c30876dfa	1748
Kojto	107:4f6c30876dfa	1749	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
Kojto	107:4f6c30876dfa	1750
Kojto	107:4f6c30876dfa	1751	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
Kojto	107:4f6c30876dfa	1752
Kojto	107:4f6c30876dfa	1753	/**
Kojto	107:4f6c30876dfa	1754	* @}
Kojto	107:4f6c30876dfa	1755	*/
Kojto	107:4f6c30876dfa	1756
Kojto	107:4f6c30876dfa	1757	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
Kojto	107:4f6c30876dfa	1758	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	1759	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1760	* power consumption.
Kojto	107:4f6c30876dfa	1761	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1762	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1763	* @{
Kojto	107:4f6c30876dfa	1764	*/
Kojto	107:4f6c30876dfa	1765
Kojto	107:4f6c30876dfa	1766	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
Kojto	107:4f6c30876dfa	1767
Kojto	107:4f6c30876dfa	1768	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
Kojto	107:4f6c30876dfa	1769
Kojto	107:4f6c30876dfa	1770	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
Kojto	107:4f6c30876dfa	1771
Kojto	107:4f6c30876dfa	1772	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
Kojto	107:4f6c30876dfa	1773
Kojto	107:4f6c30876dfa	1774	/**
Kojto	107:4f6c30876dfa	1775	* @}
Kojto	107:4f6c30876dfa	1776	*/
Kojto	107:4f6c30876dfa	1777
Kojto	107:4f6c30876dfa	1778	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
Kojto	107:4f6c30876dfa	1779	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	1780	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1781	* power consumption.
Kojto	107:4f6c30876dfa	1782	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1783	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1784	* @{
Kojto	107:4f6c30876dfa	1785	*/
Kojto	107:4f6c30876dfa	1786
Kojto	107:4f6c30876dfa	1787	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
Kojto	107:4f6c30876dfa	1788
Kojto	107:4f6c30876dfa	1789	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
Kojto	107:4f6c30876dfa	1790
Kojto	107:4f6c30876dfa	1791	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
Kojto	107:4f6c30876dfa	1792
Kojto	107:4f6c30876dfa	1793	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
Kojto	107:4f6c30876dfa	1794
Kojto	107:4f6c30876dfa	1795	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
Kojto	107:4f6c30876dfa	1796
Kojto	107:4f6c30876dfa	1797	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
Kojto	107:4f6c30876dfa	1798
Kojto	107:4f6c30876dfa	1799	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
Kojto	107:4f6c30876dfa	1800
Kojto	107:4f6c30876dfa	1801	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
Kojto	107:4f6c30876dfa	1802
Kojto	107:4f6c30876dfa	1803	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
Kojto	107:4f6c30876dfa	1804
Kojto	107:4f6c30876dfa	1805	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
Kojto	107:4f6c30876dfa	1806
Kojto	107:4f6c30876dfa	1807	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
Kojto	107:4f6c30876dfa	1808
Kojto	107:4f6c30876dfa	1809	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
Kojto	107:4f6c30876dfa	1810
Kojto	107:4f6c30876dfa	1811	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
Kojto	107:4f6c30876dfa	1812
Kojto	107:4f6c30876dfa	1813	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
Kojto	107:4f6c30876dfa	1814
Kojto	107:4f6c30876dfa	1815	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
Kojto	107:4f6c30876dfa	1816
Kojto	107:4f6c30876dfa	1817	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
Kojto	107:4f6c30876dfa	1818
Kojto	107:4f6c30876dfa	1819	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
Kojto	107:4f6c30876dfa	1820
Kojto	107:4f6c30876dfa	1821	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
Kojto	107:4f6c30876dfa	1822
Kojto	107:4f6c30876dfa	1823	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
Kojto	107:4f6c30876dfa	1824
Kojto	107:4f6c30876dfa	1825	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
Kojto	107:4f6c30876dfa	1826
Kojto	107:4f6c30876dfa	1827	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
Kojto	107:4f6c30876dfa	1828
Kojto	107:4f6c30876dfa	1829	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
Kojto	107:4f6c30876dfa	1830
Kojto	107:4f6c30876dfa	1831	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
Kojto	107:4f6c30876dfa	1832
Kojto	107:4f6c30876dfa	1833	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
Kojto	107:4f6c30876dfa	1834
Kojto	107:4f6c30876dfa	1835	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
Kojto	107:4f6c30876dfa	1836
Kojto	107:4f6c30876dfa	1837	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
Kojto	107:4f6c30876dfa	1838
Kojto	107:4f6c30876dfa	1839	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
Kojto	107:4f6c30876dfa	1840
Kojto	107:4f6c30876dfa	1841	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
Kojto	107:4f6c30876dfa	1842
Kojto	107:4f6c30876dfa	1843	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
Kojto	107:4f6c30876dfa	1844
Kojto	107:4f6c30876dfa	1845	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
Kojto	107:4f6c30876dfa	1846
Kojto	107:4f6c30876dfa	1847	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
Kojto	107:4f6c30876dfa	1848
Kojto	107:4f6c30876dfa	1849	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
Kojto	107:4f6c30876dfa	1850
Kojto	107:4f6c30876dfa	1851	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
Kojto	107:4f6c30876dfa	1852
Kojto	107:4f6c30876dfa	1853	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
Kojto	107:4f6c30876dfa	1854
Kojto	107:4f6c30876dfa	1855	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
Kojto	107:4f6c30876dfa	1856
Kojto	107:4f6c30876dfa	1857	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
Kojto	107:4f6c30876dfa	1858
Kojto	107:4f6c30876dfa	1859	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
Kojto	107:4f6c30876dfa	1860
Kojto	107:4f6c30876dfa	1861	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
Kojto	107:4f6c30876dfa	1862
Kojto	107:4f6c30876dfa	1863	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
Kojto	107:4f6c30876dfa	1864
Kojto	107:4f6c30876dfa	1865	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
Kojto	107:4f6c30876dfa	1866
Kojto	107:4f6c30876dfa	1867	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
Kojto	107:4f6c30876dfa	1868
Kojto	107:4f6c30876dfa	1869	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
Kojto	107:4f6c30876dfa	1870
Kojto	107:4f6c30876dfa	1871	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
Kojto	107:4f6c30876dfa	1872
Kojto	107:4f6c30876dfa	1873	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
Kojto	107:4f6c30876dfa	1874
Kojto	107:4f6c30876dfa	1875	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
Kojto	107:4f6c30876dfa	1876
Kojto	107:4f6c30876dfa	1877	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
Kojto	107:4f6c30876dfa	1878
Kojto	107:4f6c30876dfa	1879	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
Kojto	107:4f6c30876dfa	1880
Kojto	107:4f6c30876dfa	1881	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
Kojto	107:4f6c30876dfa	1882
Kojto	107:4f6c30876dfa	1883	/**
Kojto	107:4f6c30876dfa	1884	* @}
Kojto	107:4f6c30876dfa	1885	*/
Kojto	107:4f6c30876dfa	1886
Kojto	107:4f6c30876dfa	1887	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
Kojto	107:4f6c30876dfa	1888	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	1889	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1890	* power consumption.
Kojto	107:4f6c30876dfa	1891	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1892	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1893	* @{
Kojto	107:4f6c30876dfa	1894	*/
Kojto	107:4f6c30876dfa	1895
Kojto	107:4f6c30876dfa	1896	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
Kojto	107:4f6c30876dfa	1897
Kojto	107:4f6c30876dfa	1898	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
Kojto	107:4f6c30876dfa	1899
Kojto	107:4f6c30876dfa	1900	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
Kojto	107:4f6c30876dfa	1901
Kojto	107:4f6c30876dfa	1902	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
Kojto	107:4f6c30876dfa	1903
Kojto	107:4f6c30876dfa	1904	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
Kojto	107:4f6c30876dfa	1905
Kojto	107:4f6c30876dfa	1906	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
Kojto	107:4f6c30876dfa	1907
Kojto	107:4f6c30876dfa	1908	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
Kojto	107:4f6c30876dfa	1909
Kojto	107:4f6c30876dfa	1910	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
Kojto	107:4f6c30876dfa	1911
Kojto	107:4f6c30876dfa	1912	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
Kojto	107:4f6c30876dfa	1913
Kojto	107:4f6c30876dfa	1914	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
Kojto	107:4f6c30876dfa	1915
Kojto	107:4f6c30876dfa	1916	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
Kojto	107:4f6c30876dfa	1917
Kojto	107:4f6c30876dfa	1918	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
Kojto	107:4f6c30876dfa	1919
Kojto	107:4f6c30876dfa	1920	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
Kojto	107:4f6c30876dfa	1921
Kojto	107:4f6c30876dfa	1922	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
Kojto	107:4f6c30876dfa	1923
Kojto	107:4f6c30876dfa	1924	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
Kojto	107:4f6c30876dfa	1925
Kojto	107:4f6c30876dfa	1926	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
Kojto	107:4f6c30876dfa	1927
Kojto	107:4f6c30876dfa	1928	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
Kojto	107:4f6c30876dfa	1929
Kojto	107:4f6c30876dfa	1930	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
Kojto	107:4f6c30876dfa	1931
Kojto	107:4f6c30876dfa	1932	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
Kojto	107:4f6c30876dfa	1933
Kojto	107:4f6c30876dfa	1934	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
Kojto	107:4f6c30876dfa	1935
Kojto	107:4f6c30876dfa	1936	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
Kojto	107:4f6c30876dfa	1937
Kojto	107:4f6c30876dfa	1938	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
Kojto	107:4f6c30876dfa	1939
Kojto	107:4f6c30876dfa	1940	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
Kojto	107:4f6c30876dfa	1941
Kojto	107:4f6c30876dfa	1942	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
Kojto	107:4f6c30876dfa	1943
Kojto	107:4f6c30876dfa	1944	/**
Kojto	107:4f6c30876dfa	1945	* @}
Kojto	107:4f6c30876dfa	1946	*/
Kojto	107:4f6c30876dfa	1947
Kojto	107:4f6c30876dfa	1948	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1949	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto	107:4f6c30876dfa	1950	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1951	* power consumption.
Kojto	107:4f6c30876dfa	1952	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1953	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1954	* @{
Kojto	107:4f6c30876dfa	1955	*/
Kojto	107:4f6c30876dfa	1956
Kojto	107:4f6c30876dfa	1957	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
Kojto	107:4f6c30876dfa	1958
Kojto	107:4f6c30876dfa	1959	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
Kojto	107:4f6c30876dfa	1960
Kojto	107:4f6c30876dfa	1961	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
Kojto	107:4f6c30876dfa	1962
Kojto	107:4f6c30876dfa	1963	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
Kojto	107:4f6c30876dfa	1964
Kojto	107:4f6c30876dfa	1965	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
Kojto	107:4f6c30876dfa	1966
Kojto	107:4f6c30876dfa	1967	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
Kojto	107:4f6c30876dfa	1968
Kojto	107:4f6c30876dfa	1969	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
Kojto	107:4f6c30876dfa	1970
Kojto	107:4f6c30876dfa	1971	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
Kojto	107:4f6c30876dfa	1972
Kojto	107:4f6c30876dfa	1973	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
Kojto	107:4f6c30876dfa	1974
Kojto	107:4f6c30876dfa	1975	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
Kojto	107:4f6c30876dfa	1976
Kojto	107:4f6c30876dfa	1977	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
Kojto	107:4f6c30876dfa	1978
Kojto	107:4f6c30876dfa	1979	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
Kojto	107:4f6c30876dfa	1980
Kojto	107:4f6c30876dfa	1981	/**
Kojto	107:4f6c30876dfa	1982	* @}
Kojto	107:4f6c30876dfa	1983	*/
Kojto	107:4f6c30876dfa	1984
Kojto	107:4f6c30876dfa	1985	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto	107:4f6c30876dfa	1986	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto	107:4f6c30876dfa	1987	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	1988	* power consumption.
Kojto	107:4f6c30876dfa	1989	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	1990	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	1991	* @{
Kojto	107:4f6c30876dfa	1992	*/
Kojto	107:4f6c30876dfa	1993
Kojto	107:4f6c30876dfa	1994	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
Kojto	107:4f6c30876dfa	1995
Kojto	107:4f6c30876dfa	1996	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
Kojto	107:4f6c30876dfa	1997
Kojto	107:4f6c30876dfa	1998	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
Kojto	107:4f6c30876dfa	1999
Kojto	107:4f6c30876dfa	2000	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
Kojto	107:4f6c30876dfa	2001
Kojto	107:4f6c30876dfa	2002	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
Kojto	107:4f6c30876dfa	2003
Kojto	107:4f6c30876dfa	2004	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
Kojto	107:4f6c30876dfa	2005
Kojto	107:4f6c30876dfa	2006	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
Kojto	107:4f6c30876dfa	2007
Kojto	107:4f6c30876dfa	2008	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
Kojto	107:4f6c30876dfa	2009
Kojto	107:4f6c30876dfa	2010	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2011
Kojto	107:4f6c30876dfa	2012	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
Kojto	107:4f6c30876dfa	2013
Kojto	107:4f6c30876dfa	2014	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
Kojto	107:4f6c30876dfa	2015
Kojto	107:4f6c30876dfa	2016	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
Kojto	107:4f6c30876dfa	2017
Kojto	107:4f6c30876dfa	2018	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
Kojto	107:4f6c30876dfa	2019
Kojto	107:4f6c30876dfa	2020	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
Kojto	107:4f6c30876dfa	2021
Kojto	107:4f6c30876dfa	2022	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
Kojto	107:4f6c30876dfa	2023
Kojto	107:4f6c30876dfa	2024	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
Kojto	107:4f6c30876dfa	2025
Kojto	107:4f6c30876dfa	2026	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
Kojto	107:4f6c30876dfa	2027
Kojto	107:4f6c30876dfa	2028	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
Kojto	107:4f6c30876dfa	2029
Kojto	107:4f6c30876dfa	2030	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
Kojto	107:4f6c30876dfa	2031
Kojto	107:4f6c30876dfa	2032	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
Kojto	107:4f6c30876dfa	2033
Kojto	107:4f6c30876dfa	2034	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2035
Kojto	107:4f6c30876dfa	2036	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
Kojto	107:4f6c30876dfa	2037
Kojto	107:4f6c30876dfa	2038	/**
Kojto	107:4f6c30876dfa	2039	* @}
Kojto	107:4f6c30876dfa	2040	*/
Kojto	107:4f6c30876dfa	2041
Kojto	107:4f6c30876dfa	2042	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
Kojto	107:4f6c30876dfa	2043	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto	107:4f6c30876dfa	2044	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	2045	* power consumption.
Kojto	107:4f6c30876dfa	2046	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	2047	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	2048	* @{
Kojto	107:4f6c30876dfa	2049	*/
Kojto	107:4f6c30876dfa	2050
Kojto	107:4f6c30876dfa	2051	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
Kojto	107:4f6c30876dfa	2052
Kojto	107:4f6c30876dfa	2053	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
Kojto	107:4f6c30876dfa	2054
Kojto	107:4f6c30876dfa	2055	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
Kojto	107:4f6c30876dfa	2056
Kojto	107:4f6c30876dfa	2057	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
Kojto	107:4f6c30876dfa	2058
Kojto	107:4f6c30876dfa	2059	/**
Kojto	107:4f6c30876dfa	2060	* @}
Kojto	107:4f6c30876dfa	2061	*/
Kojto	107:4f6c30876dfa	2062
Kojto	107:4f6c30876dfa	2063	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto	107:4f6c30876dfa	2064	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto	107:4f6c30876dfa	2065	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	2066	* power consumption.
Kojto	107:4f6c30876dfa	2067	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	2068	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	2069	* @{
Kojto	107:4f6c30876dfa	2070	*/
Kojto	107:4f6c30876dfa	2071
Kojto	107:4f6c30876dfa	2072	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2073
Kojto	107:4f6c30876dfa	2074	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
Kojto	107:4f6c30876dfa	2075
Kojto	107:4f6c30876dfa	2076	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
Kojto	107:4f6c30876dfa	2077
Kojto	107:4f6c30876dfa	2078	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
Kojto	107:4f6c30876dfa	2079
Kojto	107:4f6c30876dfa	2080	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
Kojto	107:4f6c30876dfa	2081
Kojto	107:4f6c30876dfa	2082	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
Kojto	107:4f6c30876dfa	2083
Kojto	107:4f6c30876dfa	2084	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
Kojto	107:4f6c30876dfa	2085
Kojto	107:4f6c30876dfa	2086	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2087
Kojto	107:4f6c30876dfa	2088	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
Kojto	107:4f6c30876dfa	2089
Kojto	107:4f6c30876dfa	2090	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2091
Kojto	107:4f6c30876dfa	2092	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
Kojto	107:4f6c30876dfa	2093
Kojto	107:4f6c30876dfa	2094	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
Kojto	107:4f6c30876dfa	2095
Kojto	107:4f6c30876dfa	2096	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
Kojto	107:4f6c30876dfa	2097
Kojto	107:4f6c30876dfa	2098	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2099
Kojto	107:4f6c30876dfa	2100	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2101
Kojto	107:4f6c30876dfa	2102	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
Kojto	107:4f6c30876dfa	2103
Kojto	107:4f6c30876dfa	2104	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2105
Kojto	107:4f6c30876dfa	2106	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
Kojto	107:4f6c30876dfa	2107
Kojto	107:4f6c30876dfa	2108	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2109
Kojto	107:4f6c30876dfa	2110	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
Kojto	107:4f6c30876dfa	2111
Kojto	107:4f6c30876dfa	2112	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2113
Kojto	107:4f6c30876dfa	2114	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2115
Kojto	107:4f6c30876dfa	2116	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2117
Kojto	107:4f6c30876dfa	2118	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2119
Kojto	107:4f6c30876dfa	2120	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2121
Kojto	107:4f6c30876dfa	2122	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
Kojto	107:4f6c30876dfa	2123
Kojto	107:4f6c30876dfa	2124	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
Kojto	107:4f6c30876dfa	2125
Kojto	107:4f6c30876dfa	2126	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
Kojto	107:4f6c30876dfa	2127
Kojto	107:4f6c30876dfa	2128	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
Kojto	107:4f6c30876dfa	2129
Kojto	107:4f6c30876dfa	2130	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
Kojto	107:4f6c30876dfa	2131
Kojto	107:4f6c30876dfa	2132	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
Kojto	107:4f6c30876dfa	2133
Kojto	107:4f6c30876dfa	2134	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2135
Kojto	107:4f6c30876dfa	2136	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
Kojto	107:4f6c30876dfa	2137
Kojto	107:4f6c30876dfa	2138	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2139
Kojto	107:4f6c30876dfa	2140	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
Kojto	107:4f6c30876dfa	2141
Kojto	107:4f6c30876dfa	2142	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
Kojto	107:4f6c30876dfa	2143
Kojto	107:4f6c30876dfa	2144	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
Kojto	107:4f6c30876dfa	2145
Kojto	107:4f6c30876dfa	2146	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2147
Kojto	107:4f6c30876dfa	2148	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2149
Kojto	107:4f6c30876dfa	2150	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
Kojto	107:4f6c30876dfa	2151
Kojto	107:4f6c30876dfa	2152	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2153
Kojto	107:4f6c30876dfa	2154	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
Kojto	107:4f6c30876dfa	2155
Kojto	107:4f6c30876dfa	2156	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2157
Kojto	107:4f6c30876dfa	2158	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
Kojto	107:4f6c30876dfa	2159
Kojto	107:4f6c30876dfa	2160	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2161
Kojto	107:4f6c30876dfa	2162	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2163
Kojto	107:4f6c30876dfa	2164	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2165
Kojto	107:4f6c30876dfa	2166	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2167
Kojto	107:4f6c30876dfa	2168	/**
Kojto	107:4f6c30876dfa	2169	* @}
Kojto	107:4f6c30876dfa	2170	*/
Kojto	107:4f6c30876dfa	2171
Kojto	107:4f6c30876dfa	2172	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto	107:4f6c30876dfa	2173	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto	107:4f6c30876dfa	2174	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	2175	* power consumption.
Kojto	107:4f6c30876dfa	2176	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	2177	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	2178	* @{
Kojto	107:4f6c30876dfa	2179	*/
Kojto	107:4f6c30876dfa	2180
Kojto	107:4f6c30876dfa	2181	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
Kojto	107:4f6c30876dfa	2182
Kojto	107:4f6c30876dfa	2183	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2184
Kojto	107:4f6c30876dfa	2185	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2186
Kojto	107:4f6c30876dfa	2187	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2188
Kojto	107:4f6c30876dfa	2189	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
Kojto	107:4f6c30876dfa	2190
Kojto	107:4f6c30876dfa	2191	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2192
Kojto	107:4f6c30876dfa	2193	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
Kojto	107:4f6c30876dfa	2194
Kojto	107:4f6c30876dfa	2195	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
Kojto	107:4f6c30876dfa	2196
Kojto	107:4f6c30876dfa	2197	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
Kojto	107:4f6c30876dfa	2198
Kojto	107:4f6c30876dfa	2199	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
Kojto	107:4f6c30876dfa	2200
Kojto	107:4f6c30876dfa	2201	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
Kojto	107:4f6c30876dfa	2202
Kojto	107:4f6c30876dfa	2203	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) != RESET)
Kojto	107:4f6c30876dfa	2204
Kojto	107:4f6c30876dfa	2205	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
Kojto	107:4f6c30876dfa	2206
Kojto	107:4f6c30876dfa	2207	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2208
Kojto	107:4f6c30876dfa	2209	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2210
Kojto	107:4f6c30876dfa	2211	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2212
Kojto	107:4f6c30876dfa	2213	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
Kojto	107:4f6c30876dfa	2214
Kojto	107:4f6c30876dfa	2215	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2216
Kojto	107:4f6c30876dfa	2217	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
Kojto	107:4f6c30876dfa	2218
Kojto	107:4f6c30876dfa	2219	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
Kojto	107:4f6c30876dfa	2220
Kojto	107:4f6c30876dfa	2221	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
Kojto	107:4f6c30876dfa	2222
Kojto	107:4f6c30876dfa	2223	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
Kojto	107:4f6c30876dfa	2224
Kojto	107:4f6c30876dfa	2225	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
Kojto	107:4f6c30876dfa	2226
Kojto	107:4f6c30876dfa	2227	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) == RESET)
Kojto	107:4f6c30876dfa	2228
Kojto	107:4f6c30876dfa	2229	/**
Kojto	107:4f6c30876dfa	2230	* @}
Kojto	107:4f6c30876dfa	2231	*/
Kojto	107:4f6c30876dfa	2232
Kojto	107:4f6c30876dfa	2233	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
Kojto	107:4f6c30876dfa	2234	* @{
Kojto	107:4f6c30876dfa	2235	*/
Kojto	107:4f6c30876dfa	2236
Kojto	107:4f6c30876dfa	2237	/** @brief Macros to force or release the Backup domain reset.
Kojto	107:4f6c30876dfa	2238	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	107:4f6c30876dfa	2239	* and the RTC clock source selection in RCC_CSR register.
Kojto	107:4f6c30876dfa	2240	* @note The BKPSRAM is not affected by this reset.
Kojto	107:4f6c30876dfa	2241	* @retval None
Kojto	107:4f6c30876dfa	2242	*/
Kojto	107:4f6c30876dfa	2243	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto	107:4f6c30876dfa	2244
Kojto	107:4f6c30876dfa	2245	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto	107:4f6c30876dfa	2246
Kojto	107:4f6c30876dfa	2247	/**
Kojto	107:4f6c30876dfa	2248	* @}
Kojto	107:4f6c30876dfa	2249	*/
Kojto	107:4f6c30876dfa	2250
Kojto	107:4f6c30876dfa	2251	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto	107:4f6c30876dfa	2252	* @{
Kojto	107:4f6c30876dfa	2253	*/
Kojto	107:4f6c30876dfa	2254
Kojto	107:4f6c30876dfa	2255	/** @brief Macros to enable or disable the RTC clock.
Kojto	107:4f6c30876dfa	2256	* @note As the RTC is in the Backup domain and write access is denied to
Kojto	107:4f6c30876dfa	2257	* this domain after reset, you have to enable write access using
Kojto	107:4f6c30876dfa	2258	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
Kojto	107:4f6c30876dfa	2259	* (to be done once after reset).
Kojto	107:4f6c30876dfa	2260	* @note These macros must be used after the RTC clock source was selected.
Kojto	107:4f6c30876dfa	2261	* @retval None
Kojto	107:4f6c30876dfa	2262	*/
Kojto	107:4f6c30876dfa	2263	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto	107:4f6c30876dfa	2264
Kojto	107:4f6c30876dfa	2265	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto	107:4f6c30876dfa	2266
Kojto	107:4f6c30876dfa	2267	/**
Kojto	107:4f6c30876dfa	2268	* @}
Kojto	107:4f6c30876dfa	2269	*/
Kojto	107:4f6c30876dfa	2270
Kojto	107:4f6c30876dfa	2271	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	107:4f6c30876dfa	2272	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	2273	* It is used (enabled by hardware) as system clock source after startup
Kojto	107:4f6c30876dfa	2274	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	107:4f6c30876dfa	2275	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	107:4f6c30876dfa	2276	* Security System CSS is enabled).
Kojto	107:4f6c30876dfa	2277	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	107:4f6c30876dfa	2278	* you have to select another source of the system clock then stop the HSI.
Kojto	107:4f6c30876dfa	2279	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	107:4f6c30876dfa	2280	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	107:4f6c30876dfa	2281	* system clock source.
Kojto	107:4f6c30876dfa	2282	* This parameter can be: ENABLE or DISABLE.
Kojto	107:4f6c30876dfa	2283	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	107:4f6c30876dfa	2284	* clock cycles.
Kojto	107:4f6c30876dfa	2285	* @retval None
Kojto	107:4f6c30876dfa	2286	*/
Kojto	107:4f6c30876dfa	2287	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto	107:4f6c30876dfa	2288
Kojto	107:4f6c30876dfa	2289	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto	107:4f6c30876dfa	2290
Kojto	107:4f6c30876dfa	2291	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	107:4f6c30876dfa	2292	* @note The calibration is used to compensate for the variations in voltage
Kojto	107:4f6c30876dfa	2293	* and temperature that influence the frequency of the internal HSI RC.
Kojto	107:4f6c30876dfa	2294	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
Kojto	107:4f6c30876dfa	2295	* (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	107:4f6c30876dfa	2296	* This parameter must be a number between 0 and 31.
Kojto	107:4f6c30876dfa	2297	* @retval None
Kojto	107:4f6c30876dfa	2298	*/
Kojto	107:4f6c30876dfa	2299	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
Kojto	107:4f6c30876dfa	2300	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Kojto	107:4f6c30876dfa	2301
Kojto	107:4f6c30876dfa	2302	/**
Kojto	107:4f6c30876dfa	2303	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
Kojto	107:4f6c30876dfa	2304	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
Kojto	107:4f6c30876dfa	2305	* @note The enable of this function has not effect on the HSION bit.
Kojto	107:4f6c30876dfa	2306	* This parameter can be: ENABLE or DISABLE.
Kojto	107:4f6c30876dfa	2307	* @retval None
Kojto	107:4f6c30876dfa	2308	*/
Kojto	107:4f6c30876dfa	2309	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
Kojto	107:4f6c30876dfa	2310
Kojto	107:4f6c30876dfa	2311	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
Kojto	107:4f6c30876dfa	2312
Kojto	107:4f6c30876dfa	2313	/**
Kojto	107:4f6c30876dfa	2314	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
Kojto	107:4f6c30876dfa	2315	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
Kojto	107:4f6c30876dfa	2316	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
Kojto	107:4f6c30876dfa	2317	* speed because of the HSI startup time.
Kojto	107:4f6c30876dfa	2318	* @note The enable of this function has not effect on the HSION bit.
Kojto	107:4f6c30876dfa	2319	* This parameter can be: ENABLE or DISABLE.
Kojto	107:4f6c30876dfa	2320	* @retval None
Kojto	107:4f6c30876dfa	2321	*/
Kojto	107:4f6c30876dfa	2322	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto	107:4f6c30876dfa	2323
Kojto	107:4f6c30876dfa	2324	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto	107:4f6c30876dfa	2325
Kojto	107:4f6c30876dfa	2326	/**
Kojto	107:4f6c30876dfa	2327	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto	107:4f6c30876dfa	2328	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	2329	* It is used (enabled by hardware) as system clock source after
Kojto	107:4f6c30876dfa	2330	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
Kojto	107:4f6c30876dfa	2331	* of failure of the HSE used directly or indirectly as system clock
Kojto	107:4f6c30876dfa	2332	* (if the Clock Security System CSS is enabled).
Kojto	107:4f6c30876dfa	2333	* @note MSI can not be stopped if it is used as system clock source.
Kojto	107:4f6c30876dfa	2334	* In this case, you have to select another source of the system
Kojto	107:4f6c30876dfa	2335	* clock then stop the MSI.
Kojto	107:4f6c30876dfa	2336	* @note After enabling the MSI, the application software should wait on
Kojto	107:4f6c30876dfa	2337	* MSIRDY flag to be set indicating that MSI clock is stable and can
Kojto	107:4f6c30876dfa	2338	* be used as system clock source.
Kojto	107:4f6c30876dfa	2339	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto	107:4f6c30876dfa	2340	* clock cycles.
Kojto	107:4f6c30876dfa	2341	* @retval None
Kojto	107:4f6c30876dfa	2342	*/
Kojto	107:4f6c30876dfa	2343	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Kojto	107:4f6c30876dfa	2344
Kojto	107:4f6c30876dfa	2345	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
Kojto	107:4f6c30876dfa	2346
Kojto	107:4f6c30876dfa	2347	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
Kojto	107:4f6c30876dfa	2348	* @note The calibration is used to compensate for the variations in voltage
Kojto	107:4f6c30876dfa	2349	* and temperature that influence the frequency of the internal MSI RC.
Kojto	107:4f6c30876dfa	2350	* Refer to the Application Note AN3300 for more details on how to
Kojto	107:4f6c30876dfa	2351	* calibrate the MSI.
Kojto	107:4f6c30876dfa	2352	* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
Kojto	107:4f6c30876dfa	2353	* (default is RCC_MSICALIBRATION_DEFAULT).
Kojto	107:4f6c30876dfa	2354	* This parameter must be a number between 0 and 255.
Kojto	107:4f6c30876dfa	2355	* @retval None
Kojto	107:4f6c30876dfa	2356	*/
Kojto	107:4f6c30876dfa	2357	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
Kojto	107:4f6c30876dfa	2358	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
Kojto	107:4f6c30876dfa	2359
Kojto	107:4f6c30876dfa	2360	/**
Kojto	107:4f6c30876dfa	2361	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
Kojto	107:4f6c30876dfa	2362	* @note After restart from Reset , the MSI clock is around 4 MHz.
Kojto	107:4f6c30876dfa	2363	* After stop the startup clock can be MSI (at any of its possible
Kojto	107:4f6c30876dfa	2364	* frequencies, the one that was used before entering stop mode) or HSI.
Kojto	107:4f6c30876dfa	2365	* After Standby its frequency can be selected between 4 possible values
Kojto	107:4f6c30876dfa	2366	* (1, 2, 4 or 8 MHz).
Kojto	107:4f6c30876dfa	2367	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
Kojto	107:4f6c30876dfa	2368	* (MSIRDY=1).
Kojto	107:4f6c30876dfa	2369	* @note The MSI clock range after reset can be modified on the fly.
Kojto	107:4f6c30876dfa	2370	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
Kojto	107:4f6c30876dfa	2371	* This parameter must be one of the following values:
Kojto	107:4f6c30876dfa	2372	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
Kojto	107:4f6c30876dfa	2373	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
Kojto	107:4f6c30876dfa	2374	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
Kojto	107:4f6c30876dfa	2375	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
Kojto	107:4f6c30876dfa	2376	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
Kojto	107:4f6c30876dfa	2377	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
Kojto	107:4f6c30876dfa	2378	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
Kojto	107:4f6c30876dfa	2379	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
Kojto	107:4f6c30876dfa	2380	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
Kojto	107:4f6c30876dfa	2381	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
Kojto	107:4f6c30876dfa	2382	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
Kojto	107:4f6c30876dfa	2383	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
Kojto	107:4f6c30876dfa	2384	* @retval None
Kojto	107:4f6c30876dfa	2385	*/
Kojto	107:4f6c30876dfa	2386	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
Kojto	107:4f6c30876dfa	2387	do { \
Kojto	107:4f6c30876dfa	2388	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
Kojto	107:4f6c30876dfa	2389	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
Kojto	107:4f6c30876dfa	2390	} while(0)
Kojto	107:4f6c30876dfa	2391
Kojto	107:4f6c30876dfa	2392	/**
Kojto	107:4f6c30876dfa	2393	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
Kojto	107:4f6c30876dfa	2394	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
Kojto	107:4f6c30876dfa	2395	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
Kojto	107:4f6c30876dfa	2396	* This parameter must be one of the following values:
Kojto	107:4f6c30876dfa	2397	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
Kojto	107:4f6c30876dfa	2398	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
Kojto	107:4f6c30876dfa	2399	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
Kojto	107:4f6c30876dfa	2400	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
Kojto	107:4f6c30876dfa	2401	* @retval None
Kojto	107:4f6c30876dfa	2402	*/
Kojto	107:4f6c30876dfa	2403	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
Kojto	107:4f6c30876dfa	2404	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
Kojto	107:4f6c30876dfa	2405
Kojto	107:4f6c30876dfa	2406	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
Kojto	107:4f6c30876dfa	2407	* @retval MSI clock range.
Kojto	107:4f6c30876dfa	2408	* This parameter must be one of the following values:
Kojto	107:4f6c30876dfa	2409	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
Kojto	107:4f6c30876dfa	2410	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
Kojto	107:4f6c30876dfa	2411	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
Kojto	107:4f6c30876dfa	2412	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
Kojto	107:4f6c30876dfa	2413	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
Kojto	107:4f6c30876dfa	2414	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
Kojto	107:4f6c30876dfa	2415	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
Kojto	107:4f6c30876dfa	2416	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
Kojto	107:4f6c30876dfa	2417	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
Kojto	107:4f6c30876dfa	2418	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
Kojto	107:4f6c30876dfa	2419	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
Kojto	107:4f6c30876dfa	2420	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
Kojto	107:4f6c30876dfa	2421	*/
Kojto	107:4f6c30876dfa	2422	#define __HAL_RCC_GET_MSI_RANGE() \
Kojto	107:4f6c30876dfa	2423	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
Kojto	107:4f6c30876dfa	2424	(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
Kojto	107:4f6c30876dfa	2425	(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
Kojto	107:4f6c30876dfa	2426
Kojto	107:4f6c30876dfa	2427	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	107:4f6c30876dfa	2428	* @note After enabling the LSI, the application software should wait on
Kojto	107:4f6c30876dfa	2429	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	107:4f6c30876dfa	2430	* be used to clock the IWDG and/or the RTC.
Kojto	107:4f6c30876dfa	2431	* @note LSI can not be disabled if the IWDG is running.
Kojto	107:4f6c30876dfa	2432	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	107:4f6c30876dfa	2433	* clock cycles.
Kojto	107:4f6c30876dfa	2434	* @retval None
Kojto	107:4f6c30876dfa	2435	*/
Kojto	107:4f6c30876dfa	2436	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	107:4f6c30876dfa	2437
Kojto	107:4f6c30876dfa	2438	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	107:4f6c30876dfa	2439
Kojto	107:4f6c30876dfa	2440	/**
Kojto	107:4f6c30876dfa	2441	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	107:4f6c30876dfa	2442	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto	107:4f6c30876dfa	2443	* supported by this macro. User should request a transition to HSE Off
Kojto	107:4f6c30876dfa	2444	* first and then HSE On or HSE Bypass.
Kojto	107:4f6c30876dfa	2445	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	107:4f6c30876dfa	2446	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	107:4f6c30876dfa	2447	* is stable and can be used to clock the PLL and/or system clock.
Kojto	107:4f6c30876dfa	2448	* @note HSE state can not be changed if it is used directly or through the
Kojto	107:4f6c30876dfa	2449	* PLL as system clock. In this case, you have to select another source
Kojto	107:4f6c30876dfa	2450	* of the system clock then change the HSE state (ex. disable it).
Kojto	107:4f6c30876dfa	2451	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	2452	* @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto	107:4f6c30876dfa	2453	* was previously enabled you have to enable it again after calling this
Kojto	107:4f6c30876dfa	2454	* function.
Kojto	107:4f6c30876dfa	2455	* @param __STATE__: specifies the new state of the HSE.
Kojto	107:4f6c30876dfa	2456	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2457	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	107:4f6c30876dfa	2458	* 6 HSE oscillator clock cycles.
Kojto	107:4f6c30876dfa	2459	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto	107:4f6c30876dfa	2460	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto	107:4f6c30876dfa	2461	* @retval None
Kojto	107:4f6c30876dfa	2462	*/
Kojto	107:4f6c30876dfa	2463	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	107:4f6c30876dfa	2464	do { \
Kojto	107:4f6c30876dfa	2465	if((__STATE__) == RCC_HSE_ON) \
Kojto	107:4f6c30876dfa	2466	{ \
Kojto	107:4f6c30876dfa	2467	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	2468	} \
Kojto	107:4f6c30876dfa	2469	else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto	107:4f6c30876dfa	2470	{ \
Kojto	107:4f6c30876dfa	2471	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	2472	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	107:4f6c30876dfa	2473	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	2474	} \
Kojto	107:4f6c30876dfa	2475	else \
Kojto	107:4f6c30876dfa	2476	{ \
Kojto	107:4f6c30876dfa	2477	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	2478	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	107:4f6c30876dfa	2479	} \
Kojto	107:4f6c30876dfa	2480	} while(0)
Kojto	107:4f6c30876dfa	2481
Kojto	107:4f6c30876dfa	2482	/**
Kojto	107:4f6c30876dfa	2483	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	107:4f6c30876dfa	2484	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
Kojto	107:4f6c30876dfa	2485	* supported by this macro. User should request a transition to LSE Off
Kojto	107:4f6c30876dfa	2486	* first and then LSE On or LSE Bypass.
Kojto	107:4f6c30876dfa	2487	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	107:4f6c30876dfa	2488	* this domain after reset, you have to enable write access using
Kojto	107:4f6c30876dfa	2489	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	107:4f6c30876dfa	2490	* (to be done once after reset).
Kojto	107:4f6c30876dfa	2491	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	107:4f6c30876dfa	2492	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	107:4f6c30876dfa	2493	* is stable and can be used to clock the RTC.
Kojto	107:4f6c30876dfa	2494	* @param __STATE__: specifies the new state of the LSE.
Kojto	107:4f6c30876dfa	2495	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2496	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	107:4f6c30876dfa	2497	* 6 LSE oscillator clock cycles.
Kojto	107:4f6c30876dfa	2498	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	107:4f6c30876dfa	2499	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto	107:4f6c30876dfa	2500	* @retval None
Kojto	107:4f6c30876dfa	2501	*/
Kojto	107:4f6c30876dfa	2502	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	107:4f6c30876dfa	2503	do { \
Kojto	107:4f6c30876dfa	2504	if((__STATE__) == RCC_LSE_ON) \
Kojto	107:4f6c30876dfa	2505	{ \
Kojto	107:4f6c30876dfa	2506	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	2507	} \
Kojto	107:4f6c30876dfa	2508	else if((__STATE__) == RCC_LSE_OFF) \
Kojto	107:4f6c30876dfa	2509	{ \
Kojto	107:4f6c30876dfa	2510	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	2511	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	107:4f6c30876dfa	2512	} \
Kojto	107:4f6c30876dfa	2513	else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto	107:4f6c30876dfa	2514	{ \
Kojto	107:4f6c30876dfa	2515	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	2516	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	107:4f6c30876dfa	2517	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	2518	} \
Kojto	107:4f6c30876dfa	2519	else \
Kojto	107:4f6c30876dfa	2520	{ \
Kojto	107:4f6c30876dfa	2521	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	2522	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	107:4f6c30876dfa	2523	} \
Kojto	107:4f6c30876dfa	2524	} while(0)
Kojto	107:4f6c30876dfa	2525
Kojto	107:4f6c30876dfa	2526	/** @brief Macros to configure the RTC clock (RTCCLK).
Kojto	107:4f6c30876dfa	2527	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	107:4f6c30876dfa	2528	* access is denied to this domain after reset, you have to enable write
Kojto	107:4f6c30876dfa	2529	* access using the Power Backup Access macro before to configure
Kojto	107:4f6c30876dfa	2530	* the RTC clock source (to be done once after reset).
Kojto	107:4f6c30876dfa	2531	* @note Once the RTC clock is configured it cannot be changed unless the
Kojto	107:4f6c30876dfa	2532	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto	107:4f6c30876dfa	2533	* a Power On Reset (POR).
Kojto	107:4f6c30876dfa	2534	*
Kojto	107:4f6c30876dfa	2535	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto	107:4f6c30876dfa	2536	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2537	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto	107:4f6c30876dfa	2538	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto	107:4f6c30876dfa	2539	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
Kojto	107:4f6c30876dfa	2540	*
Kojto	107:4f6c30876dfa	2541	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	107:4f6c30876dfa	2542	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	107:4f6c30876dfa	2543	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	107:4f6c30876dfa	2544	* cannot be used in STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	2545	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	107:4f6c30876dfa	2546	* RTC clock source).
Kojto	107:4f6c30876dfa	2547	* @retval None
Kojto	107:4f6c30876dfa	2548	*/
Kojto	107:4f6c30876dfa	2549	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
Kojto	107:4f6c30876dfa	2550	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto	107:4f6c30876dfa	2551
Kojto	107:4f6c30876dfa	2552
Kojto	107:4f6c30876dfa	2553	/** @brief Macro to get the RTC clock source.
Kojto	107:4f6c30876dfa	2554	* @retval The returned value can be one of the following:
Kojto	107:4f6c30876dfa	2555	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto	107:4f6c30876dfa	2556	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto	107:4f6c30876dfa	2557	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
Kojto	107:4f6c30876dfa	2558	*/
Kojto	107:4f6c30876dfa	2559	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto	107:4f6c30876dfa	2560
Kojto	107:4f6c30876dfa	2561	/** @brief Macros to enable or disable the main PLL.
Kojto	107:4f6c30876dfa	2562	* @note After enabling the main PLL, the application software should wait on
Kojto	107:4f6c30876dfa	2563	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	107:4f6c30876dfa	2564	* be used as system clock source.
Kojto	107:4f6c30876dfa	2565	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	107:4f6c30876dfa	2566	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	2567	* @retval None
Kojto	107:4f6c30876dfa	2568	*/
Kojto	107:4f6c30876dfa	2569	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	107:4f6c30876dfa	2570
Kojto	107:4f6c30876dfa	2571	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	107:4f6c30876dfa	2572
Kojto	107:4f6c30876dfa	2573	/** @brief Macro to configure the PLL clock source.
Kojto	107:4f6c30876dfa	2574	* @note This function must be used only when the main PLL is disabled.
Kojto	107:4f6c30876dfa	2575	* @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto	107:4f6c30876dfa	2576	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2577	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2578	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2579	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2580	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2581	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Kojto	107:4f6c30876dfa	2582	* @retval None
Kojto	107:4f6c30876dfa	2583	*
Kojto	107:4f6c30876dfa	2584	*/
Kojto	107:4f6c30876dfa	2585	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
Kojto	107:4f6c30876dfa	2586	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto	107:4f6c30876dfa	2587
Kojto	107:4f6c30876dfa	2588	/** @brief Macro to configure the PLL multiplication factor.
Kojto	107:4f6c30876dfa	2589	* @note This function must be used only when the main PLL is disabled.
Kojto	107:4f6c30876dfa	2590	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	107:4f6c30876dfa	2591	* This parameter must be a number between Min_Data = 1 and Max_Data = 8.
Kojto	107:4f6c30876dfa	2592	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	107:4f6c30876dfa	2593	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
Kojto	107:4f6c30876dfa	2594	* of 16 MHz to limit PLL jitter.
Kojto	107:4f6c30876dfa	2595	* @retval None
Kojto	107:4f6c30876dfa	2596	*
Kojto	107:4f6c30876dfa	2597	*/
Kojto	107:4f6c30876dfa	2598	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
Kojto	107:4f6c30876dfa	2599	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
Kojto	107:4f6c30876dfa	2600
Kojto	107:4f6c30876dfa	2601	/**
Kojto	107:4f6c30876dfa	2602	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	107:4f6c30876dfa	2603	* @note This function must be used only when the main PLL is disabled.
Kojto	107:4f6c30876dfa	2604	*
Kojto	107:4f6c30876dfa	2605	* @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto	107:4f6c30876dfa	2606	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2607	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2608	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2609	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2610	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	2611	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Kojto	107:4f6c30876dfa	2612	*
Kojto	107:4f6c30876dfa	2613	* @param __PLLM__: specifies the division factor for PLL VCO input clock.
Kojto	107:4f6c30876dfa	2614	* This parameter must be a number between 1 and 8.
Kojto	107:4f6c30876dfa	2615	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	107:4f6c30876dfa	2616	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
Kojto	107:4f6c30876dfa	2617	* of 16 MHz to limit PLL jitter.
Kojto	107:4f6c30876dfa	2618	*
Kojto	107:4f6c30876dfa	2619	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
Kojto	107:4f6c30876dfa	2620	* This parameter must be a number between 8 and 86.
Kojto	107:4f6c30876dfa	2621	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	107:4f6c30876dfa	2622	* output frequency is between 64 and 344 MHz.
Kojto	107:4f6c30876dfa	2623	*
Kojto	107:4f6c30876dfa	2624	* @param __PLLP__: specifies the division factor for SAI clock.
Kojto	107:4f6c30876dfa	2625	* This parameter must be a number in the range (7 or 17).
Kojto	107:4f6c30876dfa	2626	*
Kojto	107:4f6c30876dfa	2627	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
Kojto	107:4f6c30876dfa	2628	* This parameter must be in the range (2, 4, 6 or 8).
Kojto	107:4f6c30876dfa	2629	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	107:4f6c30876dfa	2630	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	107:4f6c30876dfa	2631	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	107:4f6c30876dfa	2632	* correctly.
Kojto	107:4f6c30876dfa	2633	* @param __PLLR__: specifies the division factor for the main system clock.
Kojto	107:4f6c30876dfa	2634	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
Kojto	107:4f6c30876dfa	2635	* This parameter must be in the range (2, 4, 6 or 8).
Kojto	107:4f6c30876dfa	2636	* @retval None
Kojto	107:4f6c30876dfa	2637	*/
Kojto	107:4f6c30876dfa	2638	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
Kojto	107:4f6c30876dfa	2639	(RCC->PLLCFGR = (((__PLLM__) - 1) << 4U) \| ((__PLLN__) << 8U) \| (((__PLLP__) >> 4U ) << 17U) \| \
Kojto	107:4f6c30876dfa	2640	(__PLLSOURCE__) \| ((((__PLLQ__) >> 1U) - 1) << 21U) \| ((((__PLLR__) >> 1U) - 1) << 25U))
Kojto	107:4f6c30876dfa	2641
Kojto	107:4f6c30876dfa	2642	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	107:4f6c30876dfa	2643	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	107:4f6c30876dfa	2644	* of the following:
Kojto	107:4f6c30876dfa	2645	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
Kojto	107:4f6c30876dfa	2646	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
Kojto	107:4f6c30876dfa	2647	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	107:4f6c30876dfa	2648	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	107:4f6c30876dfa	2649	*/
Kojto	107:4f6c30876dfa	2650	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto	107:4f6c30876dfa	2651
Kojto	107:4f6c30876dfa	2652	/**
Kojto	107:4f6c30876dfa	2653	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
Kojto	107:4f6c30876dfa	2654	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
Kojto	107:4f6c30876dfa	2655	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
Kojto	107:4f6c30876dfa	2656	* be stopped if used as System Clock.
Kojto	107:4f6c30876dfa	2657	* @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
Kojto	107:4f6c30876dfa	2658	* This parameter can be one or a combination of the following values:
Kojto	107:4f6c30876dfa	2659	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
Kojto	107:4f6c30876dfa	2660	* high-quality audio performance on SAI interface in case.
Kojto	107:4f6c30876dfa	2661	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto	107:4f6c30876dfa	2662	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
Kojto	107:4f6c30876dfa	2663	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
Kojto	107:4f6c30876dfa	2664	* @retval None
Kojto	107:4f6c30876dfa	2665	*/
Kojto	107:4f6c30876dfa	2666	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto	107:4f6c30876dfa	2667
Kojto	107:4f6c30876dfa	2668	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto	107:4f6c30876dfa	2669
Kojto	107:4f6c30876dfa	2670	/**
Kojto	107:4f6c30876dfa	2671	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
Kojto	107:4f6c30876dfa	2672	* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
Kojto	107:4f6c30876dfa	2673	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2674	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
Kojto	107:4f6c30876dfa	2675	* high-quality audio performance on SAI interface in case.
Kojto	107:4f6c30876dfa	2676	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto	107:4f6c30876dfa	2677	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
Kojto	107:4f6c30876dfa	2678	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
Kojto	107:4f6c30876dfa	2679	* @retval SET / RESET
Kojto	107:4f6c30876dfa	2680	*/
Kojto	107:4f6c30876dfa	2681	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto	107:4f6c30876dfa	2682
Kojto	107:4f6c30876dfa	2683	/**
Kojto	107:4f6c30876dfa	2684	* @brief Macro to configure the system clock source.
Kojto	107:4f6c30876dfa	2685	* @param __SYSCLKSOURCE__: specifies the system clock source.
Kojto	107:4f6c30876dfa	2686	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2687	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
Kojto	107:4f6c30876dfa	2688	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto	107:4f6c30876dfa	2689	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto	107:4f6c30876dfa	2690	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto	107:4f6c30876dfa	2691	* @retval None
Kojto	107:4f6c30876dfa	2692	*/
Kojto	107:4f6c30876dfa	2693	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
Kojto	107:4f6c30876dfa	2694	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Kojto	107:4f6c30876dfa	2695
Kojto	107:4f6c30876dfa	2696	/** @brief Macro to get the clock source used as system clock.
Kojto	107:4f6c30876dfa	2697	* @retval The clock source used as system clock. The returned value can be one
Kojto	107:4f6c30876dfa	2698	* of the following:
Kojto	107:4f6c30876dfa	2699	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
Kojto	107:4f6c30876dfa	2700	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto	107:4f6c30876dfa	2701	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto	107:4f6c30876dfa	2702	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto	107:4f6c30876dfa	2703	*/
Kojto	107:4f6c30876dfa	2704	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto	107:4f6c30876dfa	2705
Kojto	107:4f6c30876dfa	2706	/**
Kojto	107:4f6c30876dfa	2707	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
Kojto	107:4f6c30876dfa	2708	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	107:4f6c30876dfa	2709	* this domain after reset, you have to enable write access using
Kojto	107:4f6c30876dfa	2710	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	107:4f6c30876dfa	2711	* (to be done once after reset).
Kojto	107:4f6c30876dfa	2712	* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
Kojto	107:4f6c30876dfa	2713	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2714	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
Kojto	107:4f6c30876dfa	2715	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
Kojto	107:4f6c30876dfa	2716	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
Kojto	107:4f6c30876dfa	2717	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Kojto	107:4f6c30876dfa	2718	* @retval None
Kojto	107:4f6c30876dfa	2719	*/
Kojto	107:4f6c30876dfa	2720	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
Kojto	107:4f6c30876dfa	2721	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Kojto	107:4f6c30876dfa	2722
Kojto	107:4f6c30876dfa	2723	/**
Kojto	107:4f6c30876dfa	2724	* @brief Macro to configures the wake up from stop clock.
Kojto	107:4f6c30876dfa	2725	* @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
Kojto	107:4f6c30876dfa	2726	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2727	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
Kojto	107:4f6c30876dfa	2728	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
Kojto	107:4f6c30876dfa	2729	* @retval None
Kojto	107:4f6c30876dfa	2730	*/
Kojto	107:4f6c30876dfa	2731	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
Kojto	107:4f6c30876dfa	2732	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
Kojto	107:4f6c30876dfa	2733
Kojto	107:4f6c30876dfa	2734
Kojto	107:4f6c30876dfa	2735	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto	107:4f6c30876dfa	2736	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	107:4f6c30876dfa	2737	* @{
Kojto	107:4f6c30876dfa	2738	*/
Kojto	107:4f6c30876dfa	2739
Kojto	107:4f6c30876dfa	2740	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	107:4f6c30876dfa	2741	* the selected interrupts).
Kojto	107:4f6c30876dfa	2742	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	107:4f6c30876dfa	2743	* This parameter can be any combination of the following values:
Kojto	107:4f6c30876dfa	2744	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	107:4f6c30876dfa	2745	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	107:4f6c30876dfa	2746	* @arg RCC_IT_MSIRDY: HSI ready interrupt
Kojto	107:4f6c30876dfa	2747	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	107:4f6c30876dfa	2748	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	107:4f6c30876dfa	2749	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	107:4f6c30876dfa	2750	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
Kojto	107:4f6c30876dfa	2751	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
Kojto	107:4f6c30876dfa	2752	* @arg RCC_IT_LSECSS: Clock security system interrupt
Kojto	107:4f6c30876dfa	2753	* @retval None
Kojto	107:4f6c30876dfa	2754	*/
Kojto	107:4f6c30876dfa	2755	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Kojto	107:4f6c30876dfa	2756
Kojto	107:4f6c30876dfa	2757	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	107:4f6c30876dfa	2758	* the selected interrupts).
Kojto	107:4f6c30876dfa	2759	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	107:4f6c30876dfa	2760	* This parameter can be any combination of the following values:
Kojto	107:4f6c30876dfa	2761	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	107:4f6c30876dfa	2762	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	107:4f6c30876dfa	2763	* @arg RCC_IT_MSIRDY: HSI ready interrupt
Kojto	107:4f6c30876dfa	2764	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	107:4f6c30876dfa	2765	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	107:4f6c30876dfa	2766	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	107:4f6c30876dfa	2767	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
Kojto	107:4f6c30876dfa	2768	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
Kojto	107:4f6c30876dfa	2769	* @arg RCC_IT_LSECSS: Clock security system interrupt
Kojto	107:4f6c30876dfa	2770	* @retval None
Kojto	107:4f6c30876dfa	2771	*/
Kojto	107:4f6c30876dfa	2772	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Kojto	107:4f6c30876dfa	2773
Kojto	107:4f6c30876dfa	2774	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto	107:4f6c30876dfa	2775	* bits to clear the selected interrupt pending bits.
Kojto	107:4f6c30876dfa	2776	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	107:4f6c30876dfa	2777	* This parameter can be any combination of the following values:
Kojto	107:4f6c30876dfa	2778	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	107:4f6c30876dfa	2779	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	107:4f6c30876dfa	2780	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	107:4f6c30876dfa	2781	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	107:4f6c30876dfa	2782	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	107:4f6c30876dfa	2783	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	107:4f6c30876dfa	2784	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
Kojto	107:4f6c30876dfa	2785	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
Kojto	107:4f6c30876dfa	2786	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
Kojto	107:4f6c30876dfa	2787	* @arg RCC_IT_LSECSS: Clock security system interrupt
Kojto	107:4f6c30876dfa	2788	* @retval None
Kojto	107:4f6c30876dfa	2789	*/
Kojto	107:4f6c30876dfa	2790	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Kojto	107:4f6c30876dfa	2791
Kojto	107:4f6c30876dfa	2792	/** @brief Check whether the RCC interrupt has occurred or not.
Kojto	107:4f6c30876dfa	2793	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	107:4f6c30876dfa	2794	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2795	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	107:4f6c30876dfa	2796	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	107:4f6c30876dfa	2797	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	107:4f6c30876dfa	2798	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	107:4f6c30876dfa	2799	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	107:4f6c30876dfa	2800	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	107:4f6c30876dfa	2801	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
Kojto	107:4f6c30876dfa	2802	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
Kojto	107:4f6c30876dfa	2803	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
Kojto	107:4f6c30876dfa	2804	* @arg RCC_IT_LSECSS: Clock security system interrupt
Kojto	107:4f6c30876dfa	2805	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	107:4f6c30876dfa	2806	*/
Kojto	107:4f6c30876dfa	2807	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	107:4f6c30876dfa	2808
Kojto	107:4f6c30876dfa	2809	/** @brief Set RMVF bit to clear the reset flags.
Kojto	107:4f6c30876dfa	2810	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
Kojto	107:4f6c30876dfa	2811	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto	107:4f6c30876dfa	2812	* @retval None
Kojto	107:4f6c30876dfa	2813	*/
Kojto	107:4f6c30876dfa	2814	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	107:4f6c30876dfa	2815
Kojto	107:4f6c30876dfa	2816	/** @brief Check whether the selected RCC flag is set or not.
Kojto	107:4f6c30876dfa	2817	* @param __FLAG__: specifies the flag to check.
Kojto	107:4f6c30876dfa	2818	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	2819	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
Kojto	107:4f6c30876dfa	2820	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto	107:4f6c30876dfa	2821	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto	107:4f6c30876dfa	2822	* @arg RCC_FLAG_PLLRDY: main PLL clock ready
Kojto	107:4f6c30876dfa	2823	* @arg RCC_FLAG_PLLSAI2RDY: PLLSAI2 clock ready
Kojto	107:4f6c30876dfa	2824	* @arg RCC_FLAG_PLLSAI1RDY: PLLSAI1 clock ready
Kojto	107:4f6c30876dfa	2825	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto	107:4f6c30876dfa	2826	* @arg RCC_FLAG_LSECSSD: Clock security system failure on LSE oscillator detection
Kojto	107:4f6c30876dfa	2827	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto	107:4f6c30876dfa	2828	* @arg RCC_FLAG_BORRST: BOR reset
Kojto	107:4f6c30876dfa	2829	* @arg RCC_FLAG_OBLRST: OBLRST reset
Kojto	107:4f6c30876dfa	2830	* @arg RCC_FLAG_PINRST: Pin reset
Kojto	107:4f6c30876dfa	2831	* @arg RCC_FLAG_FWRST: FIREWALL reset
Kojto	107:4f6c30876dfa	2832	* @arg RCC_FLAG_RMVF: Remove reset Flag
Kojto	107:4f6c30876dfa	2833	* @arg RCC_FLAG_SFTRST: Software reset
Kojto	107:4f6c30876dfa	2834	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto	107:4f6c30876dfa	2835	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto	107:4f6c30876dfa	2836	* @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto	107:4f6c30876dfa	2837	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	107:4f6c30876dfa	2838	*/
Kojto	107:4f6c30876dfa	2839	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
Kojto	107:4f6c30876dfa	2840	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
Kojto	107:4f6c30876dfa	2841	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
Kojto	107:4f6c30876dfa	2842	((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0) \
Kojto	107:4f6c30876dfa	2843	? 1 : 0)
Kojto	107:4f6c30876dfa	2844
Kojto	107:4f6c30876dfa	2845	/**
Kojto	107:4f6c30876dfa	2846	* @}
Kojto	107:4f6c30876dfa	2847	*/
Kojto	107:4f6c30876dfa	2848
Kojto	107:4f6c30876dfa	2849	/**
Kojto	107:4f6c30876dfa	2850	* @}
Kojto	107:4f6c30876dfa	2851	*/
Kojto	107:4f6c30876dfa	2852
Kojto	107:4f6c30876dfa	2853	/* Private constants ---------------------------------------------------------*/
Kojto	107:4f6c30876dfa	2854	/** @defgroup RCC_Private_Constants RCC Private Constants
Kojto	107:4f6c30876dfa	2855	* @{
Kojto	107:4f6c30876dfa	2856	*/
Kojto	107:4f6c30876dfa	2857	/* Defines used for Flags */
Kojto	107:4f6c30876dfa	2858	#define CR_REG_INDEX ((uint8_t)1)
Kojto	107:4f6c30876dfa	2859	#define BDCR_REG_INDEX ((uint8_t)2)
Kojto	107:4f6c30876dfa	2860	#define CSR_REG_INDEX ((uint8_t)3)
Kojto	107:4f6c30876dfa	2861
Kojto	107:4f6c30876dfa	2862	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	107:4f6c30876dfa	2863	/**
Kojto	107:4f6c30876dfa	2864	* @}
Kojto	107:4f6c30876dfa	2865	*/
Kojto	107:4f6c30876dfa	2866
Kojto	107:4f6c30876dfa	2867	/* Private macros ------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	2868	/** @addtogroup RCC_Private_Macros
Kojto	107:4f6c30876dfa	2869	* @{
Kojto	107:4f6c30876dfa	2870	*/
Kojto	107:4f6c30876dfa	2871
Kojto	107:4f6c30876dfa	2872	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	107:4f6c30876dfa	2873	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	107:4f6c30876dfa	2874	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	107:4f6c30876dfa	2875	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
Kojto	107:4f6c30876dfa	2876	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	107:4f6c30876dfa	2877	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto	107:4f6c30876dfa	2878
Kojto	107:4f6c30876dfa	2879	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	107:4f6c30876dfa	2880	((__HSE__) == RCC_HSE_BYPASS))
Kojto	107:4f6c30876dfa	2881
Kojto	107:4f6c30876dfa	2882	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	107:4f6c30876dfa	2883	((__LSE__) == RCC_LSE_BYPASS))
Kojto	107:4f6c30876dfa	2884
Kojto	107:4f6c30876dfa	2885	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
Kojto	107:4f6c30876dfa	2886
Kojto	107:4f6c30876dfa	2887	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31)
Kojto	107:4f6c30876dfa	2888
Kojto	107:4f6c30876dfa	2889	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	107:4f6c30876dfa	2890
Kojto	107:4f6c30876dfa	2891	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
Kojto	107:4f6c30876dfa	2892
Kojto	107:4f6c30876dfa	2893	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255)
Kojto	107:4f6c30876dfa	2894
Kojto	107:4f6c30876dfa	2895	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
Kojto	107:4f6c30876dfa	2896	((__PLL__) == RCC_PLL_ON))
Kojto	107:4f6c30876dfa	2897
Kojto	107:4f6c30876dfa	2898	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
Kojto	107:4f6c30876dfa	2899	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
Kojto	107:4f6c30876dfa	2900	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	107:4f6c30876dfa	2901	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	107:4f6c30876dfa	2902
Kojto	107:4f6c30876dfa	2903	#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= 8)
Kojto	107:4f6c30876dfa	2904
Kojto	107:4f6c30876dfa	2905	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
Kojto	107:4f6c30876dfa	2906
Kojto	107:4f6c30876dfa	2907	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7) \|\| ((__VALUE__) == 17) )
Kojto	107:4f6c30876dfa	2908
Kojto	107:4f6c30876dfa	2909	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
Kojto	107:4f6c30876dfa	2910	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
Kojto	107:4f6c30876dfa	2911
Kojto	107:4f6c30876dfa	2912	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
Kojto	107:4f6c30876dfa	2913	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
Kojto	107:4f6c30876dfa	2914
Kojto	107:4f6c30876dfa	2915	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
Kojto	107:4f6c30876dfa	2916	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
Kojto	107:4f6c30876dfa	2917	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
Kojto	107:4f6c30876dfa	2918	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0))
Kojto	107:4f6c30876dfa	2919
Kojto	107:4f6c30876dfa	2920	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK ) \|\| \
Kojto	107:4f6c30876dfa	2921	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
Kojto	107:4f6c30876dfa	2922	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0))
Kojto	107:4f6c30876dfa	2923
Kojto	107:4f6c30876dfa	2924	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
Kojto	107:4f6c30876dfa	2925	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
Kojto	107:4f6c30876dfa	2926	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
Kojto	107:4f6c30876dfa	2927	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
Kojto	107:4f6c30876dfa	2928	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Kojto	107:4f6c30876dfa	2929	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Kojto	107:4f6c30876dfa	2930	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
Kojto	107:4f6c30876dfa	2931	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
Kojto	107:4f6c30876dfa	2932	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
Kojto	107:4f6c30876dfa	2933	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
Kojto	107:4f6c30876dfa	2934	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
Kojto	107:4f6c30876dfa	2935	((__RANGE__) == RCC_MSIRANGE_11))
Kojto	107:4f6c30876dfa	2936
Kojto	107:4f6c30876dfa	2937	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Kojto	107:4f6c30876dfa	2938	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Kojto	107:4f6c30876dfa	2939	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
Kojto	107:4f6c30876dfa	2940	((__RANGE__) == RCC_MSIRANGE_7))
Kojto	107:4f6c30876dfa	2941
Kojto	107:4f6c30876dfa	2942	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto	107:4f6c30876dfa	2943
Kojto	107:4f6c30876dfa	2944	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
Kojto	107:4f6c30876dfa	2945	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	107:4f6c30876dfa	2946	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	107:4f6c30876dfa	2947	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	107:4f6c30876dfa	2948
Kojto	107:4f6c30876dfa	2949	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	107:4f6c30876dfa	2950	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	107:4f6c30876dfa	2951	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	107:4f6c30876dfa	2952	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	107:4f6c30876dfa	2953	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	107:4f6c30876dfa	2954
Kojto	107:4f6c30876dfa	2955	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	107:4f6c30876dfa	2956	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	107:4f6c30876dfa	2957	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	107:4f6c30876dfa	2958
Kojto	107:4f6c30876dfa	2959	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	107:4f6c30876dfa	2960	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	107:4f6c30876dfa	2961	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto	107:4f6c30876dfa	2962
Kojto	107:4f6c30876dfa	2963	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
Kojto	107:4f6c30876dfa	2964
Kojto	107:4f6c30876dfa	2965	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	107:4f6c30876dfa	2966	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Kojto	107:4f6c30876dfa	2967	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
Kojto	107:4f6c30876dfa	2968	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
Kojto	107:4f6c30876dfa	2969	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	107:4f6c30876dfa	2970	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
Kojto	107:4f6c30876dfa	2971	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Kojto	107:4f6c30876dfa	2972
Kojto	107:4f6c30876dfa	2973	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
Kojto	107:4f6c30876dfa	2974	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
Kojto	107:4f6c30876dfa	2975	((__DIV__) == RCC_MCODIV_16))
Kojto	107:4f6c30876dfa	2976
Kojto	107:4f6c30876dfa	2977	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
Kojto	107:4f6c30876dfa	2978	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
Kojto	107:4f6c30876dfa	2979	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
Kojto	107:4f6c30876dfa	2980	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
Kojto	107:4f6c30876dfa	2981
Kojto	107:4f6c30876dfa	2982	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
Kojto	107:4f6c30876dfa	2983	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
Kojto	107:4f6c30876dfa	2984	/**
Kojto	107:4f6c30876dfa	2985	* @}
Kojto	107:4f6c30876dfa	2986	*/
Kojto	107:4f6c30876dfa	2987
Kojto	107:4f6c30876dfa	2988	/* Include RCC HAL Extended module */
Kojto	107:4f6c30876dfa	2989	#include "stm32l4xx_hal_rcc_ex.h"
Kojto	107:4f6c30876dfa	2990
Kojto	107:4f6c30876dfa	2991	/* Exported functions --------------------------------------------------------*/
Kojto	107:4f6c30876dfa	2992	/** @addtogroup RCC_Exported_Functions
Kojto	107:4f6c30876dfa	2993	* @{
Kojto	107:4f6c30876dfa	2994	*/
Kojto	107:4f6c30876dfa	2995
Kojto	107:4f6c30876dfa	2996
Kojto	107:4f6c30876dfa	2997	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	107:4f6c30876dfa	2998	* @{
Kojto	107:4f6c30876dfa	2999	*/
Kojto	107:4f6c30876dfa	3000
Kojto	107:4f6c30876dfa	3001	/* Initialization and de-initialization functions ******************************/
Kojto	107:4f6c30876dfa	3002	void HAL_RCC_DeInit(void);
Kojto	107:4f6c30876dfa	3003	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	107:4f6c30876dfa	3004	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	107:4f6c30876dfa	3005
Kojto	107:4f6c30876dfa	3006	/**
Kojto	107:4f6c30876dfa	3007	* @}
Kojto	107:4f6c30876dfa	3008	*/
Kojto	107:4f6c30876dfa	3009
Kojto	107:4f6c30876dfa	3010	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	107:4f6c30876dfa	3011	* @{
Kojto	107:4f6c30876dfa	3012	*/
Kojto	107:4f6c30876dfa	3013
Kojto	107:4f6c30876dfa	3014	/* Peripheral Control functions ************************************************/
Kojto	107:4f6c30876dfa	3015	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	107:4f6c30876dfa	3016	void HAL_RCC_EnableCSS(void);
Kojto	107:4f6c30876dfa	3017	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	107:4f6c30876dfa	3018	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	107:4f6c30876dfa	3019	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	107:4f6c30876dfa	3020	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	107:4f6c30876dfa	3021	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	107:4f6c30876dfa	3022	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	107:4f6c30876dfa	3023	/* CSS NMI IRQ handler */
Kojto	107:4f6c30876dfa	3024	void HAL_RCC_NMI_IRQHandler(void);
Kojto	107:4f6c30876dfa	3025	/* User Callbacks in non blocking mode (IT mode) */
Kojto	107:4f6c30876dfa	3026	void HAL_RCC_CSSCallback(void);
Kojto	107:4f6c30876dfa	3027
Kojto	107:4f6c30876dfa	3028	/**
Kojto	107:4f6c30876dfa	3029	* @}
Kojto	107:4f6c30876dfa	3030	*/
Kojto	107:4f6c30876dfa	3031
Kojto	107:4f6c30876dfa	3032	/**
Kojto	107:4f6c30876dfa	3033	* @}
Kojto	107:4f6c30876dfa	3034	*/
Kojto	107:4f6c30876dfa	3035
Kojto	107:4f6c30876dfa	3036	/**
Kojto	107:4f6c30876dfa	3037	* @}
Kojto	107:4f6c30876dfa	3038	*/
Kojto	107:4f6c30876dfa	3039
Kojto	107:4f6c30876dfa	3040	/**
Kojto	107:4f6c30876dfa	3041	* @}
Kojto	107:4f6c30876dfa	3042	*/
Kojto	107:4f6c30876dfa	3043
Kojto	107:4f6c30876dfa	3044	#ifdef __cplusplus
Kojto	107:4f6c30876dfa	3045	}
Kojto	107:4f6c30876dfa	3046	#endif
Kojto	107:4f6c30876dfa	3047
Kojto	107:4f6c30876dfa	3048	#endif /* __STM32L4xx_HAL_RCC_H */
Kojto	107:4f6c30876dfa	3049
Kojto	107:4f6c30876dfa	3050	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_DISCO_L476VG/stm32l4xx_hal_rcc.h@107:4f6c30876dfa, 2015-09-16 (annotated)

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