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TARGET_SAMR21G18A/comp_nvmctrl.h@111:4336505e4b1c, 2015-12-15 (annotated)

Committer:
Kojto
Date:
Tue Dec 15 14:39:38 2015 +0000
Revision:
111:4336505e4b1c
Release 111 of the mbed library



Changes:

- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)

- Streams - add var argument (vprintf, vscanf)

- MAXWSNENV - BLE stack library additio

- LPC1768 - fix slave read

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for NVMCTRL
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_NVMCTRL_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_NVMCTRL_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR NVMCTRL */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_NVMCTRL Non-Volatile Memory Controller */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define NVMCTRL_U2207
Kojto 111:4336505e4b1c 54 #define REV_NVMCTRL 0x106
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint16_t CMD:7; /*!< bit: 0.. 6 Command */
Kojto 111:4336505e4b1c 61 uint16_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 62 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
Kojto 111:4336505e4b1c 63 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 64 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 65 } NVMCTRL_CTRLA_Type;
Kojto 111:4336505e4b1c 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 67
Kojto 111:4336505e4b1c 68 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
Kojto 111:4336505e4b1c 69 #define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
Kojto 111:4336505e4b1c 70
Kojto 111:4336505e4b1c 71 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
Kojto 111:4336505e4b1c 72 #define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 73 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
Kojto 111:4336505e4b1c 74 #define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
Kojto 111:4336505e4b1c 75 #define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
Kojto 111:4336505e4b1c 76 #define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
Kojto 111:4336505e4b1c 77 #define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
Kojto 111:4336505e4b1c 78 #define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
Kojto 111:4336505e4b1c 79 #define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */
Kojto 111:4336505e4b1c 80 #define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
Kojto 111:4336505e4b1c 81 #define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
Kojto 111:4336505e4b1c 82 #define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
Kojto 111:4336505e4b1c 83 #define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
Kojto 111:4336505e4b1c 84 #define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
Kojto 111:4336505e4b1c 85 #define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
Kojto 111:4336505e4b1c 86 #define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
Kojto 111:4336505e4b1c 87 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 88 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 89 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 90 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 91 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 92 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 93 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 94 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 95 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 96 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 97 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 98 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 99 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
Kojto 111:4336505e4b1c 100 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
Kojto 111:4336505e4b1c 101 #define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
Kojto 111:4336505e4b1c 102 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
Kojto 111:4336505e4b1c 103 #define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
Kojto 111:4336505e4b1c 104 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
Kojto 111:4336505e4b1c 105 #define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 106
Kojto 111:4336505e4b1c 107 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
Kojto 111:4336505e4b1c 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 109 typedef union {
Kojto 111:4336505e4b1c 110 struct {
Kojto 111:4336505e4b1c 111 uint32_t :1; /*!< bit: 0 Reserved */
Kojto 111:4336505e4b1c 112 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
Kojto 111:4336505e4b1c 113 uint32_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 114 uint32_t MANW:1; /*!< bit: 7 Manual Write */
Kojto 111:4336505e4b1c 115 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
Kojto 111:4336505e4b1c 116 uint32_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 117 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
Kojto 111:4336505e4b1c 118 uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
Kojto 111:4336505e4b1c 119 uint32_t :13; /*!< bit: 19..31 Reserved */
Kojto 111:4336505e4b1c 120 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 121 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 122 } NVMCTRL_CTRLB_Type;
Kojto 111:4336505e4b1c 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 124
Kojto 111:4336505e4b1c 125 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
Kojto 111:4336505e4b1c 126 #define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
Kojto 111:4336505e4b1c 127
Kojto 111:4336505e4b1c 128 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
Kojto 111:4336505e4b1c 129 #define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
Kojto 111:4336505e4b1c 130 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
Kojto 111:4336505e4b1c 131 #define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
Kojto 111:4336505e4b1c 132 #define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
Kojto 111:4336505e4b1c 133 #define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
Kojto 111:4336505e4b1c 134 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
Kojto 111:4336505e4b1c 135 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
Kojto 111:4336505e4b1c 136 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
Kojto 111:4336505e4b1c 137 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
Kojto 111:4336505e4b1c 138 #define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
Kojto 111:4336505e4b1c 139 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
Kojto 111:4336505e4b1c 140 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
Kojto 111:4336505e4b1c 141 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
Kojto 111:4336505e4b1c 142 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
Kojto 111:4336505e4b1c 143 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
Kojto 111:4336505e4b1c 144 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
Kojto 111:4336505e4b1c 145 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
Kojto 111:4336505e4b1c 146 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
Kojto 111:4336505e4b1c 147 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
Kojto 111:4336505e4b1c 148 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
Kojto 111:4336505e4b1c 149 #define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
Kojto 111:4336505e4b1c 150 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
Kojto 111:4336505e4b1c 151 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
Kojto 111:4336505e4b1c 152 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
Kojto 111:4336505e4b1c 153 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
Kojto 111:4336505e4b1c 154 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
Kojto 111:4336505e4b1c 155 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
Kojto 111:4336505e4b1c 156 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
Kojto 111:4336505e4b1c 157 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
Kojto 111:4336505e4b1c 158 #define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
Kojto 111:4336505e4b1c 159 #define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 160
Kojto 111:4336505e4b1c 161 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
Kojto 111:4336505e4b1c 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 163 typedef union {
Kojto 111:4336505e4b1c 164 struct {
Kojto 111:4336505e4b1c 165 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
Kojto 111:4336505e4b1c 166 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
Kojto 111:4336505e4b1c 167 uint32_t :13; /*!< bit: 19..31 Reserved */
Kojto 111:4336505e4b1c 168 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 169 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 170 } NVMCTRL_PARAM_Type;
Kojto 111:4336505e4b1c 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 172
Kojto 111:4336505e4b1c 173 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
Kojto 111:4336505e4b1c 174 #define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
Kojto 111:4336505e4b1c 175
Kojto 111:4336505e4b1c 176 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
Kojto 111:4336505e4b1c 177 #define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
Kojto 111:4336505e4b1c 178 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
Kojto 111:4336505e4b1c 179 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
Kojto 111:4336505e4b1c 180 #define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 181 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
Kojto 111:4336505e4b1c 182 #define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
Kojto 111:4336505e4b1c 183 #define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
Kojto 111:4336505e4b1c 184 #define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
Kojto 111:4336505e4b1c 185 #define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */
Kojto 111:4336505e4b1c 186 #define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */
Kojto 111:4336505e4b1c 187 #define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */
Kojto 111:4336505e4b1c 188 #define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */
Kojto 111:4336505e4b1c 189 #define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */
Kojto 111:4336505e4b1c 190 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 191 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 192 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 193 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 194 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 195 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 196 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 197 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
Kojto 111:4336505e4b1c 198 #define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
Kojto 111:4336505e4b1c 199
Kojto 111:4336505e4b1c 200 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 202 typedef union {
Kojto 111:4336505e4b1c 203 struct {
Kojto 111:4336505e4b1c 204 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
Kojto 111:4336505e4b1c 205 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
Kojto 111:4336505e4b1c 206 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 207 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 208 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 209 } NVMCTRL_INTENCLR_Type;
Kojto 111:4336505e4b1c 210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 211
Kojto 111:4336505e4b1c 212 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 213 #define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 214
Kojto 111:4336505e4b1c 215 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
Kojto 111:4336505e4b1c 216 #define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
Kojto 111:4336505e4b1c 217 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
Kojto 111:4336505e4b1c 218 #define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
Kojto 111:4336505e4b1c 219 #define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 220
Kojto 111:4336505e4b1c 221 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 223 typedef union {
Kojto 111:4336505e4b1c 224 struct {
Kojto 111:4336505e4b1c 225 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
Kojto 111:4336505e4b1c 226 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
Kojto 111:4336505e4b1c 227 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 228 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 229 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 230 } NVMCTRL_INTENSET_Type;
Kojto 111:4336505e4b1c 231 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 232
Kojto 111:4336505e4b1c 233 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 234 #define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 235
Kojto 111:4336505e4b1c 236 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
Kojto 111:4336505e4b1c 237 #define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos)
Kojto 111:4336505e4b1c 238 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
Kojto 111:4336505e4b1c 239 #define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
Kojto 111:4336505e4b1c 240 #define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 241
Kojto 111:4336505e4b1c 242 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 244 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 245 struct {
Kojto 111:4336505e4b1c 246 __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
Kojto 111:4336505e4b1c 247 __I uint8_t ERROR:1; /*!< bit: 1 Error */
Kojto 111:4336505e4b1c 248 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 249 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 250 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 251 } NVMCTRL_INTFLAG_Type;
Kojto 111:4336505e4b1c 252 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 253
Kojto 111:4336505e4b1c 254 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 255 #define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 256
Kojto 111:4336505e4b1c 257 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
Kojto 111:4336505e4b1c 258 #define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
Kojto 111:4336505e4b1c 259 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
Kojto 111:4336505e4b1c 260 #define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
Kojto 111:4336505e4b1c 261 #define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 262
Kojto 111:4336505e4b1c 263 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
Kojto 111:4336505e4b1c 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 265 typedef union {
Kojto 111:4336505e4b1c 266 struct {
Kojto 111:4336505e4b1c 267 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
Kojto 111:4336505e4b1c 268 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
Kojto 111:4336505e4b1c 269 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
Kojto 111:4336505e4b1c 270 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
Kojto 111:4336505e4b1c 271 uint16_t NVME:1; /*!< bit: 4 NVM Error */
Kojto 111:4336505e4b1c 272 uint16_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 273 uint16_t SB:1; /*!< bit: 8 Security Bit Status */
Kojto 111:4336505e4b1c 274 uint16_t :7; /*!< bit: 9..15 Reserved */
Kojto 111:4336505e4b1c 275 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 276 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 277 } NVMCTRL_STATUS_Type;
Kojto 111:4336505e4b1c 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 279
Kojto 111:4336505e4b1c 280 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
Kojto 111:4336505e4b1c 281 #define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */
Kojto 111:4336505e4b1c 282
Kojto 111:4336505e4b1c 283 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
Kojto 111:4336505e4b1c 284 #define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos)
Kojto 111:4336505e4b1c 285 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
Kojto 111:4336505e4b1c 286 #define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
Kojto 111:4336505e4b1c 287 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
Kojto 111:4336505e4b1c 288 #define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
Kojto 111:4336505e4b1c 289 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
Kojto 111:4336505e4b1c 290 #define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
Kojto 111:4336505e4b1c 291 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
Kojto 111:4336505e4b1c 292 #define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos)
Kojto 111:4336505e4b1c 293 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
Kojto 111:4336505e4b1c 294 #define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos)
Kojto 111:4336505e4b1c 295 #define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */
Kojto 111:4336505e4b1c 296
Kojto 111:4336505e4b1c 297 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
Kojto 111:4336505e4b1c 298 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 299 typedef union {
Kojto 111:4336505e4b1c 300 struct {
Kojto 111:4336505e4b1c 301 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
Kojto 111:4336505e4b1c 302 uint32_t :10; /*!< bit: 22..31 Reserved */
Kojto 111:4336505e4b1c 303 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 304 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 305 } NVMCTRL_ADDR_Type;
Kojto 111:4336505e4b1c 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 307
Kojto 111:4336505e4b1c 308 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
Kojto 111:4336505e4b1c 309 #define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
Kojto 111:4336505e4b1c 310
Kojto 111:4336505e4b1c 311 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
Kojto 111:4336505e4b1c 312 #define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
Kojto 111:4336505e4b1c 313 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
Kojto 111:4336505e4b1c 314 #define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
Kojto 111:4336505e4b1c 315
Kojto 111:4336505e4b1c 316 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
Kojto 111:4336505e4b1c 317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 318 typedef union {
Kojto 111:4336505e4b1c 319 struct {
Kojto 111:4336505e4b1c 320 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
Kojto 111:4336505e4b1c 321 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 322 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 323 } NVMCTRL_LOCK_Type;
Kojto 111:4336505e4b1c 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 325
Kojto 111:4336505e4b1c 326 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
Kojto 111:4336505e4b1c 327
Kojto 111:4336505e4b1c 328 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
Kojto 111:4336505e4b1c 329 #define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
Kojto 111:4336505e4b1c 330 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
Kojto 111:4336505e4b1c 331 #define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
Kojto 111:4336505e4b1c 332
Kojto 111:4336505e4b1c 333 /** \brief NVMCTRL APB hardware registers */
Kojto 111:4336505e4b1c 334 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 335 typedef struct {
Kojto 111:4336505e4b1c 336 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
Kojto 111:4336505e4b1c 337 RoReg8 Reserved1[0x2];
Kojto 111:4336505e4b1c 338 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
Kojto 111:4336505e4b1c 339 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
Kojto 111:4336505e4b1c 340 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 341 RoReg8 Reserved2[0x3];
Kojto 111:4336505e4b1c 342 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
Kojto 111:4336505e4b1c 343 RoReg8 Reserved3[0x3];
Kojto 111:4336505e4b1c 344 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 345 RoReg8 Reserved4[0x3];
Kojto 111:4336505e4b1c 346 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
Kojto 111:4336505e4b1c 347 RoReg8 Reserved5[0x2];
Kojto 111:4336505e4b1c 348 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
Kojto 111:4336505e4b1c 349 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
Kojto 111:4336505e4b1c 350 } Nvmctrl;
Kojto 111:4336505e4b1c 351 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 352 #define SECTION_NVMCTRL_CAL
Kojto 111:4336505e4b1c 353 #define SECTION_NVMCTRL_LOCKBIT
Kojto 111:4336505e4b1c 354 #define SECTION_NVMCTRL_OTP1
Kojto 111:4336505e4b1c 355 #define SECTION_NVMCTRL_OTP2
Kojto 111:4336505e4b1c 356 #define SECTION_NVMCTRL_OTP4
Kojto 111:4336505e4b1c 357 #define SECTION_NVMCTRL_TEMP_LOG
Kojto 111:4336505e4b1c 358 #define SECTION_NVMCTRL_USER
Kojto 111:4336505e4b1c 359
Kojto 111:4336505e4b1c 360 /*@}*/
Kojto 111:4336505e4b1c 361
Kojto 111:4336505e4b1c 362 /* ************************************************************************** */
Kojto 111:4336505e4b1c 363 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
Kojto 111:4336505e4b1c 364 /* ************************************************************************** */
Kojto 111:4336505e4b1c 365 /** \addtogroup fuses_api Peripheral Software API */
Kojto 111:4336505e4b1c 366 /*@{*/
Kojto 111:4336505e4b1c 367
Kojto 111:4336505e4b1c 368
Kojto 111:4336505e4b1c 369 #define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 370 #define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
Kojto 111:4336505e4b1c 371 #define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
Kojto 111:4336505e4b1c 372 #define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
Kojto 111:4336505e4b1c 373
Kojto 111:4336505e4b1c 374 #define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
Kojto 111:4336505e4b1c 375 #define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
Kojto 111:4336505e4b1c 376 #define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
Kojto 111:4336505e4b1c 377 #define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
Kojto 111:4336505e4b1c 378
Kojto 111:4336505e4b1c 379 #define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 380 #define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
Kojto 111:4336505e4b1c 381 #define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
Kojto 111:4336505e4b1c 382 #define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
Kojto 111:4336505e4b1c 383
Kojto 111:4336505e4b1c 384 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 385 #define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
Kojto 111:4336505e4b1c 386 #define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
Kojto 111:4336505e4b1c 387 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
Kojto 111:4336505e4b1c 388
Kojto 111:4336505e4b1c 389 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 390 #define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
Kojto 111:4336505e4b1c 391 #define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
Kojto 111:4336505e4b1c 392 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
Kojto 111:4336505e4b1c 393
Kojto 111:4336505e4b1c 394 #define FUSES_BOD33_EN_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 395 #define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
Kojto 111:4336505e4b1c 396 #define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos)
Kojto 111:4336505e4b1c 397
Kojto 111:4336505e4b1c 398 #define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
Kojto 111:4336505e4b1c 399 #define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
Kojto 111:4336505e4b1c 400 #define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos)
Kojto 111:4336505e4b1c 401
Kojto 111:4336505e4b1c 402 #define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 403 #define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
Kojto 111:4336505e4b1c 404 #define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
Kojto 111:4336505e4b1c 405 #define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
Kojto 111:4336505e4b1c 406
Kojto 111:4336505e4b1c 407 #define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
Kojto 111:4336505e4b1c 408 #define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
Kojto 111:4336505e4b1c 409 #define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
Kojto 111:4336505e4b1c 410 #define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
Kojto 111:4336505e4b1c 411
Kojto 111:4336505e4b1c 412 #define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
Kojto 111:4336505e4b1c 413 #define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
Kojto 111:4336505e4b1c 414 #define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
Kojto 111:4336505e4b1c 415 #define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
Kojto 111:4336505e4b1c 416
Kojto 111:4336505e4b1c 417 #define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
Kojto 111:4336505e4b1c 418 #define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
Kojto 111:4336505e4b1c 419 #define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
Kojto 111:4336505e4b1c 420 #define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
Kojto 111:4336505e4b1c 421
Kojto 111:4336505e4b1c 422 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
Kojto 111:4336505e4b1c 423 #define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
Kojto 111:4336505e4b1c 424 #define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
Kojto 111:4336505e4b1c 425 #define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
Kojto 111:4336505e4b1c 426
Kojto 111:4336505e4b1c 427 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
Kojto 111:4336505e4b1c 428 #define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
Kojto 111:4336505e4b1c 429 #define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
Kojto 111:4336505e4b1c 430 #define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
Kojto 111:4336505e4b1c 431
Kojto 111:4336505e4b1c 432 #define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 433 #define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
Kojto 111:4336505e4b1c 434 #define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
Kojto 111:4336505e4b1c 435 #define FUSES_OSC32K_CAL(value) (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
Kojto 111:4336505e4b1c 436
Kojto 111:4336505e4b1c 437 #define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
Kojto 111:4336505e4b1c 438 #define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
Kojto 111:4336505e4b1c 439 #define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
Kojto 111:4336505e4b1c 440 #define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
Kojto 111:4336505e4b1c 441
Kojto 111:4336505e4b1c 442 #define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
Kojto 111:4336505e4b1c 443 #define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
Kojto 111:4336505e4b1c 444 #define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
Kojto 111:4336505e4b1c 445 #define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
Kojto 111:4336505e4b1c 446
Kojto 111:4336505e4b1c 447 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
Kojto 111:4336505e4b1c 448 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
Kojto 111:4336505e4b1c 449 #define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
Kojto 111:4336505e4b1c 450 #define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
Kojto 111:4336505e4b1c 451
Kojto 111:4336505e4b1c 452 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
Kojto 111:4336505e4b1c 453 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
Kojto 111:4336505e4b1c 454 #define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
Kojto 111:4336505e4b1c 455 #define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
Kojto 111:4336505e4b1c 456
Kojto 111:4336505e4b1c 457 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 458 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
Kojto 111:4336505e4b1c 459 #define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
Kojto 111:4336505e4b1c 460 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
Kojto 111:4336505e4b1c 461
Kojto 111:4336505e4b1c 462 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 463 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
Kojto 111:4336505e4b1c 464 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
Kojto 111:4336505e4b1c 465 #define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
Kojto 111:4336505e4b1c 466
Kojto 111:4336505e4b1c 467 #define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
Kojto 111:4336505e4b1c 468 #define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
Kojto 111:4336505e4b1c 469 #define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
Kojto 111:4336505e4b1c 470 #define NVMCTRL_FUSES_NVMP(value) (NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))
Kojto 111:4336505e4b1c 471
Kojto 111:4336505e4b1c 472 #define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
Kojto 111:4336505e4b1c 473 #define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
Kojto 111:4336505e4b1c 474 #define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
Kojto 111:4336505e4b1c 475 #define NVMCTRL_FUSES_NVM_LOCK(value) (NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))
Kojto 111:4336505e4b1c 476
Kojto 111:4336505e4b1c 477 #define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
Kojto 111:4336505e4b1c 478 #define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
Kojto 111:4336505e4b1c 479 #define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
Kojto 111:4336505e4b1c 480 #define NVMCTRL_FUSES_PSZ(value) (NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))
Kojto 111:4336505e4b1c 481
Kojto 111:4336505e4b1c 482 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
Kojto 111:4336505e4b1c 483 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
Kojto 111:4336505e4b1c 484 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
Kojto 111:4336505e4b1c 485 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
Kojto 111:4336505e4b1c 486
Kojto 111:4336505e4b1c 487 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 488 #define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
Kojto 111:4336505e4b1c 489 #define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
Kojto 111:4336505e4b1c 490 #define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
Kojto 111:4336505e4b1c 491
Kojto 111:4336505e4b1c 492 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 493 #define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
Kojto 111:4336505e4b1c 494 #define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
Kojto 111:4336505e4b1c 495 #define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
Kojto 111:4336505e4b1c 496
Kojto 111:4336505e4b1c 497 #define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
Kojto 111:4336505e4b1c 498 #define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
Kojto 111:4336505e4b1c 499 #define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
Kojto 111:4336505e4b1c 500 #define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
Kojto 111:4336505e4b1c 501
Kojto 111:4336505e4b1c 502 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 503 #define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
Kojto 111:4336505e4b1c 504 #define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos)
Kojto 111:4336505e4b1c 505
Kojto 111:4336505e4b1c 506 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 507 #define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
Kojto 111:4336505e4b1c 508 #define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos)
Kojto 111:4336505e4b1c 509
Kojto 111:4336505e4b1c 510 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
Kojto 111:4336505e4b1c 511 #define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
Kojto 111:4336505e4b1c 512 #define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
Kojto 111:4336505e4b1c 513 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
Kojto 111:4336505e4b1c 514
Kojto 111:4336505e4b1c 515 #define WDT_FUSES_PER_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 516 #define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
Kojto 111:4336505e4b1c 517 #define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
Kojto 111:4336505e4b1c 518 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
Kojto 111:4336505e4b1c 519
Kojto 111:4336505e4b1c 520 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
Kojto 111:4336505e4b1c 521 #define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
Kojto 111:4336505e4b1c 522 #define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos)
Kojto 111:4336505e4b1c 523
Kojto 111:4336505e4b1c 524 #define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
Kojto 111:4336505e4b1c 525 #define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
Kojto 111:4336505e4b1c 526 #define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos)
Kojto 111:4336505e4b1c 527
Kojto 111:4336505e4b1c 528 #define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
Kojto 111:4336505e4b1c 529 #define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
Kojto 111:4336505e4b1c 530 #define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
Kojto 111:4336505e4b1c 531 #define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
Kojto 111:4336505e4b1c 532
Kojto 111:4336505e4b1c 533 /*@}*/
Kojto 111:4336505e4b1c 534
Kojto 111:4336505e4b1c 535 #endif /* _SAMR21_NVMCTRL_COMPONENT_ */