Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMD21G18A/ins_tc5.h@111:4336505e4b1c, 2015-12-15 (annotated)

Committer:
Kojto
Date:
Tue Dec 15 14:39:38 2015 +0000
Revision:
111:4336505e4b1c
Release 111 of the mbed library



Changes:

- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)

- Streams - add var argument (vprintf, vscanf)

- MAXWSNENV - BLE stack library additio

- LPC1768 - fix slave read

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Instance description for TC5
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_TC5_INSTANCE_
Kojto 111:4336505e4b1c 48 #define _SAMD21_TC5_INSTANCE_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========== Register definition for TC5 peripheral ========== */
Kojto 111:4336505e4b1c 51 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 52 #define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */
Kojto 111:4336505e4b1c 53 #define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */
Kojto 111:4336505e4b1c 54 #define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */
Kojto 111:4336505e4b1c 55 #define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */
Kojto 111:4336505e4b1c 56 #define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */
Kojto 111:4336505e4b1c 57 #define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */
Kojto 111:4336505e4b1c 58 #define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */
Kojto 111:4336505e4b1c 59 #define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 60 #define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
Kojto 111:4336505e4b1c 61 #define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 62 #define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */
Kojto 111:4336505e4b1c 63 #define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
Kojto 111:4336505e4b1c 64 #define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
Kojto 111:4336505e4b1c 65 #define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
Kojto 111:4336505e4b1c 66 #define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
Kojto 111:4336505e4b1c 67 #define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
Kojto 111:4336505e4b1c 68 #define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
Kojto 111:4336505e4b1c 69 #define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
Kojto 111:4336505e4b1c 70 #define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
Kojto 111:4336505e4b1c 71 #define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
Kojto 111:4336505e4b1c 72 #define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
Kojto 111:4336505e4b1c 73 #else
Kojto 111:4336505e4b1c 74 #define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
Kojto 111:4336505e4b1c 75 #define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
Kojto 111:4336505e4b1c 76 #define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
Kojto 111:4336505e4b1c 77 #define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
Kojto 111:4336505e4b1c 78 #define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
Kojto 111:4336505e4b1c 79 #define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
Kojto 111:4336505e4b1c 80 #define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
Kojto 111:4336505e4b1c 81 #define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 82 #define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
Kojto 111:4336505e4b1c 83 #define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 84 #define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
Kojto 111:4336505e4b1c 85 #define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
Kojto 111:4336505e4b1c 86 #define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
Kojto 111:4336505e4b1c 87 #define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
Kojto 111:4336505e4b1c 88 #define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
Kojto 111:4336505e4b1c 89 #define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
Kojto 111:4336505e4b1c 90 #define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
Kojto 111:4336505e4b1c 91 #define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
Kojto 111:4336505e4b1c 92 #define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
Kojto 111:4336505e4b1c 93 #define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
Kojto 111:4336505e4b1c 94 #define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
Kojto 111:4336505e4b1c 95 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 96
Kojto 111:4336505e4b1c 97 /* ========== Instance parameters for TC5 peripheral ========== */
Kojto 111:4336505e4b1c 98 #define TC5_CC8_NUM 2 // Number of 8-bit Counters
Kojto 111:4336505e4b1c 99 #define TC5_CC16_NUM 2 // Number of 16-bit Counters
Kojto 111:4336505e4b1c 100 #define TC5_CC32_NUM 2 // Number of 32-bit Counters
Kojto 111:4336505e4b1c 101 #define TC5_DITHERING_EXT 0 // Dithering feature implemented
Kojto 111:4336505e4b1c 102 #define TC5_DMAC_ID_MC_0 31
Kojto 111:4336505e4b1c 103 #define TC5_DMAC_ID_MC_1 32
Kojto 111:4336505e4b1c 104 #define TC5_DMAC_ID_MC_LSB 31
Kojto 111:4336505e4b1c 105 #define TC5_DMAC_ID_MC_MSB 32
Kojto 111:4336505e4b1c 106 #define TC5_DMAC_ID_MC_SIZE 2
Kojto 111:4336505e4b1c 107 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
Kojto 111:4336505e4b1c 108 #define TC5_GCLK_ID 28 // Index of Generic Clock
Kojto 111:4336505e4b1c 109 #define TC5_MASTER 0
Kojto 111:4336505e4b1c 110 #define TC5_OW_NUM 2 // Number of Output Waveforms
Kojto 111:4336505e4b1c 111 #define TC5_PERIOD_EXT 0 // Period feature implemented
Kojto 111:4336505e4b1c 112 #define TC5_SHADOW_EXT 0 // Shadow feature implemented
Kojto 111:4336505e4b1c 113
Kojto 111:4336505e4b1c 114 #endif /* _SAMD21_TC5_INSTANCE_ */