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TARGET_NUCLEO_F070RB/stm32_hal_legacy.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:: Kojto
Date:: Fri Oct 02 07:35:07 2015 +0200
Revision:: 108:34e6b704fe68

Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	108:34e6b704fe68	1	/**
Kojto	108:34e6b704fe68	2	******************************************************************************
Kojto	108:34e6b704fe68	3	* @file stm32_hal_legacy.h
Kojto	108:34e6b704fe68	4	* @author MCD Application Team
Kojto	108:34e6b704fe68	5	* @version V1.3.0
Kojto	108:34e6b704fe68	6	* @date 26-June-2015
Kojto	108:34e6b704fe68	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto	108:34e6b704fe68	8	* macros and functions maintained for legacy purpose.
Kojto	108:34e6b704fe68	9	******************************************************************************
Kojto	108:34e6b704fe68	10	* @attention
Kojto	108:34e6b704fe68	11	*
Kojto	108:34e6b704fe68	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	108:34e6b704fe68	13	*
Kojto	108:34e6b704fe68	14	* Redistribution and use in source and binary forms, with or without modification,
Kojto	108:34e6b704fe68	15	* are permitted provided that the following conditions are met:
Kojto	108:34e6b704fe68	16	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	108:34e6b704fe68	17	* this list of conditions and the following disclaimer.
Kojto	108:34e6b704fe68	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	108:34e6b704fe68	19	* this list of conditions and the following disclaimer in the documentation
Kojto	108:34e6b704fe68	20	* and/or other materials provided with the distribution.
Kojto	108:34e6b704fe68	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	108:34e6b704fe68	22	* may be used to endorse or promote products derived from this software
Kojto	108:34e6b704fe68	23	* without specific prior written permission.
Kojto	108:34e6b704fe68	24	*
Kojto	108:34e6b704fe68	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	108:34e6b704fe68	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	108:34e6b704fe68	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	108:34e6b704fe68	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	108:34e6b704fe68	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	108:34e6b704fe68	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	108:34e6b704fe68	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	108:34e6b704fe68	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	108:34e6b704fe68	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	108:34e6b704fe68	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	108:34e6b704fe68	35	*
Kojto	108:34e6b704fe68	36	******************************************************************************
Kojto	108:34e6b704fe68	37	*/
Kojto	108:34e6b704fe68	38
Kojto	108:34e6b704fe68	39	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	108:34e6b704fe68	40	#ifndef __STM32_HAL_LEGACY
Kojto	108:34e6b704fe68	41	#define __STM32_HAL_LEGACY
Kojto	108:34e6b704fe68	42
Kojto	108:34e6b704fe68	43	#ifdef __cplusplus
Kojto	108:34e6b704fe68	44	extern "C" {
Kojto	108:34e6b704fe68	45	#endif
Kojto	108:34e6b704fe68	46
Kojto	108:34e6b704fe68	47	/* Includes ------------------------------------------------------------------*/
Kojto	108:34e6b704fe68	48	/* Exported types ------------------------------------------------------------*/
Kojto	108:34e6b704fe68	49	/* Exported constants --------------------------------------------------------*/
Kojto	108:34e6b704fe68	50
Kojto	108:34e6b704fe68	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	52	* @{
Kojto	108:34e6b704fe68	53	*/
Kojto	108:34e6b704fe68	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto	108:34e6b704fe68	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto	108:34e6b704fe68	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto	108:34e6b704fe68	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto	108:34e6b704fe68	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto	108:34e6b704fe68	59
Kojto	108:34e6b704fe68	60	/**
Kojto	108:34e6b704fe68	61	* @}
Kojto	108:34e6b704fe68	62	*/
Kojto	108:34e6b704fe68	63
Kojto	108:34e6b704fe68	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	65	* @{
Kojto	108:34e6b704fe68	66	*/
Kojto	108:34e6b704fe68	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto	108:34e6b704fe68	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto	108:34e6b704fe68	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto	108:34e6b704fe68	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto	108:34e6b704fe68	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto	108:34e6b704fe68	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto	108:34e6b704fe68	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto	108:34e6b704fe68	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto	108:34e6b704fe68	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto	108:34e6b704fe68	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto	108:34e6b704fe68	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto	108:34e6b704fe68	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto	108:34e6b704fe68	79	#define AWD_EVENT ADC_AWD_EVENT
Kojto	108:34e6b704fe68	80	#define AWD1_EVENT ADC_AWD1_EVENT
Kojto	108:34e6b704fe68	81	#define AWD2_EVENT ADC_AWD2_EVENT
Kojto	108:34e6b704fe68	82	#define AWD3_EVENT ADC_AWD3_EVENT
Kojto	108:34e6b704fe68	83	#define OVR_EVENT ADC_OVR_EVENT
Kojto	108:34e6b704fe68	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto	108:34e6b704fe68	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto	108:34e6b704fe68	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto	108:34e6b704fe68	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto	108:34e6b704fe68	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto	108:34e6b704fe68	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto	108:34e6b704fe68	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
Kojto	108:34e6b704fe68	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
Kojto	108:34e6b704fe68	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
Kojto	108:34e6b704fe68	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
Kojto	108:34e6b704fe68	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
Kojto	108:34e6b704fe68	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto	108:34e6b704fe68	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto	108:34e6b704fe68	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto	108:34e6b704fe68	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto	108:34e6b704fe68	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto	108:34e6b704fe68	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto	108:34e6b704fe68	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto	108:34e6b704fe68	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto	108:34e6b704fe68	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto	108:34e6b704fe68	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto	108:34e6b704fe68	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto	108:34e6b704fe68	106	/**
Kojto	108:34e6b704fe68	107	* @}
Kojto	108:34e6b704fe68	108	*/
Kojto	108:34e6b704fe68	109
Kojto	108:34e6b704fe68	110	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	111	* @{
Kojto	108:34e6b704fe68	112	*/
Kojto	108:34e6b704fe68	113
Kojto	108:34e6b704fe68	114	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto	108:34e6b704fe68	115
Kojto	108:34e6b704fe68	116	/**
Kojto	108:34e6b704fe68	117	* @}
Kojto	108:34e6b704fe68	118	*/
Kojto	108:34e6b704fe68	119
Kojto	108:34e6b704fe68	120	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	121	* @{
Kojto	108:34e6b704fe68	122	*/
Kojto	108:34e6b704fe68	123
Kojto	108:34e6b704fe68	124	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto	108:34e6b704fe68	125	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto	108:34e6b704fe68	126	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto	108:34e6b704fe68	127	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto	108:34e6b704fe68	128
Kojto	108:34e6b704fe68	129	/**
Kojto	108:34e6b704fe68	130	* @}
Kojto	108:34e6b704fe68	131	*/
Kojto	108:34e6b704fe68	132
Kojto	108:34e6b704fe68	133	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	134	* @{
Kojto	108:34e6b704fe68	135	*/
Kojto	108:34e6b704fe68	136
Kojto	108:34e6b704fe68	137	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto	108:34e6b704fe68	138	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto	108:34e6b704fe68	139
Kojto	108:34e6b704fe68	140	/**
Kojto	108:34e6b704fe68	141	* @}
Kojto	108:34e6b704fe68	142	*/
Kojto	108:34e6b704fe68	143
Kojto	108:34e6b704fe68	144	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	145	* @{
Kojto	108:34e6b704fe68	146	*/
Kojto	108:34e6b704fe68	147
Kojto	108:34e6b704fe68	148	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto	108:34e6b704fe68	149	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto	108:34e6b704fe68	150	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto	108:34e6b704fe68	151	#define DAC_WAVE_NONE ((uint32_t)0x00000000)
Kojto	108:34e6b704fe68	152	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto	108:34e6b704fe68	153	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto	108:34e6b704fe68	154	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto	108:34e6b704fe68	155	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto	108:34e6b704fe68	156	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto	108:34e6b704fe68	157
Kojto	108:34e6b704fe68	158	/**
Kojto	108:34e6b704fe68	159	* @}
Kojto	108:34e6b704fe68	160	*/
Kojto	108:34e6b704fe68	161
Kojto	108:34e6b704fe68	162	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	163	* @{
Kojto	108:34e6b704fe68	164	*/
Kojto	108:34e6b704fe68	165	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
Kojto	108:34e6b704fe68	166	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
Kojto	108:34e6b704fe68	167	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
Kojto	108:34e6b704fe68	168	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
Kojto	108:34e6b704fe68	169	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
Kojto	108:34e6b704fe68	170	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto	108:34e6b704fe68	171	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
Kojto	108:34e6b704fe68	172	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
Kojto	108:34e6b704fe68	173	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
Kojto	108:34e6b704fe68	174	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
Kojto	108:34e6b704fe68	175	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto	108:34e6b704fe68	176	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
Kojto	108:34e6b704fe68	177	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
Kojto	108:34e6b704fe68	178	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
Kojto	108:34e6b704fe68	179	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
Kojto	108:34e6b704fe68	180
Kojto	108:34e6b704fe68	181	#define IS_HAL_REMAPDMA IS_DMA_REMAP
Kojto	108:34e6b704fe68	182	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
Kojto	108:34e6b704fe68	183	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
Kojto	108:34e6b704fe68	184
Kojto	108:34e6b704fe68	185
Kojto	108:34e6b704fe68	186
Kojto	108:34e6b704fe68	187	/**
Kojto	108:34e6b704fe68	188	* @}
Kojto	108:34e6b704fe68	189	*/
Kojto	108:34e6b704fe68	190
Kojto	108:34e6b704fe68	191	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	192	* @{
Kojto	108:34e6b704fe68	193	*/
Kojto	108:34e6b704fe68	194
Kojto	108:34e6b704fe68	195	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto	108:34e6b704fe68	196	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto	108:34e6b704fe68	197	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto	108:34e6b704fe68	198	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto	108:34e6b704fe68	199	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto	108:34e6b704fe68	200	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto	108:34e6b704fe68	201	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto	108:34e6b704fe68	202	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto	108:34e6b704fe68	203	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto	108:34e6b704fe68	204	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto	108:34e6b704fe68	205	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto	108:34e6b704fe68	206	#define OBEX_PCROP OPTIONBYTE_PCROP
Kojto	108:34e6b704fe68	207	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto	108:34e6b704fe68	208	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto	108:34e6b704fe68	209	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto	108:34e6b704fe68	210	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto	108:34e6b704fe68	211	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto	108:34e6b704fe68	212	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto	108:34e6b704fe68	213	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto	108:34e6b704fe68	214	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto	108:34e6b704fe68	215	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto	108:34e6b704fe68	216	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto	108:34e6b704fe68	217	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto	108:34e6b704fe68	218	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto	108:34e6b704fe68	219	#define PAGESIZE FLASH_PAGE_SIZE
Kojto	108:34e6b704fe68	220	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto	108:34e6b704fe68	221	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto	108:34e6b704fe68	222	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto	108:34e6b704fe68	223	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto	108:34e6b704fe68	224	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto	108:34e6b704fe68	225	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto	108:34e6b704fe68	226	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto	108:34e6b704fe68	227	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto	108:34e6b704fe68	228	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto	108:34e6b704fe68	229	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto	108:34e6b704fe68	230	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto	108:34e6b704fe68	231	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto	108:34e6b704fe68	232	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto	108:34e6b704fe68	233	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto	108:34e6b704fe68	234	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto	108:34e6b704fe68	235	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto	108:34e6b704fe68	236	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto	108:34e6b704fe68	237	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto	108:34e6b704fe68	238	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto	108:34e6b704fe68	239	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto	108:34e6b704fe68	240	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto	108:34e6b704fe68	241	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto	108:34e6b704fe68	242	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto	108:34e6b704fe68	243	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto	108:34e6b704fe68	244	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto	108:34e6b704fe68	245	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto	108:34e6b704fe68	246	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto	108:34e6b704fe68	247	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto	108:34e6b704fe68	248	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto	108:34e6b704fe68	249	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto	108:34e6b704fe68	250	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto	108:34e6b704fe68	251	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto	108:34e6b704fe68	252	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto	108:34e6b704fe68	253	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto	108:34e6b704fe68	254	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto	108:34e6b704fe68	255	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto	108:34e6b704fe68	256	#define OB_WDG_SW OB_IWDG_SW
Kojto	108:34e6b704fe68	257	#define OB_WDG_HW OB_IWDG_HW
Kojto	108:34e6b704fe68	258
Kojto	108:34e6b704fe68	259	/**
Kojto	108:34e6b704fe68	260	* @}
Kojto	108:34e6b704fe68	261	*/
Kojto	108:34e6b704fe68	262
Kojto	108:34e6b704fe68	263	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	264	* @{
Kojto	108:34e6b704fe68	265	*/
Kojto	108:34e6b704fe68	266
Kojto	108:34e6b704fe68	267	#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto	108:34e6b704fe68	268	#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto	108:34e6b704fe68	269	#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto	108:34e6b704fe68	270	#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto	108:34e6b704fe68	271	#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto	108:34e6b704fe68	272	#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto	108:34e6b704fe68	273	#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto	108:34e6b704fe68	274
Kojto	108:34e6b704fe68	275	/**
Kojto	108:34e6b704fe68	276	* @}
Kojto	108:34e6b704fe68	277	*/
Kojto	108:34e6b704fe68	278
Kojto	108:34e6b704fe68	279
Kojto	108:34e6b704fe68	280	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
Kojto	108:34e6b704fe68	281	* @{
Kojto	108:34e6b704fe68	282	*/
Kojto	108:34e6b704fe68	283	#if defined(STM32L4) \|\| defined(STM32F7)
Kojto	108:34e6b704fe68	284	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
Kojto	108:34e6b704fe68	285	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
Kojto	108:34e6b704fe68	286	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
Kojto	108:34e6b704fe68	287	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
Kojto	108:34e6b704fe68	288	#else
Kojto	108:34e6b704fe68	289	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
Kojto	108:34e6b704fe68	290	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
Kojto	108:34e6b704fe68	291	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
Kojto	108:34e6b704fe68	292	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
Kojto	108:34e6b704fe68	293	#endif
Kojto	108:34e6b704fe68	294	/**
Kojto	108:34e6b704fe68	295	* @}
Kojto	108:34e6b704fe68	296	*/
Kojto	108:34e6b704fe68	297
Kojto	108:34e6b704fe68	298	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	299	* @{
Kojto	108:34e6b704fe68	300	*/
Kojto	108:34e6b704fe68	301
Kojto	108:34e6b704fe68	302	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto	108:34e6b704fe68	303	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto	108:34e6b704fe68	304	/**
Kojto	108:34e6b704fe68	305	* @}
Kojto	108:34e6b704fe68	306	*/
Kojto	108:34e6b704fe68	307
Kojto	108:34e6b704fe68	308	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	309	* @{
Kojto	108:34e6b704fe68	310	*/
Kojto	108:34e6b704fe68	311	#define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto	108:34e6b704fe68	312	#define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto	108:34e6b704fe68	313
Kojto	108:34e6b704fe68	314	#if defined(STM32F4)
Kojto	108:34e6b704fe68	315	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
Kojto	108:34e6b704fe68	316	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
Kojto	108:34e6b704fe68	317	#endif
Kojto	108:34e6b704fe68	318
Kojto	108:34e6b704fe68	319	#if defined(STM32F7)
Kojto	108:34e6b704fe68	320	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto	108:34e6b704fe68	321	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto	108:34e6b704fe68	322	#endif
Kojto	108:34e6b704fe68	323
Kojto	108:34e6b704fe68	324	#if defined(STM32L4)
Kojto	108:34e6b704fe68	325	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto	108:34e6b704fe68	326	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto	108:34e6b704fe68	327	#endif
Kojto	108:34e6b704fe68	328
Kojto	108:34e6b704fe68	329	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
Kojto	108:34e6b704fe68	330	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
Kojto	108:34e6b704fe68	331	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
Kojto	108:34e6b704fe68	332
Kojto	108:34e6b704fe68	333	/**
Kojto	108:34e6b704fe68	334	* @}
Kojto	108:34e6b704fe68	335	*/
Kojto	108:34e6b704fe68	336
Kojto	108:34e6b704fe68	337	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	338	* @{
Kojto	108:34e6b704fe68	339	*/
Kojto	108:34e6b704fe68	340	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
Kojto	108:34e6b704fe68	341	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
Kojto	108:34e6b704fe68	342	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
Kojto	108:34e6b704fe68	343	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
Kojto	108:34e6b704fe68	344	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
Kojto	108:34e6b704fe68	345	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
Kojto	108:34e6b704fe68	346	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
Kojto	108:34e6b704fe68	347	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
Kojto	108:34e6b704fe68	348	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Kojto	108:34e6b704fe68	349	/**
Kojto	108:34e6b704fe68	350	* @}
Kojto	108:34e6b704fe68	351	*/
Kojto	108:34e6b704fe68	352
Kojto	108:34e6b704fe68	353	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	354	* @{
Kojto	108:34e6b704fe68	355	*/
Kojto	108:34e6b704fe68	356	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto	108:34e6b704fe68	357	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto	108:34e6b704fe68	358	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto	108:34e6b704fe68	359	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto	108:34e6b704fe68	360	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto	108:34e6b704fe68	361	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto	108:34e6b704fe68	362	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto	108:34e6b704fe68	363	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto	108:34e6b704fe68	364	/**
Kojto	108:34e6b704fe68	365	* @}
Kojto	108:34e6b704fe68	366	*/
Kojto	108:34e6b704fe68	367
Kojto	108:34e6b704fe68	368	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	369	* @{
Kojto	108:34e6b704fe68	370	*/
Kojto	108:34e6b704fe68	371	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto	108:34e6b704fe68	372	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto	108:34e6b704fe68	373
Kojto	108:34e6b704fe68	374	/**
Kojto	108:34e6b704fe68	375	* @}
Kojto	108:34e6b704fe68	376	*/
Kojto	108:34e6b704fe68	377
Kojto	108:34e6b704fe68	378	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	379	* @{
Kojto	108:34e6b704fe68	380	*/
Kojto	108:34e6b704fe68	381	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto	108:34e6b704fe68	382	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto	108:34e6b704fe68	383	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto	108:34e6b704fe68	384	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto	108:34e6b704fe68	385	/**
Kojto	108:34e6b704fe68	386	* @}
Kojto	108:34e6b704fe68	387	*/
Kojto	108:34e6b704fe68	388
Kojto	108:34e6b704fe68	389	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	390	* @{
Kojto	108:34e6b704fe68	391	*/
Kojto	108:34e6b704fe68	392
Kojto	108:34e6b704fe68	393	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto	108:34e6b704fe68	394	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto	108:34e6b704fe68	395	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto	108:34e6b704fe68	396	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto	108:34e6b704fe68	397
Kojto	108:34e6b704fe68	398	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto	108:34e6b704fe68	399	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto	108:34e6b704fe68	400	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto	108:34e6b704fe68	401
Kojto	108:34e6b704fe68	402	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS
Kojto	108:34e6b704fe68	403	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS
Kojto	108:34e6b704fe68	404	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS
Kojto	108:34e6b704fe68	405
Kojto	108:34e6b704fe68	406	/**
Kojto	108:34e6b704fe68	407	* @}
Kojto	108:34e6b704fe68	408	*/
Kojto	108:34e6b704fe68	409
Kojto	108:34e6b704fe68	410	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	411	* @{
Kojto	108:34e6b704fe68	412	*/
Kojto	108:34e6b704fe68	413	#define NAND_AddressTypedef NAND_AddressTypeDef
Kojto	108:34e6b704fe68	414
Kojto	108:34e6b704fe68	415	#define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto	108:34e6b704fe68	416	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto	108:34e6b704fe68	417	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto	108:34e6b704fe68	418	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto	108:34e6b704fe68	419	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto	108:34e6b704fe68	420	/**
Kojto	108:34e6b704fe68	421	* @}
Kojto	108:34e6b704fe68	422	*/
Kojto	108:34e6b704fe68	423
Kojto	108:34e6b704fe68	424	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	425	* @{
Kojto	108:34e6b704fe68	426	*/
Kojto	108:34e6b704fe68	427	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto	108:34e6b704fe68	428	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto	108:34e6b704fe68	429	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto	108:34e6b704fe68	430	#define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto	108:34e6b704fe68	431	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto	108:34e6b704fe68	432
Kojto	108:34e6b704fe68	433	#define __NOR_WRITE NOR_WRITE
Kojto	108:34e6b704fe68	434	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto	108:34e6b704fe68	435	/**
Kojto	108:34e6b704fe68	436	* @}
Kojto	108:34e6b704fe68	437	*/
Kojto	108:34e6b704fe68	438
Kojto	108:34e6b704fe68	439	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	440	* @{
Kojto	108:34e6b704fe68	441	*/
Kojto	108:34e6b704fe68	442
Kojto	108:34e6b704fe68	443	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto	108:34e6b704fe68	444	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	445	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto	108:34e6b704fe68	446	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto	108:34e6b704fe68	447
Kojto	108:34e6b704fe68	448	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto	108:34e6b704fe68	449	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	450	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto	108:34e6b704fe68	451	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto	108:34e6b704fe68	452
Kojto	108:34e6b704fe68	453	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto	108:34e6b704fe68	454	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	455
Kojto	108:34e6b704fe68	456	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto	108:34e6b704fe68	457	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	458
Kojto	108:34e6b704fe68	459	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto	108:34e6b704fe68	460	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	461
Kojto	108:34e6b704fe68	462	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	463
Kojto	108:34e6b704fe68	464	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto	108:34e6b704fe68	465	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto	108:34e6b704fe68	466	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto	108:34e6b704fe68	467
Kojto	108:34e6b704fe68	468	/**
Kojto	108:34e6b704fe68	469	* @}
Kojto	108:34e6b704fe68	470	*/
Kojto	108:34e6b704fe68	471
Kojto	108:34e6b704fe68	472	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	473	* @{
Kojto	108:34e6b704fe68	474	*/
Kojto	108:34e6b704fe68	475	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto	108:34e6b704fe68	476	/**
Kojto	108:34e6b704fe68	477	* @}
Kojto	108:34e6b704fe68	478	*/
Kojto	108:34e6b704fe68	479
Kojto	108:34e6b704fe68	480	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	481	* @{
Kojto	108:34e6b704fe68	482	*/
Kojto	108:34e6b704fe68	483
Kojto	108:34e6b704fe68	484	/* Compact Flash-ATA registers description */
Kojto	108:34e6b704fe68	485	#define CF_DATA ATA_DATA
Kojto	108:34e6b704fe68	486	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto	108:34e6b704fe68	487	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto	108:34e6b704fe68	488	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto	108:34e6b704fe68	489	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto	108:34e6b704fe68	490	#define CF_CARD_HEAD ATA_CARD_HEAD
Kojto	108:34e6b704fe68	491	#define CF_STATUS_CMD ATA_STATUS_CMD
Kojto	108:34e6b704fe68	492	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto	108:34e6b704fe68	493	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto	108:34e6b704fe68	494
Kojto	108:34e6b704fe68	495	/* Compact Flash-ATA commands */
Kojto	108:34e6b704fe68	496	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto	108:34e6b704fe68	497	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto	108:34e6b704fe68	498	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto	108:34e6b704fe68	499	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto	108:34e6b704fe68	500
Kojto	108:34e6b704fe68	501	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto	108:34e6b704fe68	502	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto	108:34e6b704fe68	503	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto	108:34e6b704fe68	504	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto	108:34e6b704fe68	505	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto	108:34e6b704fe68	506	/**
Kojto	108:34e6b704fe68	507	* @}
Kojto	108:34e6b704fe68	508	*/
Kojto	108:34e6b704fe68	509
Kojto	108:34e6b704fe68	510	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	511	* @{
Kojto	108:34e6b704fe68	512	*/
Kojto	108:34e6b704fe68	513
Kojto	108:34e6b704fe68	514	#define FORMAT_BIN RTC_FORMAT_BIN
Kojto	108:34e6b704fe68	515	#define FORMAT_BCD RTC_FORMAT_BCD
Kojto	108:34e6b704fe68	516
Kojto	108:34e6b704fe68	517	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto	108:34e6b704fe68	518	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto	108:34e6b704fe68	519	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto	108:34e6b704fe68	520	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	108:34e6b704fe68	521	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	108:34e6b704fe68	522
Kojto	108:34e6b704fe68	523	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	108:34e6b704fe68	524	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	108:34e6b704fe68	525	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto	108:34e6b704fe68	526	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto	108:34e6b704fe68	527	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	108:34e6b704fe68	528	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	108:34e6b704fe68	529	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto	108:34e6b704fe68	530	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto	108:34e6b704fe68	531
Kojto	108:34e6b704fe68	532	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Kojto	108:34e6b704fe68	533
Kojto	108:34e6b704fe68	534	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
Kojto	108:34e6b704fe68	535	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Kojto	108:34e6b704fe68	536
Kojto	108:34e6b704fe68	537	/**
Kojto	108:34e6b704fe68	538	* @}
Kojto	108:34e6b704fe68	539	*/
Kojto	108:34e6b704fe68	540
Kojto	108:34e6b704fe68	541
Kojto	108:34e6b704fe68	542	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	543	* @{
Kojto	108:34e6b704fe68	544	*/
Kojto	108:34e6b704fe68	545	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto	108:34e6b704fe68	546	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto	108:34e6b704fe68	547
Kojto	108:34e6b704fe68	548	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto	108:34e6b704fe68	549	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto	108:34e6b704fe68	550	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto	108:34e6b704fe68	551	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto	108:34e6b704fe68	552
Kojto	108:34e6b704fe68	553	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto	108:34e6b704fe68	554	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto	108:34e6b704fe68	555
Kojto	108:34e6b704fe68	556	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto	108:34e6b704fe68	557	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto	108:34e6b704fe68	558	/**
Kojto	108:34e6b704fe68	559	* @}
Kojto	108:34e6b704fe68	560	*/
Kojto	108:34e6b704fe68	561
Kojto	108:34e6b704fe68	562
Kojto	108:34e6b704fe68	563	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	564	* @{
Kojto	108:34e6b704fe68	565	*/
Kojto	108:34e6b704fe68	566	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto	108:34e6b704fe68	567	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto	108:34e6b704fe68	568	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto	108:34e6b704fe68	569	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto	108:34e6b704fe68	570	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto	108:34e6b704fe68	571	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto	108:34e6b704fe68	572	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto	108:34e6b704fe68	573	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto	108:34e6b704fe68	574	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
Kojto	108:34e6b704fe68	575	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
Kojto	108:34e6b704fe68	576	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto	108:34e6b704fe68	577	/**
Kojto	108:34e6b704fe68	578	* @}
Kojto	108:34e6b704fe68	579	*/
Kojto	108:34e6b704fe68	580
Kojto	108:34e6b704fe68	581	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	582	* @{
Kojto	108:34e6b704fe68	583	*/
Kojto	108:34e6b704fe68	584	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto	108:34e6b704fe68	585	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto	108:34e6b704fe68	586
Kojto	108:34e6b704fe68	587	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto	108:34e6b704fe68	588	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto	108:34e6b704fe68	589
Kojto	108:34e6b704fe68	590	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto	108:34e6b704fe68	591	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto	108:34e6b704fe68	592
Kojto	108:34e6b704fe68	593	/**
Kojto	108:34e6b704fe68	594	* @}
Kojto	108:34e6b704fe68	595	*/
Kojto	108:34e6b704fe68	596
Kojto	108:34e6b704fe68	597	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	598	* @{
Kojto	108:34e6b704fe68	599	*/
Kojto	108:34e6b704fe68	600	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto	108:34e6b704fe68	601	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto	108:34e6b704fe68	602
Kojto	108:34e6b704fe68	603	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto	108:34e6b704fe68	604	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto	108:34e6b704fe68	605	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto	108:34e6b704fe68	606	#define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto	108:34e6b704fe68	607	#define TIM_DMABase_SR TIM_DMABASE_SR
Kojto	108:34e6b704fe68	608	#define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto	108:34e6b704fe68	609	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto	108:34e6b704fe68	610	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto	108:34e6b704fe68	611	#define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto	108:34e6b704fe68	612	#define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto	108:34e6b704fe68	613	#define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto	108:34e6b704fe68	614	#define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto	108:34e6b704fe68	615	#define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto	108:34e6b704fe68	616	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto	108:34e6b704fe68	617	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto	108:34e6b704fe68	618	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto	108:34e6b704fe68	619	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto	108:34e6b704fe68	620	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto	108:34e6b704fe68	621	#define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto	108:34e6b704fe68	622	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto	108:34e6b704fe68	623	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto	108:34e6b704fe68	624	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto	108:34e6b704fe68	625	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto	108:34e6b704fe68	626	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto	108:34e6b704fe68	627	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto	108:34e6b704fe68	628	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto	108:34e6b704fe68	629	#define TIM_DMABase_OR TIM_DMABASE_OR
Kojto	108:34e6b704fe68	630
Kojto	108:34e6b704fe68	631	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto	108:34e6b704fe68	632	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto	108:34e6b704fe68	633	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto	108:34e6b704fe68	634	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto	108:34e6b704fe68	635	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto	108:34e6b704fe68	636	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto	108:34e6b704fe68	637	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto	108:34e6b704fe68	638	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto	108:34e6b704fe68	639	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto	108:34e6b704fe68	640
Kojto	108:34e6b704fe68	641	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto	108:34e6b704fe68	642	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto	108:34e6b704fe68	643	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto	108:34e6b704fe68	644	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto	108:34e6b704fe68	645	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto	108:34e6b704fe68	646	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto	108:34e6b704fe68	647	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto	108:34e6b704fe68	648	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto	108:34e6b704fe68	649	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto	108:34e6b704fe68	650	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto	108:34e6b704fe68	651	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto	108:34e6b704fe68	652	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto	108:34e6b704fe68	653	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto	108:34e6b704fe68	654	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto	108:34e6b704fe68	655	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto	108:34e6b704fe68	656	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto	108:34e6b704fe68	657	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto	108:34e6b704fe68	658	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto	108:34e6b704fe68	659
Kojto	108:34e6b704fe68	660	/**
Kojto	108:34e6b704fe68	661	* @}
Kojto	108:34e6b704fe68	662	*/
Kojto	108:34e6b704fe68	663
Kojto	108:34e6b704fe68	664	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	665	* @{
Kojto	108:34e6b704fe68	666	*/
Kojto	108:34e6b704fe68	667	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto	108:34e6b704fe68	668	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto	108:34e6b704fe68	669	/**
Kojto	108:34e6b704fe68	670	* @}
Kojto	108:34e6b704fe68	671	*/
Kojto	108:34e6b704fe68	672
Kojto	108:34e6b704fe68	673	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	674	* @{
Kojto	108:34e6b704fe68	675	*/
Kojto	108:34e6b704fe68	676	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto	108:34e6b704fe68	677	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto	108:34e6b704fe68	678	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto	108:34e6b704fe68	679	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto	108:34e6b704fe68	680
Kojto	108:34e6b704fe68	681	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto	108:34e6b704fe68	682	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto	108:34e6b704fe68	683
Kojto	108:34e6b704fe68	684	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto	108:34e6b704fe68	685	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto	108:34e6b704fe68	686	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto	108:34e6b704fe68	687	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto	108:34e6b704fe68	688
Kojto	108:34e6b704fe68	689	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto	108:34e6b704fe68	690	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto	108:34e6b704fe68	691	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto	108:34e6b704fe68	692	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto	108:34e6b704fe68	693
Kojto	108:34e6b704fe68	694	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto	108:34e6b704fe68	695	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto	108:34e6b704fe68	696
Kojto	108:34e6b704fe68	697	/**
Kojto	108:34e6b704fe68	698	* @}
Kojto	108:34e6b704fe68	699	*/
Kojto	108:34e6b704fe68	700
Kojto	108:34e6b704fe68	701
Kojto	108:34e6b704fe68	702	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	703	* @{
Kojto	108:34e6b704fe68	704	*/
Kojto	108:34e6b704fe68	705
Kojto	108:34e6b704fe68	706	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto	108:34e6b704fe68	707	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto	108:34e6b704fe68	708
Kojto	108:34e6b704fe68	709	#define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto	108:34e6b704fe68	710	#define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto	108:34e6b704fe68	711	/**
Kojto	108:34e6b704fe68	712	* @}
Kojto	108:34e6b704fe68	713	*/
Kojto	108:34e6b704fe68	714
Kojto	108:34e6b704fe68	715	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	716	* @{
Kojto	108:34e6b704fe68	717	*/
Kojto	108:34e6b704fe68	718	#define CFR_BASE WWDG_CFR_BASE
Kojto	108:34e6b704fe68	719
Kojto	108:34e6b704fe68	720	/**
Kojto	108:34e6b704fe68	721	* @}
Kojto	108:34e6b704fe68	722	*/
Kojto	108:34e6b704fe68	723
Kojto	108:34e6b704fe68	724	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	725	* @{
Kojto	108:34e6b704fe68	726	*/
Kojto	108:34e6b704fe68	727	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto	108:34e6b704fe68	728	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto	108:34e6b704fe68	729	#define CAN_IT_RQCP0 CAN_IT_TME
Kojto	108:34e6b704fe68	730	#define CAN_IT_RQCP1 CAN_IT_TME
Kojto	108:34e6b704fe68	731	#define CAN_IT_RQCP2 CAN_IT_TME
Kojto	108:34e6b704fe68	732	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto	108:34e6b704fe68	733	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto	108:34e6b704fe68	734	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
Kojto	108:34e6b704fe68	735	#define CAN_TXSTATUS_OK ((uint8_t)0x01)
Kojto	108:34e6b704fe68	736	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
Kojto	108:34e6b704fe68	737
Kojto	108:34e6b704fe68	738	/**
Kojto	108:34e6b704fe68	739	* @}
Kojto	108:34e6b704fe68	740	*/
Kojto	108:34e6b704fe68	741
Kojto	108:34e6b704fe68	742	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	743	* @{
Kojto	108:34e6b704fe68	744	*/
Kojto	108:34e6b704fe68	745
Kojto	108:34e6b704fe68	746	#define VLAN_TAG ETH_VLAN_TAG
Kojto	108:34e6b704fe68	747	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto	108:34e6b704fe68	748	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto	108:34e6b704fe68	749	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto	108:34e6b704fe68	750	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto	108:34e6b704fe68	751	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto	108:34e6b704fe68	752	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto	108:34e6b704fe68	753	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto	108:34e6b704fe68	754
Kojto	108:34e6b704fe68	755	#define ETH_MMCCR ((uint32_t)0x00000100)
Kojto	108:34e6b704fe68	756	#define ETH_MMCRIR ((uint32_t)0x00000104)
Kojto	108:34e6b704fe68	757	#define ETH_MMCTIR ((uint32_t)0x00000108)
Kojto	108:34e6b704fe68	758	#define ETH_MMCRIMR ((uint32_t)0x0000010C)
Kojto	108:34e6b704fe68	759	#define ETH_MMCTIMR ((uint32_t)0x00000110)
Kojto	108:34e6b704fe68	760	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
Kojto	108:34e6b704fe68	761	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
Kojto	108:34e6b704fe68	762	#define ETH_MMCTGFCR ((uint32_t)0x00000168)
Kojto	108:34e6b704fe68	763	#define ETH_MMCRFCECR ((uint32_t)0x00000194)
Kojto	108:34e6b704fe68	764	#define ETH_MMCRFAECR ((uint32_t)0x00000198)
Kojto	108:34e6b704fe68	765	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
Kojto	108:34e6b704fe68	766
Kojto	108:34e6b704fe68	767	/**
Kojto	108:34e6b704fe68	768	* @}
Kojto	108:34e6b704fe68	769	*/
Kojto	108:34e6b704fe68	770
Kojto	108:34e6b704fe68	771	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto	108:34e6b704fe68	772	* @{
Kojto	108:34e6b704fe68	773	*/
Kojto	108:34e6b704fe68	774
Kojto	108:34e6b704fe68	775	/**
Kojto	108:34e6b704fe68	776	* @}
Kojto	108:34e6b704fe68	777	*/
Kojto	108:34e6b704fe68	778
Kojto	108:34e6b704fe68	779	/* Exported functions --------------------------------------------------------*/
Kojto	108:34e6b704fe68	780
Kojto	108:34e6b704fe68	781	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	782	* @{
Kojto	108:34e6b704fe68	783	*/
Kojto	108:34e6b704fe68	784	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto	108:34e6b704fe68	785	/**
Kojto	108:34e6b704fe68	786	* @}
Kojto	108:34e6b704fe68	787	*/
Kojto	108:34e6b704fe68	788
Kojto	108:34e6b704fe68	789	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	790	* @{
Kojto	108:34e6b704fe68	791	*/
Kojto	108:34e6b704fe68	792
Kojto	108:34e6b704fe68	793	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto	108:34e6b704fe68	794	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto	108:34e6b704fe68	795	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto	108:34e6b704fe68	796	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto	108:34e6b704fe68	797
Kojto	108:34e6b704fe68	798	/HASH Algorithm Selection/
Kojto	108:34e6b704fe68	799
Kojto	108:34e6b704fe68	800	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto	108:34e6b704fe68	801	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto	108:34e6b704fe68	802	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto	108:34e6b704fe68	803	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto	108:34e6b704fe68	804
Kojto	108:34e6b704fe68	805	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto	108:34e6b704fe68	806	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto	108:34e6b704fe68	807
Kojto	108:34e6b704fe68	808	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto	108:34e6b704fe68	809	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto	108:34e6b704fe68	810	/**
Kojto	108:34e6b704fe68	811	* @}
Kojto	108:34e6b704fe68	812	*/
Kojto	108:34e6b704fe68	813
Kojto	108:34e6b704fe68	814	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	815	* @{
Kojto	108:34e6b704fe68	816	*/
Kojto	108:34e6b704fe68	817	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto	108:34e6b704fe68	818	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto	108:34e6b704fe68	819	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto	108:34e6b704fe68	820	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto	108:34e6b704fe68	821	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto	108:34e6b704fe68	822	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto	108:34e6b704fe68	823	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto	108:34e6b704fe68	824	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto	108:34e6b704fe68	825	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto	108:34e6b704fe68	826	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto	108:34e6b704fe68	827	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto	108:34e6b704fe68	828	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto	108:34e6b704fe68	829	/**
Kojto	108:34e6b704fe68	830	* @}
Kojto	108:34e6b704fe68	831	*/
Kojto	108:34e6b704fe68	832
Kojto	108:34e6b704fe68	833	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	834	* @{
Kojto	108:34e6b704fe68	835	*/
Kojto	108:34e6b704fe68	836	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto	108:34e6b704fe68	837	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto	108:34e6b704fe68	838	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto	108:34e6b704fe68	839	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto	108:34e6b704fe68	840	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto	108:34e6b704fe68	841	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto	108:34e6b704fe68	842	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto	108:34e6b704fe68	843
Kojto	108:34e6b704fe68	844	/**
Kojto	108:34e6b704fe68	845	* @}
Kojto	108:34e6b704fe68	846	*/
Kojto	108:34e6b704fe68	847
Kojto	108:34e6b704fe68	848	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	849	* @{
Kojto	108:34e6b704fe68	850	*/
Kojto	108:34e6b704fe68	851	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto	108:34e6b704fe68	852	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto	108:34e6b704fe68	853
Kojto	108:34e6b704fe68	854	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto	108:34e6b704fe68	855	/**
Kojto	108:34e6b704fe68	856	* @}
Kojto	108:34e6b704fe68	857	*/
Kojto	108:34e6b704fe68	858
Kojto	108:34e6b704fe68	859	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto	108:34e6b704fe68	860	* @{
Kojto	108:34e6b704fe68	861	*/
Kojto	108:34e6b704fe68	862	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto	108:34e6b704fe68	863	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto	108:34e6b704fe68	864	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto	108:34e6b704fe68	865	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto	108:34e6b704fe68	866	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto	108:34e6b704fe68	867	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto	108:34e6b704fe68	868	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto	108:34e6b704fe68	869	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto	108:34e6b704fe68	870	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto	108:34e6b704fe68	871	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto	108:34e6b704fe68	872	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto	108:34e6b704fe68	873	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto	108:34e6b704fe68	874	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto	108:34e6b704fe68	875	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto	108:34e6b704fe68	876	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto	108:34e6b704fe68	877	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto	108:34e6b704fe68	878
Kojto	108:34e6b704fe68	879	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto	108:34e6b704fe68	880	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto	108:34e6b704fe68	881	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto	108:34e6b704fe68	882	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto	108:34e6b704fe68	883	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto	108:34e6b704fe68	884	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto	108:34e6b704fe68	885	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto	108:34e6b704fe68	886
Kojto	108:34e6b704fe68	887	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto	108:34e6b704fe68	888	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto	108:34e6b704fe68	889
Kojto	108:34e6b704fe68	890	#define DBP_BitNumber DBP_BIT_NUMBER
Kojto	108:34e6b704fe68	891	#define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto	108:34e6b704fe68	892	#define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto	108:34e6b704fe68	893	#define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto	108:34e6b704fe68	894	#define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto	108:34e6b704fe68	895	#define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto	108:34e6b704fe68	896	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto	108:34e6b704fe68	897	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto	108:34e6b704fe68	898	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto	108:34e6b704fe68	899	#define BRE_BitNumber BRE_BIT_NUMBER
Kojto	108:34e6b704fe68	900
Kojto	108:34e6b704fe68	901	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto	108:34e6b704fe68	902
Kojto	108:34e6b704fe68	903	/**
Kojto	108:34e6b704fe68	904	* @}
Kojto	108:34e6b704fe68	905	*/
Kojto	108:34e6b704fe68	906
Kojto	108:34e6b704fe68	907	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	908	* @{
Kojto	108:34e6b704fe68	909	*/
Kojto	108:34e6b704fe68	910	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto	108:34e6b704fe68	911	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto	108:34e6b704fe68	912	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto	108:34e6b704fe68	913	/**
Kojto	108:34e6b704fe68	914	* @}
Kojto	108:34e6b704fe68	915	*/
Kojto	108:34e6b704fe68	916
Kojto	108:34e6b704fe68	917	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	918	* @{
Kojto	108:34e6b704fe68	919	*/
Kojto	108:34e6b704fe68	920	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto	108:34e6b704fe68	921	/**
Kojto	108:34e6b704fe68	922	* @}
Kojto	108:34e6b704fe68	923	*/
Kojto	108:34e6b704fe68	924
Kojto	108:34e6b704fe68	925	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	926	* @{
Kojto	108:34e6b704fe68	927	*/
Kojto	108:34e6b704fe68	928	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto	108:34e6b704fe68	929	#define HAL_TIM_DMAError TIM_DMAError
Kojto	108:34e6b704fe68	930	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto	108:34e6b704fe68	931	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto	108:34e6b704fe68	932	/**
Kojto	108:34e6b704fe68	933	* @}
Kojto	108:34e6b704fe68	934	*/
Kojto	108:34e6b704fe68	935
Kojto	108:34e6b704fe68	936	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	937	* @{
Kojto	108:34e6b704fe68	938	*/
Kojto	108:34e6b704fe68	939	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto	108:34e6b704fe68	940	/**
Kojto	108:34e6b704fe68	941	* @}
Kojto	108:34e6b704fe68	942	*/
Kojto	108:34e6b704fe68	943
Kojto	108:34e6b704fe68	944	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	945	* @{
Kojto	108:34e6b704fe68	946	*/
Kojto	108:34e6b704fe68	947	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
Kojto	108:34e6b704fe68	948	/**
Kojto	108:34e6b704fe68	949	* @}
Kojto	108:34e6b704fe68	950	*/
Kojto	108:34e6b704fe68	951
Kojto	108:34e6b704fe68	952
Kojto	108:34e6b704fe68	953	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto	108:34e6b704fe68	954	* @{
Kojto	108:34e6b704fe68	955	*/
Kojto	108:34e6b704fe68	956
Kojto	108:34e6b704fe68	957	/**
Kojto	108:34e6b704fe68	958	* @}
Kojto	108:34e6b704fe68	959	*/
Kojto	108:34e6b704fe68	960
Kojto	108:34e6b704fe68	961	/* Exported macros ------------------------------------------------------------*/
Kojto	108:34e6b704fe68	962
Kojto	108:34e6b704fe68	963	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	964	* @{
Kojto	108:34e6b704fe68	965	*/
Kojto	108:34e6b704fe68	966	#define AES_IT_CC CRYP_IT_CC
Kojto	108:34e6b704fe68	967	#define AES_IT_ERR CRYP_IT_ERR
Kojto	108:34e6b704fe68	968	#define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto	108:34e6b704fe68	969	/**
Kojto	108:34e6b704fe68	970	* @}
Kojto	108:34e6b704fe68	971	*/
Kojto	108:34e6b704fe68	972
Kojto	108:34e6b704fe68	973	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	974	* @{
Kojto	108:34e6b704fe68	975	*/
Kojto	108:34e6b704fe68	976	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto	108:34e6b704fe68	977	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto	108:34e6b704fe68	978	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto	108:34e6b704fe68	979	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto	108:34e6b704fe68	980	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto	108:34e6b704fe68	981	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto	108:34e6b704fe68	982	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto	108:34e6b704fe68	983	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto	108:34e6b704fe68	984	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto	108:34e6b704fe68	985	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto	108:34e6b704fe68	986	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto	108:34e6b704fe68	987	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto	108:34e6b704fe68	988	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto	108:34e6b704fe68	989
Kojto	108:34e6b704fe68	990	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto	108:34e6b704fe68	991	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto	108:34e6b704fe68	992	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto	108:34e6b704fe68	993	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto	108:34e6b704fe68	994	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto	108:34e6b704fe68	995
Kojto	108:34e6b704fe68	996	/**
Kojto	108:34e6b704fe68	997	* @}
Kojto	108:34e6b704fe68	998	*/
Kojto	108:34e6b704fe68	999
Kojto	108:34e6b704fe68	1000
Kojto	108:34e6b704fe68	1001	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1002	* @{
Kojto	108:34e6b704fe68	1003	*/
Kojto	108:34e6b704fe68	1004	#define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto	108:34e6b704fe68	1005	#define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto	108:34e6b704fe68	1006	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto	108:34e6b704fe68	1007	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto	108:34e6b704fe68	1008	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto	108:34e6b704fe68	1009	#define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto	108:34e6b704fe68	1010	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto	108:34e6b704fe68	1011	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto	108:34e6b704fe68	1012	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto	108:34e6b704fe68	1013	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto	108:34e6b704fe68	1014	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto	108:34e6b704fe68	1015	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto	108:34e6b704fe68	1016	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto	108:34e6b704fe68	1017
Kojto	108:34e6b704fe68	1018	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto	108:34e6b704fe68	1019	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto	108:34e6b704fe68	1020	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto	108:34e6b704fe68	1021	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto	108:34e6b704fe68	1022	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto	108:34e6b704fe68	1023	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto	108:34e6b704fe68	1024	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto	108:34e6b704fe68	1025	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto	108:34e6b704fe68	1026	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto	108:34e6b704fe68	1027	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto	108:34e6b704fe68	1028	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto	108:34e6b704fe68	1029	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto	108:34e6b704fe68	1030	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto	108:34e6b704fe68	1031	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto	108:34e6b704fe68	1032	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto	108:34e6b704fe68	1033	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto	108:34e6b704fe68	1034	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto	108:34e6b704fe68	1035	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto	108:34e6b704fe68	1036	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto	108:34e6b704fe68	1037	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto	108:34e6b704fe68	1038
Kojto	108:34e6b704fe68	1039	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto	108:34e6b704fe68	1040	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto	108:34e6b704fe68	1041	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto	108:34e6b704fe68	1042	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto	108:34e6b704fe68	1043	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto	108:34e6b704fe68	1044	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto	108:34e6b704fe68	1045	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto	108:34e6b704fe68	1046	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto	108:34e6b704fe68	1047	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto	108:34e6b704fe68	1048	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto	108:34e6b704fe68	1049
Kojto	108:34e6b704fe68	1050	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto	108:34e6b704fe68	1051	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto	108:34e6b704fe68	1052	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto	108:34e6b704fe68	1053	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto	108:34e6b704fe68	1054	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto	108:34e6b704fe68	1055	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto	108:34e6b704fe68	1056	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto	108:34e6b704fe68	1057	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto	108:34e6b704fe68	1058
Kojto	108:34e6b704fe68	1059	#define __HAL_ADC_SQR1 ADC_SQR1
Kojto	108:34e6b704fe68	1060	#define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto	108:34e6b704fe68	1061	#define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto	108:34e6b704fe68	1062	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto	108:34e6b704fe68	1063	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto	108:34e6b704fe68	1064	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto	108:34e6b704fe68	1065	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto	108:34e6b704fe68	1066	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto	108:34e6b704fe68	1067	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto	108:34e6b704fe68	1068	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto	108:34e6b704fe68	1069	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto	108:34e6b704fe68	1070	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto	108:34e6b704fe68	1071	#define __HAL_ADC_JSQR ADC_JSQR
Kojto	108:34e6b704fe68	1072
Kojto	108:34e6b704fe68	1073	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto	108:34e6b704fe68	1074	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto	108:34e6b704fe68	1075	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto	108:34e6b704fe68	1076	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto	108:34e6b704fe68	1077	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto	108:34e6b704fe68	1078	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto	108:34e6b704fe68	1079	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto	108:34e6b704fe68	1080	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto	108:34e6b704fe68	1081
Kojto	108:34e6b704fe68	1082	/**
Kojto	108:34e6b704fe68	1083	* @}
Kojto	108:34e6b704fe68	1084	*/
Kojto	108:34e6b704fe68	1085
Kojto	108:34e6b704fe68	1086	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1087	* @{
Kojto	108:34e6b704fe68	1088	*/
Kojto	108:34e6b704fe68	1089	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto	108:34e6b704fe68	1090	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto	108:34e6b704fe68	1091	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto	108:34e6b704fe68	1092	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto	108:34e6b704fe68	1093
Kojto	108:34e6b704fe68	1094	/**
Kojto	108:34e6b704fe68	1095	* @}
Kojto	108:34e6b704fe68	1096	*/
Kojto	108:34e6b704fe68	1097
Kojto	108:34e6b704fe68	1098	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1099	* @{
Kojto	108:34e6b704fe68	1100	*/
Kojto	108:34e6b704fe68	1101	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto	108:34e6b704fe68	1102	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto	108:34e6b704fe68	1103	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto	108:34e6b704fe68	1104	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto	108:34e6b704fe68	1105	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto	108:34e6b704fe68	1106	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto	108:34e6b704fe68	1107	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto	108:34e6b704fe68	1108	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto	108:34e6b704fe68	1109	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto	108:34e6b704fe68	1110	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto	108:34e6b704fe68	1111	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto	108:34e6b704fe68	1112	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto	108:34e6b704fe68	1113	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto	108:34e6b704fe68	1114	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto	108:34e6b704fe68	1115	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto	108:34e6b704fe68	1116	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto	108:34e6b704fe68	1117
Kojto	108:34e6b704fe68	1118	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto	108:34e6b704fe68	1119	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto	108:34e6b704fe68	1120	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto	108:34e6b704fe68	1121	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto	108:34e6b704fe68	1122	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto	108:34e6b704fe68	1123	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto	108:34e6b704fe68	1124	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto	108:34e6b704fe68	1125	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto	108:34e6b704fe68	1126	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto	108:34e6b704fe68	1127	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto	108:34e6b704fe68	1128	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto	108:34e6b704fe68	1129	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto	108:34e6b704fe68	1130	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto	108:34e6b704fe68	1131	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto	108:34e6b704fe68	1132
Kojto	108:34e6b704fe68	1133
Kojto	108:34e6b704fe68	1134	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto	108:34e6b704fe68	1135	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto	108:34e6b704fe68	1136	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto	108:34e6b704fe68	1137	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto	108:34e6b704fe68	1138	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto	108:34e6b704fe68	1139	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto	108:34e6b704fe68	1140	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto	108:34e6b704fe68	1141	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto	108:34e6b704fe68	1142	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto	108:34e6b704fe68	1143	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto	108:34e6b704fe68	1144	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto	108:34e6b704fe68	1145	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto	108:34e6b704fe68	1146	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto	108:34e6b704fe68	1147	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto	108:34e6b704fe68	1148	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto	108:34e6b704fe68	1149	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto	108:34e6b704fe68	1150	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto	108:34e6b704fe68	1151	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto	108:34e6b704fe68	1152	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto	108:34e6b704fe68	1153	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto	108:34e6b704fe68	1154	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto	108:34e6b704fe68	1155	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto	108:34e6b704fe68	1156	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto	108:34e6b704fe68	1157	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto	108:34e6b704fe68	1158
Kojto	108:34e6b704fe68	1159	/**
Kojto	108:34e6b704fe68	1160	* @}
Kojto	108:34e6b704fe68	1161	*/
Kojto	108:34e6b704fe68	1162
Kojto	108:34e6b704fe68	1163	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1164	* @{
Kojto	108:34e6b704fe68	1165	*/
Kojto	108:34e6b704fe68	1166
Kojto	108:34e6b704fe68	1167	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	108:34e6b704fe68	1168	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto	108:34e6b704fe68	1169	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	108:34e6b704fe68	1170	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto	108:34e6b704fe68	1171	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	108:34e6b704fe68	1172	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto	108:34e6b704fe68	1173	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	108:34e6b704fe68	1174	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto	108:34e6b704fe68	1175	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto	108:34e6b704fe68	1176	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto	108:34e6b704fe68	1177	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto	108:34e6b704fe68	1178	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto	108:34e6b704fe68	1179	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto	108:34e6b704fe68	1180	__HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto	108:34e6b704fe68	1181	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto	108:34e6b704fe68	1182	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto	108:34e6b704fe68	1183	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto	108:34e6b704fe68	1184
Kojto	108:34e6b704fe68	1185	/**
Kojto	108:34e6b704fe68	1186	* @}
Kojto	108:34e6b704fe68	1187	*/
Kojto	108:34e6b704fe68	1188
Kojto	108:34e6b704fe68	1189	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1190	* @{
Kojto	108:34e6b704fe68	1191	*/
Kojto	108:34e6b704fe68	1192
Kojto	108:34e6b704fe68	1193	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
Kojto	108:34e6b704fe68	1194	((WAVE) == DAC_WAVE_NOISE)\|\| \
Kojto	108:34e6b704fe68	1195	((WAVE) == DAC_WAVE_TRIANGLE))
Kojto	108:34e6b704fe68	1196
Kojto	108:34e6b704fe68	1197	/**
Kojto	108:34e6b704fe68	1198	* @}
Kojto	108:34e6b704fe68	1199	*/
Kojto	108:34e6b704fe68	1200
Kojto	108:34e6b704fe68	1201	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1202	* @{
Kojto	108:34e6b704fe68	1203	*/
Kojto	108:34e6b704fe68	1204
Kojto	108:34e6b704fe68	1205	#define IS_WRPAREA IS_OB_WRPAREA
Kojto	108:34e6b704fe68	1206	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto	108:34e6b704fe68	1207	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto	108:34e6b704fe68	1208	#define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto	108:34e6b704fe68	1209	#define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto	108:34e6b704fe68	1210	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Kojto	108:34e6b704fe68	1211
Kojto	108:34e6b704fe68	1212	/**
Kojto	108:34e6b704fe68	1213	* @}
Kojto	108:34e6b704fe68	1214	*/
Kojto	108:34e6b704fe68	1215
Kojto	108:34e6b704fe68	1216	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1217	* @{
Kojto	108:34e6b704fe68	1218	*/
Kojto	108:34e6b704fe68	1219
Kojto	108:34e6b704fe68	1220	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto	108:34e6b704fe68	1221	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto	108:34e6b704fe68	1222	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto	108:34e6b704fe68	1223	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto	108:34e6b704fe68	1224	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto	108:34e6b704fe68	1225	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto	108:34e6b704fe68	1226	#define __HAL_I2C_SPEED I2C_SPEED
Kojto	108:34e6b704fe68	1227	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto	108:34e6b704fe68	1228	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto	108:34e6b704fe68	1229	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto	108:34e6b704fe68	1230	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto	108:34e6b704fe68	1231	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto	108:34e6b704fe68	1232	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto	108:34e6b704fe68	1233	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto	108:34e6b704fe68	1234	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto	108:34e6b704fe68	1235	/**
Kojto	108:34e6b704fe68	1236	* @}
Kojto	108:34e6b704fe68	1237	*/
Kojto	108:34e6b704fe68	1238
Kojto	108:34e6b704fe68	1239	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1240	* @{
Kojto	108:34e6b704fe68	1241	*/
Kojto	108:34e6b704fe68	1242
Kojto	108:34e6b704fe68	1243	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto	108:34e6b704fe68	1244	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto	108:34e6b704fe68	1245
Kojto	108:34e6b704fe68	1246	/**
Kojto	108:34e6b704fe68	1247	* @}
Kojto	108:34e6b704fe68	1248	*/
Kojto	108:34e6b704fe68	1249
Kojto	108:34e6b704fe68	1250	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1251	* @{
Kojto	108:34e6b704fe68	1252	*/
Kojto	108:34e6b704fe68	1253
Kojto	108:34e6b704fe68	1254	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto	108:34e6b704fe68	1255	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto	108:34e6b704fe68	1256
Kojto	108:34e6b704fe68	1257	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	1258	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto	108:34e6b704fe68	1259	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	1260	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto	108:34e6b704fe68	1261
Kojto	108:34e6b704fe68	1262	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto	108:34e6b704fe68	1263
Kojto	108:34e6b704fe68	1264
Kojto	108:34e6b704fe68	1265	/**
Kojto	108:34e6b704fe68	1266	* @}
Kojto	108:34e6b704fe68	1267	*/
Kojto	108:34e6b704fe68	1268
Kojto	108:34e6b704fe68	1269
Kojto	108:34e6b704fe68	1270	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1271	* @{
Kojto	108:34e6b704fe68	1272	*/
Kojto	108:34e6b704fe68	1273	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto	108:34e6b704fe68	1274	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto	108:34e6b704fe68	1275	/**
Kojto	108:34e6b704fe68	1276	* @}
Kojto	108:34e6b704fe68	1277	*/
Kojto	108:34e6b704fe68	1278
Kojto	108:34e6b704fe68	1279
Kojto	108:34e6b704fe68	1280	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1281	* @{
Kojto	108:34e6b704fe68	1282	*/
Kojto	108:34e6b704fe68	1283
Kojto	108:34e6b704fe68	1284	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto	108:34e6b704fe68	1285	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto	108:34e6b704fe68	1286	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto	108:34e6b704fe68	1287
Kojto	108:34e6b704fe68	1288	/**
Kojto	108:34e6b704fe68	1289	* @}
Kojto	108:34e6b704fe68	1290	*/
Kojto	108:34e6b704fe68	1291
Kojto	108:34e6b704fe68	1292
Kojto	108:34e6b704fe68	1293	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1294	* @{
Kojto	108:34e6b704fe68	1295	*/
Kojto	108:34e6b704fe68	1296	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto	108:34e6b704fe68	1297	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto	108:34e6b704fe68	1298	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto	108:34e6b704fe68	1299	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto	108:34e6b704fe68	1300	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto	108:34e6b704fe68	1301	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto	108:34e6b704fe68	1302	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto	108:34e6b704fe68	1303	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto	108:34e6b704fe68	1304	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto	108:34e6b704fe68	1305	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto	108:34e6b704fe68	1306	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto	108:34e6b704fe68	1307	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto	108:34e6b704fe68	1308	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto	108:34e6b704fe68	1309
Kojto	108:34e6b704fe68	1310	/**
Kojto	108:34e6b704fe68	1311	* @}
Kojto	108:34e6b704fe68	1312	*/
Kojto	108:34e6b704fe68	1313
Kojto	108:34e6b704fe68	1314
Kojto	108:34e6b704fe68	1315	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	1316	* @{
Kojto	108:34e6b704fe68	1317	*/
Kojto	108:34e6b704fe68	1318	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto	108:34e6b704fe68	1319	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto	108:34e6b704fe68	1320	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1321	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1322	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto	108:34e6b704fe68	1323	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	108:34e6b704fe68	1324	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto	108:34e6b704fe68	1325	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto	108:34e6b704fe68	1326	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto	108:34e6b704fe68	1327	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto	108:34e6b704fe68	1328	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto	108:34e6b704fe68	1329	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto	108:34e6b704fe68	1330	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto	108:34e6b704fe68	1331	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto	108:34e6b704fe68	1332	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto	108:34e6b704fe68	1333	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto	108:34e6b704fe68	1334	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
Kojto	108:34e6b704fe68	1335	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto	108:34e6b704fe68	1336	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto	108:34e6b704fe68	1337	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1338	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1339	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto	108:34e6b704fe68	1340	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	108:34e6b704fe68	1341	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1342	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	108:34e6b704fe68	1343	#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
Kojto	108:34e6b704fe68	1344	#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
Kojto	108:34e6b704fe68	1345	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto	108:34e6b704fe68	1346	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto	108:34e6b704fe68	1347	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto	108:34e6b704fe68	1348	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto	108:34e6b704fe68	1349	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1350	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	1351	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto	108:34e6b704fe68	1352	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto	108:34e6b704fe68	1353
Kojto	108:34e6b704fe68	1354	#if defined (STM32F4)
Kojto	108:34e6b704fe68	1355	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto	108:34e6b704fe68	1356	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto	108:34e6b704fe68	1357	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto	108:34e6b704fe68	1358	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto	108:34e6b704fe68	1359	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto	108:34e6b704fe68	1360	#else
Kojto	108:34e6b704fe68	1361	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto	108:34e6b704fe68	1362	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto	108:34e6b704fe68	1363	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto	108:34e6b704fe68	1364	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto	108:34e6b704fe68	1365	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto	108:34e6b704fe68	1366	#endif /* STM32F4 */
Kojto	108:34e6b704fe68	1367	/**
Kojto	108:34e6b704fe68	1368	* @}
Kojto	108:34e6b704fe68	1369	*/
Kojto	108:34e6b704fe68	1370
Kojto	108:34e6b704fe68	1371
Kojto	108:34e6b704fe68	1372	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto	108:34e6b704fe68	1373	* @{
Kojto	108:34e6b704fe68	1374	*/
Kojto	108:34e6b704fe68	1375
Kojto	108:34e6b704fe68	1376	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto	108:34e6b704fe68	1377	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto	108:34e6b704fe68	1378
Kojto	108:34e6b704fe68	1379	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto	108:34e6b704fe68	1380	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto	108:34e6b704fe68	1381
Kojto	108:34e6b704fe68	1382	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto	108:34e6b704fe68	1383	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto	108:34e6b704fe68	1384	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1385	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1386	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto	108:34e6b704fe68	1387	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto	108:34e6b704fe68	1388	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto	108:34e6b704fe68	1389	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto	108:34e6b704fe68	1390	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto	108:34e6b704fe68	1391	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto	108:34e6b704fe68	1392	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1393	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1394	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto	108:34e6b704fe68	1395	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto	108:34e6b704fe68	1396	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto	108:34e6b704fe68	1397	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto	108:34e6b704fe68	1398	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto	108:34e6b704fe68	1399	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto	108:34e6b704fe68	1400	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto	108:34e6b704fe68	1401	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto	108:34e6b704fe68	1402	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto	108:34e6b704fe68	1403	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto	108:34e6b704fe68	1404	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1405	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1406	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto	108:34e6b704fe68	1407	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto	108:34e6b704fe68	1408	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1409	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1410	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto	108:34e6b704fe68	1411	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto	108:34e6b704fe68	1412	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto	108:34e6b704fe68	1413	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto	108:34e6b704fe68	1414	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto	108:34e6b704fe68	1415	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto	108:34e6b704fe68	1416	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto	108:34e6b704fe68	1417	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto	108:34e6b704fe68	1418	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto	108:34e6b704fe68	1419	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto	108:34e6b704fe68	1420	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto	108:34e6b704fe68	1421	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto	108:34e6b704fe68	1422	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto	108:34e6b704fe68	1423	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto	108:34e6b704fe68	1424	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto	108:34e6b704fe68	1425	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto	108:34e6b704fe68	1426	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto	108:34e6b704fe68	1427	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto	108:34e6b704fe68	1428	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto	108:34e6b704fe68	1429	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto	108:34e6b704fe68	1430	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto	108:34e6b704fe68	1431	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto	108:34e6b704fe68	1432	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto	108:34e6b704fe68	1433	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto	108:34e6b704fe68	1434	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto	108:34e6b704fe68	1435	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto	108:34e6b704fe68	1436	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1437	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1438	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto	108:34e6b704fe68	1439	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto	108:34e6b704fe68	1440	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto	108:34e6b704fe68	1441	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto	108:34e6b704fe68	1442	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto	108:34e6b704fe68	1443	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto	108:34e6b704fe68	1444	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto	108:34e6b704fe68	1445	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto	108:34e6b704fe68	1446	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto	108:34e6b704fe68	1447	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto	108:34e6b704fe68	1448	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto	108:34e6b704fe68	1449	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto	108:34e6b704fe68	1450	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto	108:34e6b704fe68	1451	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto	108:34e6b704fe68	1452	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto	108:34e6b704fe68	1453	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto	108:34e6b704fe68	1454	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1455	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1456	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto	108:34e6b704fe68	1457	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto	108:34e6b704fe68	1458	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto	108:34e6b704fe68	1459	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto	108:34e6b704fe68	1460	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1461	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1462	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto	108:34e6b704fe68	1463	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto	108:34e6b704fe68	1464	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto	108:34e6b704fe68	1465	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto	108:34e6b704fe68	1466	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto	108:34e6b704fe68	1467	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto	108:34e6b704fe68	1468	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto	108:34e6b704fe68	1469	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto	108:34e6b704fe68	1470	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1471	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1472	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto	108:34e6b704fe68	1473	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto	108:34e6b704fe68	1474	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto	108:34e6b704fe68	1475	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto	108:34e6b704fe68	1476	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto	108:34e6b704fe68	1477	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto	108:34e6b704fe68	1478	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto	108:34e6b704fe68	1479	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto	108:34e6b704fe68	1480	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1481	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1482	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto	108:34e6b704fe68	1483	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto	108:34e6b704fe68	1484	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto	108:34e6b704fe68	1485	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto	108:34e6b704fe68	1486	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1487	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1488	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto	108:34e6b704fe68	1489	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto	108:34e6b704fe68	1490	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto	108:34e6b704fe68	1491	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto	108:34e6b704fe68	1492	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1493	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1494	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto	108:34e6b704fe68	1495	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto	108:34e6b704fe68	1496	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto	108:34e6b704fe68	1497	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto	108:34e6b704fe68	1498	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto	108:34e6b704fe68	1499	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto	108:34e6b704fe68	1500	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto	108:34e6b704fe68	1501	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto	108:34e6b704fe68	1502	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto	108:34e6b704fe68	1503	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto	108:34e6b704fe68	1504	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto	108:34e6b704fe68	1505	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto	108:34e6b704fe68	1506	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto	108:34e6b704fe68	1507	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto	108:34e6b704fe68	1508	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1509	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1510	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto	108:34e6b704fe68	1511	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto	108:34e6b704fe68	1512	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto	108:34e6b704fe68	1513	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto	108:34e6b704fe68	1514	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto	108:34e6b704fe68	1515	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto	108:34e6b704fe68	1516	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1517	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1518	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto	108:34e6b704fe68	1519	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto	108:34e6b704fe68	1520	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1521	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1522	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto	108:34e6b704fe68	1523	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto	108:34e6b704fe68	1524	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto	108:34e6b704fe68	1525	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto	108:34e6b704fe68	1526	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto	108:34e6b704fe68	1527	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto	108:34e6b704fe68	1528	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1529	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1530	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto	108:34e6b704fe68	1531	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto	108:34e6b704fe68	1532	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto	108:34e6b704fe68	1533	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto	108:34e6b704fe68	1534	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1535	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1536	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto	108:34e6b704fe68	1537	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto	108:34e6b704fe68	1538	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto	108:34e6b704fe68	1539	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto	108:34e6b704fe68	1540	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1541	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1542	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto	108:34e6b704fe68	1543	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto	108:34e6b704fe68	1544	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto	108:34e6b704fe68	1545	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto	108:34e6b704fe68	1546	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1547	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1548	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto	108:34e6b704fe68	1549	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto	108:34e6b704fe68	1550	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto	108:34e6b704fe68	1551	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto	108:34e6b704fe68	1552	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1553	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1554	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto	108:34e6b704fe68	1555	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto	108:34e6b704fe68	1556	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto	108:34e6b704fe68	1557	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto	108:34e6b704fe68	1558	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1559	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1560	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto	108:34e6b704fe68	1561	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto	108:34e6b704fe68	1562	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto	108:34e6b704fe68	1563	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto	108:34e6b704fe68	1564	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1565	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1566	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto	108:34e6b704fe68	1567	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto	108:34e6b704fe68	1568	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto	108:34e6b704fe68	1569	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto	108:34e6b704fe68	1570	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1571	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1572	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto	108:34e6b704fe68	1573	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto	108:34e6b704fe68	1574	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto	108:34e6b704fe68	1575	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto	108:34e6b704fe68	1576	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1577	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1578	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto	108:34e6b704fe68	1579	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto	108:34e6b704fe68	1580	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto	108:34e6b704fe68	1581	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto	108:34e6b704fe68	1582	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1583	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1584	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto	108:34e6b704fe68	1585	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto	108:34e6b704fe68	1586	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto	108:34e6b704fe68	1587	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto	108:34e6b704fe68	1588	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1589	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1590	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto	108:34e6b704fe68	1591	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto	108:34e6b704fe68	1592	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto	108:34e6b704fe68	1593	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto	108:34e6b704fe68	1594	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1595	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1596	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto	108:34e6b704fe68	1597	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto	108:34e6b704fe68	1598	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto	108:34e6b704fe68	1599	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto	108:34e6b704fe68	1600	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1601	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1602	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto	108:34e6b704fe68	1603	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto	108:34e6b704fe68	1604	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto	108:34e6b704fe68	1605	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto	108:34e6b704fe68	1606	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1607	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1608	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto	108:34e6b704fe68	1609	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto	108:34e6b704fe68	1610	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto	108:34e6b704fe68	1611	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto	108:34e6b704fe68	1612	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1613	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1614	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto	108:34e6b704fe68	1615	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto	108:34e6b704fe68	1616	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto	108:34e6b704fe68	1617	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto	108:34e6b704fe68	1618	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1619	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1620	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto	108:34e6b704fe68	1621	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto	108:34e6b704fe68	1622	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto	108:34e6b704fe68	1623	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto	108:34e6b704fe68	1624	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1625	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1626	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto	108:34e6b704fe68	1627	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto	108:34e6b704fe68	1628	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto	108:34e6b704fe68	1629	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto	108:34e6b704fe68	1630	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1631	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1632	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto	108:34e6b704fe68	1633	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto	108:34e6b704fe68	1634	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto	108:34e6b704fe68	1635	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto	108:34e6b704fe68	1636	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1637	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1638	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto	108:34e6b704fe68	1639	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto	108:34e6b704fe68	1640	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto	108:34e6b704fe68	1641	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto	108:34e6b704fe68	1642	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1643	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1644	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto	108:34e6b704fe68	1645	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto	108:34e6b704fe68	1646	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto	108:34e6b704fe68	1647	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto	108:34e6b704fe68	1648	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1649	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1650	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto	108:34e6b704fe68	1651	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto	108:34e6b704fe68	1652	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto	108:34e6b704fe68	1653	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto	108:34e6b704fe68	1654	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1655	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1656	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto	108:34e6b704fe68	1657	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto	108:34e6b704fe68	1658	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto	108:34e6b704fe68	1659	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto	108:34e6b704fe68	1660	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto	108:34e6b704fe68	1661	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto	108:34e6b704fe68	1662	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1663	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1664	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto	108:34e6b704fe68	1665	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto	108:34e6b704fe68	1666	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto	108:34e6b704fe68	1667	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto	108:34e6b704fe68	1668	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1669	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1670	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto	108:34e6b704fe68	1671	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto	108:34e6b704fe68	1672	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto	108:34e6b704fe68	1673	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto	108:34e6b704fe68	1674	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1675	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1676	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto	108:34e6b704fe68	1677	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto	108:34e6b704fe68	1678	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto	108:34e6b704fe68	1679	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto	108:34e6b704fe68	1680	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1681	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1682	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto	108:34e6b704fe68	1683	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto	108:34e6b704fe68	1684	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto	108:34e6b704fe68	1685	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto	108:34e6b704fe68	1686	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1687	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1688	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1689	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1690	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto	108:34e6b704fe68	1691	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto	108:34e6b704fe68	1692	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1693	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1694	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto	108:34e6b704fe68	1695	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto	108:34e6b704fe68	1696	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto	108:34e6b704fe68	1697	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto	108:34e6b704fe68	1698	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1699	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1700	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto	108:34e6b704fe68	1701	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto	108:34e6b704fe68	1702	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto	108:34e6b704fe68	1703	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto	108:34e6b704fe68	1704	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1705	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1706	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto	108:34e6b704fe68	1707	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto	108:34e6b704fe68	1708	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto	108:34e6b704fe68	1709	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto	108:34e6b704fe68	1710	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto	108:34e6b704fe68	1711	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto	108:34e6b704fe68	1712	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto	108:34e6b704fe68	1713	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto	108:34e6b704fe68	1714	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto	108:34e6b704fe68	1715	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto	108:34e6b704fe68	1716	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto	108:34e6b704fe68	1717	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto	108:34e6b704fe68	1718	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto	108:34e6b704fe68	1719	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto	108:34e6b704fe68	1720	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto	108:34e6b704fe68	1721	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto	108:34e6b704fe68	1722	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto	108:34e6b704fe68	1723	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto	108:34e6b704fe68	1724	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto	108:34e6b704fe68	1725	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto	108:34e6b704fe68	1726	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto	108:34e6b704fe68	1727	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto	108:34e6b704fe68	1728	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto	108:34e6b704fe68	1729	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto	108:34e6b704fe68	1730	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1731	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1732	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto	108:34e6b704fe68	1733	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto	108:34e6b704fe68	1734	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto	108:34e6b704fe68	1735	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto	108:34e6b704fe68	1736	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1737	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1738	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto	108:34e6b704fe68	1739	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto	108:34e6b704fe68	1740	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto	108:34e6b704fe68	1741	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto	108:34e6b704fe68	1742	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1743	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1744	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto	108:34e6b704fe68	1745	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto	108:34e6b704fe68	1746	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto	108:34e6b704fe68	1747	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto	108:34e6b704fe68	1748	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1749	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1750	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto	108:34e6b704fe68	1751	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto	108:34e6b704fe68	1752	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto	108:34e6b704fe68	1753	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto	108:34e6b704fe68	1754	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1755	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1756	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto	108:34e6b704fe68	1757	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto	108:34e6b704fe68	1758	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto	108:34e6b704fe68	1759	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto	108:34e6b704fe68	1760	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1761	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1762	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto	108:34e6b704fe68	1763	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto	108:34e6b704fe68	1764	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto	108:34e6b704fe68	1765	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto	108:34e6b704fe68	1766	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1767	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1768	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto	108:34e6b704fe68	1769	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto	108:34e6b704fe68	1770	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto	108:34e6b704fe68	1771	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto	108:34e6b704fe68	1772	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1773	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1774	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto	108:34e6b704fe68	1775	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto	108:34e6b704fe68	1776	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto	108:34e6b704fe68	1777	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto	108:34e6b704fe68	1778	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1779	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1780	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto	108:34e6b704fe68	1781	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto	108:34e6b704fe68	1782	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto	108:34e6b704fe68	1783	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto	108:34e6b704fe68	1784	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1785	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1786	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto	108:34e6b704fe68	1787	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto	108:34e6b704fe68	1788	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto	108:34e6b704fe68	1789	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto	108:34e6b704fe68	1790	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto	108:34e6b704fe68	1791	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto	108:34e6b704fe68	1792	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto	108:34e6b704fe68	1793	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto	108:34e6b704fe68	1794	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1795	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1796	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto	108:34e6b704fe68	1797	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto	108:34e6b704fe68	1798	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto	108:34e6b704fe68	1799	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto	108:34e6b704fe68	1800	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1801	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1802	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto	108:34e6b704fe68	1803	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto	108:34e6b704fe68	1804	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto	108:34e6b704fe68	1805	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto	108:34e6b704fe68	1806	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1807	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1808	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto	108:34e6b704fe68	1809	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto	108:34e6b704fe68	1810	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto	108:34e6b704fe68	1811	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto	108:34e6b704fe68	1812	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1813	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1814	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto	108:34e6b704fe68	1815	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto	108:34e6b704fe68	1816	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto	108:34e6b704fe68	1817	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto	108:34e6b704fe68	1818	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1819	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1820	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto	108:34e6b704fe68	1821	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto	108:34e6b704fe68	1822	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto	108:34e6b704fe68	1823	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto	108:34e6b704fe68	1824	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1825	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1826	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto	108:34e6b704fe68	1827	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto	108:34e6b704fe68	1828	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto	108:34e6b704fe68	1829	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto	108:34e6b704fe68	1830	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1831	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1832	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto	108:34e6b704fe68	1833	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto	108:34e6b704fe68	1834	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto	108:34e6b704fe68	1835	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto	108:34e6b704fe68	1836	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1837	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1838	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto	108:34e6b704fe68	1839	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto	108:34e6b704fe68	1840	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto	108:34e6b704fe68	1841	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto	108:34e6b704fe68	1842	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto	108:34e6b704fe68	1843	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto	108:34e6b704fe68	1844	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto	108:34e6b704fe68	1845	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto	108:34e6b704fe68	1846	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto	108:34e6b704fe68	1847	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto	108:34e6b704fe68	1848	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto	108:34e6b704fe68	1849	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto	108:34e6b704fe68	1850	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto	108:34e6b704fe68	1851	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1852	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1853	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto	108:34e6b704fe68	1854	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto	108:34e6b704fe68	1855	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto	108:34e6b704fe68	1856	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto	108:34e6b704fe68	1857	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto	108:34e6b704fe68	1858	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1859	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1860	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto	108:34e6b704fe68	1861	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto	108:34e6b704fe68	1862	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto	108:34e6b704fe68	1863	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto	108:34e6b704fe68	1864	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto	108:34e6b704fe68	1865	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto	108:34e6b704fe68	1866	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1867	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1868	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto	108:34e6b704fe68	1869	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto	108:34e6b704fe68	1870	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto	108:34e6b704fe68	1871	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto	108:34e6b704fe68	1872	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1873	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1874	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto	108:34e6b704fe68	1875	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto	108:34e6b704fe68	1876	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1877	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1878	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto	108:34e6b704fe68	1879	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto	108:34e6b704fe68	1880	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto	108:34e6b704fe68	1881	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto	108:34e6b704fe68	1882
Kojto	108:34e6b704fe68	1883	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto	108:34e6b704fe68	1884	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto	108:34e6b704fe68	1885	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1886	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1887	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto	108:34e6b704fe68	1888	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto	108:34e6b704fe68	1889	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto	108:34e6b704fe68	1890	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto	108:34e6b704fe68	1891	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1892	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1893	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1894	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1895	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1896	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1897	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1898	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1899	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto	108:34e6b704fe68	1900	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto	108:34e6b704fe68	1901	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto	108:34e6b704fe68	1902	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto	108:34e6b704fe68	1903	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto	108:34e6b704fe68	1904	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1905	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1906	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto	108:34e6b704fe68	1907	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto	108:34e6b704fe68	1908	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto	108:34e6b704fe68	1909	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto	108:34e6b704fe68	1910	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto	108:34e6b704fe68	1911	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1912	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1913	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto	108:34e6b704fe68	1914	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto	108:34e6b704fe68	1915	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto	108:34e6b704fe68	1916	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto	108:34e6b704fe68	1917	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1918	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1919	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto	108:34e6b704fe68	1920	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto	108:34e6b704fe68	1921	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto	108:34e6b704fe68	1922	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto	108:34e6b704fe68	1923	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1924	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1925	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1926	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1927	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1928	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1929	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1930	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1931	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1932	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1933	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1934	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1935	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1936	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto	108:34e6b704fe68	1937	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto	108:34e6b704fe68	1938	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1939	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1940	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto	108:34e6b704fe68	1941	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto	108:34e6b704fe68	1942	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto	108:34e6b704fe68	1943	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto	108:34e6b704fe68	1944	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto	108:34e6b704fe68	1945	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto	108:34e6b704fe68	1946	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1947	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1948	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto	108:34e6b704fe68	1949	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto	108:34e6b704fe68	1950	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto	108:34e6b704fe68	1951	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto	108:34e6b704fe68	1952	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1953	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1954	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto	108:34e6b704fe68	1955	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto	108:34e6b704fe68	1956	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto	108:34e6b704fe68	1957	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto	108:34e6b704fe68	1958	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1959	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1960	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto	108:34e6b704fe68	1961	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto	108:34e6b704fe68	1962	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto	108:34e6b704fe68	1963	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto	108:34e6b704fe68	1964	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1965	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1966	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto	108:34e6b704fe68	1967	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto	108:34e6b704fe68	1968	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto	108:34e6b704fe68	1969	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1970	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1971	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto	108:34e6b704fe68	1972	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto	108:34e6b704fe68	1973	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto	108:34e6b704fe68	1974	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto	108:34e6b704fe68	1975	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto	108:34e6b704fe68	1976	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto	108:34e6b704fe68	1977	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1978	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1979	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto	108:34e6b704fe68	1980	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto	108:34e6b704fe68	1981	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto	108:34e6b704fe68	1982	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto	108:34e6b704fe68	1983	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1984	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1985	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto	108:34e6b704fe68	1986	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto	108:34e6b704fe68	1987	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto	108:34e6b704fe68	1988	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto	108:34e6b704fe68	1989	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1990	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1991	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1992	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1993	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto	108:34e6b704fe68	1994	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto	108:34e6b704fe68	1995	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1996	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1997	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	1998	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	1999	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
Kojto	108:34e6b704fe68	2000	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
Kojto	108:34e6b704fe68	2001	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto	108:34e6b704fe68	2002	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto	108:34e6b704fe68	2003	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2004	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2005	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Kojto	108:34e6b704fe68	2006	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
Kojto	108:34e6b704fe68	2007	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto	108:34e6b704fe68	2008	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2009	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2010	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2011	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2012	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2013	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2014	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2015	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2016	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2017	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto	108:34e6b704fe68	2018	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto	108:34e6b704fe68	2019	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2020	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2021	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto	108:34e6b704fe68	2022	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto	108:34e6b704fe68	2023	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2024	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2025	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto	108:34e6b704fe68	2026	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto	108:34e6b704fe68	2027	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto	108:34e6b704fe68	2028	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto	108:34e6b704fe68	2029	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2030	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2031
Kojto	108:34e6b704fe68	2032	/* alias define maintained for legacy */
Kojto	108:34e6b704fe68	2033	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto	108:34e6b704fe68	2034	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto	108:34e6b704fe68	2035
Kojto	108:34e6b704fe68	2036	#if defined(STM32F4)
Kojto	108:34e6b704fe68	2037	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto	108:34e6b704fe68	2038	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto	108:34e6b704fe68	2039	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto	108:34e6b704fe68	2040	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2041	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2042	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto	108:34e6b704fe68	2043	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto	108:34e6b704fe68	2044	#define Sdmmc1ClockSelection SdioClockSelection
Kojto	108:34e6b704fe68	2045	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
Kojto	108:34e6b704fe68	2046	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
Kojto	108:34e6b704fe68	2047	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
Kojto	108:34e6b704fe68	2048	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
Kojto	108:34e6b704fe68	2049	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
Kojto	108:34e6b704fe68	2050	#endif
Kojto	108:34e6b704fe68	2051
Kojto	108:34e6b704fe68	2052	#if defined(STM32F7) \|\| defined(STM32L4)
Kojto	108:34e6b704fe68	2053	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto	108:34e6b704fe68	2054	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
Kojto	108:34e6b704fe68	2055	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
Kojto	108:34e6b704fe68	2056	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
Kojto	108:34e6b704fe68	2057	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
Kojto	108:34e6b704fe68	2058	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto	108:34e6b704fe68	2059	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
Kojto	108:34e6b704fe68	2060	#define SdioClockSelection Sdmmc1ClockSelection
Kojto	108:34e6b704fe68	2061	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
Kojto	108:34e6b704fe68	2062	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
Kojto	108:34e6b704fe68	2063	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
Kojto	108:34e6b704fe68	2064	#endif
Kojto	108:34e6b704fe68	2065
Kojto	108:34e6b704fe68	2066	#if defined(STM32F7)
Kojto	108:34e6b704fe68	2067	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
Kojto	108:34e6b704fe68	2068	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
Kojto	108:34e6b704fe68	2069	#endif
Kojto	108:34e6b704fe68	2070
Kojto	108:34e6b704fe68	2071	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto	108:34e6b704fe68	2072	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto	108:34e6b704fe68	2073
Kojto	108:34e6b704fe68	2074	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto	108:34e6b704fe68	2075
Kojto	108:34e6b704fe68	2076	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto	108:34e6b704fe68	2077	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto	108:34e6b704fe68	2078	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto	108:34e6b704fe68	2079	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto	108:34e6b704fe68	2080
Kojto	108:34e6b704fe68	2081	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto	108:34e6b704fe68	2082	#define RCC_MCO_NODIV RCC_MCODIV_1
Kojto	108:34e6b704fe68	2083	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto	108:34e6b704fe68	2084
Kojto	108:34e6b704fe68	2085	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto	108:34e6b704fe68	2086	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto	108:34e6b704fe68	2087	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto	108:34e6b704fe68	2088	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto	108:34e6b704fe68	2089	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto	108:34e6b704fe68	2090	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto	108:34e6b704fe68	2091	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto	108:34e6b704fe68	2092	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto	108:34e6b704fe68	2093	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto	108:34e6b704fe68	2094	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto	108:34e6b704fe68	2095
Kojto	108:34e6b704fe68	2096	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto	108:34e6b704fe68	2097	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto	108:34e6b704fe68	2098	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto	108:34e6b704fe68	2099	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto	108:34e6b704fe68	2100	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto	108:34e6b704fe68	2101	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto	108:34e6b704fe68	2102
Kojto	108:34e6b704fe68	2103	#define CR_HSION_BB RCC_CR_HSION_BB
Kojto	108:34e6b704fe68	2104	#define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto	108:34e6b704fe68	2105	#define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto	108:34e6b704fe68	2106	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto	108:34e6b704fe68	2107	#define CR_MSION_BB RCC_CR_MSION_BB
Kojto	108:34e6b704fe68	2108	#define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto	108:34e6b704fe68	2109	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto	108:34e6b704fe68	2110	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto	108:34e6b704fe68	2111	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto	108:34e6b704fe68	2112	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto	108:34e6b704fe68	2113	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto	108:34e6b704fe68	2114	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto	108:34e6b704fe68	2115	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto	108:34e6b704fe68	2116	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto	108:34e6b704fe68	2117	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto	108:34e6b704fe68	2118
Kojto	108:34e6b704fe68	2119	/**
Kojto	108:34e6b704fe68	2120	* @}
Kojto	108:34e6b704fe68	2121	*/
Kojto	108:34e6b704fe68	2122
Kojto	108:34e6b704fe68	2123	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2124	* @{
Kojto	108:34e6b704fe68	2125	*/
Kojto	108:34e6b704fe68	2126	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto	108:34e6b704fe68	2127
Kojto	108:34e6b704fe68	2128	/**
Kojto	108:34e6b704fe68	2129	* @}
Kojto	108:34e6b704fe68	2130	*/
Kojto	108:34e6b704fe68	2131
Kojto	108:34e6b704fe68	2132	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2133	* @{
Kojto	108:34e6b704fe68	2134	*/
Kojto	108:34e6b704fe68	2135
Kojto	108:34e6b704fe68	2136	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto	108:34e6b704fe68	2137	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto	108:34e6b704fe68	2138	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto	108:34e6b704fe68	2139
Kojto	108:34e6b704fe68	2140	#if defined (STM32F1)
Kojto	108:34e6b704fe68	2141	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto	108:34e6b704fe68	2142
Kojto	108:34e6b704fe68	2143	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto	108:34e6b704fe68	2144
Kojto	108:34e6b704fe68	2145	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto	108:34e6b704fe68	2146
Kojto	108:34e6b704fe68	2147	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto	108:34e6b704fe68	2148
Kojto	108:34e6b704fe68	2149	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto	108:34e6b704fe68	2150	#else
Kojto	108:34e6b704fe68	2151	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto	108:34e6b704fe68	2152	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto	108:34e6b704fe68	2153	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto	108:34e6b704fe68	2154	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto	108:34e6b704fe68	2155	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto	108:34e6b704fe68	2156	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto	108:34e6b704fe68	2157	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto	108:34e6b704fe68	2158	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto	108:34e6b704fe68	2159	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto	108:34e6b704fe68	2160	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto	108:34e6b704fe68	2161	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto	108:34e6b704fe68	2162	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto	108:34e6b704fe68	2163	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto	108:34e6b704fe68	2164	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto	108:34e6b704fe68	2165	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto	108:34e6b704fe68	2166	#endif /* STM32F1 */
Kojto	108:34e6b704fe68	2167
Kojto	108:34e6b704fe68	2168	#define IS_ALARM IS_RTC_ALARM
Kojto	108:34e6b704fe68	2169	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto	108:34e6b704fe68	2170	#define IS_TAMPER IS_RTC_TAMPER
Kojto	108:34e6b704fe68	2171	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto	108:34e6b704fe68	2172	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto	108:34e6b704fe68	2173	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto	108:34e6b704fe68	2174	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto	108:34e6b704fe68	2175	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto	108:34e6b704fe68	2176	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto	108:34e6b704fe68	2177	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto	108:34e6b704fe68	2178	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto	108:34e6b704fe68	2179	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto	108:34e6b704fe68	2180	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto	108:34e6b704fe68	2181	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto	108:34e6b704fe68	2182
Kojto	108:34e6b704fe68	2183	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto	108:34e6b704fe68	2184	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto	108:34e6b704fe68	2185
Kojto	108:34e6b704fe68	2186	/**
Kojto	108:34e6b704fe68	2187	* @}
Kojto	108:34e6b704fe68	2188	*/
Kojto	108:34e6b704fe68	2189
Kojto	108:34e6b704fe68	2190	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2191	* @{
Kojto	108:34e6b704fe68	2192	*/
Kojto	108:34e6b704fe68	2193
Kojto	108:34e6b704fe68	2194	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto	108:34e6b704fe68	2195	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto	108:34e6b704fe68	2196
Kojto	108:34e6b704fe68	2197	#if defined(STM32F4)
Kojto	108:34e6b704fe68	2198	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
Kojto	108:34e6b704fe68	2199	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
Kojto	108:34e6b704fe68	2200	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
Kojto	108:34e6b704fe68	2201	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
Kojto	108:34e6b704fe68	2202	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
Kojto	108:34e6b704fe68	2203	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
Kojto	108:34e6b704fe68	2204	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
Kojto	108:34e6b704fe68	2205	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
Kojto	108:34e6b704fe68	2206	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
Kojto	108:34e6b704fe68	2207	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
Kojto	108:34e6b704fe68	2208	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
Kojto	108:34e6b704fe68	2209	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
Kojto	108:34e6b704fe68	2210	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
Kojto	108:34e6b704fe68	2211	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
Kojto	108:34e6b704fe68	2212	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
Kojto	108:34e6b704fe68	2213	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
Kojto	108:34e6b704fe68	2214	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
Kojto	108:34e6b704fe68	2215	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
Kojto	108:34e6b704fe68	2216	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
Kojto	108:34e6b704fe68	2217	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
Kojto	108:34e6b704fe68	2218	/* alias CMSIS */
Kojto	108:34e6b704fe68	2219	#define SDMMC1_IRQn SDIO_IRQn
Kojto	108:34e6b704fe68	2220	#define SDMMC1_IRQHandler SDIO_IRQHandler
Kojto	108:34e6b704fe68	2221	#endif
Kojto	108:34e6b704fe68	2222
Kojto	108:34e6b704fe68	2223	#if defined(STM32F7) \|\| defined(STM32L4)
Kojto	108:34e6b704fe68	2224	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
Kojto	108:34e6b704fe68	2225	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
Kojto	108:34e6b704fe68	2226	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
Kojto	108:34e6b704fe68	2227	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
Kojto	108:34e6b704fe68	2228	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
Kojto	108:34e6b704fe68	2229	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
Kojto	108:34e6b704fe68	2230	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
Kojto	108:34e6b704fe68	2231	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
Kojto	108:34e6b704fe68	2232	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
Kojto	108:34e6b704fe68	2233	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
Kojto	108:34e6b704fe68	2234	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
Kojto	108:34e6b704fe68	2235	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
Kojto	108:34e6b704fe68	2236	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
Kojto	108:34e6b704fe68	2237	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
Kojto	108:34e6b704fe68	2238	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
Kojto	108:34e6b704fe68	2239	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
Kojto	108:34e6b704fe68	2240	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
Kojto	108:34e6b704fe68	2241	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
Kojto	108:34e6b704fe68	2242	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
Kojto	108:34e6b704fe68	2243	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
Kojto	108:34e6b704fe68	2244	/* alias CMSIS for compatibilities */
Kojto	108:34e6b704fe68	2245	#define SDIO_IRQn SDMMC1_IRQn
Kojto	108:34e6b704fe68	2246	#define SDIO_IRQHandler SDMMC1_IRQHandler
Kojto	108:34e6b704fe68	2247	#endif
Kojto	108:34e6b704fe68	2248	/**
Kojto	108:34e6b704fe68	2249	* @}
Kojto	108:34e6b704fe68	2250	*/
Kojto	108:34e6b704fe68	2251
Kojto	108:34e6b704fe68	2252	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2253	* @{
Kojto	108:34e6b704fe68	2254	*/
Kojto	108:34e6b704fe68	2255
Kojto	108:34e6b704fe68	2256	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto	108:34e6b704fe68	2257	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto	108:34e6b704fe68	2258	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto	108:34e6b704fe68	2259	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto	108:34e6b704fe68	2260	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto	108:34e6b704fe68	2261	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto	108:34e6b704fe68	2262
Kojto	108:34e6b704fe68	2263	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	2264	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	2265
Kojto	108:34e6b704fe68	2266	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto	108:34e6b704fe68	2267
Kojto	108:34e6b704fe68	2268	/**
Kojto	108:34e6b704fe68	2269	* @}
Kojto	108:34e6b704fe68	2270	*/
Kojto	108:34e6b704fe68	2271
Kojto	108:34e6b704fe68	2272	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2273	* @{
Kojto	108:34e6b704fe68	2274	*/
Kojto	108:34e6b704fe68	2275	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto	108:34e6b704fe68	2276	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto	108:34e6b704fe68	2277	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto	108:34e6b704fe68	2278	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto	108:34e6b704fe68	2279	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto	108:34e6b704fe68	2280	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto	108:34e6b704fe68	2281	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto	108:34e6b704fe68	2282	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto	108:34e6b704fe68	2283	/**
Kojto	108:34e6b704fe68	2284	* @}
Kojto	108:34e6b704fe68	2285	*/
Kojto	108:34e6b704fe68	2286
Kojto	108:34e6b704fe68	2287	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2288	* @{
Kojto	108:34e6b704fe68	2289	*/
Kojto	108:34e6b704fe68	2290
Kojto	108:34e6b704fe68	2291	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto	108:34e6b704fe68	2292	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto	108:34e6b704fe68	2293	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto	108:34e6b704fe68	2294
Kojto	108:34e6b704fe68	2295	/**
Kojto	108:34e6b704fe68	2296	* @}
Kojto	108:34e6b704fe68	2297	*/
Kojto	108:34e6b704fe68	2298
Kojto	108:34e6b704fe68	2299	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2300	* @{
Kojto	108:34e6b704fe68	2301	*/
Kojto	108:34e6b704fe68	2302
Kojto	108:34e6b704fe68	2303	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	2304	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto	108:34e6b704fe68	2305	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	2306	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto	108:34e6b704fe68	2307
Kojto	108:34e6b704fe68	2308	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto	108:34e6b704fe68	2309
Kojto	108:34e6b704fe68	2310	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto	108:34e6b704fe68	2311	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto	108:34e6b704fe68	2312
Kojto	108:34e6b704fe68	2313	/**
Kojto	108:34e6b704fe68	2314	* @}
Kojto	108:34e6b704fe68	2315	*/
Kojto	108:34e6b704fe68	2316
Kojto	108:34e6b704fe68	2317
Kojto	108:34e6b704fe68	2318	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2319	* @{
Kojto	108:34e6b704fe68	2320	*/
Kojto	108:34e6b704fe68	2321
Kojto	108:34e6b704fe68	2322	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto	108:34e6b704fe68	2323	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto	108:34e6b704fe68	2324	#define __USART_ENABLE __HAL_USART_ENABLE
Kojto	108:34e6b704fe68	2325	#define __USART_DISABLE __HAL_USART_DISABLE
Kojto	108:34e6b704fe68	2326
Kojto	108:34e6b704fe68	2327	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	2328	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto	108:34e6b704fe68	2329
Kojto	108:34e6b704fe68	2330	/**
Kojto	108:34e6b704fe68	2331	* @}
Kojto	108:34e6b704fe68	2332	*/
Kojto	108:34e6b704fe68	2333
Kojto	108:34e6b704fe68	2334	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2335	* @{
Kojto	108:34e6b704fe68	2336	*/
Kojto	108:34e6b704fe68	2337	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto	108:34e6b704fe68	2338
Kojto	108:34e6b704fe68	2339	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto	108:34e6b704fe68	2340	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto	108:34e6b704fe68	2341	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto	108:34e6b704fe68	2342	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto	108:34e6b704fe68	2343
Kojto	108:34e6b704fe68	2344	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto	108:34e6b704fe68	2345	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto	108:34e6b704fe68	2346	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto	108:34e6b704fe68	2347	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto	108:34e6b704fe68	2348
Kojto	108:34e6b704fe68	2349	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto	108:34e6b704fe68	2350	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto	108:34e6b704fe68	2351	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto	108:34e6b704fe68	2352	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto	108:34e6b704fe68	2353	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	108:34e6b704fe68	2354	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	2355	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	108:34e6b704fe68	2356
Kojto	108:34e6b704fe68	2357	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto	108:34e6b704fe68	2358	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto	108:34e6b704fe68	2359	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto	108:34e6b704fe68	2360	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto	108:34e6b704fe68	2361	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	108:34e6b704fe68	2362	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	2363	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	108:34e6b704fe68	2364	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto	108:34e6b704fe68	2365
Kojto	108:34e6b704fe68	2366	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto	108:34e6b704fe68	2367	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto	108:34e6b704fe68	2368	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto	108:34e6b704fe68	2369	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto	108:34e6b704fe68	2370	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	108:34e6b704fe68	2371	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	108:34e6b704fe68	2372	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	108:34e6b704fe68	2373	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto	108:34e6b704fe68	2374
Kojto	108:34e6b704fe68	2375	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto	108:34e6b704fe68	2376	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto	108:34e6b704fe68	2377
Kojto	108:34e6b704fe68	2378	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto	108:34e6b704fe68	2379	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto	108:34e6b704fe68	2380	/**
Kojto	108:34e6b704fe68	2381	* @}
Kojto	108:34e6b704fe68	2382	*/
Kojto	108:34e6b704fe68	2383
Kojto	108:34e6b704fe68	2384	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2385	* @{
Kojto	108:34e6b704fe68	2386	*/
Kojto	108:34e6b704fe68	2387	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto	108:34e6b704fe68	2388	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto	108:34e6b704fe68	2389
Kojto	108:34e6b704fe68	2390	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto	108:34e6b704fe68	2391	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto	108:34e6b704fe68	2392
Kojto	108:34e6b704fe68	2393	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto	108:34e6b704fe68	2394
Kojto	108:34e6b704fe68	2395	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto	108:34e6b704fe68	2396	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto	108:34e6b704fe68	2397	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto	108:34e6b704fe68	2398	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto	108:34e6b704fe68	2399	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto	108:34e6b704fe68	2400	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto	108:34e6b704fe68	2401	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto	108:34e6b704fe68	2402	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto	108:34e6b704fe68	2403	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto	108:34e6b704fe68	2404	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto	108:34e6b704fe68	2405	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto	108:34e6b704fe68	2406	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto	108:34e6b704fe68	2407
Kojto	108:34e6b704fe68	2408	#define TIM_TS_ITR0 ((uint32_t)0x0000)
Kojto	108:34e6b704fe68	2409	#define TIM_TS_ITR1 ((uint32_t)0x0010)
Kojto	108:34e6b704fe68	2410	#define TIM_TS_ITR2 ((uint32_t)0x0020)
Kojto	108:34e6b704fe68	2411	#define TIM_TS_ITR3 ((uint32_t)0x0030)
Kojto	108:34e6b704fe68	2412	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	108:34e6b704fe68	2413	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	108:34e6b704fe68	2414	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	108:34e6b704fe68	2415	((SELECTION) == TIM_TS_ITR3))
Kojto	108:34e6b704fe68	2416
Kojto	108:34e6b704fe68	2417	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
Kojto	108:34e6b704fe68	2418	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
Kojto	108:34e6b704fe68	2419	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	108:34e6b704fe68	2420	((CHANNEL) == TIM_CHANNEL_2))
Kojto	108:34e6b704fe68	2421
Kojto	108:34e6b704fe68	2422	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
Kojto	108:34e6b704fe68	2423	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
Kojto	108:34e6b704fe68	2424
Kojto	108:34e6b704fe68	2425	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
Kojto	108:34e6b704fe68	2426	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
Kojto	108:34e6b704fe68	2427
Kojto	108:34e6b704fe68	2428	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
Kojto	108:34e6b704fe68	2429	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
Kojto	108:34e6b704fe68	2430
Kojto	108:34e6b704fe68	2431	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
Kojto	108:34e6b704fe68	2432	((STATE) == TIM_OUTPUTSTATE_ENABLE))
Kojto	108:34e6b704fe68	2433	/**
Kojto	108:34e6b704fe68	2434	* @}
Kojto	108:34e6b704fe68	2435	*/
Kojto	108:34e6b704fe68	2436
Kojto	108:34e6b704fe68	2437	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2438	* @{
Kojto	108:34e6b704fe68	2439	*/
Kojto	108:34e6b704fe68	2440
Kojto	108:34e6b704fe68	2441	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto	108:34e6b704fe68	2442	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto	108:34e6b704fe68	2443	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto	108:34e6b704fe68	2444	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto	108:34e6b704fe68	2445	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto	108:34e6b704fe68	2446	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto	108:34e6b704fe68	2447	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto	108:34e6b704fe68	2448
Kojto	108:34e6b704fe68	2449	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto	108:34e6b704fe68	2450	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto	108:34e6b704fe68	2451	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto	108:34e6b704fe68	2452	/**
Kojto	108:34e6b704fe68	2453	* @}
Kojto	108:34e6b704fe68	2454	*/
Kojto	108:34e6b704fe68	2455
Kojto	108:34e6b704fe68	2456	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2457	* @{
Kojto	108:34e6b704fe68	2458	*/
Kojto	108:34e6b704fe68	2459	#define __HAL_LTDC_LAYER LTDC_LAYER
Kojto	108:34e6b704fe68	2460	/**
Kojto	108:34e6b704fe68	2461	* @}
Kojto	108:34e6b704fe68	2462	*/
Kojto	108:34e6b704fe68	2463
Kojto	108:34e6b704fe68	2464	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2465	* @{
Kojto	108:34e6b704fe68	2466	*/
Kojto	108:34e6b704fe68	2467	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto	108:34e6b704fe68	2468	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto	108:34e6b704fe68	2469	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto	108:34e6b704fe68	2470	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto	108:34e6b704fe68	2471	#define SAI_STREOMODE SAI_STEREOMODE
Kojto	108:34e6b704fe68	2472	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto	108:34e6b704fe68	2473	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto	108:34e6b704fe68	2474	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto	108:34e6b704fe68	2475	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto	108:34e6b704fe68	2476	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto	108:34e6b704fe68	2477	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto	108:34e6b704fe68	2478	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto	108:34e6b704fe68	2479
Kojto	108:34e6b704fe68	2480	/**
Kojto	108:34e6b704fe68	2481	* @}
Kojto	108:34e6b704fe68	2482	*/
Kojto	108:34e6b704fe68	2483
Kojto	108:34e6b704fe68	2484
Kojto	108:34e6b704fe68	2485	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto	108:34e6b704fe68	2486	* @{
Kojto	108:34e6b704fe68	2487	*/
Kojto	108:34e6b704fe68	2488
Kojto	108:34e6b704fe68	2489	/**
Kojto	108:34e6b704fe68	2490	* @}
Kojto	108:34e6b704fe68	2491	*/
Kojto	108:34e6b704fe68	2492
Kojto	108:34e6b704fe68	2493	#ifdef __cplusplus
Kojto	108:34e6b704fe68	2494	}
Kojto	108:34e6b704fe68	2495	#endif
Kojto	108:34e6b704fe68	2496
Kojto	108:34e6b704fe68	2497	#endif /* ___STM32_HAL_LEGACY */
Kojto	108:34e6b704fe68	2498
Kojto	108:34e6b704fe68	2499	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	108:34e6b704fe68	2500

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F070RB/stm32_hal_legacy.h@108:34e6b704fe68, 2015-10-02 (annotated)

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