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TARGET_WALLBOT_BLE/nrf51.h@120:2eb10e18b8d7, 2016-04-13 (annotated)

Committer:: elijahorr
Date:: Wed Apr 13 12:29:27 2016 +0000
Revision:: 120:2eb10e18b8d7
Parent:: 97:433970e64889

V1.1

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	97:433970e64889	1
Kojto	97:433970e64889	2	/**************************************************************************************************//
Kojto	97:433970e64889	3	* @file nRF51.h
Kojto	97:433970e64889	4	*
Kojto	97:433970e64889	5	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
Kojto	97:433970e64889	6	* nRF51 from Nordic Semiconductor.
Kojto	97:433970e64889	7	*
Kojto	97:433970e64889	8	* @version V522
Kojto	97:433970e64889	9	* @date 31. October 2014
bogdanm	92:4fc01daae5a5	10	*
Kojto	97:433970e64889	11	* @note Generated with SVDConv V2.81d
Kojto	97:433970e64889	12	* from CMSIS SVD File 'nRF51.xml' Version 522,
Kojto	97:433970e64889	13	*
Kojto	97:433970e64889	14	* @par Copyright (c) 2013, Nordic Semiconductor ASA
Kojto	97:433970e64889	15	* All rights reserved.
Kojto	97:433970e64889	16	*
Kojto	97:433970e64889	17	* Redistribution and use in source and binary forms, with or without
Kojto	97:433970e64889	18	* modification, are permitted provided that the following conditions are met:
Kojto	97:433970e64889	19	*
Kojto	97:433970e64889	20	* * Redistributions of source code must retain the above copyright notice, this
Kojto	97:433970e64889	21	* list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	22	*
Kojto	97:433970e64889	23	* * Redistributions in binary form must reproduce the above copyright notice,
Kojto	97:433970e64889	24	* this list of conditions and the following disclaimer in the documentation
Kojto	97:433970e64889	25	* and/or other materials provided with the distribution.
Kojto	97:433970e64889	26	*
Kojto	97:433970e64889	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto	97:433970e64889	28	* contributors may be used to endorse or promote products derived from
Kojto	97:433970e64889	29	* this software without specific prior written permission.
bogdanm	92:4fc01daae5a5	30	*
Kojto	97:433970e64889	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	97:433970e64889	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	97:433970e64889	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	97:433970e64889	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	97:433970e64889	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	97:433970e64889	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	97:433970e64889	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	97:433970e64889	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	97:433970e64889	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	97:433970e64889	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	97:433970e64889	41	*
Kojto	97:433970e64889	42	*
Kojto	97:433970e64889	43	*******************************************************************************************************/
bogdanm	92:4fc01daae5a5	44
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46
bogdanm	92:4fc01daae5a5	47	/** @addtogroup Nordic Semiconductor
bogdanm	92:4fc01daae5a5	48	* @{
bogdanm	92:4fc01daae5a5	49	*/
bogdanm	92:4fc01daae5a5	50
bogdanm	92:4fc01daae5a5	51	/** @addtogroup nRF51
bogdanm	92:4fc01daae5a5	52	* @{
bogdanm	92:4fc01daae5a5	53	*/
bogdanm	92:4fc01daae5a5	54
bogdanm	92:4fc01daae5a5	55	#ifndef NRF51_H
bogdanm	92:4fc01daae5a5	56	#define NRF51_H
bogdanm	92:4fc01daae5a5	57
bogdanm	92:4fc01daae5a5	58	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	59	extern "C" {
bogdanm	92:4fc01daae5a5	60	#endif
bogdanm	92:4fc01daae5a5	61
bogdanm	92:4fc01daae5a5	62
bogdanm	92:4fc01daae5a5	63	/* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm	92:4fc01daae5a5	64
bogdanm	92:4fc01daae5a5	65	typedef enum {
bogdanm	92:4fc01daae5a5	66	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
bogdanm	92:4fc01daae5a5	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	92:4fc01daae5a5	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	92:4fc01daae5a5	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
bogdanm	92:4fc01daae5a5	70	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
bogdanm	92:4fc01daae5a5	71	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
bogdanm	92:4fc01daae5a5	72	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
bogdanm	92:4fc01daae5a5	73	SysTick_IRQn = -1, /!< 15 System Tick Timer /
bogdanm	92:4fc01daae5a5	74	/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
bogdanm	92:4fc01daae5a5	75	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
bogdanm	92:4fc01daae5a5	76	RADIO_IRQn = 1, /!< 1 RADIO /
bogdanm	92:4fc01daae5a5	77	UART0_IRQn = 2, /!< 2 UART0 /
bogdanm	92:4fc01daae5a5	78	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
bogdanm	92:4fc01daae5a5	79	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
bogdanm	92:4fc01daae5a5	80	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
bogdanm	92:4fc01daae5a5	81	ADC_IRQn = 7, /!< 7 ADC /
bogdanm	92:4fc01daae5a5	82	TIMER0_IRQn = 8, /!< 8 TIMER0 /
bogdanm	92:4fc01daae5a5	83	TIMER1_IRQn = 9, /!< 9 TIMER1 /
bogdanm	92:4fc01daae5a5	84	TIMER2_IRQn = 10, /!< 10 TIMER2 /
bogdanm	92:4fc01daae5a5	85	RTC0_IRQn = 11, /!< 11 RTC0 /
bogdanm	92:4fc01daae5a5	86	TEMP_IRQn = 12, /!< 12 TEMP /
bogdanm	92:4fc01daae5a5	87	RNG_IRQn = 13, /!< 13 RNG /
bogdanm	92:4fc01daae5a5	88	ECB_IRQn = 14, /!< 14 ECB /
bogdanm	92:4fc01daae5a5	89	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
bogdanm	92:4fc01daae5a5	90	WDT_IRQn = 16, /!< 16 WDT /
bogdanm	92:4fc01daae5a5	91	RTC1_IRQn = 17, /!< 17 RTC1 /
bogdanm	92:4fc01daae5a5	92	QDEC_IRQn = 18, /!< 18 QDEC /
Kojto	97:433970e64889	93	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
bogdanm	92:4fc01daae5a5	94	SWI0_IRQn = 20, /!< 20 SWI0 /
bogdanm	92:4fc01daae5a5	95	SWI1_IRQn = 21, /!< 21 SWI1 /
bogdanm	92:4fc01daae5a5	96	SWI2_IRQn = 22, /!< 22 SWI2 /
bogdanm	92:4fc01daae5a5	97	SWI3_IRQn = 23, /!< 23 SWI3 /
bogdanm	92:4fc01daae5a5	98	SWI4_IRQn = 24, /!< 24 SWI4 /
bogdanm	92:4fc01daae5a5	99	SWI5_IRQn = 25 /!< 25 SWI5 /
bogdanm	92:4fc01daae5a5	100	} IRQn_Type;
bogdanm	92:4fc01daae5a5	101
bogdanm	92:4fc01daae5a5	102
bogdanm	92:4fc01daae5a5	103	/** @addtogroup Configuration_of_CMSIS
bogdanm	92:4fc01daae5a5	104	* @{
bogdanm	92:4fc01daae5a5	105	*/
bogdanm	92:4fc01daae5a5	106
bogdanm	92:4fc01daae5a5	107
bogdanm	92:4fc01daae5a5	108	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	109	/* ================ Processor and Core Peripheral Section ================ */
bogdanm	92:4fc01daae5a5	110	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	111
Kojto	97:433970e64889	112	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
bogdanm	92:4fc01daae5a5	113	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
bogdanm	92:4fc01daae5a5	114	#define __MPU_PRESENT 0 /!< MPU present or not /
bogdanm	92:4fc01daae5a5	115	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
bogdanm	92:4fc01daae5a5	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	92:4fc01daae5a5	117	/** @} / / End of group Configuration_of_CMSIS */
bogdanm	92:4fc01daae5a5	118
Kojto	97:433970e64889	119	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
Kojto	97:433970e64889	120	#include "system_nrf51.h" /!< nRF51 System /
bogdanm	92:4fc01daae5a5	121
bogdanm	92:4fc01daae5a5	122	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	123	/* ================ Device Specific Peripheral Section ================ */
bogdanm	92:4fc01daae5a5	124	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	125
bogdanm	92:4fc01daae5a5	126
bogdanm	92:4fc01daae5a5	127	/** @addtogroup Device_Peripheral_Registers
bogdanm	92:4fc01daae5a5	128	* @{
bogdanm	92:4fc01daae5a5	129	*/
bogdanm	92:4fc01daae5a5	130
bogdanm	92:4fc01daae5a5	131
bogdanm	92:4fc01daae5a5	132	/* ------------------- Start of section using anonymous unions ------------------ */
bogdanm	92:4fc01daae5a5	133	#if defined(__CC_ARM)
bogdanm	92:4fc01daae5a5	134	#pragma push
bogdanm	92:4fc01daae5a5	135	#pragma anon_unions
bogdanm	92:4fc01daae5a5	136	#elif defined(__ICCARM__)
bogdanm	92:4fc01daae5a5	137	#pragma language=extended
bogdanm	92:4fc01daae5a5	138	#elif defined(__GNUC__)
bogdanm	92:4fc01daae5a5	139	/* anonymous unions are enabled by default */
bogdanm	92:4fc01daae5a5	140	#elif defined(__TMS470__)
bogdanm	92:4fc01daae5a5	141	/* anonymous unions are enabled by default */
bogdanm	92:4fc01daae5a5	142	#elif defined(__TASKING__)
bogdanm	92:4fc01daae5a5	143	#pragma warning 586
bogdanm	92:4fc01daae5a5	144	#else
bogdanm	92:4fc01daae5a5	145	#warning Not supported compiler type
bogdanm	92:4fc01daae5a5	146	#endif
bogdanm	92:4fc01daae5a5	147
bogdanm	92:4fc01daae5a5	148
bogdanm	92:4fc01daae5a5	149	typedef struct {
bogdanm	92:4fc01daae5a5	150	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
bogdanm	92:4fc01daae5a5	151	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
bogdanm	92:4fc01daae5a5	152	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
bogdanm	92:4fc01daae5a5	153	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
bogdanm	92:4fc01daae5a5	154	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
bogdanm	92:4fc01daae5a5	155	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
bogdanm	92:4fc01daae5a5	156	} AMLI_RAMPRI_Type;
bogdanm	92:4fc01daae5a5	157
bogdanm	92:4fc01daae5a5	158	typedef struct {
Kojto	97:433970e64889	159	__IO uint32_t SCK; /!< Pin select for SCK. /
Kojto	97:433970e64889	160	__IO uint32_t MOSI; /!< Pin select for MOSI. /
Kojto	97:433970e64889	161	__IO uint32_t MISO; /!< Pin select for MISO. /
Kojto	97:433970e64889	162	} SPIM_PSEL_Type;
Kojto	97:433970e64889	163
Kojto	97:433970e64889	164	typedef struct {
Kojto	97:433970e64889	165	__IO uint32_t PTR; /!< Data pointer. /
Kojto	97:433970e64889	166	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
Kojto	97:433970e64889	167	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
Kojto	97:433970e64889	168	} SPIM_RXD_Type;
Kojto	97:433970e64889	169
Kojto	97:433970e64889	170	typedef struct {
Kojto	97:433970e64889	171	__IO uint32_t PTR; /!< Data pointer. /
Kojto	97:433970e64889	172	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
Kojto	97:433970e64889	173	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
Kojto	97:433970e64889	174	} SPIM_TXD_Type;
Kojto	97:433970e64889	175
Kojto	97:433970e64889	176	typedef struct {
bogdanm	92:4fc01daae5a5	177	__O uint32_t EN; /!< Enable channel group. /
bogdanm	92:4fc01daae5a5	178	__O uint32_t DIS; /!< Disable channel group. /
bogdanm	92:4fc01daae5a5	179	} PPI_TASKS_CHG_Type;
bogdanm	92:4fc01daae5a5	180
bogdanm	92:4fc01daae5a5	181	typedef struct {
bogdanm	92:4fc01daae5a5	182	__IO uint32_t EEP; /!< Channel event end-point. /
bogdanm	92:4fc01daae5a5	183	__IO uint32_t TEP; /!< Channel task end-point. /
bogdanm	92:4fc01daae5a5	184	} PPI_CH_Type;
bogdanm	92:4fc01daae5a5	185
Kojto	97:433970e64889	186	typedef struct {
Kojto	97:433970e64889	187	__I uint32_t PART; /!< Part code /
Kojto	97:433970e64889	188	__I uint32_t VARIANT; /!< Part variant /
Kojto	97:433970e64889	189	__I uint32_t PACKAGE; /!< Package option /
Kojto	97:433970e64889	190	__I uint32_t RAM; /!< RAM variant /
Kojto	97:433970e64889	191	__I uint32_t FLASH; /!< Flash variant /
Kojto	97:433970e64889	192	__I uint32_t RESERVED[3]; /!< Reserved /
Kojto	97:433970e64889	193	} FICR_INFO_Type;
Kojto	97:433970e64889	194
bogdanm	92:4fc01daae5a5	195
bogdanm	92:4fc01daae5a5	196	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	197	/* ================ POWER ================ */
bogdanm	92:4fc01daae5a5	198	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	199
bogdanm	92:4fc01daae5a5	200
bogdanm	92:4fc01daae5a5	201	/**
bogdanm	92:4fc01daae5a5	202	* @brief Power Control. (POWER)
bogdanm	92:4fc01daae5a5	203	*/
bogdanm	92:4fc01daae5a5	204
bogdanm	92:4fc01daae5a5	205	typedef struct { /!< POWER Structure /
bogdanm	92:4fc01daae5a5	206	__I uint32_t RESERVED0[30];
bogdanm	92:4fc01daae5a5	207	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
bogdanm	92:4fc01daae5a5	208	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
bogdanm	92:4fc01daae5a5	209	__I uint32_t RESERVED1[34];
bogdanm	92:4fc01daae5a5	210	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
bogdanm	92:4fc01daae5a5	211	__I uint32_t RESERVED2[126];
bogdanm	92:4fc01daae5a5	212	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	213	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	214	__I uint32_t RESERVED3[61];
bogdanm	92:4fc01daae5a5	215	__IO uint32_t RESETREAS; /!< Reset reason. /
Kojto	97:433970e64889	216	__I uint32_t RESERVED4[9];
Kojto	97:433970e64889	217	__I uint32_t RAMSTATUS; /!< Ram status register. /
Kojto	97:433970e64889	218	__I uint32_t RESERVED5[53];
bogdanm	92:4fc01daae5a5	219	__O uint32_t SYSTEMOFF; /!< System off register. /
Kojto	97:433970e64889	220	__I uint32_t RESERVED6[3];
bogdanm	92:4fc01daae5a5	221	__IO uint32_t POFCON; /!< Power failure configuration. /
Kojto	97:433970e64889	222	__I uint32_t RESERVED7[2];
bogdanm	92:4fc01daae5a5	223	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
bogdanm	92:4fc01daae5a5	224	register. */
Kojto	97:433970e64889	225	__I uint32_t RESERVED8;
bogdanm	92:4fc01daae5a5	226	__IO uint32_t RAMON; /!< Ram on/off. /
Kojto	97:433970e64889	227	__I uint32_t RESERVED9[7];
bogdanm	92:4fc01daae5a5	228	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
bogdanm	92:4fc01daae5a5	229	is a retained register. */
Kojto	97:433970e64889	230	__I uint32_t RESERVED10[3];
Kojto	97:433970e64889	231	__IO uint32_t RAMONB; /!< Ram on/off. /
Kojto	97:433970e64889	232	__I uint32_t RESERVED11[8];
bogdanm	92:4fc01daae5a5	233	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
Kojto	97:433970e64889	234	__I uint32_t RESERVED12[291];
Kojto	97:433970e64889	235	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
bogdanm	92:4fc01daae5a5	236	} NRF_POWER_Type;
bogdanm	92:4fc01daae5a5	237
bogdanm	92:4fc01daae5a5	238
bogdanm	92:4fc01daae5a5	239	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	240	/* ================ CLOCK ================ */
bogdanm	92:4fc01daae5a5	241	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	242
bogdanm	92:4fc01daae5a5	243
bogdanm	92:4fc01daae5a5	244	/**
bogdanm	92:4fc01daae5a5	245	* @brief Clock control. (CLOCK)
bogdanm	92:4fc01daae5a5	246	*/
bogdanm	92:4fc01daae5a5	247
bogdanm	92:4fc01daae5a5	248	typedef struct { /!< CLOCK Structure /
bogdanm	92:4fc01daae5a5	249	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
bogdanm	92:4fc01daae5a5	250	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
bogdanm	92:4fc01daae5a5	251	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
bogdanm	92:4fc01daae5a5	252	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
bogdanm	92:4fc01daae5a5	253	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
bogdanm	92:4fc01daae5a5	254	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
bogdanm	92:4fc01daae5a5	255	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
bogdanm	92:4fc01daae5a5	256	__I uint32_t RESERVED0[57];
bogdanm	92:4fc01daae5a5	257	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
bogdanm	92:4fc01daae5a5	258	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
bogdanm	92:4fc01daae5a5	259	__I uint32_t RESERVED1;
Kojto	97:433970e64889	260	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
Kojto	97:433970e64889	261	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
bogdanm	92:4fc01daae5a5	262	__I uint32_t RESERVED2[124];
bogdanm	92:4fc01daae5a5	263	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	264	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	97:433970e64889	265	__I uint32_t RESERVED3[63];
Kojto	97:433970e64889	266	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
bogdanm	92:4fc01daae5a5	267	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
Kojto	97:433970e64889	268	__I uint32_t RESERVED4;
Kojto	97:433970e64889	269	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
bogdanm	92:4fc01daae5a5	270	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
Kojto	97:433970e64889	271	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto	97:433970e64889	272	triggered. */
Kojto	97:433970e64889	273	__I uint32_t RESERVED5[62];
bogdanm	92:4fc01daae5a5	274	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
bogdanm	92:4fc01daae5a5	275	__I uint32_t RESERVED6[7];
bogdanm	92:4fc01daae5a5	276	__IO uint32_t CTIV; /!< Calibration timer interval. /
bogdanm	92:4fc01daae5a5	277	__I uint32_t RESERVED7[5];
bogdanm	92:4fc01daae5a5	278	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
bogdanm	92:4fc01daae5a5	279	} NRF_CLOCK_Type;
bogdanm	92:4fc01daae5a5	280
bogdanm	92:4fc01daae5a5	281
bogdanm	92:4fc01daae5a5	282	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	283	/* ================ MPU ================ */
bogdanm	92:4fc01daae5a5	284	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	285
bogdanm	92:4fc01daae5a5	286
bogdanm	92:4fc01daae5a5	287	/**
bogdanm	92:4fc01daae5a5	288	* @brief Memory Protection Unit. (MPU)
bogdanm	92:4fc01daae5a5	289	*/
bogdanm	92:4fc01daae5a5	290
bogdanm	92:4fc01daae5a5	291	typedef struct { /!< MPU Structure /
bogdanm	92:4fc01daae5a5	292	__I uint32_t RESERVED0[330];
bogdanm	92:4fc01daae5a5	293	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
bogdanm	92:4fc01daae5a5	294	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
bogdanm	92:4fc01daae5a5	295	__I uint32_t RESERVED1[52];
Kojto	97:433970e64889	296	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
Kojto	97:433970e64889	297	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
Kojto	97:433970e64889	298	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
Kojto	97:433970e64889	299	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
bogdanm	92:4fc01daae5a5	300	} NRF_MPU_Type;
bogdanm	92:4fc01daae5a5	301
bogdanm	92:4fc01daae5a5	302
bogdanm	92:4fc01daae5a5	303	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	304	/* ================ PU ================ */
bogdanm	92:4fc01daae5a5	305	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	306
bogdanm	92:4fc01daae5a5	307
bogdanm	92:4fc01daae5a5	308	/**
bogdanm	92:4fc01daae5a5	309	* @brief Patch unit. (PU)
bogdanm	92:4fc01daae5a5	310	*/
bogdanm	92:4fc01daae5a5	311
bogdanm	92:4fc01daae5a5	312	typedef struct { /!< PU Structure /
bogdanm	92:4fc01daae5a5	313	__I uint32_t RESERVED0[448];
bogdanm	92:4fc01daae5a5	314	__IO uint32_t REPLACEADDR[8]; /!< Address of first instruction to replace. /
bogdanm	92:4fc01daae5a5	315	__I uint32_t RESERVED1[24];
bogdanm	92:4fc01daae5a5	316	__IO uint32_t PATCHADDR[8]; /!< Relative address of patch instructions. /
bogdanm	92:4fc01daae5a5	317	__I uint32_t RESERVED2[24];
bogdanm	92:4fc01daae5a5	318	__IO uint32_t PATCHEN; /!< Patch enable register. /
bogdanm	92:4fc01daae5a5	319	__IO uint32_t PATCHENSET; /!< Patch enable register. /
bogdanm	92:4fc01daae5a5	320	__IO uint32_t PATCHENCLR; /!< Patch disable register. /
bogdanm	92:4fc01daae5a5	321	} NRF_PU_Type;
bogdanm	92:4fc01daae5a5	322
bogdanm	92:4fc01daae5a5	323
bogdanm	92:4fc01daae5a5	324	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	325	/* ================ AMLI ================ */
bogdanm	92:4fc01daae5a5	326	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	327
bogdanm	92:4fc01daae5a5	328
bogdanm	92:4fc01daae5a5	329	/**
bogdanm	92:4fc01daae5a5	330	* @brief AHB Multi-Layer Interface. (AMLI)
bogdanm	92:4fc01daae5a5	331	*/
bogdanm	92:4fc01daae5a5	332
bogdanm	92:4fc01daae5a5	333	typedef struct { /!< AMLI Structure /
bogdanm	92:4fc01daae5a5	334	__I uint32_t RESERVED0[896];
bogdanm	92:4fc01daae5a5	335	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
bogdanm	92:4fc01daae5a5	336	} NRF_AMLI_Type;
bogdanm	92:4fc01daae5a5	337
bogdanm	92:4fc01daae5a5	338
bogdanm	92:4fc01daae5a5	339	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	340	/* ================ RADIO ================ */
bogdanm	92:4fc01daae5a5	341	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	342
bogdanm	92:4fc01daae5a5	343
bogdanm	92:4fc01daae5a5	344	/**
bogdanm	92:4fc01daae5a5	345	* @brief The radio. (RADIO)
bogdanm	92:4fc01daae5a5	346	*/
bogdanm	92:4fc01daae5a5	347
bogdanm	92:4fc01daae5a5	348	typedef struct { /!< RADIO Structure /
bogdanm	92:4fc01daae5a5	349	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
bogdanm	92:4fc01daae5a5	350	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
bogdanm	92:4fc01daae5a5	351	__O uint32_t TASKS_START; /!< Start radio. /
bogdanm	92:4fc01daae5a5	352	__O uint32_t TASKS_STOP; /!< Stop radio. /
bogdanm	92:4fc01daae5a5	353	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
bogdanm	92:4fc01daae5a5	354	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
bogdanm	92:4fc01daae5a5	355	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
bogdanm	92:4fc01daae5a5	356	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
bogdanm	92:4fc01daae5a5	357	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
bogdanm	92:4fc01daae5a5	358	__I uint32_t RESERVED0[55];
bogdanm	92:4fc01daae5a5	359	__IO uint32_t EVENTS_READY; /!< Ready event. /
bogdanm	92:4fc01daae5a5	360	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
bogdanm	92:4fc01daae5a5	361	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
bogdanm	92:4fc01daae5a5	362	__IO uint32_t EVENTS_END; /!< End event. /
bogdanm	92:4fc01daae5a5	363	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
bogdanm	92:4fc01daae5a5	364	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
bogdanm	92:4fc01daae5a5	365	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
bogdanm	92:4fc01daae5a5	366	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
bogdanm	92:4fc01daae5a5	367	sample is ready for readout at the RSSISAMPLE register. */
bogdanm	92:4fc01daae5a5	368	__I uint32_t RESERVED1[2];
bogdanm	92:4fc01daae5a5	369	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BC register. /
bogdanm	92:4fc01daae5a5	370	__I uint32_t RESERVED2[53];
Kojto	97:433970e64889	371	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
bogdanm	92:4fc01daae5a5	372	__I uint32_t RESERVED3[64];
bogdanm	92:4fc01daae5a5	373	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	374	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	375	__I uint32_t RESERVED4[61];
bogdanm	92:4fc01daae5a5	376	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
Kojto	97:433970e64889	377	__I uint32_t CD; /!< Carrier detect. /
bogdanm	92:4fc01daae5a5	378	__I uint32_t RXMATCH; /!< Received address. /
bogdanm	92:4fc01daae5a5	379	__I uint32_t RXCRC; /!< Received CRC. /
Kojto	97:433970e64889	380	__I uint32_t DAI; /!< Device address match index. /
Kojto	97:433970e64889	381	__I uint32_t RESERVED5[60];
bogdanm	92:4fc01daae5a5	382	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
bogdanm	92:4fc01daae5a5	383	__IO uint32_t FREQUENCY; /!< Frequency. /
bogdanm	92:4fc01daae5a5	384	__IO uint32_t TXPOWER; /!< Output power. /
bogdanm	92:4fc01daae5a5	385	__IO uint32_t MODE; /!< Data rate and modulation. /
bogdanm	92:4fc01daae5a5	386	__IO uint32_t PCNF0; /!< Packet configuration 0. /
bogdanm	92:4fc01daae5a5	387	__IO uint32_t PCNF1; /!< Packet configuration 1. /
bogdanm	92:4fc01daae5a5	388	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
bogdanm	92:4fc01daae5a5	389	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
bogdanm	92:4fc01daae5a5	390	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
bogdanm	92:4fc01daae5a5	391	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
bogdanm	92:4fc01daae5a5	392	__IO uint32_t TXADDRESS; /!< Transmit address select. /
bogdanm	92:4fc01daae5a5	393	__IO uint32_t RXADDRESSES; /!< Receive address select. /
bogdanm	92:4fc01daae5a5	394	__IO uint32_t CRCCNF; /!< CRC configuration. /
bogdanm	92:4fc01daae5a5	395	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
bogdanm	92:4fc01daae5a5	396	__IO uint32_t CRCINIT; /!< CRC initial value. /
bogdanm	92:4fc01daae5a5	397	__IO uint32_t TEST; /!< Test features enable register. /
bogdanm	92:4fc01daae5a5	398	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
Kojto	97:433970e64889	399	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
Kojto	97:433970e64889	400	__I uint32_t RESERVED6;
bogdanm	92:4fc01daae5a5	401	__I uint32_t STATE; /!< Current radio state. /
bogdanm	92:4fc01daae5a5	402	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
Kojto	97:433970e64889	403	__I uint32_t RESERVED7[2];
bogdanm	92:4fc01daae5a5	404	__IO uint32_t BCC; /!< Bit counter compare. /
Kojto	97:433970e64889	405	__I uint32_t RESERVED8[39];
bogdanm	92:4fc01daae5a5	406	__IO uint32_t DAB[8]; /!< Device address base segment. /
bogdanm	92:4fc01daae5a5	407	__IO uint32_t DAP[8]; /!< Device address prefix. /
bogdanm	92:4fc01daae5a5	408	__IO uint32_t DACNF; /!< Device address match configuration. /
Kojto	97:433970e64889	409	__I uint32_t RESERVED9[56];
bogdanm	92:4fc01daae5a5	410	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
bogdanm	92:4fc01daae5a5	411	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
bogdanm	92:4fc01daae5a5	412	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
bogdanm	92:4fc01daae5a5	413	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
bogdanm	92:4fc01daae5a5	414	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
Kojto	97:433970e64889	415	__I uint32_t RESERVED10[561];
bogdanm	92:4fc01daae5a5	416	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	417	} NRF_RADIO_Type;
bogdanm	92:4fc01daae5a5	418
bogdanm	92:4fc01daae5a5	419
bogdanm	92:4fc01daae5a5	420	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	421	/* ================ UART ================ */
bogdanm	92:4fc01daae5a5	422	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	423
bogdanm	92:4fc01daae5a5	424
bogdanm	92:4fc01daae5a5	425	/**
bogdanm	92:4fc01daae5a5	426	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
bogdanm	92:4fc01daae5a5	427	*/
bogdanm	92:4fc01daae5a5	428
bogdanm	92:4fc01daae5a5	429	typedef struct { /!< UART Structure /
bogdanm	92:4fc01daae5a5	430	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
bogdanm	92:4fc01daae5a5	431	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
bogdanm	92:4fc01daae5a5	432	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
bogdanm	92:4fc01daae5a5	433	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
bogdanm	92:4fc01daae5a5	434	__I uint32_t RESERVED0[3];
bogdanm	92:4fc01daae5a5	435	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
bogdanm	92:4fc01daae5a5	436	__I uint32_t RESERVED1[56];
bogdanm	92:4fc01daae5a5	437	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
bogdanm	92:4fc01daae5a5	438	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
bogdanm	92:4fc01daae5a5	439	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
bogdanm	92:4fc01daae5a5	440	__I uint32_t RESERVED2[4];
bogdanm	92:4fc01daae5a5	441	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
bogdanm	92:4fc01daae5a5	442	__I uint32_t RESERVED3;
bogdanm	92:4fc01daae5a5	443	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
bogdanm	92:4fc01daae5a5	444	__I uint32_t RESERVED4[7];
bogdanm	92:4fc01daae5a5	445	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
bogdanm	92:4fc01daae5a5	446	__I uint32_t RESERVED5[46];
Kojto	97:433970e64889	447	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
Kojto	97:433970e64889	448	__I uint32_t RESERVED6[64];
bogdanm	92:4fc01daae5a5	449	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	450	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	451	__I uint32_t RESERVED7[93];
bogdanm	92:4fc01daae5a5	452	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
bogdanm	92:4fc01daae5a5	453	__I uint32_t RESERVED8[31];
bogdanm	92:4fc01daae5a5	454	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
bogdanm	92:4fc01daae5a5	455	__I uint32_t RESERVED9;
bogdanm	92:4fc01daae5a5	456	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
bogdanm	92:4fc01daae5a5	457	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
bogdanm	92:4fc01daae5a5	458	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
bogdanm	92:4fc01daae5a5	459	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
bogdanm	92:4fc01daae5a5	460	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto	97:433970e64889	461	Once read the character is consumed. If read when no character
bogdanm	92:4fc01daae5a5	462	available, the UART will stop working. */
bogdanm	92:4fc01daae5a5	463	__O uint32_t TXD; /!< TXD register. /
bogdanm	92:4fc01daae5a5	464	__I uint32_t RESERVED10;
bogdanm	92:4fc01daae5a5	465	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
bogdanm	92:4fc01daae5a5	466	__I uint32_t RESERVED11[17];
bogdanm	92:4fc01daae5a5	467	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
bogdanm	92:4fc01daae5a5	468	__I uint32_t RESERVED12[675];
bogdanm	92:4fc01daae5a5	469	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	470	} NRF_UART_Type;
bogdanm	92:4fc01daae5a5	471
bogdanm	92:4fc01daae5a5	472
bogdanm	92:4fc01daae5a5	473	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	474	/* ================ SPI ================ */
bogdanm	92:4fc01daae5a5	475	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	476
bogdanm	92:4fc01daae5a5	477
bogdanm	92:4fc01daae5a5	478	/**
bogdanm	92:4fc01daae5a5	479	* @brief SPI master 0. (SPI)
bogdanm	92:4fc01daae5a5	480	*/
bogdanm	92:4fc01daae5a5	481
bogdanm	92:4fc01daae5a5	482	typedef struct { /!< SPI Structure /
bogdanm	92:4fc01daae5a5	483	__I uint32_t RESERVED0[66];
bogdanm	92:4fc01daae5a5	484	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
bogdanm	92:4fc01daae5a5	485	__I uint32_t RESERVED1[126];
bogdanm	92:4fc01daae5a5	486	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	487	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	488	__I uint32_t RESERVED2[125];
bogdanm	92:4fc01daae5a5	489	__IO uint32_t ENABLE; /!< Enable SPI. /
bogdanm	92:4fc01daae5a5	490	__I uint32_t RESERVED3;
bogdanm	92:4fc01daae5a5	491	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
bogdanm	92:4fc01daae5a5	492	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
bogdanm	92:4fc01daae5a5	493	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
bogdanm	92:4fc01daae5a5	494	__I uint32_t RESERVED4;
Kojto	97:433970e64889	495	__I uint32_t RXD; /!< RX data. /
bogdanm	92:4fc01daae5a5	496	__IO uint32_t TXD; /!< TX data. /
bogdanm	92:4fc01daae5a5	497	__I uint32_t RESERVED5;
bogdanm	92:4fc01daae5a5	498	__IO uint32_t FREQUENCY; /!< SPI frequency /
bogdanm	92:4fc01daae5a5	499	__I uint32_t RESERVED6[11];
bogdanm	92:4fc01daae5a5	500	__IO uint32_t CONFIG; /!< Configuration register. /
bogdanm	92:4fc01daae5a5	501	__I uint32_t RESERVED7[681];
bogdanm	92:4fc01daae5a5	502	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	503	} NRF_SPI_Type;
bogdanm	92:4fc01daae5a5	504
bogdanm	92:4fc01daae5a5	505
bogdanm	92:4fc01daae5a5	506	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	507	/* ================ TWI ================ */
bogdanm	92:4fc01daae5a5	508	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	509
bogdanm	92:4fc01daae5a5	510
bogdanm	92:4fc01daae5a5	511	/**
bogdanm	92:4fc01daae5a5	512	* @brief Two-wire interface master 0. (TWI)
bogdanm	92:4fc01daae5a5	513	*/
bogdanm	92:4fc01daae5a5	514
bogdanm	92:4fc01daae5a5	515	typedef struct { /!< TWI Structure /
bogdanm	92:4fc01daae5a5	516	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
bogdanm	92:4fc01daae5a5	517	__I uint32_t RESERVED0;
bogdanm	92:4fc01daae5a5	518	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
bogdanm	92:4fc01daae5a5	519	__I uint32_t RESERVED1[2];
bogdanm	92:4fc01daae5a5	520	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
bogdanm	92:4fc01daae5a5	521	__I uint32_t RESERVED2;
bogdanm	92:4fc01daae5a5	522	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
bogdanm	92:4fc01daae5a5	523	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
bogdanm	92:4fc01daae5a5	524	__I uint32_t RESERVED3[56];
bogdanm	92:4fc01daae5a5	525	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
bogdanm	92:4fc01daae5a5	526	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
bogdanm	92:4fc01daae5a5	527	__I uint32_t RESERVED4[4];
bogdanm	92:4fc01daae5a5	528	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
bogdanm	92:4fc01daae5a5	529	__I uint32_t RESERVED5;
bogdanm	92:4fc01daae5a5	530	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
bogdanm	92:4fc01daae5a5	531	__I uint32_t RESERVED6[4];
bogdanm	92:4fc01daae5a5	532	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
Kojto	97:433970e64889	533	__I uint32_t RESERVED7[3];
Kojto	97:433970e64889	534	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
Kojto	97:433970e64889	535	__I uint32_t RESERVED8[45];
bogdanm	92:4fc01daae5a5	536	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
Kojto	97:433970e64889	537	__I uint32_t RESERVED9[64];
bogdanm	92:4fc01daae5a5	538	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	539	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	97:433970e64889	540	__I uint32_t RESERVED10[110];
bogdanm	92:4fc01daae5a5	541	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
Kojto	97:433970e64889	542	__I uint32_t RESERVED11[14];
bogdanm	92:4fc01daae5a5	543	__IO uint32_t ENABLE; /!< Enable two-wire master. /
Kojto	97:433970e64889	544	__I uint32_t RESERVED12;
bogdanm	92:4fc01daae5a5	545	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
bogdanm	92:4fc01daae5a5	546	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
Kojto	97:433970e64889	547	__I uint32_t RESERVED13[2];
Kojto	97:433970e64889	548	__I uint32_t RXD; /!< RX data register. /
bogdanm	92:4fc01daae5a5	549	__IO uint32_t TXD; /!< TX data register. /
Kojto	97:433970e64889	550	__I uint32_t RESERVED14;
bogdanm	92:4fc01daae5a5	551	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
Kojto	97:433970e64889	552	__I uint32_t RESERVED15[24];
bogdanm	92:4fc01daae5a5	553	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
Kojto	97:433970e64889	554	__I uint32_t RESERVED16[668];
bogdanm	92:4fc01daae5a5	555	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	556	} NRF_TWI_Type;
bogdanm	92:4fc01daae5a5	557
bogdanm	92:4fc01daae5a5	558
bogdanm	92:4fc01daae5a5	559	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	560	/* ================ SPIS ================ */
bogdanm	92:4fc01daae5a5	561	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	562
bogdanm	92:4fc01daae5a5	563
bogdanm	92:4fc01daae5a5	564	/**
bogdanm	92:4fc01daae5a5	565	* @brief SPI slave 1. (SPIS)
bogdanm	92:4fc01daae5a5	566	*/
bogdanm	92:4fc01daae5a5	567
bogdanm	92:4fc01daae5a5	568	typedef struct { /!< SPIS Structure /
bogdanm	92:4fc01daae5a5	569	__I uint32_t RESERVED0[9];
bogdanm	92:4fc01daae5a5	570	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
bogdanm	92:4fc01daae5a5	571	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
bogdanm	92:4fc01daae5a5	572	__I uint32_t RESERVED1[54];
bogdanm	92:4fc01daae5a5	573	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
bogdanm	92:4fc01daae5a5	574	__I uint32_t RESERVED2[8];
bogdanm	92:4fc01daae5a5	575	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
bogdanm	92:4fc01daae5a5	576	__I uint32_t RESERVED3[53];
bogdanm	92:4fc01daae5a5	577	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
bogdanm	92:4fc01daae5a5	578	__I uint32_t RESERVED4[64];
bogdanm	92:4fc01daae5a5	579	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	580	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	581	__I uint32_t RESERVED5[61];
bogdanm	92:4fc01daae5a5	582	__I uint32_t SEMSTAT; /!< Semaphore status. /
bogdanm	92:4fc01daae5a5	583	__I uint32_t RESERVED6[15];
bogdanm	92:4fc01daae5a5	584	__IO uint32_t STATUS; /!< Status from last transaction. /
bogdanm	92:4fc01daae5a5	585	__I uint32_t RESERVED7[47];
bogdanm	92:4fc01daae5a5	586	__IO uint32_t ENABLE; /!< Enable SPIS. /
bogdanm	92:4fc01daae5a5	587	__I uint32_t RESERVED8;
bogdanm	92:4fc01daae5a5	588	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
bogdanm	92:4fc01daae5a5	589	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
bogdanm	92:4fc01daae5a5	590	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
bogdanm	92:4fc01daae5a5	591	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
bogdanm	92:4fc01daae5a5	592	__I uint32_t RESERVED9[7];
bogdanm	92:4fc01daae5a5	593	__IO uint32_t RXDPTR; /!< RX data pointer. /
bogdanm	92:4fc01daae5a5	594	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
Kojto	97:433970e64889	595	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
bogdanm	92:4fc01daae5a5	596	__I uint32_t RESERVED10;
bogdanm	92:4fc01daae5a5	597	__IO uint32_t TXDPTR; /!< TX data pointer. /
bogdanm	92:4fc01daae5a5	598	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
Kojto	97:433970e64889	599	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
bogdanm	92:4fc01daae5a5	600	__I uint32_t RESERVED11;
bogdanm	92:4fc01daae5a5	601	__IO uint32_t CONFIG; /!< Configuration register. /
bogdanm	92:4fc01daae5a5	602	__I uint32_t RESERVED12;
bogdanm	92:4fc01daae5a5	603	__IO uint32_t DEF; /!< Default character. /
bogdanm	92:4fc01daae5a5	604	__I uint32_t RESERVED13[24];
bogdanm	92:4fc01daae5a5	605	__IO uint32_t ORC; /!< Over-read character. /
bogdanm	92:4fc01daae5a5	606	__I uint32_t RESERVED14[654];
bogdanm	92:4fc01daae5a5	607	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	608	} NRF_SPIS_Type;
bogdanm	92:4fc01daae5a5	609
bogdanm	92:4fc01daae5a5	610
bogdanm	92:4fc01daae5a5	611	/* ================================================================================ */
Kojto	97:433970e64889	612	/* ================ SPIM ================ */
Kojto	97:433970e64889	613	/* ================================================================================ */
Kojto	97:433970e64889	614
Kojto	97:433970e64889	615
Kojto	97:433970e64889	616	/**
Kojto	97:433970e64889	617	* @brief SPI master with easyDMA 1. (SPIM)
Kojto	97:433970e64889	618	*/
Kojto	97:433970e64889	619
Kojto	97:433970e64889	620	typedef struct { /!< SPIM Structure /
Kojto	97:433970e64889	621	__I uint32_t RESERVED0[4];
Kojto	97:433970e64889	622	__O uint32_t TASKS_START; /!< Start SPI transaction. /
Kojto	97:433970e64889	623	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
Kojto	97:433970e64889	624	__I uint32_t RESERVED1;
Kojto	97:433970e64889	625	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
Kojto	97:433970e64889	626	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
Kojto	97:433970e64889	627	__I uint32_t RESERVED2[56];
Kojto	97:433970e64889	628	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
Kojto	97:433970e64889	629	__I uint32_t RESERVED3[2];
Kojto	97:433970e64889	630	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
Kojto	97:433970e64889	631	__I uint32_t RESERVED4;
Kojto	97:433970e64889	632	__IO uint32_t EVENTS_END; /!< End of RXD buffer and TXD buffer reached. /
Kojto	97:433970e64889	633	__I uint32_t RESERVED5;
Kojto	97:433970e64889	634	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
Kojto	97:433970e64889	635	__I uint32_t RESERVED6[10];
Kojto	97:433970e64889	636	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
Kojto	97:433970e64889	637	__I uint32_t RESERVED7[44];
Kojto	97:433970e64889	638	__IO uint32_t SHORTS; /!< Shortcuts for SPIM. /
Kojto	97:433970e64889	639	__I uint32_t RESERVED8[64];
Kojto	97:433970e64889	640	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	97:433970e64889	641	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	97:433970e64889	642	__I uint32_t RESERVED9[125];
Kojto	97:433970e64889	643	__IO uint32_t ENABLE; /!< Enable SPIM. /
Kojto	97:433970e64889	644	__I uint32_t RESERVED10;
Kojto	97:433970e64889	645	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
Kojto	97:433970e64889	646	__I uint32_t RESERVED11;
Kojto	97:433970e64889	647	__I uint32_t RXDDATA; /!< RXD register. /
Kojto	97:433970e64889	648	__IO uint32_t TXDDATA; /!< TXD register. /
Kojto	97:433970e64889	649	__I uint32_t RESERVED12;
Kojto	97:433970e64889	650	__IO uint32_t FREQUENCY; /!< SPI frequency. /
Kojto	97:433970e64889	651	__I uint32_t RESERVED13[3];
Kojto	97:433970e64889	652	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
Kojto	97:433970e64889	653	__I uint32_t RESERVED14;
Kojto	97:433970e64889	654	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
Kojto	97:433970e64889	655	__I uint32_t RESERVED15;
Kojto	97:433970e64889	656	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	97:433970e64889	657	__I uint32_t RESERVED16[26];
Kojto	97:433970e64889	658	__IO uint32_t ORC; /!< Over-read character. /
Kojto	97:433970e64889	659	__I uint32_t RESERVED17[654];
Kojto	97:433970e64889	660	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	97:433970e64889	661	} NRF_SPIM_Type;
Kojto	97:433970e64889	662
Kojto	97:433970e64889	663
Kojto	97:433970e64889	664	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	665	/* ================ GPIOTE ================ */
bogdanm	92:4fc01daae5a5	666	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	667
bogdanm	92:4fc01daae5a5	668
bogdanm	92:4fc01daae5a5	669	/**
bogdanm	92:4fc01daae5a5	670	* @brief GPIO tasks and events. (GPIOTE)
bogdanm	92:4fc01daae5a5	671	*/
bogdanm	92:4fc01daae5a5	672
bogdanm	92:4fc01daae5a5	673	typedef struct { /!< GPIOTE Structure /
bogdanm	92:4fc01daae5a5	674	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
bogdanm	92:4fc01daae5a5	675	__I uint32_t RESERVED0[60];
bogdanm	92:4fc01daae5a5	676	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
bogdanm	92:4fc01daae5a5	677	__I uint32_t RESERVED1[27];
bogdanm	92:4fc01daae5a5	678	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
bogdanm	92:4fc01daae5a5	679	__I uint32_t RESERVED2[97];
bogdanm	92:4fc01daae5a5	680	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	681	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	682	__I uint32_t RESERVED3[129];
bogdanm	92:4fc01daae5a5	683	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
bogdanm	92:4fc01daae5a5	684	__I uint32_t RESERVED4[695];
bogdanm	92:4fc01daae5a5	685	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	686	} NRF_GPIOTE_Type;
bogdanm	92:4fc01daae5a5	687
bogdanm	92:4fc01daae5a5	688
bogdanm	92:4fc01daae5a5	689	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	690	/* ================ ADC ================ */
bogdanm	92:4fc01daae5a5	691	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	692
bogdanm	92:4fc01daae5a5	693
bogdanm	92:4fc01daae5a5	694	/**
bogdanm	92:4fc01daae5a5	695	* @brief Analog to digital converter. (ADC)
bogdanm	92:4fc01daae5a5	696	*/
bogdanm	92:4fc01daae5a5	697
bogdanm	92:4fc01daae5a5	698	typedef struct { /!< ADC Structure /
bogdanm	92:4fc01daae5a5	699	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
bogdanm	92:4fc01daae5a5	700	__O uint32_t TASKS_STOP; /!< Stop ADC. /
bogdanm	92:4fc01daae5a5	701	__I uint32_t RESERVED0[62];
bogdanm	92:4fc01daae5a5	702	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
bogdanm	92:4fc01daae5a5	703	__I uint32_t RESERVED1[128];
bogdanm	92:4fc01daae5a5	704	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	705	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	706	__I uint32_t RESERVED2[61];
bogdanm	92:4fc01daae5a5	707	__I uint32_t BUSY; /!< ADC busy register. /
bogdanm	92:4fc01daae5a5	708	__I uint32_t RESERVED3[63];
bogdanm	92:4fc01daae5a5	709	__IO uint32_t ENABLE; /!< ADC enable. /
bogdanm	92:4fc01daae5a5	710	__IO uint32_t CONFIG; /!< ADC configuration register. /
bogdanm	92:4fc01daae5a5	711	__I uint32_t RESULT; /!< Result of ADC conversion. /
bogdanm	92:4fc01daae5a5	712	__I uint32_t RESERVED4[700];
bogdanm	92:4fc01daae5a5	713	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	714	} NRF_ADC_Type;
bogdanm	92:4fc01daae5a5	715
bogdanm	92:4fc01daae5a5	716
bogdanm	92:4fc01daae5a5	717	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	718	/* ================ TIMER ================ */
bogdanm	92:4fc01daae5a5	719	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	720
bogdanm	92:4fc01daae5a5	721
bogdanm	92:4fc01daae5a5	722	/**
bogdanm	92:4fc01daae5a5	723	* @brief Timer 0. (TIMER)
bogdanm	92:4fc01daae5a5	724	*/
bogdanm	92:4fc01daae5a5	725
bogdanm	92:4fc01daae5a5	726	typedef struct { /!< TIMER Structure /
bogdanm	92:4fc01daae5a5	727	__O uint32_t TASKS_START; /!< Start Timer. /
bogdanm	92:4fc01daae5a5	728	__O uint32_t TASKS_STOP; /!< Stop Timer. /
bogdanm	92:4fc01daae5a5	729	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
bogdanm	92:4fc01daae5a5	730	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
Kojto	97:433970e64889	731	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
Kojto	97:433970e64889	732	__I uint32_t RESERVED0[11];
bogdanm	92:4fc01daae5a5	733	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
bogdanm	92:4fc01daae5a5	734	__I uint32_t RESERVED1[60];
bogdanm	92:4fc01daae5a5	735	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
bogdanm	92:4fc01daae5a5	736	__I uint32_t RESERVED2[44];
bogdanm	92:4fc01daae5a5	737	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
bogdanm	92:4fc01daae5a5	738	__I uint32_t RESERVED3[64];
bogdanm	92:4fc01daae5a5	739	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	740	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	741	__I uint32_t RESERVED4[126];
bogdanm	92:4fc01daae5a5	742	__IO uint32_t MODE; /!< Timer Mode selection. /
bogdanm	92:4fc01daae5a5	743	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
bogdanm	92:4fc01daae5a5	744	__I uint32_t RESERVED5;
bogdanm	92:4fc01daae5a5	745	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
bogdanm	92:4fc01daae5a5	746	clock frequency is divided by 2^SCALE. */
bogdanm	92:4fc01daae5a5	747	__I uint32_t RESERVED6[11];
bogdanm	92:4fc01daae5a5	748	__IO uint32_t CC[4]; /!< Capture/compare registers. /
bogdanm	92:4fc01daae5a5	749	__I uint32_t RESERVED7[683];
bogdanm	92:4fc01daae5a5	750	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	751	} NRF_TIMER_Type;
bogdanm	92:4fc01daae5a5	752
bogdanm	92:4fc01daae5a5	753
bogdanm	92:4fc01daae5a5	754	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	755	/* ================ RTC ================ */
bogdanm	92:4fc01daae5a5	756	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	757
bogdanm	92:4fc01daae5a5	758
bogdanm	92:4fc01daae5a5	759	/**
bogdanm	92:4fc01daae5a5	760	* @brief Real time counter 0. (RTC)
bogdanm	92:4fc01daae5a5	761	*/
bogdanm	92:4fc01daae5a5	762
bogdanm	92:4fc01daae5a5	763	typedef struct { /!< RTC Structure /
bogdanm	92:4fc01daae5a5	764	__O uint32_t TASKS_START; /!< Start RTC Counter. /
bogdanm	92:4fc01daae5a5	765	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
bogdanm	92:4fc01daae5a5	766	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
bogdanm	92:4fc01daae5a5	767	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
bogdanm	92:4fc01daae5a5	768	__I uint32_t RESERVED0[60];
bogdanm	92:4fc01daae5a5	769	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
bogdanm	92:4fc01daae5a5	770	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
bogdanm	92:4fc01daae5a5	771	__I uint32_t RESERVED1[14];
bogdanm	92:4fc01daae5a5	772	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
bogdanm	92:4fc01daae5a5	773	__I uint32_t RESERVED2[109];
bogdanm	92:4fc01daae5a5	774	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	775	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	776	__I uint32_t RESERVED3[13];
bogdanm	92:4fc01daae5a5	777	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
bogdanm	92:4fc01daae5a5	778	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
bogdanm	92:4fc01daae5a5	779	the value of EVTEN. */
bogdanm	92:4fc01daae5a5	780	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
bogdanm	92:4fc01daae5a5	781	gives the value of EVTEN. */
bogdanm	92:4fc01daae5a5	782	__I uint32_t RESERVED4[110];
Kojto	97:433970e64889	783	__I uint32_t COUNTER; /!< Current COUNTER value. /
bogdanm	92:4fc01daae5a5	784	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
bogdanm	92:4fc01daae5a5	785	Must be written when RTC is STOPed. */
bogdanm	92:4fc01daae5a5	786	__I uint32_t RESERVED5[13];
bogdanm	92:4fc01daae5a5	787	__IO uint32_t CC[4]; /!< Capture/compare registers. /
bogdanm	92:4fc01daae5a5	788	__I uint32_t RESERVED6[683];
bogdanm	92:4fc01daae5a5	789	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	790	} NRF_RTC_Type;
bogdanm	92:4fc01daae5a5	791
bogdanm	92:4fc01daae5a5	792
bogdanm	92:4fc01daae5a5	793	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	794	/* ================ TEMP ================ */
bogdanm	92:4fc01daae5a5	795	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	796
bogdanm	92:4fc01daae5a5	797
bogdanm	92:4fc01daae5a5	798	/**
bogdanm	92:4fc01daae5a5	799	* @brief Temperature Sensor. (TEMP)
bogdanm	92:4fc01daae5a5	800	*/
bogdanm	92:4fc01daae5a5	801
bogdanm	92:4fc01daae5a5	802	typedef struct { /!< TEMP Structure /
bogdanm	92:4fc01daae5a5	803	__O uint32_t TASKS_START; /!< Start temperature measurement. /
bogdanm	92:4fc01daae5a5	804	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
bogdanm	92:4fc01daae5a5	805	__I uint32_t RESERVED0[62];
bogdanm	92:4fc01daae5a5	806	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
bogdanm	92:4fc01daae5a5	807	__I uint32_t RESERVED1[128];
bogdanm	92:4fc01daae5a5	808	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	809	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	810	__I uint32_t RESERVED2[127];
bogdanm	92:4fc01daae5a5	811	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
bogdanm	92:4fc01daae5a5	812	__I uint32_t RESERVED3[700];
bogdanm	92:4fc01daae5a5	813	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	814	} NRF_TEMP_Type;
bogdanm	92:4fc01daae5a5	815
bogdanm	92:4fc01daae5a5	816
bogdanm	92:4fc01daae5a5	817	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	818	/* ================ RNG ================ */
bogdanm	92:4fc01daae5a5	819	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	820
bogdanm	92:4fc01daae5a5	821
bogdanm	92:4fc01daae5a5	822	/**
bogdanm	92:4fc01daae5a5	823	* @brief Random Number Generator. (RNG)
bogdanm	92:4fc01daae5a5	824	*/
bogdanm	92:4fc01daae5a5	825
bogdanm	92:4fc01daae5a5	826	typedef struct { /!< RNG Structure /
bogdanm	92:4fc01daae5a5	827	__O uint32_t TASKS_START; /!< Start the random number generator. /
bogdanm	92:4fc01daae5a5	828	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
bogdanm	92:4fc01daae5a5	829	__I uint32_t RESERVED0[62];
bogdanm	92:4fc01daae5a5	830	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
bogdanm	92:4fc01daae5a5	831	__I uint32_t RESERVED1[63];
Kojto	97:433970e64889	832	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
bogdanm	92:4fc01daae5a5	833	__I uint32_t RESERVED2[64];
bogdanm	92:4fc01daae5a5	834	__IO uint32_t INTENSET; /!< Interrupt enable set register /
bogdanm	92:4fc01daae5a5	835	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
bogdanm	92:4fc01daae5a5	836	__I uint32_t RESERVED3[126];
bogdanm	92:4fc01daae5a5	837	__IO uint32_t CONFIG; /!< Configuration register. /
bogdanm	92:4fc01daae5a5	838	__I uint32_t VALUE; /!< RNG random number. /
bogdanm	92:4fc01daae5a5	839	__I uint32_t RESERVED4[700];
bogdanm	92:4fc01daae5a5	840	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	841	} NRF_RNG_Type;
bogdanm	92:4fc01daae5a5	842
bogdanm	92:4fc01daae5a5	843
bogdanm	92:4fc01daae5a5	844	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	845	/* ================ ECB ================ */
bogdanm	92:4fc01daae5a5	846	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	847
bogdanm	92:4fc01daae5a5	848
bogdanm	92:4fc01daae5a5	849	/**
bogdanm	92:4fc01daae5a5	850	* @brief AES ECB Mode Encryption. (ECB)
bogdanm	92:4fc01daae5a5	851	*/
bogdanm	92:4fc01daae5a5	852
bogdanm	92:4fc01daae5a5	853	typedef struct { /!< ECB Structure /
bogdanm	92:4fc01daae5a5	854	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
bogdanm	92:4fc01daae5a5	855	will not initiate a new encryption and the ERRORECB event will
bogdanm	92:4fc01daae5a5	856	be triggered. */
bogdanm	92:4fc01daae5a5	857	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
bogdanm	92:4fc01daae5a5	858	this will will trigger the ERRORECB event. */
bogdanm	92:4fc01daae5a5	859	__I uint32_t RESERVED0[62];
bogdanm	92:4fc01daae5a5	860	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
bogdanm	92:4fc01daae5a5	861	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
bogdanm	92:4fc01daae5a5	862	error. */
bogdanm	92:4fc01daae5a5	863	__I uint32_t RESERVED1[127];
bogdanm	92:4fc01daae5a5	864	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	865	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	866	__I uint32_t RESERVED2[126];
bogdanm	92:4fc01daae5a5	867	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
bogdanm	92:4fc01daae5a5	868	__I uint32_t RESERVED3[701];
bogdanm	92:4fc01daae5a5	869	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	870	} NRF_ECB_Type;
bogdanm	92:4fc01daae5a5	871
bogdanm	92:4fc01daae5a5	872
bogdanm	92:4fc01daae5a5	873	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	874	/* ================ AAR ================ */
bogdanm	92:4fc01daae5a5	875	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	876
bogdanm	92:4fc01daae5a5	877
bogdanm	92:4fc01daae5a5	878	/**
bogdanm	92:4fc01daae5a5	879	* @brief Accelerated Address Resolver. (AAR)
bogdanm	92:4fc01daae5a5	880	*/
bogdanm	92:4fc01daae5a5	881
bogdanm	92:4fc01daae5a5	882	typedef struct { /!< AAR Structure /
bogdanm	92:4fc01daae5a5	883	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
bogdanm	92:4fc01daae5a5	884	data structure. */
bogdanm	92:4fc01daae5a5	885	__I uint32_t RESERVED0;
bogdanm	92:4fc01daae5a5	886	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
bogdanm	92:4fc01daae5a5	887	__I uint32_t RESERVED1[61];
bogdanm	92:4fc01daae5a5	888	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
bogdanm	92:4fc01daae5a5	889	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
bogdanm	92:4fc01daae5a5	890	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
bogdanm	92:4fc01daae5a5	891	__I uint32_t RESERVED2[126];
bogdanm	92:4fc01daae5a5	892	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	893	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	894	__I uint32_t RESERVED3[61];
bogdanm	92:4fc01daae5a5	895	__I uint32_t STATUS; /!< Resolution status. /
bogdanm	92:4fc01daae5a5	896	__I uint32_t RESERVED4[63];
bogdanm	92:4fc01daae5a5	897	__IO uint32_t ENABLE; /!< Enable AAR. /
bogdanm	92:4fc01daae5a5	898	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
bogdanm	92:4fc01daae5a5	899	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
bogdanm	92:4fc01daae5a5	900	__I uint32_t RESERVED5;
bogdanm	92:4fc01daae5a5	901	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
Kojto	97:433970e64889	902	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto	97:433970e64889	903	during resolution. A minimum of 3 bytes must be reserved. */
bogdanm	92:4fc01daae5a5	904	__I uint32_t RESERVED6[697];
bogdanm	92:4fc01daae5a5	905	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	906	} NRF_AAR_Type;
bogdanm	92:4fc01daae5a5	907
bogdanm	92:4fc01daae5a5	908
bogdanm	92:4fc01daae5a5	909	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	910	/* ================ CCM ================ */
bogdanm	92:4fc01daae5a5	911	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	912
bogdanm	92:4fc01daae5a5	913
bogdanm	92:4fc01daae5a5	914	/**
bogdanm	92:4fc01daae5a5	915	* @brief AES CCM Mode Encryption. (CCM)
bogdanm	92:4fc01daae5a5	916	*/
bogdanm	92:4fc01daae5a5	917
bogdanm	92:4fc01daae5a5	918	typedef struct { /!< CCM Structure /
bogdanm	92:4fc01daae5a5	919	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
bogdanm	92:4fc01daae5a5	920	itself when completed. */
bogdanm	92:4fc01daae5a5	921	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
bogdanm	92:4fc01daae5a5	922	completed. */
bogdanm	92:4fc01daae5a5	923	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
bogdanm	92:4fc01daae5a5	924	__I uint32_t RESERVED0[61];
bogdanm	92:4fc01daae5a5	925	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
bogdanm	92:4fc01daae5a5	926	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
bogdanm	92:4fc01daae5a5	927	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
bogdanm	92:4fc01daae5a5	928	__I uint32_t RESERVED1[61];
Kojto	97:433970e64889	929	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
bogdanm	92:4fc01daae5a5	930	__I uint32_t RESERVED2[64];
bogdanm	92:4fc01daae5a5	931	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	932	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	933	__I uint32_t RESERVED3[61];
bogdanm	92:4fc01daae5a5	934	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
bogdanm	92:4fc01daae5a5	935	__I uint32_t RESERVED4[63];
bogdanm	92:4fc01daae5a5	936	__IO uint32_t ENABLE; /!< CCM enable. /
bogdanm	92:4fc01daae5a5	937	__IO uint32_t MODE; /!< Operation mode. /
Kojto	97:433970e64889	938	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
Kojto	97:433970e64889	939	__IO uint32_t INPTR; /!< Pointer to the input packet. /
Kojto	97:433970e64889	940	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
Kojto	97:433970e64889	941	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto	97:433970e64889	942	during resolution. A minimum of 43 bytes must be reserved. */
bogdanm	92:4fc01daae5a5	943	__I uint32_t RESERVED5[697];
bogdanm	92:4fc01daae5a5	944	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	945	} NRF_CCM_Type;
bogdanm	92:4fc01daae5a5	946
bogdanm	92:4fc01daae5a5	947
bogdanm	92:4fc01daae5a5	948	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	949	/* ================ WDT ================ */
bogdanm	92:4fc01daae5a5	950	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	951
bogdanm	92:4fc01daae5a5	952
bogdanm	92:4fc01daae5a5	953	/**
bogdanm	92:4fc01daae5a5	954	* @brief Watchdog Timer. (WDT)
bogdanm	92:4fc01daae5a5	955	*/
bogdanm	92:4fc01daae5a5	956
bogdanm	92:4fc01daae5a5	957	typedef struct { /!< WDT Structure /
bogdanm	92:4fc01daae5a5	958	__O uint32_t TASKS_START; /!< Start the watchdog. /
bogdanm	92:4fc01daae5a5	959	__I uint32_t RESERVED0[63];
bogdanm	92:4fc01daae5a5	960	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
bogdanm	92:4fc01daae5a5	961	__I uint32_t RESERVED1[128];
bogdanm	92:4fc01daae5a5	962	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	963	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	964	__I uint32_t RESERVED2[61];
bogdanm	92:4fc01daae5a5	965	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
bogdanm	92:4fc01daae5a5	966	__I uint32_t REQSTATUS; /!< Request status. /
bogdanm	92:4fc01daae5a5	967	__I uint32_t RESERVED3[63];
bogdanm	92:4fc01daae5a5	968	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
bogdanm	92:4fc01daae5a5	969	__IO uint32_t RREN; /!< Reload request enable. /
bogdanm	92:4fc01daae5a5	970	__IO uint32_t CONFIG; /!< Configuration register. /
bogdanm	92:4fc01daae5a5	971	__I uint32_t RESERVED4[60];
bogdanm	92:4fc01daae5a5	972	__O uint32_t RR[8]; /!< Reload requests registers. /
bogdanm	92:4fc01daae5a5	973	__I uint32_t RESERVED5[631];
bogdanm	92:4fc01daae5a5	974	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	975	} NRF_WDT_Type;
bogdanm	92:4fc01daae5a5	976
bogdanm	92:4fc01daae5a5	977
bogdanm	92:4fc01daae5a5	978	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	979	/* ================ QDEC ================ */
bogdanm	92:4fc01daae5a5	980	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	981
bogdanm	92:4fc01daae5a5	982
bogdanm	92:4fc01daae5a5	983	/**
bogdanm	92:4fc01daae5a5	984	* @brief Rotary decoder. (QDEC)
bogdanm	92:4fc01daae5a5	985	*/
bogdanm	92:4fc01daae5a5	986
bogdanm	92:4fc01daae5a5	987	typedef struct { /!< QDEC Structure /
bogdanm	92:4fc01daae5a5	988	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
bogdanm	92:4fc01daae5a5	989	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
bogdanm	92:4fc01daae5a5	990	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
bogdanm	92:4fc01daae5a5	991	and clears the ACC registers. */
bogdanm	92:4fc01daae5a5	992	__I uint32_t RESERVED0[61];
bogdanm	92:4fc01daae5a5	993	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
bogdanm	92:4fc01daae5a5	994	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
bogdanm	92:4fc01daae5a5	995	ACC register different than zero. */
bogdanm	92:4fc01daae5a5	996	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
bogdanm	92:4fc01daae5a5	997	__I uint32_t RESERVED1[61];
Kojto	97:433970e64889	998	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
bogdanm	92:4fc01daae5a5	999	__I uint32_t RESERVED2[64];
bogdanm	92:4fc01daae5a5	1000	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	1001	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	1002	__I uint32_t RESERVED3[125];
bogdanm	92:4fc01daae5a5	1003	__IO uint32_t ENABLE; /!< Enable the QDEC. /
bogdanm	92:4fc01daae5a5	1004	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
bogdanm	92:4fc01daae5a5	1005	__IO uint32_t SAMPLEPER; /!< Sample period. /
bogdanm	92:4fc01daae5a5	1006	__I int32_t SAMPLE; /!< Motion sample value. /
bogdanm	92:4fc01daae5a5	1007	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
bogdanm	92:4fc01daae5a5	1008	__I int32_t ACC; /!< Accumulated valid transitions register. /
bogdanm	92:4fc01daae5a5	1009	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
bogdanm	92:4fc01daae5a5	1010	task. */
bogdanm	92:4fc01daae5a5	1011	__IO uint32_t PSELLED; /!< Pin select for LED output. /
bogdanm	92:4fc01daae5a5	1012	__IO uint32_t PSELA; /!< Pin select for phase A input. /
bogdanm	92:4fc01daae5a5	1013	__IO uint32_t PSELB; /!< Pin select for phase B input. /
bogdanm	92:4fc01daae5a5	1014	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
bogdanm	92:4fc01daae5a5	1015	__I uint32_t RESERVED4[5];
bogdanm	92:4fc01daae5a5	1016	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
bogdanm	92:4fc01daae5a5	1017	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
bogdanm	92:4fc01daae5a5	1018	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
bogdanm	92:4fc01daae5a5	1019	task. */
bogdanm	92:4fc01daae5a5	1020	__I uint32_t RESERVED5[684];
bogdanm	92:4fc01daae5a5	1021	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	1022	} NRF_QDEC_Type;
bogdanm	92:4fc01daae5a5	1023
bogdanm	92:4fc01daae5a5	1024
bogdanm	92:4fc01daae5a5	1025	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1026	/* ================ LPCOMP ================ */
bogdanm	92:4fc01daae5a5	1027	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1028
bogdanm	92:4fc01daae5a5	1029
bogdanm	92:4fc01daae5a5	1030	/**
Kojto	97:433970e64889	1031	* @brief Low power comparator. (LPCOMP)
bogdanm	92:4fc01daae5a5	1032	*/
bogdanm	92:4fc01daae5a5	1033
bogdanm	92:4fc01daae5a5	1034	typedef struct { /!< LPCOMP Structure /
bogdanm	92:4fc01daae5a5	1035	__O uint32_t TASKS_START; /!< Start the comparator. /
bogdanm	92:4fc01daae5a5	1036	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
bogdanm	92:4fc01daae5a5	1037	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
bogdanm	92:4fc01daae5a5	1038	__I uint32_t RESERVED0[61];
bogdanm	92:4fc01daae5a5	1039	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
bogdanm	92:4fc01daae5a5	1040	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
bogdanm	92:4fc01daae5a5	1041	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
bogdanm	92:4fc01daae5a5	1042	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
bogdanm	92:4fc01daae5a5	1043	__I uint32_t RESERVED1[60];
Kojto	97:433970e64889	1044	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
bogdanm	92:4fc01daae5a5	1045	__I uint32_t RESERVED2[64];
bogdanm	92:4fc01daae5a5	1046	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
bogdanm	92:4fc01daae5a5	1047	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
bogdanm	92:4fc01daae5a5	1048	__I uint32_t RESERVED3[61];
bogdanm	92:4fc01daae5a5	1049	__I uint32_t RESULT; /!< Result of last compare. /
bogdanm	92:4fc01daae5a5	1050	__I uint32_t RESERVED4[63];
bogdanm	92:4fc01daae5a5	1051	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
bogdanm	92:4fc01daae5a5	1052	__IO uint32_t PSEL; /!< Input pin select. /
bogdanm	92:4fc01daae5a5	1053	__IO uint32_t REFSEL; /!< Reference select. /
bogdanm	92:4fc01daae5a5	1054	__IO uint32_t EXTREFSEL; /!< External reference select. /
bogdanm	92:4fc01daae5a5	1055	__I uint32_t RESERVED5[4];
bogdanm	92:4fc01daae5a5	1056	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
bogdanm	92:4fc01daae5a5	1057	__I uint32_t RESERVED6[694];
bogdanm	92:4fc01daae5a5	1058	__IO uint32_t POWER; /!< Peripheral power control. /
bogdanm	92:4fc01daae5a5	1059	} NRF_LPCOMP_Type;
bogdanm	92:4fc01daae5a5	1060
bogdanm	92:4fc01daae5a5	1061
bogdanm	92:4fc01daae5a5	1062	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1063	/* ================ SWI ================ */
bogdanm	92:4fc01daae5a5	1064	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1065
bogdanm	92:4fc01daae5a5	1066
bogdanm	92:4fc01daae5a5	1067	/**
bogdanm	92:4fc01daae5a5	1068	* @brief SW Interrupts. (SWI)
bogdanm	92:4fc01daae5a5	1069	*/
bogdanm	92:4fc01daae5a5	1070
bogdanm	92:4fc01daae5a5	1071	typedef struct { /!< SWI Structure /
bogdanm	92:4fc01daae5a5	1072	__I uint32_t UNUSED; /!< Unused. /
bogdanm	92:4fc01daae5a5	1073	} NRF_SWI_Type;
bogdanm	92:4fc01daae5a5	1074
bogdanm	92:4fc01daae5a5	1075
bogdanm	92:4fc01daae5a5	1076	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1077	/* ================ NVMC ================ */
bogdanm	92:4fc01daae5a5	1078	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1079
bogdanm	92:4fc01daae5a5	1080
bogdanm	92:4fc01daae5a5	1081	/**
bogdanm	92:4fc01daae5a5	1082	* @brief Non Volatile Memory Controller. (NVMC)
bogdanm	92:4fc01daae5a5	1083	*/
bogdanm	92:4fc01daae5a5	1084
bogdanm	92:4fc01daae5a5	1085	typedef struct { /!< NVMC Structure /
bogdanm	92:4fc01daae5a5	1086	__I uint32_t RESERVED0[256];
bogdanm	92:4fc01daae5a5	1087	__I uint32_t READY; /!< Ready flag. /
bogdanm	92:4fc01daae5a5	1088	__I uint32_t RESERVED1[64];
bogdanm	92:4fc01daae5a5	1089	__IO uint32_t CONFIG; /!< Configuration register. /
bogdanm	92:4fc01daae5a5	1090	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
bogdanm	92:4fc01daae5a5	1091	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
bogdanm	92:4fc01daae5a5	1092	__IO uint32_t ERASEPROTECTEDPAGE; /!< Register for erasing a protected non-volatile memory page. /
bogdanm	92:4fc01daae5a5	1093	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
bogdanm	92:4fc01daae5a5	1094	} NRF_NVMC_Type;
bogdanm	92:4fc01daae5a5	1095
bogdanm	92:4fc01daae5a5	1096
bogdanm	92:4fc01daae5a5	1097	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1098	/* ================ PPI ================ */
bogdanm	92:4fc01daae5a5	1099	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1100
bogdanm	92:4fc01daae5a5	1101
bogdanm	92:4fc01daae5a5	1102	/**
bogdanm	92:4fc01daae5a5	1103	* @brief PPI controller. (PPI)
bogdanm	92:4fc01daae5a5	1104	*/
bogdanm	92:4fc01daae5a5	1105
bogdanm	92:4fc01daae5a5	1106	typedef struct { /!< PPI Structure /
bogdanm	92:4fc01daae5a5	1107	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
bogdanm	92:4fc01daae5a5	1108	__I uint32_t RESERVED0[312];
bogdanm	92:4fc01daae5a5	1109	__IO uint32_t CHEN; /!< Channel enable. /
bogdanm	92:4fc01daae5a5	1110	__IO uint32_t CHENSET; /!< Channel enable set. /
bogdanm	92:4fc01daae5a5	1111	__IO uint32_t CHENCLR; /!< Channel enable clear. /
bogdanm	92:4fc01daae5a5	1112	__I uint32_t RESERVED1;
bogdanm	92:4fc01daae5a5	1113	PPI_CH_Type CH[16]; /!< PPI Channel. /
bogdanm	92:4fc01daae5a5	1114	__I uint32_t RESERVED2[156];
bogdanm	92:4fc01daae5a5	1115	__IO uint32_t CHG[4]; /!< Channel group configuration. /
bogdanm	92:4fc01daae5a5	1116	} NRF_PPI_Type;
bogdanm	92:4fc01daae5a5	1117
bogdanm	92:4fc01daae5a5	1118
bogdanm	92:4fc01daae5a5	1119	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1120	/* ================ FICR ================ */
bogdanm	92:4fc01daae5a5	1121	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1122
bogdanm	92:4fc01daae5a5	1123
bogdanm	92:4fc01daae5a5	1124	/**
bogdanm	92:4fc01daae5a5	1125	* @brief Factory Information Configuration. (FICR)
bogdanm	92:4fc01daae5a5	1126	*/
bogdanm	92:4fc01daae5a5	1127
bogdanm	92:4fc01daae5a5	1128	typedef struct { /!< FICR Structure /
bogdanm	92:4fc01daae5a5	1129	__I uint32_t RESERVED0[4];
bogdanm	92:4fc01daae5a5	1130	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
bogdanm	92:4fc01daae5a5	1131	__I uint32_t CODESIZE; /!< Code memory size in pages. /
bogdanm	92:4fc01daae5a5	1132	__I uint32_t RESERVED1[4];
bogdanm	92:4fc01daae5a5	1133	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
bogdanm	92:4fc01daae5a5	1134	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
bogdanm	92:4fc01daae5a5	1135	__I uint32_t RESERVED2;
bogdanm	92:4fc01daae5a5	1136	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
Kojto	97:433970e64889	1137
Kojto	97:433970e64889	1138	union {
Kojto	97:433970e64889	1139	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto	97:433970e64889	1140	kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto	97:433970e64889	1141	instead. */
Kojto	97:433970e64889	1142	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
Kojto	97:433970e64889	1143	};
bogdanm	92:4fc01daae5a5	1144	__I uint32_t RESERVED3[5];
bogdanm	92:4fc01daae5a5	1145	__I uint32_t CONFIGID; /!< Configuration identifier. /
bogdanm	92:4fc01daae5a5	1146	__I uint32_t DEVICEID[2]; /!< Device identifier. /
bogdanm	92:4fc01daae5a5	1147	__I uint32_t RESERVED4[6];
bogdanm	92:4fc01daae5a5	1148	__I uint32_t ER[4]; /!< Encryption root. /
bogdanm	92:4fc01daae5a5	1149	__I uint32_t IR[4]; /!< Identity root. /
bogdanm	92:4fc01daae5a5	1150	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
bogdanm	92:4fc01daae5a5	1151	__I uint32_t DEVICEADDR[2]; /!< Device address. /
bogdanm	92:4fc01daae5a5	1152	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
Kojto	97:433970e64889	1153	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto	97:433970e64889	1154	mode. */
Kojto	97:433970e64889	1155	__I uint32_t RESERVED5[10];
bogdanm	92:4fc01daae5a5	1156	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
bogdanm	92:4fc01daae5a5	1157	mode. */
Kojto	97:433970e64889	1158	FICR_INFO_Type INFO; /!< Device info /
bogdanm	92:4fc01daae5a5	1159	} NRF_FICR_Type;
bogdanm	92:4fc01daae5a5	1160
bogdanm	92:4fc01daae5a5	1161
bogdanm	92:4fc01daae5a5	1162	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1163	/* ================ UICR ================ */
bogdanm	92:4fc01daae5a5	1164	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1165
bogdanm	92:4fc01daae5a5	1166
bogdanm	92:4fc01daae5a5	1167	/**
bogdanm	92:4fc01daae5a5	1168	* @brief User Information Configuration. (UICR)
bogdanm	92:4fc01daae5a5	1169	*/
bogdanm	92:4fc01daae5a5	1170
bogdanm	92:4fc01daae5a5	1171	typedef struct { /!< UICR Structure /
bogdanm	92:4fc01daae5a5	1172	__IO uint32_t CLENR0; /!< Length of code region 0. /
bogdanm	92:4fc01daae5a5	1173	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
bogdanm	92:4fc01daae5a5	1174	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
bogdanm	92:4fc01daae5a5	1175	__I uint32_t RESERVED0;
bogdanm	92:4fc01daae5a5	1176	__I uint32_t FWID; /!< Firmware ID. /
bogdanm	92:4fc01daae5a5	1177	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
bogdanm	92:4fc01daae5a5	1178	} NRF_UICR_Type;
bogdanm	92:4fc01daae5a5	1179
bogdanm	92:4fc01daae5a5	1180
bogdanm	92:4fc01daae5a5	1181	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1182	/* ================ GPIO ================ */
bogdanm	92:4fc01daae5a5	1183	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1184
bogdanm	92:4fc01daae5a5	1185
bogdanm	92:4fc01daae5a5	1186	/**
bogdanm	92:4fc01daae5a5	1187	* @brief General purpose input and output. (GPIO)
bogdanm	92:4fc01daae5a5	1188	*/
bogdanm	92:4fc01daae5a5	1189
bogdanm	92:4fc01daae5a5	1190	typedef struct { /!< GPIO Structure /
bogdanm	92:4fc01daae5a5	1191	__I uint32_t RESERVED0[321];
bogdanm	92:4fc01daae5a5	1192	__IO uint32_t OUT; /!< Write GPIO port. /
bogdanm	92:4fc01daae5a5	1193	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
bogdanm	92:4fc01daae5a5	1194	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
bogdanm	92:4fc01daae5a5	1195	__I uint32_t IN; /!< Read GPIO port. /
bogdanm	92:4fc01daae5a5	1196	__IO uint32_t DIR; /!< Direction of GPIO pins. /
bogdanm	92:4fc01daae5a5	1197	__IO uint32_t DIRSET; /!< DIR set register. /
bogdanm	92:4fc01daae5a5	1198	__IO uint32_t DIRCLR; /!< DIR clear register. /
bogdanm	92:4fc01daae5a5	1199	__I uint32_t RESERVED1[120];
bogdanm	92:4fc01daae5a5	1200	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
bogdanm	92:4fc01daae5a5	1201	} NRF_GPIO_Type;
bogdanm	92:4fc01daae5a5	1202
bogdanm	92:4fc01daae5a5	1203
bogdanm	92:4fc01daae5a5	1204	/* -------------------- End of section using anonymous unions ------------------- */
bogdanm	92:4fc01daae5a5	1205	#if defined(__CC_ARM)
bogdanm	92:4fc01daae5a5	1206	#pragma pop
bogdanm	92:4fc01daae5a5	1207	#elif defined(__ICCARM__)
bogdanm	92:4fc01daae5a5	1208	/* leave anonymous unions enabled */
bogdanm	92:4fc01daae5a5	1209	#elif defined(__GNUC__)
bogdanm	92:4fc01daae5a5	1210	/* anonymous unions are enabled by default */
bogdanm	92:4fc01daae5a5	1211	#elif defined(__TMS470__)
bogdanm	92:4fc01daae5a5	1212	/* anonymous unions are enabled by default */
bogdanm	92:4fc01daae5a5	1213	#elif defined(__TASKING__)
bogdanm	92:4fc01daae5a5	1214	#pragma warning restore
bogdanm	92:4fc01daae5a5	1215	#else
bogdanm	92:4fc01daae5a5	1216	#warning Not supported compiler type
bogdanm	92:4fc01daae5a5	1217	#endif
bogdanm	92:4fc01daae5a5	1218
bogdanm	92:4fc01daae5a5	1219
bogdanm	92:4fc01daae5a5	1220
bogdanm	92:4fc01daae5a5	1221
bogdanm	92:4fc01daae5a5	1222	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1223	/* ================ Peripheral memory map ================ */
bogdanm	92:4fc01daae5a5	1224	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1225
bogdanm	92:4fc01daae5a5	1226	#define NRF_POWER_BASE 0x40000000UL
bogdanm	92:4fc01daae5a5	1227	#define NRF_CLOCK_BASE 0x40000000UL
bogdanm	92:4fc01daae5a5	1228	#define NRF_MPU_BASE 0x40000000UL
bogdanm	92:4fc01daae5a5	1229	#define NRF_PU_BASE 0x40000000UL
bogdanm	92:4fc01daae5a5	1230	#define NRF_AMLI_BASE 0x40000000UL
bogdanm	92:4fc01daae5a5	1231	#define NRF_RADIO_BASE 0x40001000UL
bogdanm	92:4fc01daae5a5	1232	#define NRF_UART0_BASE 0x40002000UL
bogdanm	92:4fc01daae5a5	1233	#define NRF_SPI0_BASE 0x40003000UL
bogdanm	92:4fc01daae5a5	1234	#define NRF_TWI0_BASE 0x40003000UL
bogdanm	92:4fc01daae5a5	1235	#define NRF_SPI1_BASE 0x40004000UL
bogdanm	92:4fc01daae5a5	1236	#define NRF_TWI1_BASE 0x40004000UL
bogdanm	92:4fc01daae5a5	1237	#define NRF_SPIS1_BASE 0x40004000UL
Kojto	97:433970e64889	1238	#define NRF_SPIM1_BASE 0x40004000UL
bogdanm	92:4fc01daae5a5	1239	#define NRF_GPIOTE_BASE 0x40006000UL
bogdanm	92:4fc01daae5a5	1240	#define NRF_ADC_BASE 0x40007000UL
bogdanm	92:4fc01daae5a5	1241	#define NRF_TIMER0_BASE 0x40008000UL
bogdanm	92:4fc01daae5a5	1242	#define NRF_TIMER1_BASE 0x40009000UL
bogdanm	92:4fc01daae5a5	1243	#define NRF_TIMER2_BASE 0x4000A000UL
bogdanm	92:4fc01daae5a5	1244	#define NRF_RTC0_BASE 0x4000B000UL
bogdanm	92:4fc01daae5a5	1245	#define NRF_TEMP_BASE 0x4000C000UL
bogdanm	92:4fc01daae5a5	1246	#define NRF_RNG_BASE 0x4000D000UL
bogdanm	92:4fc01daae5a5	1247	#define NRF_ECB_BASE 0x4000E000UL
bogdanm	92:4fc01daae5a5	1248	#define NRF_AAR_BASE 0x4000F000UL
bogdanm	92:4fc01daae5a5	1249	#define NRF_CCM_BASE 0x4000F000UL
bogdanm	92:4fc01daae5a5	1250	#define NRF_WDT_BASE 0x40010000UL
bogdanm	92:4fc01daae5a5	1251	#define NRF_RTC1_BASE 0x40011000UL
bogdanm	92:4fc01daae5a5	1252	#define NRF_QDEC_BASE 0x40012000UL
bogdanm	92:4fc01daae5a5	1253	#define NRF_LPCOMP_BASE 0x40013000UL
bogdanm	92:4fc01daae5a5	1254	#define NRF_SWI_BASE 0x40014000UL
bogdanm	92:4fc01daae5a5	1255	#define NRF_NVMC_BASE 0x4001E000UL
bogdanm	92:4fc01daae5a5	1256	#define NRF_PPI_BASE 0x4001F000UL
bogdanm	92:4fc01daae5a5	1257	#define NRF_FICR_BASE 0x10000000UL
bogdanm	92:4fc01daae5a5	1258	#define NRF_UICR_BASE 0x10001000UL
bogdanm	92:4fc01daae5a5	1259	#define NRF_GPIO_BASE 0x50000000UL
bogdanm	92:4fc01daae5a5	1260
bogdanm	92:4fc01daae5a5	1261
bogdanm	92:4fc01daae5a5	1262	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1263	/* ================ Peripheral declaration ================ */
bogdanm	92:4fc01daae5a5	1264	/* ================================================================================ */
bogdanm	92:4fc01daae5a5	1265
bogdanm	92:4fc01daae5a5	1266	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
bogdanm	92:4fc01daae5a5	1267	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
bogdanm	92:4fc01daae5a5	1268	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
bogdanm	92:4fc01daae5a5	1269	#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
bogdanm	92:4fc01daae5a5	1270	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
bogdanm	92:4fc01daae5a5	1271	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
bogdanm	92:4fc01daae5a5	1272	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
bogdanm	92:4fc01daae5a5	1273	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
bogdanm	92:4fc01daae5a5	1274	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
bogdanm	92:4fc01daae5a5	1275	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
bogdanm	92:4fc01daae5a5	1276	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
bogdanm	92:4fc01daae5a5	1277	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto	97:433970e64889	1278	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
bogdanm	92:4fc01daae5a5	1279	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
bogdanm	92:4fc01daae5a5	1280	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
bogdanm	92:4fc01daae5a5	1281	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
bogdanm	92:4fc01daae5a5	1282	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
bogdanm	92:4fc01daae5a5	1283	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
bogdanm	92:4fc01daae5a5	1284	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
bogdanm	92:4fc01daae5a5	1285	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
bogdanm	92:4fc01daae5a5	1286	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
bogdanm	92:4fc01daae5a5	1287	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
bogdanm	92:4fc01daae5a5	1288	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
bogdanm	92:4fc01daae5a5	1289	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
bogdanm	92:4fc01daae5a5	1290	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
bogdanm	92:4fc01daae5a5	1291	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
bogdanm	92:4fc01daae5a5	1292	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
bogdanm	92:4fc01daae5a5	1293	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
bogdanm	92:4fc01daae5a5	1294	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
bogdanm	92:4fc01daae5a5	1295	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
bogdanm	92:4fc01daae5a5	1296	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
bogdanm	92:4fc01daae5a5	1297	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
bogdanm	92:4fc01daae5a5	1298	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
bogdanm	92:4fc01daae5a5	1299	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
bogdanm	92:4fc01daae5a5	1300
bogdanm	92:4fc01daae5a5	1301
bogdanm	92:4fc01daae5a5	1302	/** @} / / End of group Device_Peripheral_Registers */
bogdanm	92:4fc01daae5a5	1303	/** @} / / End of group nRF51 */
bogdanm	92:4fc01daae5a5	1304	/** @} / / End of group Nordic Semiconductor */
bogdanm	92:4fc01daae5a5	1305
bogdanm	92:4fc01daae5a5	1306	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	1307	}
bogdanm	92:4fc01daae5a5	1308	#endif
bogdanm	92:4fc01daae5a5	1309
bogdanm	92:4fc01daae5a5	1310
bogdanm	92:4fc01daae5a5	1311	#endif /* nRF51_H */
Kojto	97:433970e64889	1312

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_WALLBOT_BLE/nrf51.h@120:2eb10e18b8d7, 2016-04-13 (annotated)

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