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TARGET_NUCLEO_L073RZ/stm32l0xx_hal_rcc.h@120:2eb10e18b8d7, 2016-04-13 (annotated)

Committer:: elijahorr
Date:: Wed Apr 13 12:29:27 2016 +0000
Revision:: 120:2eb10e18b8d7
Parent:: 116:c0f6e94411f5

V1.1

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	116:c0f6e94411f5	1	/**
Kojto	116:c0f6e94411f5	2	******************************************************************************
Kojto	116:c0f6e94411f5	3	* @file stm32l0xx_hal_rcc.h
Kojto	116:c0f6e94411f5	4	* @author MCD Application Team
Kojto	116:c0f6e94411f5	5	* @version V1.2.0
Kojto	116:c0f6e94411f5	6	* @date 06-February-2015
Kojto	116:c0f6e94411f5	7	* @brief Header file of RCC HAL module.
Kojto	116:c0f6e94411f5	8	******************************************************************************
Kojto	116:c0f6e94411f5	9	* @attention
Kojto	116:c0f6e94411f5	10	*
Kojto	116:c0f6e94411f5	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	116:c0f6e94411f5	12	*
Kojto	116:c0f6e94411f5	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	116:c0f6e94411f5	14	* are permitted provided that the following conditions are met:
Kojto	116:c0f6e94411f5	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	116:c0f6e94411f5	16	* this list of conditions and the following disclaimer.
Kojto	116:c0f6e94411f5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	116:c0f6e94411f5	18	* this list of conditions and the following disclaimer in the documentation
Kojto	116:c0f6e94411f5	19	* and/or other materials provided with the distribution.
Kojto	116:c0f6e94411f5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	116:c0f6e94411f5	21	* may be used to endorse or promote products derived from this software
Kojto	116:c0f6e94411f5	22	* without specific prior written permission.
Kojto	116:c0f6e94411f5	23	*
Kojto	116:c0f6e94411f5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	116:c0f6e94411f5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	116:c0f6e94411f5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	116:c0f6e94411f5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	116:c0f6e94411f5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	116:c0f6e94411f5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	116:c0f6e94411f5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	116:c0f6e94411f5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	116:c0f6e94411f5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	116:c0f6e94411f5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	116:c0f6e94411f5	34	*
Kojto	116:c0f6e94411f5	35	******************************************************************************
Kojto	116:c0f6e94411f5	36	*/
Kojto	116:c0f6e94411f5	37
Kojto	116:c0f6e94411f5	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	116:c0f6e94411f5	39	#ifndef __STM32L0xx_HAL_RCC_H
Kojto	116:c0f6e94411f5	40	#define __STM32L0xx_HAL_RCC_H
Kojto	116:c0f6e94411f5	41
Kojto	116:c0f6e94411f5	42	#ifdef __cplusplus
Kojto	116:c0f6e94411f5	43	extern "C" {
Kojto	116:c0f6e94411f5	44	#endif
Kojto	116:c0f6e94411f5	45
Kojto	116:c0f6e94411f5	46	/* Includes ------------------------------------------------------------------*/
Kojto	116:c0f6e94411f5	47	#include "stm32l0xx_hal_def.h"
Kojto	116:c0f6e94411f5	48
Kojto	116:c0f6e94411f5	49	/** @addtogroup STM32L0xx_HAL_Driver
Kojto	116:c0f6e94411f5	50	* @{
Kojto	116:c0f6e94411f5	51	*/
Kojto	116:c0f6e94411f5	52
Kojto	116:c0f6e94411f5	53	/** @defgroup RCC RCC
Kojto	116:c0f6e94411f5	54	* @{
Kojto	116:c0f6e94411f5	55	*/
Kojto	116:c0f6e94411f5	56
Kojto	116:c0f6e94411f5	57	/* Exported types ------------------------------------------------------------*/
Kojto	116:c0f6e94411f5	58
Kojto	116:c0f6e94411f5	59	/**
Kojto	116:c0f6e94411f5	60	* @brief RCC PLL configuration structure definition
Kojto	116:c0f6e94411f5	61	*/
Kojto	116:c0f6e94411f5	62	typedef struct
Kojto	116:c0f6e94411f5	63	{
Kojto	116:c0f6e94411f5	64	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	116:c0f6e94411f5	65	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	116:c0f6e94411f5	66
Kojto	116:c0f6e94411f5	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	116:c0f6e94411f5	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	116:c0f6e94411f5	69
Kojto	116:c0f6e94411f5	70	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
Kojto	116:c0f6e94411f5	71	This parameter must of @ref RCC_PLLMultiplication_Factor */
Kojto	116:c0f6e94411f5	72
Kojto	116:c0f6e94411f5	73	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
Kojto	116:c0f6e94411f5	74	This parameter must be a value of @ref RCC_PLLDivider_Factor */
Kojto	116:c0f6e94411f5	75
Kojto	116:c0f6e94411f5	76	}RCC_PLLInitTypeDef;
Kojto	116:c0f6e94411f5	77
Kojto	116:c0f6e94411f5	78	/**
Kojto	116:c0f6e94411f5	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	116:c0f6e94411f5	80	*/
Kojto	116:c0f6e94411f5	81	typedef struct
Kojto	116:c0f6e94411f5	82	{
Kojto	116:c0f6e94411f5	83	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	116:c0f6e94411f5	84	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	116:c0f6e94411f5	85
Kojto	116:c0f6e94411f5	86	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	116:c0f6e94411f5	87	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	116:c0f6e94411f5	88
Kojto	116:c0f6e94411f5	89	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	116:c0f6e94411f5	90	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	116:c0f6e94411f5	91
Kojto	116:c0f6e94411f5	92	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	116:c0f6e94411f5	93	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	116:c0f6e94411f5	94
Kojto	116:c0f6e94411f5	95	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	116:c0f6e94411f5	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	116:c0f6e94411f5	97
Kojto	116:c0f6e94411f5	98	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	116:c0f6e94411f5	99	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	116:c0f6e94411f5	100
Kojto	116:c0f6e94411f5	101	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	102	uint32_t HSI48State; /*!< The new state of the HSI48.
Kojto	116:c0f6e94411f5	103	This parameter can be a value of @ref RCC_HSI48_Config */
Kojto	116:c0f6e94411f5	104	#endif
Kojto	116:c0f6e94411f5	105
Kojto	116:c0f6e94411f5	106	uint32_t MSIState; /*!< The new state of the MSI.
Kojto	116:c0f6e94411f5	107	This parameter can be a value of @ref RCC_MSI_Config */
Kojto	116:c0f6e94411f5	108
Kojto	116:c0f6e94411f5	109	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
Kojto	116:c0f6e94411f5	110	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto	116:c0f6e94411f5	111
Kojto	116:c0f6e94411f5	112	uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto	116:c0f6e94411f5	113	This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto	116:c0f6e94411f5	114
Kojto	116:c0f6e94411f5	115	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	116:c0f6e94411f5	116
Kojto	116:c0f6e94411f5	117	}RCC_OscInitTypeDef;
Kojto	116:c0f6e94411f5	118
Kojto	116:c0f6e94411f5	119	/**
Kojto	116:c0f6e94411f5	120	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	116:c0f6e94411f5	121	*/
Kojto	116:c0f6e94411f5	122	typedef struct
Kojto	116:c0f6e94411f5	123	{
Kojto	116:c0f6e94411f5	124	uint32_t ClockType; /*!< The clock to be configured.
Kojto	116:c0f6e94411f5	125	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	116:c0f6e94411f5	126
Kojto	116:c0f6e94411f5	127	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	116:c0f6e94411f5	128	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	116:c0f6e94411f5	129
Kojto	116:c0f6e94411f5	130	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	116:c0f6e94411f5	131	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	116:c0f6e94411f5	132
Kojto	116:c0f6e94411f5	133	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	116:c0f6e94411f5	134	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	116:c0f6e94411f5	135
Kojto	116:c0f6e94411f5	136	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	116:c0f6e94411f5	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	116:c0f6e94411f5	138
Kojto	116:c0f6e94411f5	139	}RCC_ClkInitTypeDef;
Kojto	116:c0f6e94411f5	140
Kojto	116:c0f6e94411f5	141
Kojto	116:c0f6e94411f5	142	/** @defgroup RCC_Private_Constants RCC Private constatnts
Kojto	116:c0f6e94411f5	143	* @brief RCC registers bit address in the alias region
Kojto	116:c0f6e94411f5	144	* @{
Kojto	116:c0f6e94411f5	145	*/
Kojto	116:c0f6e94411f5	146	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	116:c0f6e94411f5	147	/* --- CR Register ---*/
Kojto	116:c0f6e94411f5	148	/* Alias word address of HSION bit */
Kojto	116:c0f6e94411f5	149	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto	116:c0f6e94411f5	150	/* --- CFGR Register ---*/
Kojto	116:c0f6e94411f5	151	/* Alias word address of I2SSRC bit */
Kojto	116:c0f6e94411f5	152	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto	116:c0f6e94411f5	153	/* --- CSR Register ---*/
Kojto	116:c0f6e94411f5	154	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto	116:c0f6e94411f5	155
Kojto	116:c0f6e94411f5	156	/* CR register byte 3 (Bits[23:16]) base address */
Kojto	116:c0f6e94411f5	157	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto	116:c0f6e94411f5	158
Kojto	116:c0f6e94411f5	159	/* CIER register byte 0 (Bits[0:8]) base address */
Kojto	116:c0f6e94411f5	160	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
Kojto	116:c0f6e94411f5	161
Kojto	116:c0f6e94411f5	162	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	116:c0f6e94411f5	163	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	116:c0f6e94411f5	164
Kojto	116:c0f6e94411f5	165	/**
Kojto	116:c0f6e94411f5	166	* @}
Kojto	116:c0f6e94411f5	167	*/
Kojto	116:c0f6e94411f5	168
Kojto	116:c0f6e94411f5	169	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	116:c0f6e94411f5	170	* @{
Kojto	116:c0f6e94411f5	171	*/
Kojto	116:c0f6e94411f5	172
Kojto	116:c0f6e94411f5	173	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto	116:c0f6e94411f5	174	* @{
Kojto	116:c0f6e94411f5	175	*/
Kojto	116:c0f6e94411f5	176	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	177	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	116:c0f6e94411f5	178	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	116:c0f6e94411f5	179	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	116:c0f6e94411f5	180	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	116:c0f6e94411f5	181	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
Kojto	116:c0f6e94411f5	182	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	183	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto	116:c0f6e94411f5	184	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
Kojto	116:c0f6e94411f5	185	#else
Kojto	116:c0f6e94411f5	186	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
Kojto	116:c0f6e94411f5	187	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	116:c0f6e94411f5	188
Kojto	116:c0f6e94411f5	189	/**
Kojto	116:c0f6e94411f5	190	* @}
Kojto	116:c0f6e94411f5	191	*/
Kojto	116:c0f6e94411f5	192
Kojto	116:c0f6e94411f5	193	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	116:c0f6e94411f5	194	* @{
Kojto	116:c0f6e94411f5	195	*/
Kojto	116:c0f6e94411f5	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	197	#define RCC_HSE_ON RCC_CR_HSEON
Kojto	116:c0f6e94411f5	198	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
Kojto	116:c0f6e94411f5	199
Kojto	116:c0f6e94411f5	200	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	116:c0f6e94411f5	201	((__HSE__) == RCC_HSE_BYPASS))
Kojto	116:c0f6e94411f5	202	/**
Kojto	116:c0f6e94411f5	203	* @}
Kojto	116:c0f6e94411f5	204	*/
Kojto	116:c0f6e94411f5	205
Kojto	116:c0f6e94411f5	206	/** @defgroup RCC_LSE_Config RCC LSE Config
Kojto	116:c0f6e94411f5	207	* @{
Kojto	116:c0f6e94411f5	208	*/
Kojto	116:c0f6e94411f5	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	210	#define RCC_LSE_ON RCC_CSR_LSEON
Kojto	116:c0f6e94411f5	211	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
Kojto	116:c0f6e94411f5	212
Kojto	116:c0f6e94411f5	213	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	116:c0f6e94411f5	214	((__LSE__) == RCC_LSE_BYPASS))
Kojto	116:c0f6e94411f5	215	/**
Kojto	116:c0f6e94411f5	216	* @}
Kojto	116:c0f6e94411f5	217	*/
Kojto	116:c0f6e94411f5	218
Kojto	116:c0f6e94411f5	219
Kojto	116:c0f6e94411f5	220
Kojto	116:c0f6e94411f5	221	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
Kojto	116:c0f6e94411f5	222	* @{
Kojto	116:c0f6e94411f5	223	*/
Kojto	116:c0f6e94411f5	224
Kojto	116:c0f6e94411f5	225	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
Kojto	116:c0f6e94411f5	226	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
Kojto	116:c0f6e94411f5	227	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
Kojto	116:c0f6e94411f5	228	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
Kojto	116:c0f6e94411f5	229	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
Kojto	116:c0f6e94411f5	230	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
Kojto	116:c0f6e94411f5	231	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
Kojto	116:c0f6e94411f5	232
Kojto	116:c0f6e94411f5	233	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
Kojto	116:c0f6e94411f5	234	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
Kojto	116:c0f6e94411f5	235	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
Kojto	116:c0f6e94411f5	236	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
Kojto	116:c0f6e94411f5	237	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Kojto	116:c0f6e94411f5	238	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Kojto	116:c0f6e94411f5	239	((__RANGE__) == RCC_MSIRANGE_6))
Kojto	116:c0f6e94411f5	240
Kojto	116:c0f6e94411f5	241	/**
Kojto	116:c0f6e94411f5	242	* @}
Kojto	116:c0f6e94411f5	243	*/
Kojto	116:c0f6e94411f5	244
Kojto	116:c0f6e94411f5	245	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	116:c0f6e94411f5	246	* @{
Kojto	116:c0f6e94411f5	247	*/
Kojto	116:c0f6e94411f5	248	#define RCC_LSI_OFF ((uint8_t)0x00)
Kojto	116:c0f6e94411f5	249	#define RCC_LSI_ON ((uint8_t)0x01)
Kojto	116:c0f6e94411f5	250
Kojto	116:c0f6e94411f5	251	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
Kojto	116:c0f6e94411f5	252
Kojto	116:c0f6e94411f5	253	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	116:c0f6e94411f5	254	/**
Kojto	116:c0f6e94411f5	255	* @}
Kojto	116:c0f6e94411f5	256	*/
Kojto	116:c0f6e94411f5	257
Kojto	116:c0f6e94411f5	258
Kojto	116:c0f6e94411f5	259	/** @defgroup RCC_MSI_Config RCC MSI Config
Kojto	116:c0f6e94411f5	260	* @{
Kojto	116:c0f6e94411f5	261	*/
Kojto	116:c0f6e94411f5	262	#define RCC_MSI_OFF ((uint8_t)0x00)
Kojto	116:c0f6e94411f5	263	#define RCC_MSI_ON ((uint8_t)0x01)
Kojto	116:c0f6e94411f5	264
Kojto	116:c0f6e94411f5	265	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	116:c0f6e94411f5	266
Kojto	116:c0f6e94411f5	267	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
Kojto	116:c0f6e94411f5	268	/**
Kojto	116:c0f6e94411f5	269	* @}
Kojto	116:c0f6e94411f5	270	*/
Kojto	116:c0f6e94411f5	271
Kojto	116:c0f6e94411f5	272	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	273	/** @defgroup RCC_HSI48_Config
Kojto	116:c0f6e94411f5	274	* @{
Kojto	116:c0f6e94411f5	275	*/
Kojto	116:c0f6e94411f5	276	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	116:c0f6e94411f5	277	#define RCC_HSI48_ON ((uint8_t)0x01)
Kojto	116:c0f6e94411f5	278
Kojto	116:c0f6e94411f5	279	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
Kojto	116:c0f6e94411f5	280	/**
Kojto	116:c0f6e94411f5	281	* @}
Kojto	116:c0f6e94411f5	282	*/
Kojto	116:c0f6e94411f5	283	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	116:c0f6e94411f5	284
Kojto	116:c0f6e94411f5	285	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	116:c0f6e94411f5	286	* @{
Kojto	116:c0f6e94411f5	287	*/
Kojto	116:c0f6e94411f5	288	#define RCC_PLL_NONE ((uint8_t)0x00)
Kojto	116:c0f6e94411f5	289	#define RCC_PLL_OFF ((uint8_t)0x01)
Kojto	116:c0f6e94411f5	290	#define RCC_PLL_ON ((uint8_t)0x02)
Kojto	116:c0f6e94411f5	291
Kojto	116:c0f6e94411f5	292	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
Kojto	116:c0f6e94411f5	293	/**
Kojto	116:c0f6e94411f5	294	* @}
Kojto	116:c0f6e94411f5	295	*/
Kojto	116:c0f6e94411f5	296
Kojto	116:c0f6e94411f5	297	/** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source
Kojto	116:c0f6e94411f5	298	* @{
Kojto	116:c0f6e94411f5	299	*/
Kojto	116:c0f6e94411f5	300	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
Kojto	116:c0f6e94411f5	301	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
Kojto	116:c0f6e94411f5	302
Kojto	116:c0f6e94411f5	303	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	116:c0f6e94411f5	304	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	116:c0f6e94411f5	305
Kojto	116:c0f6e94411f5	306	/**
Kojto	116:c0f6e94411f5	307	* @}
Kojto	116:c0f6e94411f5	308	*/
Kojto	116:c0f6e94411f5	309
Kojto	116:c0f6e94411f5	310	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
Kojto	116:c0f6e94411f5	311	* @{
Kojto	116:c0f6e94411f5	312	*/
Kojto	116:c0f6e94411f5	313
Kojto	116:c0f6e94411f5	314	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
Kojto	116:c0f6e94411f5	315	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
Kojto	116:c0f6e94411f5	316	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
Kojto	116:c0f6e94411f5	317	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
Kojto	116:c0f6e94411f5	318	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
Kojto	116:c0f6e94411f5	319	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
Kojto	116:c0f6e94411f5	320	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
Kojto	116:c0f6e94411f5	321	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
Kojto	116:c0f6e94411f5	322	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
Kojto	116:c0f6e94411f5	323	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
Kojto	116:c0f6e94411f5	324	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
Kojto	116:c0f6e94411f5	325	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
Kojto	116:c0f6e94411f5	326	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
Kojto	116:c0f6e94411f5	327	((__MUL__) == RCC_PLLMUL_48))
Kojto	116:c0f6e94411f5	328	/**
Kojto	116:c0f6e94411f5	329	* @}
Kojto	116:c0f6e94411f5	330	*/
Kojto	116:c0f6e94411f5	331
Kojto	116:c0f6e94411f5	332	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
Kojto	116:c0f6e94411f5	333	* @{
Kojto	116:c0f6e94411f5	334	*/
Kojto	116:c0f6e94411f5	335
Kojto	116:c0f6e94411f5	336	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
Kojto	116:c0f6e94411f5	337	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
Kojto	116:c0f6e94411f5	338	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
Kojto	116:c0f6e94411f5	339	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
Kojto	116:c0f6e94411f5	340	((__DIV__) == RCC_PLLDIV_4))
Kojto	116:c0f6e94411f5	341	/**
Kojto	116:c0f6e94411f5	342	* @}
Kojto	116:c0f6e94411f5	343	*/
Kojto	116:c0f6e94411f5	344
Kojto	116:c0f6e94411f5	345	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	116:c0f6e94411f5	346	* @{
Kojto	116:c0f6e94411f5	347	*/
Kojto	116:c0f6e94411f5	348	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	116:c0f6e94411f5	349	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	116:c0f6e94411f5	350	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	116:c0f6e94411f5	351	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	116:c0f6e94411f5	352
Kojto	116:c0f6e94411f5	353	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto	116:c0f6e94411f5	354	/**
Kojto	116:c0f6e94411f5	355	* @}
Kojto	116:c0f6e94411f5	356	*/
Kojto	116:c0f6e94411f5	357
Kojto	116:c0f6e94411f5	358	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	116:c0f6e94411f5	359	* @{
Kojto	116:c0f6e94411f5	360	*/
Kojto	116:c0f6e94411f5	361	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
Kojto	116:c0f6e94411f5	362	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	116:c0f6e94411f5	363	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	116:c0f6e94411f5	364	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	116:c0f6e94411f5	365
Kojto	116:c0f6e94411f5	366	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	116:c0f6e94411f5	367	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	116:c0f6e94411f5	368	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
Kojto	116:c0f6e94411f5	369	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	116:c0f6e94411f5	370	/**
Kojto	116:c0f6e94411f5	371	* @}
Kojto	116:c0f6e94411f5	372	*/
Kojto	116:c0f6e94411f5	373
Kojto	116:c0f6e94411f5	374	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	116:c0f6e94411f5	375	* @{
Kojto	116:c0f6e94411f5	376	*/
Kojto	116:c0f6e94411f5	377	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto	116:c0f6e94411f5	378	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto	116:c0f6e94411f5	379	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto	116:c0f6e94411f5	380
Kojto	116:c0f6e94411f5	381	/**
Kojto	116:c0f6e94411f5	382	* @}
Kojto	116:c0f6e94411f5	383	*/
Kojto	116:c0f6e94411f5	384
Kojto	116:c0f6e94411f5	385	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce
Kojto	116:c0f6e94411f5	386	* @{
Kojto	116:c0f6e94411f5	387	*/
Kojto	116:c0f6e94411f5	388	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	116:c0f6e94411f5	389	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	116:c0f6e94411f5	390	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	116:c0f6e94411f5	391	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	116:c0f6e94411f5	392	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	116:c0f6e94411f5	393	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	116:c0f6e94411f5	394	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	116:c0f6e94411f5	395	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	116:c0f6e94411f5	396	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	116:c0f6e94411f5	397
Kojto	116:c0f6e94411f5	398	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	116:c0f6e94411f5	399	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	116:c0f6e94411f5	400	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	116:c0f6e94411f5	401	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	116:c0f6e94411f5	402	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	116:c0f6e94411f5	403	/**
Kojto	116:c0f6e94411f5	404	* @}
Kojto	116:c0f6e94411f5	405	*/
Kojto	116:c0f6e94411f5	406
Kojto	116:c0f6e94411f5	407	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source
Kojto	116:c0f6e94411f5	408	* @{
Kojto	116:c0f6e94411f5	409	*/
Kojto	116:c0f6e94411f5	410	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto	116:c0f6e94411f5	411	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto	116:c0f6e94411f5	412	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto	116:c0f6e94411f5	413	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto	116:c0f6e94411f5	414	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto	116:c0f6e94411f5	415
Kojto	116:c0f6e94411f5	416	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	116:c0f6e94411f5	417	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	116:c0f6e94411f5	418	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	116:c0f6e94411f5	419	/**
Kojto	116:c0f6e94411f5	420	* @}
Kojto	116:c0f6e94411f5	421	*/
Kojto	116:c0f6e94411f5	422
Kojto	116:c0f6e94411f5	423	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto	116:c0f6e94411f5	424	* @{
Kojto	116:c0f6e94411f5	425	*/
Kojto	116:c0f6e94411f5	426	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	427	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
Kojto	116:c0f6e94411f5	428	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
Kojto	116:c0f6e94411f5	429	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
Kojto	116:c0f6e94411f5	430	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
Kojto	116:c0f6e94411f5	431	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
Kojto	116:c0f6e94411f5	432	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
Kojto	116:c0f6e94411f5	433	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	116:c0f6e94411f5	434	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	116:c0f6e94411f5	435	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
Kojto	116:c0f6e94411f5	436	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
Kojto	116:c0f6e94411f5	437	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
Kojto	116:c0f6e94411f5	438	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
Kojto	116:c0f6e94411f5	439	/**
Kojto	116:c0f6e94411f5	440	* @}
Kojto	116:c0f6e94411f5	441	*/
Kojto	116:c0f6e94411f5	442
Kojto	116:c0f6e94411f5	443	/** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source
Kojto	116:c0f6e94411f5	444	* @{
Kojto	116:c0f6e94411f5	445	*/
Kojto	116:c0f6e94411f5	446
Kojto	116:c0f6e94411f5	447	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto	116:c0f6e94411f5	448	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	116:c0f6e94411f5	449	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	116:c0f6e94411f5	450	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
Kojto	116:c0f6e94411f5	451	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	116:c0f6e94411f5	452	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
Kojto	116:c0f6e94411f5	453	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	116:c0f6e94411f5	454	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	116:c0f6e94411f5	455	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	456	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto	116:c0f6e94411f5	457	#endif
Kojto	116:c0f6e94411f5	458
Kojto	116:c0f6e94411f5	459	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	460	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	116:c0f6e94411f5	461	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Kojto	116:c0f6e94411f5	462	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	116:c0f6e94411f5	463	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	116:c0f6e94411f5	464	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
Kojto	116:c0f6e94411f5	465	#else
Kojto	116:c0f6e94411f5	466	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	116:c0f6e94411f5	467	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Kojto	116:c0f6e94411f5	468	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	116:c0f6e94411f5	469	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Kojto	116:c0f6e94411f5	470	#endif
Kojto	116:c0f6e94411f5	471
Kojto	116:c0f6e94411f5	472	/**
Kojto	116:c0f6e94411f5	473	* @}
Kojto	116:c0f6e94411f5	474	*/
Kojto	116:c0f6e94411f5	475
Kojto	116:c0f6e94411f5	476	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
Kojto	116:c0f6e94411f5	477	* @{
Kojto	116:c0f6e94411f5	478	*/
Kojto	116:c0f6e94411f5	479
Kojto	116:c0f6e94411f5	480	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
Kojto	116:c0f6e94411f5	481	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
Kojto	116:c0f6e94411f5	482	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
Kojto	116:c0f6e94411f5	483	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
Kojto	116:c0f6e94411f5	484	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
Kojto	116:c0f6e94411f5	485
Kojto	116:c0f6e94411f5	486	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
Kojto	116:c0f6e94411f5	487	((__DIV__) == RCC_MCODIV_2) \|\| \
Kojto	116:c0f6e94411f5	488	((__DIV__) == RCC_MCODIV_4) \|\| \
Kojto	116:c0f6e94411f5	489	((__DIV__) == RCC_MCODIV_8) \|\| \
Kojto	116:c0f6e94411f5	490	((__DIV__) == RCC_MCODIV_16))
Kojto	116:c0f6e94411f5	491	/**
Kojto	116:c0f6e94411f5	492	* @}
Kojto	116:c0f6e94411f5	493	*/
Kojto	116:c0f6e94411f5	494
Kojto	116:c0f6e94411f5	495	/** @defgroup RCC_MCO_Index RCC MCO Index
Kojto	116:c0f6e94411f5	496	* @{
Kojto	116:c0f6e94411f5	497	*/
Kojto	116:c0f6e94411f5	498	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	499	#define RCC_MCO2 ((uint32_t)0x00000001)
Kojto	116:c0f6e94411f5	500
Kojto	116:c0f6e94411f5	501	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
Kojto	116:c0f6e94411f5	502	/**
Kojto	116:c0f6e94411f5	503	* @}
Kojto	116:c0f6e94411f5	504	*/
Kojto	116:c0f6e94411f5	505
Kojto	116:c0f6e94411f5	506	/** @defgroup RCC_Interrupt RCC Interruptions
Kojto	116:c0f6e94411f5	507	* @{
Kojto	116:c0f6e94411f5	508	*/
Kojto	116:c0f6e94411f5	509	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
Kojto	116:c0f6e94411f5	510	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
Kojto	116:c0f6e94411f5	511	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
Kojto	116:c0f6e94411f5	512	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
Kojto	116:c0f6e94411f5	513	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
Kojto	116:c0f6e94411f5	514	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
Kojto	116:c0f6e94411f5	515
Kojto	116:c0f6e94411f5	516	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
Kojto	116:c0f6e94411f5	517	#define RCC_IT_CSS RCC_CIFR_CSSF
Kojto	116:c0f6e94411f5	518	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	519	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
Kojto	116:c0f6e94411f5	520
Kojto	116:c0f6e94411f5	521	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	116:c0f6e94411f5	522	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	116:c0f6e94411f5	523	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	116:c0f6e94411f5	524	((__IT__) == RCC_IT_HSI48RDY) \|\| ((__IT__) == RCC_IT_LSECSS))
Kojto	116:c0f6e94411f5	525
Kojto	116:c0f6e94411f5	526	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	116:c0f6e94411f5	527	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	116:c0f6e94411f5	528	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	116:c0f6e94411f5	529	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
Kojto	116:c0f6e94411f5	530	((__IT__) == RCC_IT_LSECSS))
Kojto	116:c0f6e94411f5	531
Kojto	116:c0f6e94411f5	532	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	116:c0f6e94411f5	533	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	116:c0f6e94411f5	534	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	116:c0f6e94411f5	535	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
Kojto	116:c0f6e94411f5	536	((__IT__) == RCC_IT_LSECSS))
Kojto	116:c0f6e94411f5	537	#else
Kojto	116:c0f6e94411f5	538	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	116:c0f6e94411f5	539	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	116:c0f6e94411f5	540	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	116:c0f6e94411f5	541	((__IT__) == RCC_IT_LSECSS))
Kojto	116:c0f6e94411f5	542
Kojto	116:c0f6e94411f5	543	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	116:c0f6e94411f5	544	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	116:c0f6e94411f5	545	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	116:c0f6e94411f5	546	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
Kojto	116:c0f6e94411f5	547
Kojto	116:c0f6e94411f5	548
Kojto	116:c0f6e94411f5	549	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	116:c0f6e94411f5	550	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	116:c0f6e94411f5	551	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	116:c0f6e94411f5	552	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
Kojto	116:c0f6e94411f5	553
Kojto	116:c0f6e94411f5	554	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	116:c0f6e94411f5	555	/**
Kojto	116:c0f6e94411f5	556	* @}
Kojto	116:c0f6e94411f5	557	*/
Kojto	116:c0f6e94411f5	558
Kojto	116:c0f6e94411f5	559	/** @defgroup RCC_Flag
Kojto	116:c0f6e94411f5	560	* Elements values convention: 0XXYYYYYb
Kojto	116:c0f6e94411f5	561	* - YYYYY : Flag position in the register
Kojto	116:c0f6e94411f5	562	* - 0XX : Register index
Kojto	116:c0f6e94411f5	563	* - 01: CR register
Kojto	116:c0f6e94411f5	564	* - 10: CSR register
Kojto	116:c0f6e94411f5	565	* - 11: CRRCR register
Kojto	116:c0f6e94411f5	566	* @{
Kojto	116:c0f6e94411f5	567	*/
Kojto	116:c0f6e94411f5	568	/* Flags in the CR register */
Kojto	116:c0f6e94411f5	569	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
Kojto	116:c0f6e94411f5	570	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
Kojto	116:c0f6e94411f5	571	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
Kojto	116:c0f6e94411f5	572	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto	116:c0f6e94411f5	573	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto	116:c0f6e94411f5	574
Kojto	116:c0f6e94411f5	575	/* Flags in the CSR register */
Kojto	116:c0f6e94411f5	576	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
Kojto	116:c0f6e94411f5	577	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
Kojto	116:c0f6e94411f5	578	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
Kojto	116:c0f6e94411f5	579	#define RCC_FLAG_FWRST ((uint8_t)0x58)
Kojto	116:c0f6e94411f5	580	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
Kojto	116:c0f6e94411f5	581	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
Kojto	116:c0f6e94411f5	582	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
Kojto	116:c0f6e94411f5	583	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
Kojto	116:c0f6e94411f5	584	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
Kojto	116:c0f6e94411f5	585	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
Kojto	116:c0f6e94411f5	586	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
Kojto	116:c0f6e94411f5	587
Kojto	116:c0f6e94411f5	588	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	116:c0f6e94411f5	589	/* Flags in the CRRCR register */
Kojto	116:c0f6e94411f5	590	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
Kojto	116:c0f6e94411f5	591	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	116:c0f6e94411f5	592
Kojto	116:c0f6e94411f5	593	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	116:c0f6e94411f5	594	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
Kojto	116:c0f6e94411f5	595
Kojto	116:c0f6e94411f5	596	/**
Kojto	116:c0f6e94411f5	597	* @}
Kojto	116:c0f6e94411f5	598	*/
Kojto	116:c0f6e94411f5	599
Kojto	116:c0f6e94411f5	600	/**
Kojto	116:c0f6e94411f5	601	* @}
Kojto	116:c0f6e94411f5	602	*/
Kojto	116:c0f6e94411f5	603	/* Exported macro ------------------------------------------------------------*/
Kojto	116:c0f6e94411f5	604	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	116:c0f6e94411f5	605	* @{
Kojto	116:c0f6e94411f5	606	*/
Kojto	116:c0f6e94411f5	607
Kojto	116:c0f6e94411f5	608	/** @brief Enable or disable the AHB peripheral clock.
Kojto	116:c0f6e94411f5	609	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	116:c0f6e94411f5	610	* is disabled and the application software has to enable this clock before
Kojto	116:c0f6e94411f5	611	* using it.
Kojto	116:c0f6e94411f5	612	*/
Kojto	116:c0f6e94411f5	613	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	614	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	615	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	116:c0f6e94411f5	616	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	617	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	116:c0f6e94411f5	618	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	619	} while(0)
Kojto	116:c0f6e94411f5	620
Kojto	116:c0f6e94411f5	621	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	622	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	623	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
Kojto	116:c0f6e94411f5	624	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	625	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
Kojto	116:c0f6e94411f5	626	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	627	} while(0)
Kojto	116:c0f6e94411f5	628
Kojto	116:c0f6e94411f5	629	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	630	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	631	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	116:c0f6e94411f5	632	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	633	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	116:c0f6e94411f5	634	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	635	} while(0)
Kojto	116:c0f6e94411f5	636
Kojto	116:c0f6e94411f5	637
Kojto	116:c0f6e94411f5	638	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
Kojto	116:c0f6e94411f5	639	#define __HAL_RCC_MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
Kojto	116:c0f6e94411f5	640	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
Kojto	116:c0f6e94411f5	641
Kojto	116:c0f6e94411f5	642
Kojto	116:c0f6e94411f5	643	/** @brief Enable or disable the IOPORT peripheral clock.
Kojto	116:c0f6e94411f5	644	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	116:c0f6e94411f5	645	* is disabled and the application software has to enable this clock before
Kojto	116:c0f6e94411f5	646	* using it.
Kojto	116:c0f6e94411f5	647	*/
Kojto	116:c0f6e94411f5	648	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	649	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	650	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
Kojto	116:c0f6e94411f5	651	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	652	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
Kojto	116:c0f6e94411f5	653	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	654	} while(0)
Kojto	116:c0f6e94411f5	655
Kojto	116:c0f6e94411f5	656	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	657	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	658	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
Kojto	116:c0f6e94411f5	659	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	660	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
Kojto	116:c0f6e94411f5	661	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	662	} while(0)
Kojto	116:c0f6e94411f5	663
Kojto	116:c0f6e94411f5	664	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	665	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	666	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
Kojto	116:c0f6e94411f5	667	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	668	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
Kojto	116:c0f6e94411f5	669	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	670	} while(0)
Kojto	116:c0f6e94411f5	671
Kojto	116:c0f6e94411f5	672	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	673	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	674	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
Kojto	116:c0f6e94411f5	675	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	676	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
Kojto	116:c0f6e94411f5	677	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	678	} while(0)
Kojto	116:c0f6e94411f5	679
Kojto	116:c0f6e94411f5	680	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	681	__IO uint32_t tmpreg; \
Kojto	116:c0f6e94411f5	682	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
Kojto	116:c0f6e94411f5	683	/* Delay after an RCC peripheral clock enabling */ \
Kojto	116:c0f6e94411f5	684	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
Kojto	116:c0f6e94411f5	685	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	686	} while(0)
Kojto	116:c0f6e94411f5	687
Kojto	116:c0f6e94411f5	688
Kojto	116:c0f6e94411f5	689	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
Kojto	116:c0f6e94411f5	690	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
Kojto	116:c0f6e94411f5	691	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
Kojto	116:c0f6e94411f5	692	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
Kojto	116:c0f6e94411f5	693	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
Kojto	116:c0f6e94411f5	694
Kojto	116:c0f6e94411f5	695
Kojto	116:c0f6e94411f5	696	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	116:c0f6e94411f5	697	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	116:c0f6e94411f5	698	* is disabled and the application software has to enable this clock before
Kojto	116:c0f6e94411f5	699	* using it.
Kojto	116:c0f6e94411f5	700	*/
Kojto	116:c0f6e94411f5	701	#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
Kojto	116:c0f6e94411f5	702	#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
Kojto	116:c0f6e94411f5	703
Kojto	116:c0f6e94411f5	704	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
Kojto	116:c0f6e94411f5	705	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
Kojto	116:c0f6e94411f5	706
Kojto	116:c0f6e94411f5	707	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	116:c0f6e94411f5	708	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	116:c0f6e94411f5	709	* is disabled and the application software has to enable this clock before
Kojto	116:c0f6e94411f5	710	* using it.
Kojto	116:c0f6e94411f5	711	*/
Kojto	116:c0f6e94411f5	712	#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
Kojto	116:c0f6e94411f5	713	#define __HAL_RCC_DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
Kojto	116:c0f6e94411f5	714
Kojto	116:c0f6e94411f5	715	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
Kojto	116:c0f6e94411f5	716	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
Kojto	116:c0f6e94411f5	717
Kojto	116:c0f6e94411f5	718	/** @brief Force or release AHB peripheral reset.
Kojto	116:c0f6e94411f5	719	*/
Kojto	116:c0f6e94411f5	720	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	116:c0f6e94411f5	721	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
Kojto	116:c0f6e94411f5	722	#define __HAL_RCC_MIF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_MIFRST))
Kojto	116:c0f6e94411f5	723	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
Kojto	116:c0f6e94411f5	724
Kojto	116:c0f6e94411f5	725	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	116:c0f6e94411f5	726	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
Kojto	116:c0f6e94411f5	727	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
Kojto	116:c0f6e94411f5	728	#define __HAL_RCC_MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
Kojto	116:c0f6e94411f5	729
Kojto	116:c0f6e94411f5	730
Kojto	116:c0f6e94411f5	731	/** @brief Force or release IOPORT peripheral reset.
Kojto	116:c0f6e94411f5	732	*/
Kojto	116:c0f6e94411f5	733	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
Kojto	116:c0f6e94411f5	734	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOARST))
Kojto	116:c0f6e94411f5	735	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOBRST))
Kojto	116:c0f6e94411f5	736	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOCRST))
Kojto	116:c0f6e94411f5	737	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIODRST))
Kojto	116:c0f6e94411f5	738	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOHRST))
Kojto	116:c0f6e94411f5	739
Kojto	116:c0f6e94411f5	740	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
Kojto	116:c0f6e94411f5	741	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
Kojto	116:c0f6e94411f5	742	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
Kojto	116:c0f6e94411f5	743	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
Kojto	116:c0f6e94411f5	744	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
Kojto	116:c0f6e94411f5	745	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
Kojto	116:c0f6e94411f5	746
Kojto	116:c0f6e94411f5	747	/** @brief Force or release APB1 peripheral reset.
Kojto	116:c0f6e94411f5	748	*/
Kojto	116:c0f6e94411f5	749	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	116:c0f6e94411f5	750	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	116:c0f6e94411f5	751	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	116:c0f6e94411f5	752
Kojto	116:c0f6e94411f5	753	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	116:c0f6e94411f5	754	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
Kojto	116:c0f6e94411f5	755	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
Kojto	116:c0f6e94411f5	756
Kojto	116:c0f6e94411f5	757	/** @brief Force or release APB2 peripheral reset.
Kojto	116:c0f6e94411f5	758	*/
Kojto	116:c0f6e94411f5	759	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	116:c0f6e94411f5	760	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
Kojto	116:c0f6e94411f5	761	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	116:c0f6e94411f5	762
Kojto	116:c0f6e94411f5	763	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	116:c0f6e94411f5	764	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
Kojto	116:c0f6e94411f5	765	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
Kojto	116:c0f6e94411f5	766
Kojto	116:c0f6e94411f5	767	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
Kojto	116:c0f6e94411f5	768	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	116:c0f6e94411f5	769	* power consumption.
Kojto	116:c0f6e94411f5	770	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	116:c0f6e94411f5	771	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto	116:c0f6e94411f5	772	*/
Kojto	116:c0f6e94411f5	773	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_CRCSMEN))
Kojto	116:c0f6e94411f5	774	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_MIFSMEN))
Kojto	116:c0f6e94411f5	775	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_SRAMSMEN))
Kojto	116:c0f6e94411f5	776	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_DMA1SMEN))
Kojto	116:c0f6e94411f5	777
Kojto	116:c0f6e94411f5	778	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
Kojto	116:c0f6e94411f5	779	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
Kojto	116:c0f6e94411f5	780	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
Kojto	116:c0f6e94411f5	781	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
Kojto	116:c0f6e94411f5	782
Kojto	116:c0f6e94411f5	783	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
Kojto	116:c0f6e94411f5	784	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	116:c0f6e94411f5	785	* power consumption.
Kojto	116:c0f6e94411f5	786	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	116:c0f6e94411f5	787	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto	116:c0f6e94411f5	788	*/
Kojto	116:c0f6e94411f5	789
Kojto	116:c0f6e94411f5	790	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOASMEN))
Kojto	116:c0f6e94411f5	791	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOBSMEN))
Kojto	116:c0f6e94411f5	792	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOCSMEN))
Kojto	116:c0f6e94411f5	793	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIODSMEN))
Kojto	116:c0f6e94411f5	794	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOHSMEN))
Kojto	116:c0f6e94411f5	795
Kojto	116:c0f6e94411f5	796	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
Kojto	116:c0f6e94411f5	797	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
Kojto	116:c0f6e94411f5	798	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
Kojto	116:c0f6e94411f5	799	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
Kojto	116:c0f6e94411f5	800	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
Kojto	116:c0f6e94411f5	801
Kojto	116:c0f6e94411f5	802	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	116:c0f6e94411f5	803	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	116:c0f6e94411f5	804	* power consumption.
Kojto	116:c0f6e94411f5	805	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	116:c0f6e94411f5	806	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto	116:c0f6e94411f5	807	*/
Kojto	116:c0f6e94411f5	808	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_WWDGSMEN))
Kojto	116:c0f6e94411f5	809	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_PWRSMEN))
Kojto	116:c0f6e94411f5	810
Kojto	116:c0f6e94411f5	811	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
Kojto	116:c0f6e94411f5	812	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
Kojto	116:c0f6e94411f5	813
Kojto	116:c0f6e94411f5	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	116:c0f6e94411f5	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	116:c0f6e94411f5	816	* power consumption.
Kojto	116:c0f6e94411f5	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	116:c0f6e94411f5	818	* @note By default, all peripheral actiated clocks remain enabled during SLEEP mode.
Kojto	116:c0f6e94411f5	819	*/
Kojto	116:c0f6e94411f5	820	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SYSCFGSMEN))
Kojto	116:c0f6e94411f5	821	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_DBGMCUSMEN))
Kojto	116:c0f6e94411f5	822
Kojto	116:c0f6e94411f5	823	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
Kojto	116:c0f6e94411f5	824	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
Kojto	116:c0f6e94411f5	825
Kojto	116:c0f6e94411f5	826	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
Kojto	116:c0f6e94411f5	827	* @note After enabling the HSI, the application software should wait on
Kojto	116:c0f6e94411f5	828	* HSIRDY flag to be set indicating that HSI clock is stable and can
Kojto	116:c0f6e94411f5	829	* be used to clock the PLL and/or system clock.
Kojto	116:c0f6e94411f5	830	* @note HSI can not be stopped if it is used directly or through the PLL
Kojto	116:c0f6e94411f5	831	* as system clock. In this case, you have to select another source
Kojto	116:c0f6e94411f5	832	* of the system clock then stop the HSI.
Kojto	116:c0f6e94411f5	833	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	116:c0f6e94411f5	834	* @param __STATE__: specifies the new state of the HSI.
Kojto	116:c0f6e94411f5	835	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	836	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
Kojto	116:c0f6e94411f5	837	* @arg RCC_HSI_ON: turn ON the HSI oscillator
Kojto	116:c0f6e94411f5	838	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
Kojto	116:c0f6e94411f5	839	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	116:c0f6e94411f5	840	* clock cycles.
Kojto	116:c0f6e94411f5	841	*/
Kojto	116:c0f6e94411f5	842	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
Kojto	116:c0f6e94411f5	843	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
Kojto	116:c0f6e94411f5	844
Kojto	116:c0f6e94411f5	845	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	116:c0f6e94411f5	846	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	116:c0f6e94411f5	847	* It is used (enabled by hardware) as system clock source after startup
Kojto	116:c0f6e94411f5	848	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	116:c0f6e94411f5	849	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	116:c0f6e94411f5	850	* Security System CSS is enabled).
Kojto	116:c0f6e94411f5	851	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	116:c0f6e94411f5	852	* you have to select another source of the system clock then stop the HSI.
Kojto	116:c0f6e94411f5	853	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	116:c0f6e94411f5	854	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	116:c0f6e94411f5	855	* system clock source.
Kojto	116:c0f6e94411f5	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	116:c0f6e94411f5	857	* clock cycles.
Kojto	116:c0f6e94411f5	858	*/
Kojto	116:c0f6e94411f5	859	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto	116:c0f6e94411f5	860	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto	116:c0f6e94411f5	861
Kojto	116:c0f6e94411f5	862	/**
Kojto	116:c0f6e94411f5	863	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto	116:c0f6e94411f5	864	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	116:c0f6e94411f5	865	* It is used (enabled by hardware) as system clock source after
Kojto	116:c0f6e94411f5	866	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
Kojto	116:c0f6e94411f5	867	* of failure of the HSE used directly or indirectly as system clock
Kojto	116:c0f6e94411f5	868	* (if the Clock Security System CSS is enabled).
Kojto	116:c0f6e94411f5	869	* @note MSI can not be stopped if it is used as system clock source.
Kojto	116:c0f6e94411f5	870	* In this case, you have to select another source of the system
Kojto	116:c0f6e94411f5	871	* clock then stop the MSI.
Kojto	116:c0f6e94411f5	872	* @note After enabling the MSI, the application software should wait on
Kojto	116:c0f6e94411f5	873	* MSIRDY flag to be set indicating that MSI clock is stable and can
Kojto	116:c0f6e94411f5	874	* be used as system clock source.
Kojto	116:c0f6e94411f5	875	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto	116:c0f6e94411f5	876	* clock cycles.
Kojto	116:c0f6e94411f5	877	*/
Kojto	116:c0f6e94411f5	878	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Kojto	116:c0f6e94411f5	879	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
Kojto	116:c0f6e94411f5	880
Kojto	116:c0f6e94411f5	881	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	116:c0f6e94411f5	882	* @note The calibration is used to compensate for the variations in voltage
Kojto	116:c0f6e94411f5	883	* and temperature that influence the frequency of the internal HSI RC.
Kojto	116:c0f6e94411f5	884	* @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto	116:c0f6e94411f5	885	* This parameter must be a number between 0 and 0x1F.
Kojto	116:c0f6e94411f5	886	*/
Kojto	116:c0f6e94411f5	887	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
Kojto	116:c0f6e94411f5	888	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
Kojto	116:c0f6e94411f5	889
Kojto	116:c0f6e94411f5	890	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
Kojto	116:c0f6e94411f5	891	* @note The calibration is used to compensate for the variations in voltage
Kojto	116:c0f6e94411f5	892	* and temperature that influence the frequency of the internal MSI RC.
Kojto	116:c0f6e94411f5	893	* Refer to the Application Note AN3300 for more details on how to
Kojto	116:c0f6e94411f5	894	* calibrate the MSI.
Kojto	116:c0f6e94411f5	895	* @param __MSICalibrationValue__: specifies the calibration trimming value.
Kojto	116:c0f6e94411f5	896	* This parameter must be a number between 0 and 0xFF.
Kojto	116:c0f6e94411f5	897	*/
Kojto	116:c0f6e94411f5	898	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
Kojto	116:c0f6e94411f5	899	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
Kojto	116:c0f6e94411f5	900
Kojto	116:c0f6e94411f5	901	/**
Kojto	116:c0f6e94411f5	902	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
Kojto	116:c0f6e94411f5	903	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
Kojto	116:c0f6e94411f5	904	* around 2.097 MHz. The MSI clock does not change after wake-up from
Kojto	116:c0f6e94411f5	905	* STOP mode.
Kojto	116:c0f6e94411f5	906	* @note The MSI clock range can be modified on the fly.
Kojto	116:c0f6e94411f5	907	* @param RCC_MSIRange: specifies the MSI Clock range.
Kojto	116:c0f6e94411f5	908	* This parameter must be one of the following values:
Kojto	116:c0f6e94411f5	909	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
Kojto	116:c0f6e94411f5	910	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
Kojto	116:c0f6e94411f5	911	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
Kojto	116:c0f6e94411f5	912	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
Kojto	116:c0f6e94411f5	913	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
Kojto	116:c0f6e94411f5	914	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Kojto	116:c0f6e94411f5	915	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
Kojto	116:c0f6e94411f5	916	*/
Kojto	116:c0f6e94411f5	917	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
Kojto	116:c0f6e94411f5	918	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
Kojto	116:c0f6e94411f5	919
Kojto	116:c0f6e94411f5	920	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	116:c0f6e94411f5	921	* @note After enabling the LSI, the application software should wait on
Kojto	116:c0f6e94411f5	922	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	116:c0f6e94411f5	923	* be used to clock the IWDG and/or the RTC.
Kojto	116:c0f6e94411f5	924	* @note LSI can not be disabled if the IWDG is running.
Kojto	116:c0f6e94411f5	925	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	116:c0f6e94411f5	926	* clock cycles.
Kojto	116:c0f6e94411f5	927	*/
Kojto	116:c0f6e94411f5	928	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	116:c0f6e94411f5	929	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	116:c0f6e94411f5	930
Kojto	116:c0f6e94411f5	931	/**
Kojto	116:c0f6e94411f5	932	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	116:c0f6e94411f5	933	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	116:c0f6e94411f5	934	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	116:c0f6e94411f5	935	* is stable and can be used to clock the PLL and/or system clock.
Kojto	116:c0f6e94411f5	936	* @note HSE state can not be changed if it is used directly or through the
Kojto	116:c0f6e94411f5	937	* PLL as system clock. In this case, you have to select another source
Kojto	116:c0f6e94411f5	938	* of the system clock then change the HSE state (ex. disable it).
Kojto	116:c0f6e94411f5	939	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	116:c0f6e94411f5	940	* @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto	116:c0f6e94411f5	941	* was previously enabled you have to enable it again after calling this
Kojto	116:c0f6e94411f5	942	* function.
Kojto	116:c0f6e94411f5	943	* @param __STATE__: specifies the new state of the HSE.
Kojto	116:c0f6e94411f5	944	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	945	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	116:c0f6e94411f5	946	* 6 HSE oscillator clock cycles.
Kojto	116:c0f6e94411f5	947	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto	116:c0f6e94411f5	948	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto	116:c0f6e94411f5	949	*/
Kojto	116:c0f6e94411f5	950	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	116:c0f6e94411f5	951	do { \
Kojto	116:c0f6e94411f5	952	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	116:c0f6e94411f5	953	if((__STATE__) == RCC_HSE_ON) \
Kojto	116:c0f6e94411f5	954	{ \
Kojto	116:c0f6e94411f5	955	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	116:c0f6e94411f5	956	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	116:c0f6e94411f5	957	} \
Kojto	116:c0f6e94411f5	958	else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto	116:c0f6e94411f5	959	{ \
Kojto	116:c0f6e94411f5	960	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	116:c0f6e94411f5	961	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	116:c0f6e94411f5	962	} \
Kojto	116:c0f6e94411f5	963	else \
Kojto	116:c0f6e94411f5	964	{ \
Kojto	116:c0f6e94411f5	965	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	116:c0f6e94411f5	966	} \
Kojto	116:c0f6e94411f5	967	} while(0)
Kojto	116:c0f6e94411f5	968
Kojto	116:c0f6e94411f5	969	/**
Kojto	116:c0f6e94411f5	970	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	116:c0f6e94411f5	971	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	116:c0f6e94411f5	972	* this domain after reset, you have to enable write access using
Kojto	116:c0f6e94411f5	973	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	116:c0f6e94411f5	974	* (to be done once after reset).
Kojto	116:c0f6e94411f5	975	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	116:c0f6e94411f5	976	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	116:c0f6e94411f5	977	* is stable and can be used to clock the RTC.
Kojto	116:c0f6e94411f5	978	* @param __STATE__: specifies the new state of the LSE.
Kojto	116:c0f6e94411f5	979	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	980	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	116:c0f6e94411f5	981	* 6 LSE oscillator clock cycles.
Kojto	116:c0f6e94411f5	982	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	116:c0f6e94411f5	983	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto	116:c0f6e94411f5	984	*/
Kojto	116:c0f6e94411f5	985	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	116:c0f6e94411f5	986	do { \
Kojto	116:c0f6e94411f5	987	if((__STATE__) == RCC_LSE_ON) \
Kojto	116:c0f6e94411f5	988	{ \
Kojto	116:c0f6e94411f5	989	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	116:c0f6e94411f5	990	} \
Kojto	116:c0f6e94411f5	991	else if((__STATE__) == RCC_LSE_OFF) \
Kojto	116:c0f6e94411f5	992	{ \
Kojto	116:c0f6e94411f5	993	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	116:c0f6e94411f5	994	} \
Kojto	116:c0f6e94411f5	995	else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto	116:c0f6e94411f5	996	{ \
Kojto	116:c0f6e94411f5	997	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	116:c0f6e94411f5	998	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto	116:c0f6e94411f5	999	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	116:c0f6e94411f5	1000	} \
Kojto	116:c0f6e94411f5	1001	else \
Kojto	116:c0f6e94411f5	1002	{ \
Kojto	116:c0f6e94411f5	1003	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	116:c0f6e94411f5	1004	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto	116:c0f6e94411f5	1005	} \
Kojto	116:c0f6e94411f5	1006	} while(0)
Kojto	116:c0f6e94411f5	1007
Kojto	116:c0f6e94411f5	1008	/** @brief Macros to enable or disable the the RTC clock.
Kojto	116:c0f6e94411f5	1009	* @note These macros must be used only after the RTC clock source was selected.
Kojto	116:c0f6e94411f5	1010	*/
Kojto	116:c0f6e94411f5	1011	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
Kojto	116:c0f6e94411f5	1012	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
Kojto	116:c0f6e94411f5	1013
Kojto	116:c0f6e94411f5	1014	/**
Kojto	116:c0f6e94411f5	1015	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
Kojto	116:c0f6e94411f5	1016	* @note As the RTC clock configuration bits are in the RTC domain and write
Kojto	116:c0f6e94411f5	1017	* access is denied to this domain after reset, you have to enable write
Kojto	116:c0f6e94411f5	1018	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
Kojto	116:c0f6e94411f5	1019	* the RTC clock source (to be done once after reset).
Kojto	116:c0f6e94411f5	1020	* @note Once the RTC clock is configured it cannot be changed unless the RTC
Kojto	116:c0f6e94411f5	1021	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
Kojto	116:c0f6e94411f5	1022	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
Kojto	116:c0f6e94411f5	1023	*
Kojto	116:c0f6e94411f5	1024	* @param RCC_RTCCLKSource: specifies the RTC clock source.
Kojto	116:c0f6e94411f5	1025	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1026	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	116:c0f6e94411f5	1027	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	116:c0f6e94411f5	1028	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
Kojto	116:c0f6e94411f5	1029	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
Kojto	116:c0f6e94411f5	1030	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
Kojto	116:c0f6e94411f5	1031	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
Kojto	116:c0f6e94411f5	1032	*
Kojto	116:c0f6e94411f5	1033	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	116:c0f6e94411f5	1034	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	116:c0f6e94411f5	1035	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	116:c0f6e94411f5	1036	* cannot be used in STOP and STANDBY modes.
Kojto	116:c0f6e94411f5	1037	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	116:c0f6e94411f5	1038	* RTC clock source).
Kojto	116:c0f6e94411f5	1039	*/
Kojto	116:c0f6e94411f5	1040	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
Kojto	116:c0f6e94411f5	1041	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
Kojto	116:c0f6e94411f5	1042
Kojto	116:c0f6e94411f5	1043	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto	116:c0f6e94411f5	1044	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
Kojto	116:c0f6e94411f5	1045	} while (0)
Kojto	116:c0f6e94411f5	1046
Kojto	116:c0f6e94411f5	1047	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
Kojto	116:c0f6e94411f5	1048
Kojto	116:c0f6e94411f5	1049	/** @brief Macros to force or release the Backup domain reset.
Kojto	116:c0f6e94411f5	1050	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	116:c0f6e94411f5	1051	* and the RTC clock source selection in RCC_CSR register.
Kojto	116:c0f6e94411f5	1052	* @note The BKPSRAM is not affected by this reset.
Kojto	116:c0f6e94411f5	1053	*/
Kojto	116:c0f6e94411f5	1054	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
Kojto	116:c0f6e94411f5	1055	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
Kojto	116:c0f6e94411f5	1056
Kojto	116:c0f6e94411f5	1057	/** @brief Macros to enable or disable the main PLL.
Kojto	116:c0f6e94411f5	1058	* @note After enabling the main PLL, the application software should wait on
Kojto	116:c0f6e94411f5	1059	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	116:c0f6e94411f5	1060	* be used as system clock source.
Kojto	116:c0f6e94411f5	1061	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	116:c0f6e94411f5	1062	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	116:c0f6e94411f5	1063	*/
Kojto	116:c0f6e94411f5	1064	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	116:c0f6e94411f5	1065	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	116:c0f6e94411f5	1066
Kojto	116:c0f6e94411f5	1067	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	116:c0f6e94411f5	1068	* @note This function must be used only when the main PLL is disabled.
Kojto	116:c0f6e94411f5	1069	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	116:c0f6e94411f5	1070	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1071	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	116:c0f6e94411f5	1072	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	116:c0f6e94411f5	1073	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
Kojto	116:c0f6e94411f5	1074	* This parameter must be one of the following values:
Kojto	116:c0f6e94411f5	1075	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
Kojto	116:c0f6e94411f5	1076	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
Kojto	116:c0f6e94411f5	1077	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
Kojto	116:c0f6e94411f5	1078	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
Kojto	116:c0f6e94411f5	1079	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
Kojto	116:c0f6e94411f5	1080	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
Kojto	116:c0f6e94411f5	1081	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
Kojto	116:c0f6e94411f5	1082	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
Kojto	116:c0f6e94411f5	1083	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
Kojto	116:c0f6e94411f5	1084	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Kojto	116:c0f6e94411f5	1085	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
Kojto	116:c0f6e94411f5	1086	* in Range 3.
Kojto	116:c0f6e94411f5	1087	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
Kojto	116:c0f6e94411f5	1088	* This parameter must be one of the following values:
Kojto	116:c0f6e94411f5	1089	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
Kojto	116:c0f6e94411f5	1090	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
Kojto	116:c0f6e94411f5	1091	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
Kojto	116:c0f6e94411f5	1092	*/
Kojto	116:c0f6e94411f5	1093
Kojto	116:c0f6e94411f5	1094	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
Kojto	116:c0f6e94411f5	1095	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSource__)))
Kojto	116:c0f6e94411f5	1096
Kojto	116:c0f6e94411f5	1097	/** @brief Macro to get the clock source used as system clock.
Kojto	116:c0f6e94411f5	1098	* @retval The clock source used as system clock. The returned value can be one
Kojto	116:c0f6e94411f5	1099	* of the following:
Kojto	116:c0f6e94411f5	1100	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
Kojto	116:c0f6e94411f5	1101	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
Kojto	116:c0f6e94411f5	1102	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
Kojto	116:c0f6e94411f5	1103	*/
Kojto	116:c0f6e94411f5	1104	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto	116:c0f6e94411f5	1105
Kojto	116:c0f6e94411f5	1106	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	116:c0f6e94411f5	1107	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	116:c0f6e94411f5	1108	* of the following:
Kojto	116:c0f6e94411f5	1109	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	116:c0f6e94411f5	1110	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	116:c0f6e94411f5	1111	*/
Kojto	116:c0f6e94411f5	1112	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto	116:c0f6e94411f5	1113
Kojto	116:c0f6e94411f5	1114	/** @defgroup RCC_Flags_Interrupts_Management
Kojto	116:c0f6e94411f5	1115	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	116:c0f6e94411f5	1116	* @{
Kojto	116:c0f6e94411f5	1117	*/
Kojto	116:c0f6e94411f5	1118
Kojto	116:c0f6e94411f5	1119	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
Kojto	116:c0f6e94411f5	1120	* the selected interrupts).
Kojto	116:c0f6e94411f5	1121	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
Kojto	116:c0f6e94411f5	1122	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
Kojto	116:c0f6e94411f5	1123	* automatically generated. The NMI will be executed indefinitely, and
Kojto	116:c0f6e94411f5	1124	* since NMI has higher priority than any other IRQ (and main program)
Kojto	116:c0f6e94411f5	1125	* the application will be stacked in the NMI ISR unless the CSS interrupt
Kojto	116:c0f6e94411f5	1126	* pending bit is cleared.
Kojto	116:c0f6e94411f5	1127	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	116:c0f6e94411f5	1128	* This parameter can be any combination of the following values:
Kojto	116:c0f6e94411f5	1129	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	116:c0f6e94411f5	1130	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	116:c0f6e94411f5	1131	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	116:c0f6e94411f5	1132	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	116:c0f6e94411f5	1133	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	116:c0f6e94411f5	1134	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	116:c0f6e94411f5	1135	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	116:c0f6e94411f5	1136	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto	116:c0f6e94411f5	1137	*/
Kojto	116:c0f6e94411f5	1138	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER \|= (__INTERRUPT__))
Kojto	116:c0f6e94411f5	1139
Kojto	116:c0f6e94411f5	1140	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
Kojto	116:c0f6e94411f5	1141	* the selected interrupts).
Kojto	116:c0f6e94411f5	1142	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
Kojto	116:c0f6e94411f5	1143	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
Kojto	116:c0f6e94411f5	1144	* automatically generated. The NMI will be executed indefinitely, and
Kojto	116:c0f6e94411f5	1145	* since NMI has higher priority than any other IRQ (and main program)
Kojto	116:c0f6e94411f5	1146	* the application will be stacked in the NMI ISR unless the CSS interrupt
Kojto	116:c0f6e94411f5	1147	* pending bit is cleared.
Kojto	116:c0f6e94411f5	1148	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	116:c0f6e94411f5	1149	* This parameter can be any combination of the following values:
Kojto	116:c0f6e94411f5	1150	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	116:c0f6e94411f5	1151	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	116:c0f6e94411f5	1152	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	116:c0f6e94411f5	1153	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	116:c0f6e94411f5	1154	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	116:c0f6e94411f5	1155	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	116:c0f6e94411f5	1156	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto	116:c0f6e94411f5	1157	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	116:c0f6e94411f5	1158
Kojto	116:c0f6e94411f5	1159	*/
Kojto	116:c0f6e94411f5	1160	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__))
Kojto	116:c0f6e94411f5	1161
Kojto	116:c0f6e94411f5	1162	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto	116:c0f6e94411f5	1163	* bits to clear the selected interrupt pending bits.
Kojto	116:c0f6e94411f5	1164	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	116:c0f6e94411f5	1165	* This parameter can be any combination of the following values:
Kojto	116:c0f6e94411f5	1166	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	116:c0f6e94411f5	1167	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	116:c0f6e94411f5	1168	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	116:c0f6e94411f5	1169	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	116:c0f6e94411f5	1170	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	116:c0f6e94411f5	1171	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	116:c0f6e94411f5	1172	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto	116:c0f6e94411f5	1173	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	116:c0f6e94411f5	1174	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	116:c0f6e94411f5	1175	*/
Kojto	116:c0f6e94411f5	1176	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Kojto	116:c0f6e94411f5	1177
Kojto	116:c0f6e94411f5	1178	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	116:c0f6e94411f5	1179	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	116:c0f6e94411f5	1180	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1181	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	116:c0f6e94411f5	1182	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	116:c0f6e94411f5	1183	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	116:c0f6e94411f5	1184	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	116:c0f6e94411f5	1185	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	116:c0f6e94411f5	1186	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	116:c0f6e94411f5	1187	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	116:c0f6e94411f5	1188	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	116:c0f6e94411f5	1189	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	116:c0f6e94411f5	1190	*/
Kojto	116:c0f6e94411f5	1191	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	116:c0f6e94411f5	1192
Kojto	116:c0f6e94411f5	1193	/** @brief Set RMVF bit to clear the reset flags.
Kojto	116:c0f6e94411f5	1194	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto	116:c0f6e94411f5	1195	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Kojto	116:c0f6e94411f5	1196	*/
Kojto	116:c0f6e94411f5	1197	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	116:c0f6e94411f5	1198
Kojto	116:c0f6e94411f5	1199	/** @brief Check RCC flag is set or not.
Kojto	116:c0f6e94411f5	1200	* @param __FLAG__: specifies the flag to check.
Kojto	116:c0f6e94411f5	1201	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1202	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto	116:c0f6e94411f5	1203	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
Kojto	116:c0f6e94411f5	1204	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto	116:c0f6e94411f5	1205	* @arg RCC_FLAG_PLLRDY: PLL clock ready
Kojto	116:c0f6e94411f5	1206	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
Kojto	116:c0f6e94411f5	1207	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto	116:c0f6e94411f5	1208	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto	116:c0f6e94411f5	1209	* @arg RCC_FLAG_FWRST: Firewall reset
Kojto	116:c0f6e94411f5	1210	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
Kojto	116:c0f6e94411f5	1211	* @arg RCC_FLAG_PINRST: Pin reset
Kojto	116:c0f6e94411f5	1212	* @arg RCC_FLAG_PORRST: POR/PDR reset
Kojto	116:c0f6e94411f5	1213	* @arg RCC_FLAG_SFTRST: Software reset
Kojto	116:c0f6e94411f5	1214	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto	116:c0f6e94411f5	1215	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto	116:c0f6e94411f5	1216	* @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto	116:c0f6e94411f5	1217	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	116:c0f6e94411f5	1218	*/
Kojto	116:c0f6e94411f5	1219	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	116:c0f6e94411f5	1220	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
Kojto	116:c0f6e94411f5	1221	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
Kojto	116:c0f6e94411f5	1222
Kojto	116:c0f6e94411f5	1223	/**
Kojto	116:c0f6e94411f5	1224	* @}
Kojto	116:c0f6e94411f5	1225	*/
Kojto	116:c0f6e94411f5	1226
Kojto	116:c0f6e94411f5	1227	/**
Kojto	116:c0f6e94411f5	1228	* @}
Kojto	116:c0f6e94411f5	1229	*/
Kojto	116:c0f6e94411f5	1230
Kojto	116:c0f6e94411f5	1231	/* Include RCC HAL Extension module */
Kojto	116:c0f6e94411f5	1232	#include "stm32l0xx_hal_rcc_ex.h"
Kojto	116:c0f6e94411f5	1233
Kojto	116:c0f6e94411f5	1234	/** @defgroup RCC_Exported_Functions RCC Exported Functions
Kojto	116:c0f6e94411f5	1235	* @{
Kojto	116:c0f6e94411f5	1236	*/
Kojto	116:c0f6e94411f5	1237
Kojto	116:c0f6e94411f5	1238	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto	116:c0f6e94411f5	1239	* @{
Kojto	116:c0f6e94411f5	1240	*/
Kojto	116:c0f6e94411f5	1241	void HAL_RCC_DeInit(void);
Kojto	116:c0f6e94411f5	1242	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	116:c0f6e94411f5	1243	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	116:c0f6e94411f5	1244	/**
Kojto	116:c0f6e94411f5	1245	* @}
Kojto	116:c0f6e94411f5	1246	*/
Kojto	116:c0f6e94411f5	1247
Kojto	116:c0f6e94411f5	1248	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
Kojto	116:c0f6e94411f5	1249	* @{
Kojto	116:c0f6e94411f5	1250	*/
Kojto	116:c0f6e94411f5	1251	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	116:c0f6e94411f5	1252	void HAL_RCC_EnableCSS(void);
Kojto	116:c0f6e94411f5	1253	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	116:c0f6e94411f5	1254	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	116:c0f6e94411f5	1255	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	116:c0f6e94411f5	1256	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	116:c0f6e94411f5	1257	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	116:c0f6e94411f5	1258	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	116:c0f6e94411f5	1259	/* CSS NMI IRQ handler */
Kojto	116:c0f6e94411f5	1260	void HAL_RCC_NMI_IRQHandler(void);
Kojto	116:c0f6e94411f5	1261
Kojto	116:c0f6e94411f5	1262	/* User Callbacks in non blocking mode (IT mode) */
Kojto	116:c0f6e94411f5	1263	void HAL_RCC_CSSCallback(void);
Kojto	116:c0f6e94411f5	1264	/**
Kojto	116:c0f6e94411f5	1265	* @}
Kojto	116:c0f6e94411f5	1266	*/
Kojto	116:c0f6e94411f5	1267
Kojto	116:c0f6e94411f5	1268	/**
Kojto	116:c0f6e94411f5	1269	* @}
Kojto	116:c0f6e94411f5	1270	*/
Kojto	116:c0f6e94411f5	1271
Kojto	116:c0f6e94411f5	1272	/**
Kojto	116:c0f6e94411f5	1273	* @}
Kojto	116:c0f6e94411f5	1274	*/
Kojto	116:c0f6e94411f5	1275
Kojto	116:c0f6e94411f5	1276	/**
Kojto	116:c0f6e94411f5	1277	* @}
Kojto	116:c0f6e94411f5	1278	*/
Kojto	116:c0f6e94411f5	1279
Kojto	116:c0f6e94411f5	1280	#ifdef __cplusplus
Kojto	116:c0f6e94411f5	1281	}
Kojto	116:c0f6e94411f5	1282	#endif
Kojto	116:c0f6e94411f5	1283
Kojto	116:c0f6e94411f5	1284	#endif /* __STM32l0xx_HAL_RCC_H */
Kojto	116:c0f6e94411f5	1285
Kojto	116:c0f6e94411f5	1286	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	116:c0f6e94411f5	1287

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_L073RZ/stm32l0xx_hal_rcc.h@120:2eb10e18b8d7, 2016-04-13 (annotated)

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