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TARGET_ELMO_F411RE/stm32f4xx_hal_dma.h@120:2eb10e18b8d7, 2016-04-13 (annotated)

Committer:
elijahorr
Date:
Wed Apr 13 12:29:27 2016 +0000
Revision:
120:2eb10e18b8d7
Parent:
110:165afa46840b 
V1.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**
Kojto 108:34e6b704fe68 2 ******************************************************************************
Kojto 108:34e6b704fe68 3 * @file stm32f4xx_hal_dma.h
Kojto 108:34e6b704fe68 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 108:34e6b704fe68 7 * @brief Header file of DMA HAL module.
Kojto 108:34e6b704fe68 8 ******************************************************************************
Kojto 108:34e6b704fe68 9 * @attention
Kojto 108:34e6b704fe68 10 *
Kojto 108:34e6b704fe68 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 108:34e6b704fe68 12 *
Kojto 108:34e6b704fe68 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 108:34e6b704fe68 14 * are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 108:34e6b704fe68 16 * this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 108:34e6b704fe68 18 * this list of conditions and the following disclaimer in the documentation
Kojto 108:34e6b704fe68 19 * and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 108:34e6b704fe68 21 * may be used to endorse or promote products derived from this software
Kojto 108:34e6b704fe68 22 * without specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 108:34e6b704fe68 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 108:34e6b704fe68 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 108:34e6b704fe68 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 108:34e6b704fe68 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 108:34e6b704fe68 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 108:34e6b704fe68 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 108:34e6b704fe68 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 34 *
Kojto 108:34e6b704fe68 35 ******************************************************************************
Kojto 108:34e6b704fe68 36 */
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 108:34e6b704fe68 39 #ifndef __STM32F4xx_HAL_DMA_H
Kojto 108:34e6b704fe68 40 #define __STM32F4xx_HAL_DMA_H
Kojto 108:34e6b704fe68 41
Kojto 108:34e6b704fe68 42 #ifdef __cplusplus
Kojto 108:34e6b704fe68 43 extern "C" {
Kojto 108:34e6b704fe68 44 #endif
Kojto 108:34e6b704fe68 45
Kojto 108:34e6b704fe68 46 /* Includes ------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 47 #include "stm32f4xx_hal_def.h"
Kojto 108:34e6b704fe68 48
Kojto 108:34e6b704fe68 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 108:34e6b704fe68 50 * @{
Kojto 108:34e6b704fe68 51 */
Kojto 108:34e6b704fe68 52
Kojto 108:34e6b704fe68 53 /** @addtogroup DMA
Kojto 108:34e6b704fe68 54 * @{
Kojto 108:34e6b704fe68 55 */
Kojto 108:34e6b704fe68 56
Kojto 108:34e6b704fe68 57 /* Exported types ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 58
Kojto 108:34e6b704fe68 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 108:34e6b704fe68 60 * @brief DMA Exported Types
Kojto 108:34e6b704fe68 61 * @{
Kojto 108:34e6b704fe68 62 */
Kojto 108:34e6b704fe68 63
Kojto 108:34e6b704fe68 64 /**
Kojto 108:34e6b704fe68 65 * @brief DMA Configuration Structure definition
Kojto 108:34e6b704fe68 66 */
Kojto 108:34e6b704fe68 67 typedef struct
Kojto 108:34e6b704fe68 68 {
Kojto 108:34e6b704fe68 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
Kojto 108:34e6b704fe68 70 This parameter can be a value of @ref DMA_Channel_selection */
Kojto 108:34e6b704fe68 71
Kojto 108:34e6b704fe68 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 108:34e6b704fe68 73 from memory to memory or from peripheral to memory.
Kojto 108:34e6b704fe68 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 108:34e6b704fe68 75
Kojto 108:34e6b704fe68 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 108:34e6b704fe68 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 108:34e6b704fe68 78
Kojto 108:34e6b704fe68 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 108:34e6b704fe68 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 108:34e6b704fe68 81
Kojto 108:34e6b704fe68 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 108:34e6b704fe68 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 108:34e6b704fe68 84
Kojto 108:34e6b704fe68 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 108:34e6b704fe68 86 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 108:34e6b704fe68 87
Kojto 108:34e6b704fe68 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
Kojto 108:34e6b704fe68 89 This parameter can be a value of @ref DMA_mode
Kojto 108:34e6b704fe68 90 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 108:34e6b704fe68 91 data transfer is configured on the selected Stream */
Kojto 108:34e6b704fe68 92
Kojto 108:34e6b704fe68 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
Kojto 108:34e6b704fe68 94 This parameter can be a value of @ref DMA_Priority_level */
Kojto 108:34e6b704fe68 95
Kojto 108:34e6b704fe68 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
Kojto 108:34e6b704fe68 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
Kojto 108:34e6b704fe68 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
Kojto 108:34e6b704fe68 99 memory-to-memory data transfer is configured on the selected stream */
Kojto 108:34e6b704fe68 100
Kojto 108:34e6b704fe68 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
Kojto 108:34e6b704fe68 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
Kojto 108:34e6b704fe68 103
Kojto 108:34e6b704fe68 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 108:34e6b704fe68 105 It specifies the amount of data to be transferred in a single non interruptible
Kojto 108:34e6b704fe68 106 transaction.
Kojto 108:34e6b704fe68 107 This parameter can be a value of @ref DMA_Memory_burst
Kojto 108:34e6b704fe68 108 @note The burst mode is possible only if the address Increment mode is enabled. */
Kojto 108:34e6b704fe68 109
Kojto 108:34e6b704fe68 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
Kojto 108:34e6b704fe68 111 It specifies the amount of data to be transferred in a single non interruptable
Kojto 108:34e6b704fe68 112 transaction.
Kojto 108:34e6b704fe68 113 This parameter can be a value of @ref DMA_Peripheral_burst
Kojto 108:34e6b704fe68 114 @note The burst mode is possible only if the address Increment mode is enabled. */
Kojto 108:34e6b704fe68 115 }DMA_InitTypeDef;
Kojto 108:34e6b704fe68 116
Kojto 108:34e6b704fe68 117
Kojto 108:34e6b704fe68 118 /**
Kojto 108:34e6b704fe68 119 * @brief HAL DMA State structures definition
Kojto 108:34e6b704fe68 120 */
Kojto 108:34e6b704fe68 121 typedef enum
Kojto 108:34e6b704fe68 122 {
Kojto 108:34e6b704fe68 123 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
Kojto 108:34e6b704fe68 124 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
Kojto 108:34e6b704fe68 125 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
Kojto 108:34e6b704fe68 126 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
Kojto 108:34e6b704fe68 127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
Kojto 108:34e6b704fe68 128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
Kojto 108:34e6b704fe68 129 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
Kojto 108:34e6b704fe68 130 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
Kojto 108:34e6b704fe68 131 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
Kojto 108:34e6b704fe68 132 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
Kojto 108:34e6b704fe68 133 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
Kojto 108:34e6b704fe68 134 }HAL_DMA_StateTypeDef;
Kojto 108:34e6b704fe68 135
Kojto 108:34e6b704fe68 136 /**
Kojto 108:34e6b704fe68 137 * @brief HAL DMA Error Code structure definition
Kojto 108:34e6b704fe68 138 */
Kojto 108:34e6b704fe68 139 typedef enum
Kojto 108:34e6b704fe68 140 {
Kojto 108:34e6b704fe68 141 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
Kojto 108:34e6b704fe68 142 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
Kojto 108:34e6b704fe68 143 }HAL_DMA_LevelCompleteTypeDef;
Kojto 108:34e6b704fe68 144
Kojto 108:34e6b704fe68 145 /**
Kojto 108:34e6b704fe68 146 * @brief DMA handle Structure definition
Kojto 108:34e6b704fe68 147 */
Kojto 108:34e6b704fe68 148 typedef struct __DMA_HandleTypeDef
Kojto 108:34e6b704fe68 149 {
Kojto 108:34e6b704fe68 150 DMA_Stream_TypeDef *Instance; /*!< Register base address */
Kojto 108:34e6b704fe68 151
Kojto 108:34e6b704fe68 152 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 108:34e6b704fe68 153
Kojto 108:34e6b704fe68 154 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 108:34e6b704fe68 155
Kojto 108:34e6b704fe68 156 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 108:34e6b704fe68 157
Kojto 108:34e6b704fe68 158 void *Parent; /*!< Parent object state */
Kojto 108:34e6b704fe68 159
Kojto 108:34e6b704fe68 160 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 108:34e6b704fe68 161
Kojto 108:34e6b704fe68 162 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 108:34e6b704fe68 163
Kojto 108:34e6b704fe68 164 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
Kojto 108:34e6b704fe68 165
Kojto 108:34e6b704fe68 166 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 108:34e6b704fe68 167
Kojto 110:165afa46840b 168 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 110:165afa46840b 169
Kojto 110:165afa46840b 170 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
Kojto 110:165afa46840b 171
Kojto 110:165afa46840b 172 uint32_t StreamIndex; /*!< DMA Stream Index */
Kojto 108:34e6b704fe68 173 }DMA_HandleTypeDef;
Kojto 108:34e6b704fe68 174
Kojto 108:34e6b704fe68 175 /**
Kojto 108:34e6b704fe68 176 * @}
Kojto 108:34e6b704fe68 177 */
Kojto 108:34e6b704fe68 178
Kojto 108:34e6b704fe68 179 /* Exported constants --------------------------------------------------------*/
Kojto 108:34e6b704fe68 180
Kojto 108:34e6b704fe68 181 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 108:34e6b704fe68 182 * @brief DMA Exported constants
Kojto 108:34e6b704fe68 183 * @{
Kojto 108:34e6b704fe68 184 */
Kojto 108:34e6b704fe68 185
Kojto 108:34e6b704fe68 186 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 108:34e6b704fe68 187 * @brief DMA Error Code
Kojto 108:34e6b704fe68 188 * @{
Kojto 108:34e6b704fe68 189 */
Kojto 108:34e6b704fe68 190 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 108:34e6b704fe68 191 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
Kojto 108:34e6b704fe68 192 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
Kojto 108:34e6b704fe68 193 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
Kojto 108:34e6b704fe68 194 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
Kojto 108:34e6b704fe68 195 /**
Kojto 108:34e6b704fe68 196 * @}
Kojto 108:34e6b704fe68 197 */
Kojto 108:34e6b704fe68 198
Kojto 108:34e6b704fe68 199 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 108:34e6b704fe68 200 * @brief DMA channel selection
Kojto 108:34e6b704fe68 201 * @{
Kojto 108:34e6b704fe68 202 */
Kojto 108:34e6b704fe68 203 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
Kojto 108:34e6b704fe68 204 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
Kojto 108:34e6b704fe68 205 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
Kojto 108:34e6b704fe68 206 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
Kojto 108:34e6b704fe68 207 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
Kojto 108:34e6b704fe68 208 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
Kojto 108:34e6b704fe68 209 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
Kojto 108:34e6b704fe68 210 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
Kojto 108:34e6b704fe68 211 /**
Kojto 108:34e6b704fe68 212 * @}
Kojto 108:34e6b704fe68 213 */
Kojto 108:34e6b704fe68 214
Kojto 108:34e6b704fe68 215 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 108:34e6b704fe68 216 * @brief DMA data transfer direction
Kojto 108:34e6b704fe68 217 * @{
Kojto 108:34e6b704fe68 218 */
Kojto 108:34e6b704fe68 219 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
Kojto 108:34e6b704fe68 220 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
Kojto 108:34e6b704fe68 221 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
Kojto 108:34e6b704fe68 222 /**
Kojto 108:34e6b704fe68 223 * @}
Kojto 108:34e6b704fe68 224 */
Kojto 108:34e6b704fe68 225
Kojto 108:34e6b704fe68 226 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 108:34e6b704fe68 227 * @brief DMA peripheral incremented mode
Kojto 108:34e6b704fe68 228 * @{
Kojto 108:34e6b704fe68 229 */
Kojto 108:34e6b704fe68 230 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
Kojto 108:34e6b704fe68 231 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
Kojto 108:34e6b704fe68 232 /**
Kojto 108:34e6b704fe68 233 * @}
Kojto 108:34e6b704fe68 234 */
Kojto 108:34e6b704fe68 235
Kojto 108:34e6b704fe68 236 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 108:34e6b704fe68 237 * @brief DMA memory incremented mode
Kojto 108:34e6b704fe68 238 * @{
Kojto 108:34e6b704fe68 239 */
Kojto 108:34e6b704fe68 240 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
Kojto 108:34e6b704fe68 241 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
Kojto 108:34e6b704fe68 242 /**
Kojto 108:34e6b704fe68 243 * @}
Kojto 108:34e6b704fe68 244 */
Kojto 108:34e6b704fe68 245
Kojto 108:34e6b704fe68 246 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 108:34e6b704fe68 247 * @brief DMA peripheral data size
Kojto 108:34e6b704fe68 248 * @{
Kojto 108:34e6b704fe68 249 */
Kojto 108:34e6b704fe68 250 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
Kojto 108:34e6b704fe68 251 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
Kojto 108:34e6b704fe68 252 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
Kojto 108:34e6b704fe68 253 /**
Kojto 108:34e6b704fe68 254 * @}
Kojto 108:34e6b704fe68 255 */
Kojto 108:34e6b704fe68 256
Kojto 108:34e6b704fe68 257 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 108:34e6b704fe68 258 * @brief DMA memory data size
Kojto 108:34e6b704fe68 259 * @{
Kojto 108:34e6b704fe68 260 */
Kojto 108:34e6b704fe68 261 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
Kojto 108:34e6b704fe68 262 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
Kojto 108:34e6b704fe68 263 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
Kojto 108:34e6b704fe68 264 /**
Kojto 108:34e6b704fe68 265 * @}
Kojto 108:34e6b704fe68 266 */
Kojto 108:34e6b704fe68 267
Kojto 108:34e6b704fe68 268 /** @defgroup DMA_mode DMA mode
Kojto 108:34e6b704fe68 269 * @brief DMA mode
Kojto 108:34e6b704fe68 270 * @{
Kojto 108:34e6b704fe68 271 */
Kojto 108:34e6b704fe68 272 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
Kojto 108:34e6b704fe68 273 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
Kojto 108:34e6b704fe68 274 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
Kojto 108:34e6b704fe68 275 /**
Kojto 108:34e6b704fe68 276 * @}
Kojto 108:34e6b704fe68 277 */
Kojto 108:34e6b704fe68 278
Kojto 108:34e6b704fe68 279 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 108:34e6b704fe68 280 * @brief DMA priority levels
Kojto 108:34e6b704fe68 281 * @{
Kojto 108:34e6b704fe68 282 */
Kojto 108:34e6b704fe68 283 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
Kojto 108:34e6b704fe68 284 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
Kojto 108:34e6b704fe68 285 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
Kojto 108:34e6b704fe68 286 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
Kojto 108:34e6b704fe68 287 /**
Kojto 108:34e6b704fe68 288 * @}
Kojto 108:34e6b704fe68 289 */
Kojto 108:34e6b704fe68 290
Kojto 108:34e6b704fe68 291 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 108:34e6b704fe68 292 * @brief DMA FIFO direct mode
Kojto 108:34e6b704fe68 293 * @{
Kojto 108:34e6b704fe68 294 */
Kojto 108:34e6b704fe68 295 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
Kojto 108:34e6b704fe68 296 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
Kojto 108:34e6b704fe68 297 /**
Kojto 108:34e6b704fe68 298 * @}
Kojto 108:34e6b704fe68 299 */
Kojto 108:34e6b704fe68 300
Kojto 108:34e6b704fe68 301 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 108:34e6b704fe68 302 * @brief DMA FIFO level
Kojto 108:34e6b704fe68 303 * @{
Kojto 108:34e6b704fe68 304 */
Kojto 108:34e6b704fe68 305 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
Kojto 108:34e6b704fe68 306 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
Kojto 108:34e6b704fe68 307 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
Kojto 108:34e6b704fe68 308 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
Kojto 108:34e6b704fe68 309 /**
Kojto 108:34e6b704fe68 310 * @}
Kojto 108:34e6b704fe68 311 */
Kojto 108:34e6b704fe68 312
Kojto 108:34e6b704fe68 313 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 108:34e6b704fe68 314 * @brief DMA memory burst
Kojto 108:34e6b704fe68 315 * @{
Kojto 108:34e6b704fe68 316 */
Kojto 108:34e6b704fe68 317 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 318 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
Kojto 108:34e6b704fe68 319 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
Kojto 108:34e6b704fe68 320 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
Kojto 108:34e6b704fe68 321 /**
Kojto 108:34e6b704fe68 322 * @}
Kojto 108:34e6b704fe68 323 */
Kojto 108:34e6b704fe68 324
Kojto 108:34e6b704fe68 325 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 108:34e6b704fe68 326 * @brief DMA peripheral burst
Kojto 108:34e6b704fe68 327 * @{
Kojto 108:34e6b704fe68 328 */
Kojto 108:34e6b704fe68 329 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 330 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
Kojto 108:34e6b704fe68 331 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
Kojto 108:34e6b704fe68 332 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
Kojto 108:34e6b704fe68 333 /**
Kojto 108:34e6b704fe68 334 * @}
Kojto 108:34e6b704fe68 335 */
Kojto 108:34e6b704fe68 336
Kojto 108:34e6b704fe68 337 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 108:34e6b704fe68 338 * @brief DMA interrupts definition
Kojto 108:34e6b704fe68 339 * @{
Kojto 108:34e6b704fe68 340 */
Kojto 108:34e6b704fe68 341 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
Kojto 108:34e6b704fe68 342 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
Kojto 108:34e6b704fe68 343 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
Kojto 108:34e6b704fe68 344 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
Kojto 108:34e6b704fe68 345 #define DMA_IT_FE ((uint32_t)0x00000080)
Kojto 108:34e6b704fe68 346 /**
Kojto 108:34e6b704fe68 347 * @}
Kojto 108:34e6b704fe68 348 */
Kojto 108:34e6b704fe68 349
Kojto 108:34e6b704fe68 350 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 108:34e6b704fe68 351 * @brief DMA flag definitions
Kojto 108:34e6b704fe68 352 * @{
Kojto 108:34e6b704fe68 353 */
Kojto 108:34e6b704fe68 354 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
Kojto 108:34e6b704fe68 355 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
Kojto 108:34e6b704fe68 356 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
Kojto 108:34e6b704fe68 357 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
Kojto 108:34e6b704fe68 358 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
Kojto 108:34e6b704fe68 359 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
Kojto 108:34e6b704fe68 360 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
Kojto 108:34e6b704fe68 361 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
Kojto 108:34e6b704fe68 362 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
Kojto 108:34e6b704fe68 363 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
Kojto 108:34e6b704fe68 364 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
Kojto 108:34e6b704fe68 365 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
Kojto 108:34e6b704fe68 366 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
Kojto 108:34e6b704fe68 367 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
Kojto 108:34e6b704fe68 368 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
Kojto 108:34e6b704fe68 369 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
Kojto 108:34e6b704fe68 370 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
Kojto 108:34e6b704fe68 371 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
Kojto 108:34e6b704fe68 372 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
Kojto 108:34e6b704fe68 373 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
Kojto 108:34e6b704fe68 374 /**
Kojto 108:34e6b704fe68 375 * @}
Kojto 108:34e6b704fe68 376 */
Kojto 108:34e6b704fe68 377
Kojto 108:34e6b704fe68 378 /**
Kojto 108:34e6b704fe68 379 * @}
Kojto 108:34e6b704fe68 380 */
Kojto 108:34e6b704fe68 381
Kojto 108:34e6b704fe68 382 /* Exported macro ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 383
Kojto 108:34e6b704fe68 384 /** @brief Reset DMA handle state
Kojto 108:34e6b704fe68 385 * @param __HANDLE__: specifies the DMA handle.
Kojto 108:34e6b704fe68 386 * @retval None
Kojto 108:34e6b704fe68 387 */
Kojto 108:34e6b704fe68 388 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 108:34e6b704fe68 389
Kojto 108:34e6b704fe68 390 /**
Kojto 108:34e6b704fe68 391 * @brief Return the current DMA Stream FIFO filled level.
Kojto 108:34e6b704fe68 392 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 393 * @retval The FIFO filling state.
Kojto 108:34e6b704fe68 394 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
Kojto 108:34e6b704fe68 395 * and not empty.
Kojto 108:34e6b704fe68 396 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
Kojto 108:34e6b704fe68 397 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
Kojto 108:34e6b704fe68 398 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
Kojto 108:34e6b704fe68 399 * - DMA_FIFOStatus_Empty: when FIFO is empty
Kojto 108:34e6b704fe68 400 * - DMA_FIFOStatus_Full: when FIFO is full
Kojto 108:34e6b704fe68 401 */
Kojto 108:34e6b704fe68 402 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Kojto 108:34e6b704fe68 403
Kojto 108:34e6b704fe68 404 /**
Kojto 108:34e6b704fe68 405 * @brief Enable the specified DMA Stream.
Kojto 108:34e6b704fe68 406 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 407 * @retval None
Kojto 108:34e6b704fe68 408 */
Kojto 108:34e6b704fe68 409 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Kojto 108:34e6b704fe68 410
Kojto 108:34e6b704fe68 411 /**
Kojto 108:34e6b704fe68 412 * @brief Disable the specified DMA Stream.
Kojto 108:34e6b704fe68 413 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 414 * @retval None
Kojto 108:34e6b704fe68 415 */
Kojto 108:34e6b704fe68 416 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Kojto 108:34e6b704fe68 417
Kojto 108:34e6b704fe68 418 /* Interrupt & Flag management */
Kojto 108:34e6b704fe68 419
Kojto 108:34e6b704fe68 420 /**
Kojto 108:34e6b704fe68 421 * @brief Return the current DMA Stream transfer complete flag.
Kojto 108:34e6b704fe68 422 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 423 * @retval The specified transfer complete flag index.
Kojto 108:34e6b704fe68 424 */
Kojto 108:34e6b704fe68 425 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 108:34e6b704fe68 426 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto 108:34e6b704fe68 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto 108:34e6b704fe68 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto 108:34e6b704fe68 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto 108:34e6b704fe68 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto 108:34e6b704fe68 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto 108:34e6b704fe68 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto 108:34e6b704fe68 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto 108:34e6b704fe68 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto 108:34e6b704fe68 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto 108:34e6b704fe68 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto 108:34e6b704fe68 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto 108:34e6b704fe68 438 DMA_FLAG_TCIF3_7)
Kojto 108:34e6b704fe68 439
Kojto 108:34e6b704fe68 440 /**
Kojto 108:34e6b704fe68 441 * @brief Return the current DMA Stream half transfer complete flag.
Kojto 108:34e6b704fe68 442 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 443 * @retval The specified half transfer complete flag index.
Kojto 108:34e6b704fe68 444 */
Kojto 108:34e6b704fe68 445 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 108:34e6b704fe68 446 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto 108:34e6b704fe68 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto 108:34e6b704fe68 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto 108:34e6b704fe68 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto 108:34e6b704fe68 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto 108:34e6b704fe68 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto 108:34e6b704fe68 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto 108:34e6b704fe68 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto 108:34e6b704fe68 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto 108:34e6b704fe68 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto 108:34e6b704fe68 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto 108:34e6b704fe68 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto 108:34e6b704fe68 458 DMA_FLAG_HTIF3_7)
Kojto 108:34e6b704fe68 459
Kojto 108:34e6b704fe68 460 /**
Kojto 108:34e6b704fe68 461 * @brief Return the current DMA Stream transfer error flag.
Kojto 108:34e6b704fe68 462 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 463 * @retval The specified transfer error flag index.
Kojto 108:34e6b704fe68 464 */
Kojto 108:34e6b704fe68 465 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 108:34e6b704fe68 466 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto 108:34e6b704fe68 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto 108:34e6b704fe68 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto 108:34e6b704fe68 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto 108:34e6b704fe68 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto 108:34e6b704fe68 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto 108:34e6b704fe68 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto 108:34e6b704fe68 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto 108:34e6b704fe68 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto 108:34e6b704fe68 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto 108:34e6b704fe68 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto 108:34e6b704fe68 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto 108:34e6b704fe68 478 DMA_FLAG_TEIF3_7)
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 /**
Kojto 108:34e6b704fe68 481 * @brief Return the current DMA Stream FIFO error flag.
Kojto 108:34e6b704fe68 482 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 483 * @retval The specified FIFO error flag index.
Kojto 108:34e6b704fe68 484 */
Kojto 108:34e6b704fe68 485 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
Kojto 108:34e6b704fe68 486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto 108:34e6b704fe68 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto 108:34e6b704fe68 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto 108:34e6b704fe68 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto 108:34e6b704fe68 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto 108:34e6b704fe68 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto 108:34e6b704fe68 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto 108:34e6b704fe68 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto 108:34e6b704fe68 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto 108:34e6b704fe68 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto 108:34e6b704fe68 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto 108:34e6b704fe68 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto 108:34e6b704fe68 498 DMA_FLAG_FEIF3_7)
Kojto 108:34e6b704fe68 499
Kojto 108:34e6b704fe68 500 /**
Kojto 108:34e6b704fe68 501 * @brief Return the current DMA Stream direct mode error flag.
Kojto 108:34e6b704fe68 502 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 503 * @retval The specified direct mode error flag index.
Kojto 108:34e6b704fe68 504 */
Kojto 108:34e6b704fe68 505 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
Kojto 108:34e6b704fe68 506 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto 108:34e6b704fe68 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto 108:34e6b704fe68 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto 108:34e6b704fe68 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto 108:34e6b704fe68 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto 108:34e6b704fe68 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto 108:34e6b704fe68 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto 108:34e6b704fe68 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto 108:34e6b704fe68 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto 108:34e6b704fe68 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto 108:34e6b704fe68 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto 108:34e6b704fe68 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto 108:34e6b704fe68 518 DMA_FLAG_DMEIF3_7)
Kojto 108:34e6b704fe68 519
Kojto 108:34e6b704fe68 520 /**
Kojto 108:34e6b704fe68 521 * @brief Get the DMA Stream pending flags.
Kojto 108:34e6b704fe68 522 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 523 * @param __FLAG__: Get the specified flag.
Kojto 108:34e6b704fe68 524 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 525 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto 108:34e6b704fe68 526 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto 108:34e6b704fe68 527 * @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto 108:34e6b704fe68 528 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto 108:34e6b704fe68 529 * @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto 108:34e6b704fe68 530 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto 108:34e6b704fe68 531 * @retval The state of FLAG (SET or RESET).
Kojto 108:34e6b704fe68 532 */
Kojto 108:34e6b704fe68 533 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
Kojto 108:34e6b704fe68 534 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
Kojto 108:34e6b704fe68 535 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
Kojto 108:34e6b704fe68 536 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
Kojto 108:34e6b704fe68 537
Kojto 108:34e6b704fe68 538 /**
Kojto 108:34e6b704fe68 539 * @brief Clear the DMA Stream pending flags.
Kojto 108:34e6b704fe68 540 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 541 * @param __FLAG__: specifies the flag to clear.
Kojto 108:34e6b704fe68 542 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 543 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto 108:34e6b704fe68 544 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto 108:34e6b704fe68 545 * @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto 108:34e6b704fe68 546 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto 108:34e6b704fe68 547 * @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto 108:34e6b704fe68 548 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto 108:34e6b704fe68 549 * @retval None
Kojto 108:34e6b704fe68 550 */
Kojto 108:34e6b704fe68 551 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 108:34e6b704fe68 552 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
Kojto 108:34e6b704fe68 553 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
Kojto 108:34e6b704fe68 554 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
Kojto 108:34e6b704fe68 555
Kojto 108:34e6b704fe68 556 /**
Kojto 108:34e6b704fe68 557 * @brief Enable the specified DMA Stream interrupts.
Kojto 108:34e6b704fe68 558 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 559 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 108:34e6b704fe68 560 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 561 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 108:34e6b704fe68 562 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 108:34e6b704fe68 563 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 108:34e6b704fe68 564 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 108:34e6b704fe68 565 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 108:34e6b704fe68 566 * @retval None
Kojto 108:34e6b704fe68 567 */
Kojto 108:34e6b704fe68 568 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 108:34e6b704fe68 569 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
Kojto 108:34e6b704fe68 570
Kojto 108:34e6b704fe68 571 /**
Kojto 108:34e6b704fe68 572 * @brief Disable the specified DMA Stream interrupts.
Kojto 108:34e6b704fe68 573 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 574 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 108:34e6b704fe68 575 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 576 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 108:34e6b704fe68 577 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 108:34e6b704fe68 578 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 108:34e6b704fe68 579 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 108:34e6b704fe68 580 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 108:34e6b704fe68 581 * @retval None
Kojto 108:34e6b704fe68 582 */
Kojto 108:34e6b704fe68 583 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 108:34e6b704fe68 584 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
Kojto 108:34e6b704fe68 585
Kojto 108:34e6b704fe68 586 /**
Kojto 108:34e6b704fe68 587 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
Kojto 108:34e6b704fe68 588 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 589 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 108:34e6b704fe68 590 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 591 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 108:34e6b704fe68 592 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 108:34e6b704fe68 593 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 108:34e6b704fe68 594 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 108:34e6b704fe68 595 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 108:34e6b704fe68 596 * @retval The state of DMA_IT.
Kojto 108:34e6b704fe68 597 */
Kojto 108:34e6b704fe68 598 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 108:34e6b704fe68 599 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
Kojto 108:34e6b704fe68 600 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
Kojto 108:34e6b704fe68 601
Kojto 108:34e6b704fe68 602 /**
Kojto 108:34e6b704fe68 603 * @brief Writes the number of data units to be transferred on the DMA Stream.
Kojto 108:34e6b704fe68 604 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 605 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
Kojto 108:34e6b704fe68 606 * Number of data items depends only on the Peripheral data format.
Kojto 108:34e6b704fe68 607 *
Kojto 108:34e6b704fe68 608 * @note If Peripheral data format is Bytes: number of data units is equal
Kojto 108:34e6b704fe68 609 * to total number of bytes to be transferred.
Kojto 108:34e6b704fe68 610 *
Kojto 108:34e6b704fe68 611 * @note If Peripheral data format is Half-Word: number of data units is
Kojto 108:34e6b704fe68 612 * equal to total number of bytes to be transferred / 2.
Kojto 108:34e6b704fe68 613 *
Kojto 108:34e6b704fe68 614 * @note If Peripheral data format is Word: number of data units is equal
Kojto 108:34e6b704fe68 615 * to total number of bytes to be transferred / 4.
Kojto 108:34e6b704fe68 616 *
Kojto 108:34e6b704fe68 617 * @retval The number of remaining data units in the current DMAy Streamx transfer.
Kojto 108:34e6b704fe68 618 */
Kojto 108:34e6b704fe68 619 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Kojto 108:34e6b704fe68 620
Kojto 108:34e6b704fe68 621 /**
Kojto 108:34e6b704fe68 622 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
Kojto 108:34e6b704fe68 623 * @param __HANDLE__: DMA handle
Kojto 108:34e6b704fe68 624 *
Kojto 108:34e6b704fe68 625 * @retval The number of remaining data units in the current DMA Stream transfer.
Kojto 108:34e6b704fe68 626 */
Kojto 108:34e6b704fe68 627 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Kojto 108:34e6b704fe68 628
Kojto 108:34e6b704fe68 629
Kojto 108:34e6b704fe68 630 /* Include DMA HAL Extension module */
Kojto 108:34e6b704fe68 631 #include "stm32f4xx_hal_dma_ex.h"
Kojto 108:34e6b704fe68 632
Kojto 108:34e6b704fe68 633 /* Exported functions --------------------------------------------------------*/
Kojto 108:34e6b704fe68 634
Kojto 108:34e6b704fe68 635 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 108:34e6b704fe68 636 * @brief DMA Exported functions
Kojto 108:34e6b704fe68 637 * @{
Kojto 108:34e6b704fe68 638 */
Kojto 108:34e6b704fe68 639
Kojto 108:34e6b704fe68 640 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 108:34e6b704fe68 641 * @brief Initialization and de-initialization functions
Kojto 108:34e6b704fe68 642 * @{
Kojto 108:34e6b704fe68 643 */
Kojto 108:34e6b704fe68 644 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 108:34e6b704fe68 645 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 108:34e6b704fe68 646 /**
Kojto 108:34e6b704fe68 647 * @}
Kojto 108:34e6b704fe68 648 */
Kojto 108:34e6b704fe68 649
Kojto 108:34e6b704fe68 650 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 108:34e6b704fe68 651 * @brief I/O operation functions
Kojto 108:34e6b704fe68 652 * @{
Kojto 108:34e6b704fe68 653 */
Kojto 108:34e6b704fe68 654 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 108:34e6b704fe68 655 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 108:34e6b704fe68 656 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 108:34e6b704fe68 657 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
Kojto 108:34e6b704fe68 658 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 108:34e6b704fe68 659 /**
Kojto 108:34e6b704fe68 660 * @}
Kojto 108:34e6b704fe68 661 */
Kojto 108:34e6b704fe68 662
Kojto 108:34e6b704fe68 663 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 108:34e6b704fe68 664 * @brief Peripheral State functions
Kojto 108:34e6b704fe68 665 * @{
Kojto 108:34e6b704fe68 666 */
Kojto 108:34e6b704fe68 667 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 108:34e6b704fe68 668 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 108:34e6b704fe68 669 /**
Kojto 108:34e6b704fe68 670 * @}
Kojto 108:34e6b704fe68 671 */
Kojto 108:34e6b704fe68 672 /**
Kojto 108:34e6b704fe68 673 * @}
Kojto 108:34e6b704fe68 674 */
Kojto 108:34e6b704fe68 675 /* Private Constants -------------------------------------------------------------*/
Kojto 108:34e6b704fe68 676 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 108:34e6b704fe68 677 * @brief DMA private defines and constants
Kojto 108:34e6b704fe68 678 * @{
Kojto 108:34e6b704fe68 679 */
Kojto 108:34e6b704fe68 680 /**
Kojto 108:34e6b704fe68 681 * @}
Kojto 108:34e6b704fe68 682 */
Kojto 108:34e6b704fe68 683
Kojto 108:34e6b704fe68 684 /* Private macros ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 685 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 108:34e6b704fe68 686 * @brief DMA private macros
Kojto 108:34e6b704fe68 687 * @{
Kojto 108:34e6b704fe68 688 */
Kojto 108:34e6b704fe68 689 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 108:34e6b704fe68 690 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 108:34e6b704fe68 691 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 108:34e6b704fe68 692 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 108:34e6b704fe68 693 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 108:34e6b704fe68 694 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 108:34e6b704fe68 695 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 108:34e6b704fe68 696 ((CHANNEL) == DMA_CHANNEL_7))
Kojto 108:34e6b704fe68 697
Kojto 108:34e6b704fe68 698 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 108:34e6b704fe68 699 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 108:34e6b704fe68 700 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 108:34e6b704fe68 701
Kojto 108:34e6b704fe68 702 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 108:34e6b704fe68 703
Kojto 108:34e6b704fe68 704 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 108:34e6b704fe68 705 ((STATE) == DMA_PINC_DISABLE))
Kojto 108:34e6b704fe68 706
Kojto 108:34e6b704fe68 707 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 108:34e6b704fe68 708 ((STATE) == DMA_MINC_DISABLE))
Kojto 108:34e6b704fe68 709
Kojto 108:34e6b704fe68 710 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 108:34e6b704fe68 711 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 108:34e6b704fe68 712 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 108:34e6b704fe68 713
Kojto 108:34e6b704fe68 714 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 108:34e6b704fe68 715 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 108:34e6b704fe68 716 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 108:34e6b704fe68 717
Kojto 108:34e6b704fe68 718 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 108:34e6b704fe68 719 ((MODE) == DMA_CIRCULAR) || \
Kojto 108:34e6b704fe68 720 ((MODE) == DMA_PFCTRL))
Kojto 108:34e6b704fe68 721
Kojto 108:34e6b704fe68 722 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 108:34e6b704fe68 723 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 108:34e6b704fe68 724 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 108:34e6b704fe68 725 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 108:34e6b704fe68 726
Kojto 108:34e6b704fe68 727 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 108:34e6b704fe68 728 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 108:34e6b704fe68 729
Kojto 108:34e6b704fe68 730 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 108:34e6b704fe68 731 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 108:34e6b704fe68 732 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 108:34e6b704fe68 733 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 108:34e6b704fe68 734
Kojto 108:34e6b704fe68 735 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 108:34e6b704fe68 736 ((BURST) == DMA_MBURST_INC4) || \
Kojto 108:34e6b704fe68 737 ((BURST) == DMA_MBURST_INC8) || \
Kojto 108:34e6b704fe68 738 ((BURST) == DMA_MBURST_INC16))
Kojto 108:34e6b704fe68 739
Kojto 108:34e6b704fe68 740 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 108:34e6b704fe68 741 ((BURST) == DMA_PBURST_INC4) || \
Kojto 108:34e6b704fe68 742 ((BURST) == DMA_PBURST_INC8) || \
Kojto 108:34e6b704fe68 743 ((BURST) == DMA_PBURST_INC16))
Kojto 108:34e6b704fe68 744 /**
Kojto 108:34e6b704fe68 745 * @}
Kojto 108:34e6b704fe68 746 */
Kojto 108:34e6b704fe68 747
Kojto 108:34e6b704fe68 748 /* Private functions ---------------------------------------------------------*/
Kojto 108:34e6b704fe68 749 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 108:34e6b704fe68 750 * @brief DMA private functions
Kojto 108:34e6b704fe68 751 * @{
Kojto 108:34e6b704fe68 752 */
Kojto 108:34e6b704fe68 753 /**
Kojto 108:34e6b704fe68 754 * @}
Kojto 108:34e6b704fe68 755 */
Kojto 108:34e6b704fe68 756
Kojto 108:34e6b704fe68 757 /**
Kojto 108:34e6b704fe68 758 * @}
Kojto 108:34e6b704fe68 759 */
Kojto 108:34e6b704fe68 760
Kojto 108:34e6b704fe68 761 /**
Kojto 108:34e6b704fe68 762 * @}
Kojto 108:34e6b704fe68 763 */
Kojto 108:34e6b704fe68 764
Kojto 108:34e6b704fe68 765 #ifdef __cplusplus
Kojto 108:34e6b704fe68 766 }
Kojto 108:34e6b704fe68 767 #endif
Kojto 108:34e6b704fe68 768
Kojto 108:34e6b704fe68 769 #endif /* __STM32F4xx_HAL_DMA_H */
Kojto 108:34e6b704fe68 770
Kojto 108:34e6b704fe68 771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/