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TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:: Kojto
Date:: Wed Nov 25 13:21:40 2015 +0000
Revision:: 110:165afa46840b
Parent:: 106:ba1f97679dad

Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f4xx_hal_dma.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
bogdanm	86:04dd9b1680ae	7	* @brief Header file of DMA HAL module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F4xx_HAL_DMA_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F4xx_HAL_DMA_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	47	#include "stm32f4xx_hal_def.h"
bogdanm	86:04dd9b1680ae	48
bogdanm	86:04dd9b1680ae	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	86:04dd9b1680ae	50	* @{
bogdanm	86:04dd9b1680ae	51	*/
bogdanm	86:04dd9b1680ae	52
bogdanm	86:04dd9b1680ae	53	/** @addtogroup DMA
bogdanm	86:04dd9b1680ae	54	* @{
bogdanm	86:04dd9b1680ae	55	*/
bogdanm	86:04dd9b1680ae	56
bogdanm	86:04dd9b1680ae	57	/* Exported types ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	58
Kojto	99:dbbf35b96557	59	/** @defgroup DMA_Exported_Types DMA Exported Types
Kojto	99:dbbf35b96557	60	* @brief DMA Exported Types
Kojto	99:dbbf35b96557	61	* @{
Kojto	99:dbbf35b96557	62	*/
Kojto	99:dbbf35b96557	63
bogdanm	86:04dd9b1680ae	64	/**
bogdanm	86:04dd9b1680ae	65	* @brief DMA Configuration Structure definition
bogdanm	86:04dd9b1680ae	66	*/
bogdanm	86:04dd9b1680ae	67	typedef struct
bogdanm	86:04dd9b1680ae	68	{
bogdanm	86:04dd9b1680ae	69	uint32_t Channel; /*!< Specifies the channel used for the specified stream.
bogdanm	86:04dd9b1680ae	70	This parameter can be a value of @ref DMA_Channel_selection */
bogdanm	86:04dd9b1680ae	71
bogdanm	86:04dd9b1680ae	72	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm	86:04dd9b1680ae	73	from memory to memory or from peripheral to memory.
bogdanm	86:04dd9b1680ae	74	This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm	86:04dd9b1680ae	75
bogdanm	86:04dd9b1680ae	76	uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm	86:04dd9b1680ae	77	This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm	86:04dd9b1680ae	78
bogdanm	86:04dd9b1680ae	79	uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm	86:04dd9b1680ae	80	This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm	86:04dd9b1680ae	81
bogdanm	86:04dd9b1680ae	82	uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm	86:04dd9b1680ae	83	This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm	86:04dd9b1680ae	84
bogdanm	86:04dd9b1680ae	85	uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm	86:04dd9b1680ae	86	This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm	86:04dd9b1680ae	87
bogdanm	86:04dd9b1680ae	88	uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
bogdanm	86:04dd9b1680ae	89	This parameter can be a value of @ref DMA_mode
bogdanm	86:04dd9b1680ae	90	@note The circular buffer mode cannot be used if the memory-to-memory
bogdanm	86:04dd9b1680ae	91	data transfer is configured on the selected Stream */
bogdanm	86:04dd9b1680ae	92
bogdanm	86:04dd9b1680ae	93	uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
bogdanm	86:04dd9b1680ae	94	This parameter can be a value of @ref DMA_Priority_level */
bogdanm	86:04dd9b1680ae	95
bogdanm	86:04dd9b1680ae	96	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
bogdanm	86:04dd9b1680ae	97	This parameter can be a value of @ref DMA_FIFO_direct_mode
bogdanm	86:04dd9b1680ae	98	@note The Direct mode (FIFO mode disabled) cannot be used if the
bogdanm	86:04dd9b1680ae	99	memory-to-memory data transfer is configured on the selected stream */
bogdanm	86:04dd9b1680ae	100
bogdanm	86:04dd9b1680ae	101	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
bogdanm	86:04dd9b1680ae	102	This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm	86:04dd9b1680ae	103
bogdanm	86:04dd9b1680ae	104	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto	99:dbbf35b96557	105	It specifies the amount of data to be transferred in a single non interruptible
bogdanm	86:04dd9b1680ae	106	transaction.
bogdanm	86:04dd9b1680ae	107	This parameter can be a value of @ref DMA_Memory_burst
bogdanm	86:04dd9b1680ae	108	@note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm	86:04dd9b1680ae	109
bogdanm	86:04dd9b1680ae	110	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
bogdanm	86:04dd9b1680ae	111	It specifies the amount of data to be transferred in a single non interruptable
bogdanm	86:04dd9b1680ae	112	transaction.
bogdanm	86:04dd9b1680ae	113	This parameter can be a value of @ref DMA_Peripheral_burst
bogdanm	86:04dd9b1680ae	114	@note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm	86:04dd9b1680ae	115	}DMA_InitTypeDef;
bogdanm	86:04dd9b1680ae	116
Kojto	99:dbbf35b96557	117
bogdanm	86:04dd9b1680ae	118	/**
bogdanm	86:04dd9b1680ae	119	* @brief HAL DMA State structures definition
bogdanm	86:04dd9b1680ae	120	*/
bogdanm	86:04dd9b1680ae	121	typedef enum
bogdanm	86:04dd9b1680ae	122	{
bogdanm	86:04dd9b1680ae	123	HAL_DMA_STATE_RESET = 0x00, /!< DMA not yet initialized or disabled /
bogdanm	86:04dd9b1680ae	124	HAL_DMA_STATE_READY = 0x01, /!< DMA initialized and ready for use /
bogdanm	86:04dd9b1680ae	125	HAL_DMA_STATE_READY_MEM0 = 0x11, /!< DMA Mem0 process success /
bogdanm	86:04dd9b1680ae	126	HAL_DMA_STATE_READY_MEM1 = 0x21, /!< DMA Mem1 process success /
bogdanm	86:04dd9b1680ae	127	HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /!< DMA Mem0 Half process success /
bogdanm	86:04dd9b1680ae	128	HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /!< DMA Mem1 Half process success /
bogdanm	86:04dd9b1680ae	129	HAL_DMA_STATE_BUSY = 0x02, /!< DMA process is ongoing /
bogdanm	86:04dd9b1680ae	130	HAL_DMA_STATE_BUSY_MEM0 = 0x12, /!< DMA Mem0 process is ongoing /
bogdanm	86:04dd9b1680ae	131	HAL_DMA_STATE_BUSY_MEM1 = 0x22, /!< DMA Mem1 process is ongoing /
bogdanm	86:04dd9b1680ae	132	HAL_DMA_STATE_TIMEOUT = 0x03, /!< DMA timeout state /
bogdanm	86:04dd9b1680ae	133	HAL_DMA_STATE_ERROR = 0x04, /!< DMA error state /
bogdanm	86:04dd9b1680ae	134	}HAL_DMA_StateTypeDef;
bogdanm	86:04dd9b1680ae	135
bogdanm	86:04dd9b1680ae	136	/**
bogdanm	86:04dd9b1680ae	137	* @brief HAL DMA Error Code structure definition
bogdanm	86:04dd9b1680ae	138	*/
bogdanm	86:04dd9b1680ae	139	typedef enum
bogdanm	86:04dd9b1680ae	140	{
bogdanm	86:04dd9b1680ae	141	HAL_DMA_FULL_TRANSFER = 0x00, /!< Full transfer /
bogdanm	86:04dd9b1680ae	142	HAL_DMA_HALF_TRANSFER = 0x01, /!< Half Transfer /
bogdanm	86:04dd9b1680ae	143	}HAL_DMA_LevelCompleteTypeDef;
bogdanm	86:04dd9b1680ae	144
bogdanm	86:04dd9b1680ae	145	/**
bogdanm	86:04dd9b1680ae	146	* @brief DMA handle Structure definition
bogdanm	86:04dd9b1680ae	147	*/
bogdanm	86:04dd9b1680ae	148	typedef struct __DMA_HandleTypeDef
bogdanm	86:04dd9b1680ae	149	{
bogdanm	86:04dd9b1680ae	150	DMA_Stream_TypeDef Instance; /!< Register base address */
bogdanm	86:04dd9b1680ae	151
bogdanm	86:04dd9b1680ae	152	DMA_InitTypeDef Init; /!< DMA communication parameters /
bogdanm	86:04dd9b1680ae	153
bogdanm	86:04dd9b1680ae	154	HAL_LockTypeDef Lock; /!< DMA locking object /
bogdanm	86:04dd9b1680ae	155
bogdanm	86:04dd9b1680ae	156	__IO HAL_DMA_StateTypeDef State; /!< DMA transfer state /
bogdanm	86:04dd9b1680ae	157
bogdanm	86:04dd9b1680ae	158	void Parent; /!< Parent object state */
bogdanm	86:04dd9b1680ae	159
bogdanm	86:04dd9b1680ae	160	void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete callback /
bogdanm	86:04dd9b1680ae	161
bogdanm	86:04dd9b1680ae	162	void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA Half transfer complete callback /
bogdanm	86:04dd9b1680ae	163
bogdanm	86:04dd9b1680ae	164	void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete Memory1 callback /
bogdanm	86:04dd9b1680ae	165
bogdanm	86:04dd9b1680ae	166	void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer error callback /
bogdanm	86:04dd9b1680ae	167
Kojto	110:165afa46840b	168	__IO uint32_t ErrorCode; /!< DMA Error code /
Kojto	110:165afa46840b	169
Kojto	110:165afa46840b	170	uint32_t StreamBaseAddress; /!< DMA Stream Base Address /
Kojto	110:165afa46840b	171
Kojto	110:165afa46840b	172	uint32_t StreamIndex; /!< DMA Stream Index /
bogdanm	86:04dd9b1680ae	173	}DMA_HandleTypeDef;
bogdanm	86:04dd9b1680ae	174
Kojto	99:dbbf35b96557	175	/**
Kojto	99:dbbf35b96557	176	* @}
Kojto	99:dbbf35b96557	177	*/
Kojto	99:dbbf35b96557	178
bogdanm	86:04dd9b1680ae	179	/* Exported constants --------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	180
Kojto	99:dbbf35b96557	181	/** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto	99:dbbf35b96557	182	* @brief DMA Exported constants
bogdanm	86:04dd9b1680ae	183	* @{
bogdanm	86:04dd9b1680ae	184	*/
bogdanm	86:04dd9b1680ae	185
Kojto	99:dbbf35b96557	186	/** @defgroup DMA_Error_Code DMA Error Code
Kojto	99:dbbf35b96557	187	* @brief DMA Error Code
bogdanm	86:04dd9b1680ae	188	* @{
bogdanm	86:04dd9b1680ae	189	*/
bogdanm	86:04dd9b1680ae	190	#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /!< No error /
bogdanm	86:04dd9b1680ae	191	#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /!< Transfer error /
bogdanm	86:04dd9b1680ae	192	#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /!< FIFO error /
bogdanm	86:04dd9b1680ae	193	#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /!< Direct Mode error /
bogdanm	86:04dd9b1680ae	194	#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /!< Timeout error /
bogdanm	86:04dd9b1680ae	195	/**
bogdanm	86:04dd9b1680ae	196	* @}
bogdanm	86:04dd9b1680ae	197	*/
bogdanm	86:04dd9b1680ae	198
Kojto	99:dbbf35b96557	199	/** @defgroup DMA_Channel_selection DMA Channel selection
Kojto	99:dbbf35b96557	200	* @brief DMA channel selection
bogdanm	86:04dd9b1680ae	201	* @{
bogdanm	86:04dd9b1680ae	202	*/
bogdanm	86:04dd9b1680ae	203	#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /!< DMA Channel 0 /
bogdanm	86:04dd9b1680ae	204	#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /!< DMA Channel 1 /
bogdanm	86:04dd9b1680ae	205	#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /!< DMA Channel 2 /
bogdanm	86:04dd9b1680ae	206	#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /!< DMA Channel 3 /
bogdanm	86:04dd9b1680ae	207	#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /!< DMA Channel 4 /
bogdanm	86:04dd9b1680ae	208	#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /!< DMA Channel 5 /
bogdanm	86:04dd9b1680ae	209	#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /!< DMA Channel 6 /
bogdanm	86:04dd9b1680ae	210	#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /!< DMA Channel 7 /
bogdanm	86:04dd9b1680ae	211	/**
bogdanm	86:04dd9b1680ae	212	* @}
bogdanm	86:04dd9b1680ae	213	*/
bogdanm	86:04dd9b1680ae	214
Kojto	99:dbbf35b96557	215	/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto	99:dbbf35b96557	216	* @brief DMA data transfer direction
bogdanm	86:04dd9b1680ae	217	* @{
bogdanm	86:04dd9b1680ae	218	*/
bogdanm	86:04dd9b1680ae	219	#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /!< Peripheral to memory direction /
bogdanm	86:04dd9b1680ae	220	#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /!< Memory to peripheral direction /
bogdanm	86:04dd9b1680ae	221	#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /!< Memory to memory direction /
bogdanm	86:04dd9b1680ae	222	/**
bogdanm	86:04dd9b1680ae	223	* @}
Kojto	99:dbbf35b96557	224	*/
bogdanm	86:04dd9b1680ae	225
Kojto	99:dbbf35b96557	226	/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto	99:dbbf35b96557	227	* @brief DMA peripheral incremented mode
bogdanm	86:04dd9b1680ae	228	* @{
bogdanm	86:04dd9b1680ae	229	*/
bogdanm	86:04dd9b1680ae	230	#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /!< Peripheral increment mode enable /
bogdanm	86:04dd9b1680ae	231	#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /!< Peripheral increment mode disable /
bogdanm	86:04dd9b1680ae	232	/**
bogdanm	86:04dd9b1680ae	233	* @}
bogdanm	86:04dd9b1680ae	234	*/
bogdanm	86:04dd9b1680ae	235
Kojto	99:dbbf35b96557	236	/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto	99:dbbf35b96557	237	* @brief DMA memory incremented mode
bogdanm	86:04dd9b1680ae	238	* @{
bogdanm	86:04dd9b1680ae	239	*/
bogdanm	86:04dd9b1680ae	240	#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /!< Memory increment mode enable /
bogdanm	86:04dd9b1680ae	241	#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /!< Memory increment mode disable /
bogdanm	86:04dd9b1680ae	242	/**
bogdanm	86:04dd9b1680ae	243	* @}
bogdanm	86:04dd9b1680ae	244	*/
bogdanm	86:04dd9b1680ae	245
Kojto	99:dbbf35b96557	246	/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto	99:dbbf35b96557	247	* @brief DMA peripheral data size
bogdanm	86:04dd9b1680ae	248	* @{
bogdanm	86:04dd9b1680ae	249	*/
bogdanm	86:04dd9b1680ae	250	#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /!< Peripheral data alignment: Byte /
bogdanm	86:04dd9b1680ae	251	#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /!< Peripheral data alignment: HalfWord /
bogdanm	86:04dd9b1680ae	252	#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /!< Peripheral data alignment: Word /
bogdanm	86:04dd9b1680ae	253	/**
bogdanm	86:04dd9b1680ae	254	* @}
bogdanm	86:04dd9b1680ae	255	*/
bogdanm	86:04dd9b1680ae	256
Kojto	99:dbbf35b96557	257	/** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto	99:dbbf35b96557	258	* @brief DMA memory data size
bogdanm	86:04dd9b1680ae	259	* @{
bogdanm	86:04dd9b1680ae	260	*/
bogdanm	86:04dd9b1680ae	261	#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /!< Memory data alignment: Byte /
bogdanm	86:04dd9b1680ae	262	#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /!< Memory data alignment: HalfWord /
bogdanm	86:04dd9b1680ae	263	#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /!< Memory data alignment: Word /
bogdanm	86:04dd9b1680ae	264	/**
bogdanm	86:04dd9b1680ae	265	* @}
bogdanm	86:04dd9b1680ae	266	*/
bogdanm	86:04dd9b1680ae	267
Kojto	99:dbbf35b96557	268	/** @defgroup DMA_mode DMA mode
Kojto	99:dbbf35b96557	269	* @brief DMA mode
bogdanm	86:04dd9b1680ae	270	* @{
bogdanm	86:04dd9b1680ae	271	*/
bogdanm	86:04dd9b1680ae	272	#define DMA_NORMAL ((uint32_t)0x00000000) /!< Normal mode /
bogdanm	86:04dd9b1680ae	273	#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /!< Circular mode /
bogdanm	86:04dd9b1680ae	274	#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /!< Peripheral flow control mode /
bogdanm	86:04dd9b1680ae	275	/**
bogdanm	86:04dd9b1680ae	276	* @}
bogdanm	86:04dd9b1680ae	277	*/
bogdanm	86:04dd9b1680ae	278
Kojto	99:dbbf35b96557	279	/** @defgroup DMA_Priority_level DMA Priority level
Kojto	99:dbbf35b96557	280	* @brief DMA priority levels
bogdanm	86:04dd9b1680ae	281	* @{
bogdanm	86:04dd9b1680ae	282	*/
bogdanm	86:04dd9b1680ae	283	#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /!< Priority level: Low /
bogdanm	86:04dd9b1680ae	284	#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /!< Priority level: Medium /
bogdanm	86:04dd9b1680ae	285	#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /!< Priority level: High /
bogdanm	86:04dd9b1680ae	286	#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /!< Priority level: Very High /
bogdanm	86:04dd9b1680ae	287	/**
bogdanm	86:04dd9b1680ae	288	* @}
bogdanm	86:04dd9b1680ae	289	*/
bogdanm	86:04dd9b1680ae	290
Kojto	99:dbbf35b96557	291	/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto	99:dbbf35b96557	292	* @brief DMA FIFO direct mode
bogdanm	86:04dd9b1680ae	293	* @{
bogdanm	86:04dd9b1680ae	294	*/
bogdanm	86:04dd9b1680ae	295	#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /!< FIFO mode disable /
bogdanm	86:04dd9b1680ae	296	#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /!< FIFO mode enable /
bogdanm	86:04dd9b1680ae	297	/**
bogdanm	86:04dd9b1680ae	298	* @}
bogdanm	86:04dd9b1680ae	299	*/
bogdanm	86:04dd9b1680ae	300
Kojto	99:dbbf35b96557	301	/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto	99:dbbf35b96557	302	* @brief DMA FIFO level
bogdanm	86:04dd9b1680ae	303	* @{
bogdanm	86:04dd9b1680ae	304	*/
bogdanm	86:04dd9b1680ae	305	#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /!< FIFO threshold 1 quart full configuration /
bogdanm	86:04dd9b1680ae	306	#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /!< FIFO threshold half full configuration /
bogdanm	86:04dd9b1680ae	307	#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /!< FIFO threshold 3 quarts full configuration /
bogdanm	86:04dd9b1680ae	308	#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /!< FIFO threshold full configuration /
bogdanm	86:04dd9b1680ae	309	/**
bogdanm	86:04dd9b1680ae	310	* @}
bogdanm	86:04dd9b1680ae	311	*/
bogdanm	86:04dd9b1680ae	312
Kojto	99:dbbf35b96557	313	/** @defgroup DMA_Memory_burst DMA Memory burst
Kojto	99:dbbf35b96557	314	* @brief DMA memory burst
bogdanm	86:04dd9b1680ae	315	* @{
bogdanm	86:04dd9b1680ae	316	*/
bogdanm	86:04dd9b1680ae	317	#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	318	#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
bogdanm	86:04dd9b1680ae	319	#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
bogdanm	86:04dd9b1680ae	320	#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
bogdanm	86:04dd9b1680ae	321	/**
bogdanm	86:04dd9b1680ae	322	* @}
bogdanm	86:04dd9b1680ae	323	*/
bogdanm	86:04dd9b1680ae	324
Kojto	99:dbbf35b96557	325	/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto	99:dbbf35b96557	326	* @brief DMA peripheral burst
bogdanm	86:04dd9b1680ae	327	* @{
bogdanm	86:04dd9b1680ae	328	*/
bogdanm	86:04dd9b1680ae	329	#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	330	#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
bogdanm	86:04dd9b1680ae	331	#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
bogdanm	86:04dd9b1680ae	332	#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
bogdanm	86:04dd9b1680ae	333	/**
bogdanm	86:04dd9b1680ae	334	* @}
bogdanm	86:04dd9b1680ae	335	*/
bogdanm	86:04dd9b1680ae	336
Kojto	99:dbbf35b96557	337	/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto	99:dbbf35b96557	338	* @brief DMA interrupts definition
bogdanm	86:04dd9b1680ae	339	* @{
bogdanm	86:04dd9b1680ae	340	*/
bogdanm	86:04dd9b1680ae	341	#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
bogdanm	86:04dd9b1680ae	342	#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
bogdanm	86:04dd9b1680ae	343	#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
bogdanm	86:04dd9b1680ae	344	#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
bogdanm	86:04dd9b1680ae	345	#define DMA_IT_FE ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	346	/**
bogdanm	86:04dd9b1680ae	347	* @}
bogdanm	86:04dd9b1680ae	348	*/
bogdanm	86:04dd9b1680ae	349
Kojto	99:dbbf35b96557	350	/** @defgroup DMA_flag_definitions DMA flag definitions
Kojto	99:dbbf35b96557	351	* @brief DMA flag definitions
bogdanm	86:04dd9b1680ae	352	* @{
bogdanm	86:04dd9b1680ae	353	*/
bogdanm	86:04dd9b1680ae	354	#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
bogdanm	86:04dd9b1680ae	355	#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
bogdanm	86:04dd9b1680ae	356	#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	357	#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	358	#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	359	#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	360	#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
bogdanm	86:04dd9b1680ae	361	#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	362	#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
bogdanm	86:04dd9b1680ae	363	#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
bogdanm	86:04dd9b1680ae	364	#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	365	#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
bogdanm	86:04dd9b1680ae	366	#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
bogdanm	86:04dd9b1680ae	367	#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
bogdanm	86:04dd9b1680ae	368	#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
bogdanm	86:04dd9b1680ae	369	#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
bogdanm	86:04dd9b1680ae	370	#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
bogdanm	86:04dd9b1680ae	371	#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
bogdanm	86:04dd9b1680ae	372	#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
bogdanm	86:04dd9b1680ae	373	#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
bogdanm	86:04dd9b1680ae	374	/**
bogdanm	86:04dd9b1680ae	375	* @}
bogdanm	86:04dd9b1680ae	376	*/
Kojto	99:dbbf35b96557	377
bogdanm	86:04dd9b1680ae	378	/**
bogdanm	86:04dd9b1680ae	379	* @}
bogdanm	86:04dd9b1680ae	380	*/
Kojto	99:dbbf35b96557	381
bogdanm	86:04dd9b1680ae	382	/* Exported macro ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	383
bogdanm	86:04dd9b1680ae	384	/** @brief Reset DMA handle state
bogdanm	86:04dd9b1680ae	385	* @param __HANDLE__: specifies the DMA handle.
bogdanm	86:04dd9b1680ae	386	* @retval None
bogdanm	86:04dd9b1680ae	387	*/
bogdanm	86:04dd9b1680ae	388	#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm	86:04dd9b1680ae	389
bogdanm	86:04dd9b1680ae	390	/**
bogdanm	86:04dd9b1680ae	391	* @brief Return the current DMA Stream FIFO filled level.
bogdanm	86:04dd9b1680ae	392	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	393	* @retval The FIFO filling state.
bogdanm	86:04dd9b1680ae	394	* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
bogdanm	86:04dd9b1680ae	395	* and not empty.
bogdanm	86:04dd9b1680ae	396	* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm	86:04dd9b1680ae	397	* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
bogdanm	86:04dd9b1680ae	398	* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
bogdanm	86:04dd9b1680ae	399	* - DMA_FIFOStatus_Empty: when FIFO is empty
bogdanm	86:04dd9b1680ae	400	* - DMA_FIFOStatus_Full: when FIFO is full
bogdanm	86:04dd9b1680ae	401	*/
bogdanm	86:04dd9b1680ae	402	#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
bogdanm	86:04dd9b1680ae	403
bogdanm	86:04dd9b1680ae	404	/**
bogdanm	86:04dd9b1680ae	405	* @brief Enable the specified DMA Stream.
bogdanm	86:04dd9b1680ae	406	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	407	* @retval None
bogdanm	86:04dd9b1680ae	408	*/
bogdanm	86:04dd9b1680ae	409	#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DMA_SxCR_EN)
bogdanm	86:04dd9b1680ae	410
bogdanm	86:04dd9b1680ae	411	/**
bogdanm	86:04dd9b1680ae	412	* @brief Disable the specified DMA Stream.
bogdanm	86:04dd9b1680ae	413	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	414	* @retval None
bogdanm	86:04dd9b1680ae	415	*/
bogdanm	86:04dd9b1680ae	416	#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
bogdanm	86:04dd9b1680ae	417
bogdanm	86:04dd9b1680ae	418	/* Interrupt & Flag management */
bogdanm	86:04dd9b1680ae	419
bogdanm	86:04dd9b1680ae	420	/**
bogdanm	86:04dd9b1680ae	421	* @brief Return the current DMA Stream transfer complete flag.
bogdanm	86:04dd9b1680ae	422	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	423	* @retval The specified transfer complete flag index.
bogdanm	86:04dd9b1680ae	424	*/
bogdanm	86:04dd9b1680ae	425	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm	86:04dd9b1680ae	426	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm	86:04dd9b1680ae	427	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm	86:04dd9b1680ae	428	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm	86:04dd9b1680ae	429	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm	86:04dd9b1680ae	430	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm	86:04dd9b1680ae	431	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm	86:04dd9b1680ae	432	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm	86:04dd9b1680ae	433	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm	86:04dd9b1680ae	434	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm	86:04dd9b1680ae	435	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm	86:04dd9b1680ae	436	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm	86:04dd9b1680ae	437	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm	86:04dd9b1680ae	438	DMA_FLAG_TCIF3_7)
bogdanm	86:04dd9b1680ae	439
bogdanm	86:04dd9b1680ae	440	/**
bogdanm	86:04dd9b1680ae	441	* @brief Return the current DMA Stream half transfer complete flag.
bogdanm	86:04dd9b1680ae	442	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	443	* @retval The specified half transfer complete flag index.
bogdanm	86:04dd9b1680ae	444	*/
bogdanm	86:04dd9b1680ae	445	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm	86:04dd9b1680ae	446	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm	86:04dd9b1680ae	447	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm	86:04dd9b1680ae	448	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm	86:04dd9b1680ae	449	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm	86:04dd9b1680ae	450	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm	86:04dd9b1680ae	451	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm	86:04dd9b1680ae	452	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm	86:04dd9b1680ae	453	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm	86:04dd9b1680ae	454	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm	86:04dd9b1680ae	455	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm	86:04dd9b1680ae	456	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm	86:04dd9b1680ae	457	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm	86:04dd9b1680ae	458	DMA_FLAG_HTIF3_7)
bogdanm	86:04dd9b1680ae	459
bogdanm	86:04dd9b1680ae	460	/**
bogdanm	86:04dd9b1680ae	461	* @brief Return the current DMA Stream transfer error flag.
bogdanm	86:04dd9b1680ae	462	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	463	* @retval The specified transfer error flag index.
bogdanm	86:04dd9b1680ae	464	*/
bogdanm	86:04dd9b1680ae	465	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm	86:04dd9b1680ae	466	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm	86:04dd9b1680ae	467	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm	86:04dd9b1680ae	468	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm	86:04dd9b1680ae	469	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm	86:04dd9b1680ae	470	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm	86:04dd9b1680ae	471	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm	86:04dd9b1680ae	472	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm	86:04dd9b1680ae	473	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm	86:04dd9b1680ae	474	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm	86:04dd9b1680ae	475	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm	86:04dd9b1680ae	476	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm	86:04dd9b1680ae	477	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm	86:04dd9b1680ae	478	DMA_FLAG_TEIF3_7)
bogdanm	86:04dd9b1680ae	479
bogdanm	86:04dd9b1680ae	480	/**
bogdanm	86:04dd9b1680ae	481	* @brief Return the current DMA Stream FIFO error flag.
bogdanm	86:04dd9b1680ae	482	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	483	* @retval The specified FIFO error flag index.
bogdanm	86:04dd9b1680ae	484	*/
bogdanm	86:04dd9b1680ae	485	#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
bogdanm	86:04dd9b1680ae	486	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm	86:04dd9b1680ae	487	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm	86:04dd9b1680ae	488	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm	86:04dd9b1680ae	489	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm	86:04dd9b1680ae	490	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm	86:04dd9b1680ae	491	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm	86:04dd9b1680ae	492	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm	86:04dd9b1680ae	493	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm	86:04dd9b1680ae	494	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm	86:04dd9b1680ae	495	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm	86:04dd9b1680ae	496	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm	86:04dd9b1680ae	497	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm	86:04dd9b1680ae	498	DMA_FLAG_FEIF3_7)
bogdanm	86:04dd9b1680ae	499
bogdanm	86:04dd9b1680ae	500	/**
bogdanm	86:04dd9b1680ae	501	* @brief Return the current DMA Stream direct mode error flag.
bogdanm	86:04dd9b1680ae	502	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	503	* @retval The specified direct mode error flag index.
bogdanm	86:04dd9b1680ae	504	*/
bogdanm	86:04dd9b1680ae	505	#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
bogdanm	86:04dd9b1680ae	506	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm	86:04dd9b1680ae	507	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm	86:04dd9b1680ae	508	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm	86:04dd9b1680ae	509	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm	86:04dd9b1680ae	510	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm	86:04dd9b1680ae	511	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm	86:04dd9b1680ae	512	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm	86:04dd9b1680ae	513	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm	86:04dd9b1680ae	514	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm	86:04dd9b1680ae	515	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm	86:04dd9b1680ae	516	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm	86:04dd9b1680ae	517	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm	86:04dd9b1680ae	518	DMA_FLAG_DMEIF3_7)
bogdanm	86:04dd9b1680ae	519
bogdanm	86:04dd9b1680ae	520	/**
bogdanm	86:04dd9b1680ae	521	* @brief Get the DMA Stream pending flags.
bogdanm	86:04dd9b1680ae	522	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	523	* @param __FLAG__: Get the specified flag.
bogdanm	86:04dd9b1680ae	524	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	525	* @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm	86:04dd9b1680ae	526	* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm	86:04dd9b1680ae	527	* @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm	86:04dd9b1680ae	528	* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm	86:04dd9b1680ae	529	* @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm	86:04dd9b1680ae	530	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm	86:04dd9b1680ae	531	* @retval The state of FLAG (SET or RESET).
bogdanm	86:04dd9b1680ae	532	*/
bogdanm	86:04dd9b1680ae	533	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm	86:04dd9b1680ae	534	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
bogdanm	86:04dd9b1680ae	535	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
bogdanm	86:04dd9b1680ae	536	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
bogdanm	86:04dd9b1680ae	537
bogdanm	86:04dd9b1680ae	538	/**
bogdanm	86:04dd9b1680ae	539	* @brief Clear the DMA Stream pending flags.
bogdanm	86:04dd9b1680ae	540	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	541	* @param __FLAG__: specifies the flag to clear.
bogdanm	86:04dd9b1680ae	542	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	543	* @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm	86:04dd9b1680ae	544	* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm	86:04dd9b1680ae	545	* @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm	86:04dd9b1680ae	546	* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm	86:04dd9b1680ae	547	* @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm	86:04dd9b1680ae	548	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm	86:04dd9b1680ae	549	* @retval None
bogdanm	86:04dd9b1680ae	550	*/
bogdanm	86:04dd9b1680ae	551	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm	86:04dd9b1680ae	552	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
bogdanm	86:04dd9b1680ae	553	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
bogdanm	86:04dd9b1680ae	554	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
bogdanm	86:04dd9b1680ae	555
bogdanm	86:04dd9b1680ae	556	/**
bogdanm	86:04dd9b1680ae	557	* @brief Enable the specified DMA Stream interrupts.
bogdanm	86:04dd9b1680ae	558	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	559	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm	86:04dd9b1680ae	560	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	561	* @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm	86:04dd9b1680ae	562	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm	86:04dd9b1680ae	563	* @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm	86:04dd9b1680ae	564	* @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm	86:04dd9b1680ae	565	* @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm	86:04dd9b1680ae	566	* @retval None
bogdanm	86:04dd9b1680ae	567	*/
bogdanm	86:04dd9b1680ae	568	#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm	86:04dd9b1680ae	569	((__HANDLE__)->Instance->CR \|= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR \|= (__INTERRUPT__)))
bogdanm	86:04dd9b1680ae	570
bogdanm	86:04dd9b1680ae	571	/**
bogdanm	86:04dd9b1680ae	572	* @brief Disable the specified DMA Stream interrupts.
bogdanm	86:04dd9b1680ae	573	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	574	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm	86:04dd9b1680ae	575	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	576	* @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm	86:04dd9b1680ae	577	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm	86:04dd9b1680ae	578	* @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm	86:04dd9b1680ae	579	* @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm	86:04dd9b1680ae	580	* @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm	86:04dd9b1680ae	581	* @retval None
bogdanm	86:04dd9b1680ae	582	*/
bogdanm	86:04dd9b1680ae	583	#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm	86:04dd9b1680ae	584	((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
bogdanm	86:04dd9b1680ae	585
bogdanm	86:04dd9b1680ae	586	/**
Kojto	106:ba1f97679dad	587	* @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
bogdanm	86:04dd9b1680ae	588	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	589	* @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm	86:04dd9b1680ae	590	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	591	* @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm	86:04dd9b1680ae	592	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm	86:04dd9b1680ae	593	* @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm	86:04dd9b1680ae	594	* @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm	86:04dd9b1680ae	595	* @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm	86:04dd9b1680ae	596	* @retval The state of DMA_IT.
bogdanm	86:04dd9b1680ae	597	*/
bogdanm	86:04dd9b1680ae	598	#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm	86:04dd9b1680ae	599	((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
bogdanm	86:04dd9b1680ae	600	((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
bogdanm	86:04dd9b1680ae	601
bogdanm	86:04dd9b1680ae	602	/**
bogdanm	86:04dd9b1680ae	603	* @brief Writes the number of data units to be transferred on the DMA Stream.
bogdanm	86:04dd9b1680ae	604	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	605	* @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
bogdanm	86:04dd9b1680ae	606	* Number of data items depends only on the Peripheral data format.
bogdanm	86:04dd9b1680ae	607	*
bogdanm	86:04dd9b1680ae	608	* @note If Peripheral data format is Bytes: number of data units is equal
bogdanm	86:04dd9b1680ae	609	* to total number of bytes to be transferred.
bogdanm	86:04dd9b1680ae	610	*
bogdanm	86:04dd9b1680ae	611	* @note If Peripheral data format is Half-Word: number of data units is
bogdanm	86:04dd9b1680ae	612	* equal to total number of bytes to be transferred / 2.
bogdanm	86:04dd9b1680ae	613	*
bogdanm	86:04dd9b1680ae	614	* @note If Peripheral data format is Word: number of data units is equal
bogdanm	86:04dd9b1680ae	615	* to total number of bytes to be transferred / 4.
bogdanm	86:04dd9b1680ae	616	*
bogdanm	86:04dd9b1680ae	617	* @retval The number of remaining data units in the current DMAy Streamx transfer.
bogdanm	86:04dd9b1680ae	618	*/
bogdanm	86:04dd9b1680ae	619	#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
bogdanm	86:04dd9b1680ae	620
bogdanm	86:04dd9b1680ae	621	/**
bogdanm	86:04dd9b1680ae	622	* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
bogdanm	86:04dd9b1680ae	623	* @param __HANDLE__: DMA handle
bogdanm	86:04dd9b1680ae	624	*
bogdanm	86:04dd9b1680ae	625	* @retval The number of remaining data units in the current DMA Stream transfer.
bogdanm	86:04dd9b1680ae	626	*/
bogdanm	86:04dd9b1680ae	627	#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
bogdanm	86:04dd9b1680ae	628
bogdanm	86:04dd9b1680ae	629
bogdanm	86:04dd9b1680ae	630	/* Include DMA HAL Extension module */
bogdanm	86:04dd9b1680ae	631	#include "stm32f4xx_hal_dma_ex.h"
bogdanm	86:04dd9b1680ae	632
bogdanm	86:04dd9b1680ae	633	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	634
Kojto	99:dbbf35b96557	635	/** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto	99:dbbf35b96557	636	* @brief DMA Exported functions
Kojto	99:dbbf35b96557	637	* @{
Kojto	99:dbbf35b96557	638	*/
Kojto	99:dbbf35b96557	639
Kojto	99:dbbf35b96557	640	/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto	99:dbbf35b96557	641	* @brief Initialization and de-initialization functions
Kojto	99:dbbf35b96557	642	* @{
Kojto	99:dbbf35b96557	643	*/
bogdanm	86:04dd9b1680ae	644	HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm	86:04dd9b1680ae	645	HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto	99:dbbf35b96557	646	/**
Kojto	99:dbbf35b96557	647	* @}
Kojto	99:dbbf35b96557	648	*/
bogdanm	86:04dd9b1680ae	649
Kojto	99:dbbf35b96557	650	/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto	99:dbbf35b96557	651	* @brief I/O operation functions
Kojto	99:dbbf35b96557	652	* @{
Kojto	99:dbbf35b96557	653	*/
bogdanm	86:04dd9b1680ae	654	HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm	86:04dd9b1680ae	655	HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm	86:04dd9b1680ae	656	HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm	86:04dd9b1680ae	657	HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm	86:04dd9b1680ae	658	void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto	99:dbbf35b96557	659	/**
Kojto	99:dbbf35b96557	660	* @}
Kojto	99:dbbf35b96557	661	*/
bogdanm	86:04dd9b1680ae	662
Kojto	99:dbbf35b96557	663	/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto	99:dbbf35b96557	664	* @brief Peripheral State functions
Kojto	99:dbbf35b96557	665	* @{
Kojto	99:dbbf35b96557	666	*/
bogdanm	86:04dd9b1680ae	667	HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm	86:04dd9b1680ae	668	uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto	99:dbbf35b96557	669	/**
Kojto	99:dbbf35b96557	670	* @}
Kojto	99:dbbf35b96557	671	*/
Kojto	99:dbbf35b96557	672	/**
Kojto	99:dbbf35b96557	673	* @}
Kojto	99:dbbf35b96557	674	*/
Kojto	99:dbbf35b96557	675	/* Private Constants -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	676	/** @defgroup DMA_Private_Constants DMA Private Constants
Kojto	99:dbbf35b96557	677	* @brief DMA private defines and constants
Kojto	99:dbbf35b96557	678	* @{
Kojto	99:dbbf35b96557	679	*/
Kojto	99:dbbf35b96557	680	/**
Kojto	99:dbbf35b96557	681	* @}
Kojto	99:dbbf35b96557	682	*/
Kojto	99:dbbf35b96557	683
Kojto	99:dbbf35b96557	684	/* Private macros ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	685	/** @defgroup DMA_Private_Macros DMA Private Macros
Kojto	99:dbbf35b96557	686	* @brief DMA private macros
Kojto	99:dbbf35b96557	687	* @{
Kojto	99:dbbf35b96557	688	*/
Kojto	99:dbbf35b96557	689	#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) \|\| \
Kojto	99:dbbf35b96557	690	((CHANNEL) == DMA_CHANNEL_1) \|\| \
Kojto	99:dbbf35b96557	691	((CHANNEL) == DMA_CHANNEL_2) \|\| \
Kojto	99:dbbf35b96557	692	((CHANNEL) == DMA_CHANNEL_3) \|\| \
Kojto	99:dbbf35b96557	693	((CHANNEL) == DMA_CHANNEL_4) \|\| \
Kojto	99:dbbf35b96557	694	((CHANNEL) == DMA_CHANNEL_5) \|\| \
Kojto	99:dbbf35b96557	695	((CHANNEL) == DMA_CHANNEL_6) \|\| \
Kojto	99:dbbf35b96557	696	((CHANNEL) == DMA_CHANNEL_7))
Kojto	99:dbbf35b96557	697
Kojto	99:dbbf35b96557	698	#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) \|\| \
Kojto	99:dbbf35b96557	699	((DIRECTION) == DMA_MEMORY_TO_PERIPH) \|\| \
Kojto	99:dbbf35b96557	700	((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto	99:dbbf35b96557	701
Kojto	99:dbbf35b96557	702	#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto	99:dbbf35b96557	703
Kojto	99:dbbf35b96557	704	#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) \|\| \
Kojto	99:dbbf35b96557	705	((STATE) == DMA_PINC_DISABLE))
Kojto	99:dbbf35b96557	706
Kojto	99:dbbf35b96557	707	#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) \|\| \
Kojto	99:dbbf35b96557	708	((STATE) == DMA_MINC_DISABLE))
Kojto	99:dbbf35b96557	709
Kojto	99:dbbf35b96557	710	#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) \|\| \
Kojto	99:dbbf35b96557	711	((SIZE) == DMA_PDATAALIGN_HALFWORD) \|\| \
Kojto	99:dbbf35b96557	712	((SIZE) == DMA_PDATAALIGN_WORD))
Kojto	99:dbbf35b96557	713
Kojto	99:dbbf35b96557	714	#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) \|\| \
Kojto	99:dbbf35b96557	715	((SIZE) == DMA_MDATAALIGN_HALFWORD) \|\| \
Kojto	99:dbbf35b96557	716	((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto	99:dbbf35b96557	717
Kojto	99:dbbf35b96557	718	#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) \|\| \
Kojto	99:dbbf35b96557	719	((MODE) == DMA_CIRCULAR) \|\| \
Kojto	99:dbbf35b96557	720	((MODE) == DMA_PFCTRL))
Kojto	99:dbbf35b96557	721
Kojto	99:dbbf35b96557	722	#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) \|\| \
Kojto	99:dbbf35b96557	723	((PRIORITY) == DMA_PRIORITY_MEDIUM) \|\| \
Kojto	99:dbbf35b96557	724	((PRIORITY) == DMA_PRIORITY_HIGH) \|\| \
Kojto	99:dbbf35b96557	725	((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto	99:dbbf35b96557	726
Kojto	99:dbbf35b96557	727	#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) \|\| \
Kojto	99:dbbf35b96557	728	((STATE) == DMA_FIFOMODE_ENABLE))
Kojto	99:dbbf35b96557	729
Kojto	99:dbbf35b96557	730	#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) \|\| \
Kojto	99:dbbf35b96557	731	((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) \|\| \
Kojto	99:dbbf35b96557	732	((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) \|\| \
Kojto	99:dbbf35b96557	733	((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto	99:dbbf35b96557	734
Kojto	99:dbbf35b96557	735	#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) \|\| \
Kojto	99:dbbf35b96557	736	((BURST) == DMA_MBURST_INC4) \|\| \
Kojto	99:dbbf35b96557	737	((BURST) == DMA_MBURST_INC8) \|\| \
Kojto	99:dbbf35b96557	738	((BURST) == DMA_MBURST_INC16))
Kojto	99:dbbf35b96557	739
Kojto	99:dbbf35b96557	740	#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) \|\| \
Kojto	99:dbbf35b96557	741	((BURST) == DMA_PBURST_INC4) \|\| \
Kojto	99:dbbf35b96557	742	((BURST) == DMA_PBURST_INC8) \|\| \
Kojto	99:dbbf35b96557	743	((BURST) == DMA_PBURST_INC16))
Kojto	99:dbbf35b96557	744	/**
Kojto	99:dbbf35b96557	745	* @}
Kojto	99:dbbf35b96557	746	*/
Kojto	99:dbbf35b96557	747
Kojto	99:dbbf35b96557	748	/* Private functions ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	749	/** @defgroup DMA_Private_Functions DMA Private Functions
Kojto	99:dbbf35b96557	750	* @brief DMA private functions
Kojto	99:dbbf35b96557	751	* @{
Kojto	99:dbbf35b96557	752	*/
Kojto	99:dbbf35b96557	753	/**
Kojto	99:dbbf35b96557	754	* @}
Kojto	99:dbbf35b96557	755	*/
bogdanm	86:04dd9b1680ae	756
bogdanm	86:04dd9b1680ae	757	/**
bogdanm	86:04dd9b1680ae	758	* @}
bogdanm	86:04dd9b1680ae	759	*/
bogdanm	86:04dd9b1680ae	760
bogdanm	86:04dd9b1680ae	761	/**
bogdanm	86:04dd9b1680ae	762	* @}
bogdanm	86:04dd9b1680ae	763	*/
bogdanm	86:04dd9b1680ae	764
bogdanm	86:04dd9b1680ae	765	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	766	}
bogdanm	86:04dd9b1680ae	767	#endif
bogdanm	86:04dd9b1680ae	768
bogdanm	86:04dd9b1680ae	769	#endif /* __STM32F4xx_HAL_DMA_H */
bogdanm	86:04dd9b1680ae	770
bogdanm	86:04dd9b1680ae	771	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h@110:165afa46840b, 2015-11-25 (annotated)

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