Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_DISCO_F429ZI/stm32f4xx_hal_rcc.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Child:
116:c0f6e94411f5
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 110:165afa46840b 1 /**
Kojto 110:165afa46840b 2 ******************************************************************************
Kojto 110:165afa46840b 3 * @file stm32f4xx_hal_rcc.h
Kojto 110:165afa46840b 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 110:165afa46840b 7 * @brief Header file of RCC HAL module.
Kojto 110:165afa46840b 8 ******************************************************************************
Kojto 110:165afa46840b 9 * @attention
Kojto 110:165afa46840b 10 *
Kojto 110:165afa46840b 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 110:165afa46840b 12 *
Kojto 110:165afa46840b 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 110:165afa46840b 14 * are permitted provided that the following conditions are met:
Kojto 110:165afa46840b 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 110:165afa46840b 16 * this list of conditions and the following disclaimer.
Kojto 110:165afa46840b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 110:165afa46840b 18 * this list of conditions and the following disclaimer in the documentation
Kojto 110:165afa46840b 19 * and/or other materials provided with the distribution.
Kojto 110:165afa46840b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 110:165afa46840b 21 * may be used to endorse or promote products derived from this software
Kojto 110:165afa46840b 22 * without specific prior written permission.
Kojto 110:165afa46840b 23 *
Kojto 110:165afa46840b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 110:165afa46840b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 110:165afa46840b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 110:165afa46840b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 110:165afa46840b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 110:165afa46840b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 110:165afa46840b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 110:165afa46840b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 110:165afa46840b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 110:165afa46840b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 110:165afa46840b 34 *
Kojto 110:165afa46840b 35 ******************************************************************************
Kojto 110:165afa46840b 36 */
Kojto 110:165afa46840b 37
Kojto 110:165afa46840b 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 110:165afa46840b 39 #ifndef __STM32F4xx_HAL_RCC_H
Kojto 110:165afa46840b 40 #define __STM32F4xx_HAL_RCC_H
Kojto 110:165afa46840b 41
Kojto 110:165afa46840b 42 #ifdef __cplusplus
Kojto 110:165afa46840b 43 extern "C" {
Kojto 110:165afa46840b 44 #endif
Kojto 110:165afa46840b 45
Kojto 110:165afa46840b 46 /* Includes ------------------------------------------------------------------*/
Kojto 110:165afa46840b 47 #include "stm32f4xx_hal_def.h"
Kojto 110:165afa46840b 48
Kojto 110:165afa46840b 49 /* Include RCC HAL Extended module */
Kojto 110:165afa46840b 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 110:165afa46840b 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 110:165afa46840b 52
Kojto 110:165afa46840b 53 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 110:165afa46840b 54 * @{
Kojto 110:165afa46840b 55 */
Kojto 110:165afa46840b 56
Kojto 110:165afa46840b 57 /** @addtogroup RCC
Kojto 110:165afa46840b 58 * @{
Kojto 110:165afa46840b 59 */
Kojto 110:165afa46840b 60
Kojto 110:165afa46840b 61 /* Exported types ------------------------------------------------------------*/
Kojto 110:165afa46840b 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 110:165afa46840b 63 * @{
Kojto 110:165afa46840b 64 */
Kojto 110:165afa46840b 65
Kojto 110:165afa46840b 66 /**
Kojto 110:165afa46840b 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 110:165afa46840b 68 */
Kojto 110:165afa46840b 69 typedef struct
Kojto 110:165afa46840b 70 {
Kojto 110:165afa46840b 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 110:165afa46840b 72 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 110:165afa46840b 73
Kojto 110:165afa46840b 74 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 110:165afa46840b 75 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 110:165afa46840b 76
Kojto 110:165afa46840b 77 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 110:165afa46840b 78 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 110:165afa46840b 79
Kojto 110:165afa46840b 80 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 110:165afa46840b 81 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 110:165afa46840b 82
Kojto 110:165afa46840b 83 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto 110:165afa46840b 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 110:165afa46840b 85
Kojto 110:165afa46840b 86 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 110:165afa46840b 87 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 110:165afa46840b 88
Kojto 110:165afa46840b 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 110:165afa46840b 90
Kojto 110:165afa46840b 91 }RCC_OscInitTypeDef;
Kojto 110:165afa46840b 92
Kojto 110:165afa46840b 93 /**
Kojto 110:165afa46840b 94 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 110:165afa46840b 95 */
Kojto 110:165afa46840b 96 typedef struct
Kojto 110:165afa46840b 97 {
Kojto 110:165afa46840b 98 uint32_t ClockType; /*!< The clock to be configured.
Kojto 110:165afa46840b 99 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 110:165afa46840b 100
Kojto 110:165afa46840b 101 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 110:165afa46840b 102 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 110:165afa46840b 103
Kojto 110:165afa46840b 104 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 110:165afa46840b 105 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 110:165afa46840b 106
Kojto 110:165afa46840b 107 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 110:165afa46840b 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 110:165afa46840b 109
Kojto 110:165afa46840b 110 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 110:165afa46840b 111 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 110:165afa46840b 112
Kojto 110:165afa46840b 113 }RCC_ClkInitTypeDef;
Kojto 110:165afa46840b 114
Kojto 110:165afa46840b 115 /**
Kojto 110:165afa46840b 116 * @}
Kojto 110:165afa46840b 117 */
Kojto 110:165afa46840b 118
Kojto 110:165afa46840b 119 /* Exported constants --------------------------------------------------------*/
Kojto 110:165afa46840b 120 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 110:165afa46840b 121 * @{
Kojto 110:165afa46840b 122 */
Kojto 110:165afa46840b 123
Kojto 110:165afa46840b 124 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 110:165afa46840b 125 * @{
Kojto 110:165afa46840b 126 */
Kojto 110:165afa46840b 127 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 128 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 110:165afa46840b 129 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 110:165afa46840b 130 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 131 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 110:165afa46840b 132 /**
Kojto 110:165afa46840b 133 * @}
Kojto 110:165afa46840b 134 */
Kojto 110:165afa46840b 135
Kojto 110:165afa46840b 136 /** @defgroup RCC_HSE_Config HSE Config
Kojto 110:165afa46840b 137 * @{
Kojto 110:165afa46840b 138 */
Kojto 110:165afa46840b 139 #define RCC_HSE_OFF ((uint8_t)0x00)
Kojto 110:165afa46840b 140 #define RCC_HSE_ON ((uint8_t)0x01)
Kojto 110:165afa46840b 141 #define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto 110:165afa46840b 142 /**
Kojto 110:165afa46840b 143 * @}
Kojto 110:165afa46840b 144 */
Kojto 110:165afa46840b 145
Kojto 110:165afa46840b 146 /** @defgroup RCC_LSE_Config LSE Config
Kojto 110:165afa46840b 147 * @{
Kojto 110:165afa46840b 148 */
Kojto 110:165afa46840b 149 #define RCC_LSE_OFF ((uint8_t)0x00)
Kojto 110:165afa46840b 150 #define RCC_LSE_ON ((uint8_t)0x01)
Kojto 110:165afa46840b 151 #define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto 110:165afa46840b 152 /**
Kojto 110:165afa46840b 153 * @}
Kojto 110:165afa46840b 154 */
Kojto 110:165afa46840b 155
Kojto 110:165afa46840b 156 /** @defgroup RCC_HSI_Config HSI Config
Kojto 110:165afa46840b 157 * @{
Kojto 110:165afa46840b 158 */
Kojto 110:165afa46840b 159 #define RCC_HSI_OFF ((uint8_t)0x00)
Kojto 110:165afa46840b 160 #define RCC_HSI_ON ((uint8_t)0x01)
Kojto 110:165afa46840b 161 /**
Kojto 110:165afa46840b 162 * @}
Kojto 110:165afa46840b 163 */
Kojto 110:165afa46840b 164
Kojto 110:165afa46840b 165 /** @defgroup RCC_LSI_Config LSI Config
Kojto 110:165afa46840b 166 * @{
Kojto 110:165afa46840b 167 */
Kojto 110:165afa46840b 168 #define RCC_LSI_OFF ((uint8_t)0x00)
Kojto 110:165afa46840b 169 #define RCC_LSI_ON ((uint8_t)0x01)
Kojto 110:165afa46840b 170 /**
Kojto 110:165afa46840b 171 * @}
Kojto 110:165afa46840b 172 */
Kojto 110:165afa46840b 173
Kojto 110:165afa46840b 174 /** @defgroup RCC_PLL_Config PLL Config
Kojto 110:165afa46840b 175 * @{
Kojto 110:165afa46840b 176 */
Kojto 110:165afa46840b 177 #define RCC_PLL_NONE ((uint8_t)0x00)
Kojto 110:165afa46840b 178 #define RCC_PLL_OFF ((uint8_t)0x01)
Kojto 110:165afa46840b 179 #define RCC_PLL_ON ((uint8_t)0x02)
Kojto 110:165afa46840b 180 /**
Kojto 110:165afa46840b 181 * @}
Kojto 110:165afa46840b 182 */
Kojto 110:165afa46840b 183
Kojto 110:165afa46840b 184 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto 110:165afa46840b 185 * @{
Kojto 110:165afa46840b 186 */
Kojto 110:165afa46840b 187 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 188 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 189 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto 110:165afa46840b 190 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 191 /**
Kojto 110:165afa46840b 192 * @}
Kojto 110:165afa46840b 193 */
Kojto 110:165afa46840b 194
Kojto 110:165afa46840b 195 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 110:165afa46840b 196 * @{
Kojto 110:165afa46840b 197 */
Kojto 110:165afa46840b 198 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto 110:165afa46840b 199 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto 110:165afa46840b 200 /**
Kojto 110:165afa46840b 201 * @}
Kojto 110:165afa46840b 202 */
Kojto 110:165afa46840b 203
Kojto 110:165afa46840b 204 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 110:165afa46840b 205 * @{
Kojto 110:165afa46840b 206 */
Kojto 110:165afa46840b 207 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto 110:165afa46840b 208 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto 110:165afa46840b 209 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 210 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 211 /**
Kojto 110:165afa46840b 212 * @}
Kojto 110:165afa46840b 213 */
Kojto 110:165afa46840b 214
Kojto 110:165afa46840b 215 /** @defgroup RCC_System_Clock_Source System Clock Source
Kojto 110:165afa46840b 216 * @{
Kojto 110:165afa46840b 217 */
Kojto 110:165afa46840b 218 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 110:165afa46840b 219 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 110:165afa46840b 220 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 110:165afa46840b 221 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
Kojto 110:165afa46840b 222 /**
Kojto 110:165afa46840b 223 * @}
Kojto 110:165afa46840b 224 */
Kojto 110:165afa46840b 225
Kojto 110:165afa46840b 226 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 110:165afa46840b 227 * @{
Kojto 110:165afa46840b 228 */
Kojto 110:165afa46840b 229 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 110:165afa46840b 230 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 110:165afa46840b 231 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 110:165afa46840b 232 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
Kojto 110:165afa46840b 233 /**
Kojto 110:165afa46840b 234 * @}
Kojto 110:165afa46840b 235 */
Kojto 110:165afa46840b 236
Kojto 110:165afa46840b 237 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 110:165afa46840b 238 * @{
Kojto 110:165afa46840b 239 */
Kojto 110:165afa46840b 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 110:165afa46840b 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 110:165afa46840b 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 110:165afa46840b 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 110:165afa46840b 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 110:165afa46840b 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 110:165afa46840b 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 110:165afa46840b 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 110:165afa46840b 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 110:165afa46840b 249 /**
Kojto 110:165afa46840b 250 * @}
Kojto 110:165afa46840b 251 */
Kojto 110:165afa46840b 252
Kojto 110:165afa46840b 253 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
Kojto 110:165afa46840b 254 * @{
Kojto 110:165afa46840b 255 */
Kojto 110:165afa46840b 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto 110:165afa46840b 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto 110:165afa46840b 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto 110:165afa46840b 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto 110:165afa46840b 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto 110:165afa46840b 261 /**
Kojto 110:165afa46840b 262 * @}
Kojto 110:165afa46840b 263 */
Kojto 110:165afa46840b 264
Kojto 110:165afa46840b 265 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 110:165afa46840b 266 * @{
Kojto 110:165afa46840b 267 */
Kojto 110:165afa46840b 268 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto 110:165afa46840b 269 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto 110:165afa46840b 270 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto 110:165afa46840b 271 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto 110:165afa46840b 272 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto 110:165afa46840b 273 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto 110:165afa46840b 274 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto 110:165afa46840b 275 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto 110:165afa46840b 276 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto 110:165afa46840b 277 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto 110:165afa46840b 278 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto 110:165afa46840b 279 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto 110:165afa46840b 280 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto 110:165afa46840b 281 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto 110:165afa46840b 282 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto 110:165afa46840b 283 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto 110:165afa46840b 284 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto 110:165afa46840b 285 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto 110:165afa46840b 286 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto 110:165afa46840b 287 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto 110:165afa46840b 288 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto 110:165afa46840b 289 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto 110:165afa46840b 290 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto 110:165afa46840b 291 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto 110:165afa46840b 292 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto 110:165afa46840b 293 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto 110:165afa46840b 294 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto 110:165afa46840b 295 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto 110:165afa46840b 296 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto 110:165afa46840b 297 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto 110:165afa46840b 298 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto 110:165afa46840b 299 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto 110:165afa46840b 300 /**
Kojto 110:165afa46840b 301 * @}
Kojto 110:165afa46840b 302 */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 /** @defgroup RCC_MCO_Index MCO Index
Kojto 110:165afa46840b 305 * @{
Kojto 110:165afa46840b 306 */
Kojto 110:165afa46840b 307 #define RCC_MCO1 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 308 #define RCC_MCO2 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 309 /**
Kojto 110:165afa46840b 310 * @}
Kojto 110:165afa46840b 311 */
Kojto 110:165afa46840b 312
Kojto 110:165afa46840b 313 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto 110:165afa46840b 314 * @{
Kojto 110:165afa46840b 315 */
Kojto 110:165afa46840b 316 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto 110:165afa46840b 317 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto 110:165afa46840b 318 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto 110:165afa46840b 319 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto 110:165afa46840b 320 /**
Kojto 110:165afa46840b 321 * @}
Kojto 110:165afa46840b 322 */
Kojto 110:165afa46840b 323
Kojto 110:165afa46840b 324 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
Kojto 110:165afa46840b 325 * @{
Kojto 110:165afa46840b 326 */
Kojto 110:165afa46840b 327 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 328 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto 110:165afa46840b 329 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
Kojto 110:165afa46840b 330 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
Kojto 110:165afa46840b 331 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto 110:165afa46840b 332 /**
Kojto 110:165afa46840b 333 * @}
Kojto 110:165afa46840b 334 */
Kojto 110:165afa46840b 335
Kojto 110:165afa46840b 336 /** @defgroup RCC_Interrupt Interrupts
Kojto 110:165afa46840b 337 * @{
Kojto 110:165afa46840b 338 */
Kojto 110:165afa46840b 339 #define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto 110:165afa46840b 340 #define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto 110:165afa46840b 341 #define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto 110:165afa46840b 342 #define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto 110:165afa46840b 343 #define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto 110:165afa46840b 344 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto 110:165afa46840b 345 #define RCC_IT_CSS ((uint8_t)0x80)
Kojto 110:165afa46840b 346 /**
Kojto 110:165afa46840b 347 * @}
Kojto 110:165afa46840b 348 */
Kojto 110:165afa46840b 349
Kojto 110:165afa46840b 350 /** @defgroup RCC_Flag Flags
Kojto 110:165afa46840b 351 * Elements values convention: 0XXYYYYYb
Kojto 110:165afa46840b 352 * - YYYYY : Flag position in the register
Kojto 110:165afa46840b 353 * - 0XX : Register index
Kojto 110:165afa46840b 354 * - 01: CR register
Kojto 110:165afa46840b 355 * - 10: BDCR register
Kojto 110:165afa46840b 356 * - 11: CSR register
Kojto 110:165afa46840b 357 * @{
Kojto 110:165afa46840b 358 */
Kojto 110:165afa46840b 359 /* Flags in the CR register */
Kojto 110:165afa46840b 360 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto 110:165afa46840b 361 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto 110:165afa46840b 362 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto 110:165afa46840b 363 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto 110:165afa46840b 364
Kojto 110:165afa46840b 365 /* Flags in the BDCR register */
Kojto 110:165afa46840b 366 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto 110:165afa46840b 367
Kojto 110:165afa46840b 368 /* Flags in the CSR register */
Kojto 110:165afa46840b 369 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto 110:165afa46840b 370 #define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto 110:165afa46840b 371 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto 110:165afa46840b 372 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto 110:165afa46840b 373 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto 110:165afa46840b 374 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto 110:165afa46840b 375 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto 110:165afa46840b 376 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto 110:165afa46840b 377 /**
Kojto 110:165afa46840b 378 * @}
Kojto 110:165afa46840b 379 */
Kojto 110:165afa46840b 380
Kojto 110:165afa46840b 381 /**
Kojto 110:165afa46840b 382 * @}
Kojto 110:165afa46840b 383 */
Kojto 110:165afa46840b 384
Kojto 110:165afa46840b 385 /* Exported macro ------------------------------------------------------------*/
Kojto 110:165afa46840b 386 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 110:165afa46840b 387 * @{
Kojto 110:165afa46840b 388 */
Kojto 110:165afa46840b 389
Kojto 110:165afa46840b 390 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 110:165afa46840b 391 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 110:165afa46840b 392 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 110:165afa46840b 393 * is disabled and the application software has to enable this clock before
Kojto 110:165afa46840b 394 * using it.
Kojto 110:165afa46840b 395 * @{
Kojto 110:165afa46840b 396 */
Kojto 110:165afa46840b 397 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 110:165afa46840b 398 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 399 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 110:165afa46840b 400 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 401 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 110:165afa46840b 402 UNUSED(tmpreg); \
Kojto 110:165afa46840b 403 } while(0)
Kojto 110:165afa46840b 404 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 110:165afa46840b 405 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 406 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 110:165afa46840b 407 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 408 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 110:165afa46840b 409 UNUSED(tmpreg); \
Kojto 110:165afa46840b 410 } while(0)
Kojto 110:165afa46840b 411 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 110:165afa46840b 412 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 413 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 110:165afa46840b 414 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 415 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 110:165afa46840b 416 UNUSED(tmpreg); \
Kojto 110:165afa46840b 417 } while(0)
Kojto 110:165afa46840b 418 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 110:165afa46840b 419 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 420 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 110:165afa46840b 421 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 422 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 110:165afa46840b 423 UNUSED(tmpreg); \
Kojto 110:165afa46840b 424 } while(0)
Kojto 110:165afa46840b 425 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 110:165afa46840b 426 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 427 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 110:165afa46840b 428 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 429 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 110:165afa46840b 430 UNUSED(tmpreg); \
Kojto 110:165afa46840b 431 } while(0)
Kojto 110:165afa46840b 432 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 110:165afa46840b 433 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 434 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 110:165afa46840b 435 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 436 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 110:165afa46840b 437 UNUSED(tmpreg); \
Kojto 110:165afa46840b 438 } while(0)
Kojto 110:165afa46840b 439
Kojto 110:165afa46840b 440 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 110:165afa46840b 441 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 110:165afa46840b 442 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 110:165afa46840b 443 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 110:165afa46840b 444 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 110:165afa46840b 445 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 110:165afa46840b 446
Kojto 110:165afa46840b 447 /**
Kojto 110:165afa46840b 448 * @}
Kojto 110:165afa46840b 449 */
Kojto 110:165afa46840b 450
Kojto 110:165afa46840b 451 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 110:165afa46840b 452 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 110:165afa46840b 453 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 110:165afa46840b 454 * is disabled and the application software has to enable this clock before
Kojto 110:165afa46840b 455 * using it.
Kojto 110:165afa46840b 456 * @{
Kojto 110:165afa46840b 457 */
Kojto 110:165afa46840b 458 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 110:165afa46840b 459 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 460 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 110:165afa46840b 461 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 462 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 110:165afa46840b 463 UNUSED(tmpreg); \
Kojto 110:165afa46840b 464 } while(0)
Kojto 110:165afa46840b 465 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 110:165afa46840b 466 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 467 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 110:165afa46840b 468 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 469 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 110:165afa46840b 470 UNUSED(tmpreg); \
Kojto 110:165afa46840b 471 } while(0)
Kojto 110:165afa46840b 472 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 110:165afa46840b 473 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 474 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 110:165afa46840b 475 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 476 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 110:165afa46840b 477 UNUSED(tmpreg); \
Kojto 110:165afa46840b 478 } while(0)
Kojto 110:165afa46840b 479 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 110:165afa46840b 480 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 481 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 110:165afa46840b 482 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 483 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 110:165afa46840b 484 UNUSED(tmpreg); \
Kojto 110:165afa46840b 485 } while(0)
Kojto 110:165afa46840b 486 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 110:165afa46840b 487 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 110:165afa46840b 489 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 110:165afa46840b 491 UNUSED(tmpreg); \
Kojto 110:165afa46840b 492 } while(0)
Kojto 110:165afa46840b 493 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 110:165afa46840b 494 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 110:165afa46840b 496 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 110:165afa46840b 498 UNUSED(tmpreg); \
Kojto 110:165afa46840b 499 } while(0)
Kojto 110:165afa46840b 500 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 110:165afa46840b 501 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 110:165afa46840b 503 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 110:165afa46840b 505 UNUSED(tmpreg); \
Kojto 110:165afa46840b 506 } while(0)
Kojto 110:165afa46840b 507
Kojto 110:165afa46840b 508 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 110:165afa46840b 509 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 110:165afa46840b 510 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 110:165afa46840b 511 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 110:165afa46840b 512 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 110:165afa46840b 513 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 110:165afa46840b 514 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 110:165afa46840b 515 /**
Kojto 110:165afa46840b 516 * @}
Kojto 110:165afa46840b 517 */
Kojto 110:165afa46840b 518
Kojto 110:165afa46840b 519 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 110:165afa46840b 520 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 110:165afa46840b 521 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 110:165afa46840b 522 * is disabled and the application software has to enable this clock before
Kojto 110:165afa46840b 523 * using it.
Kojto 110:165afa46840b 524 * @{
Kojto 110:165afa46840b 525 */
Kojto 110:165afa46840b 526 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 110:165afa46840b 527 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 528 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 110:165afa46840b 529 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 530 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 110:165afa46840b 531 UNUSED(tmpreg); \
Kojto 110:165afa46840b 532 } while(0)
Kojto 110:165afa46840b 533 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 110:165afa46840b 534 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 110:165afa46840b 536 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 110:165afa46840b 538 UNUSED(tmpreg); \
Kojto 110:165afa46840b 539 } while(0)
Kojto 110:165afa46840b 540 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 110:165afa46840b 541 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 110:165afa46840b 543 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 110:165afa46840b 545 UNUSED(tmpreg); \
Kojto 110:165afa46840b 546 } while(0)
Kojto 110:165afa46840b 547 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 110:165afa46840b 548 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 549 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 110:165afa46840b 550 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 551 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 110:165afa46840b 552 UNUSED(tmpreg); \
Kojto 110:165afa46840b 553 } while(0)
Kojto 110:165afa46840b 554 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 110:165afa46840b 555 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 556 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 110:165afa46840b 557 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 558 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 110:165afa46840b 559 UNUSED(tmpreg); \
Kojto 110:165afa46840b 560 } while(0)
Kojto 110:165afa46840b 561 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 110:165afa46840b 562 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 563 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 110:165afa46840b 564 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 565 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 110:165afa46840b 566 UNUSED(tmpreg); \
Kojto 110:165afa46840b 567 } while(0)
Kojto 110:165afa46840b 568 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 110:165afa46840b 569 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 110:165afa46840b 571 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 110:165afa46840b 573 UNUSED(tmpreg); \
Kojto 110:165afa46840b 574 } while(0)
Kojto 110:165afa46840b 575 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 110:165afa46840b 576 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 577 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 110:165afa46840b 578 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 579 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 110:165afa46840b 580 UNUSED(tmpreg); \
Kojto 110:165afa46840b 581 } while(0)
Kojto 110:165afa46840b 582
Kojto 110:165afa46840b 583 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 110:165afa46840b 584 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 110:165afa46840b 585 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 110:165afa46840b 586 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 110:165afa46840b 587 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 110:165afa46840b 588 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 110:165afa46840b 589 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 110:165afa46840b 590 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 110:165afa46840b 591 /**
Kojto 110:165afa46840b 592 * @}
Kojto 110:165afa46840b 593 */
Kojto 110:165afa46840b 594
Kojto 110:165afa46840b 595 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 110:165afa46840b 596 * @brief Force or release AHB1 peripheral reset.
Kojto 110:165afa46840b 597 * @{
Kojto 110:165afa46840b 598 */
Kojto 110:165afa46840b 599 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto 110:165afa46840b 600 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 110:165afa46840b 601 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 110:165afa46840b 602 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 110:165afa46840b 603 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 110:165afa46840b 604 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 110:165afa46840b 605 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Kojto 110:165afa46840b 606
Kojto 110:165afa46840b 607 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto 110:165afa46840b 608 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 110:165afa46840b 609 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 110:165afa46840b 610 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 110:165afa46840b 611 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 110:165afa46840b 612 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 110:165afa46840b 613 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 110:165afa46840b 614 /**
Kojto 110:165afa46840b 615 * @}
Kojto 110:165afa46840b 616 */
Kojto 110:165afa46840b 617
Kojto 110:165afa46840b 618 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 110:165afa46840b 619 * @brief Force or release APB1 peripheral reset.
Kojto 110:165afa46840b 620 * @{
Kojto 110:165afa46840b 621 */
Kojto 110:165afa46840b 622 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 110:165afa46840b 623 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 110:165afa46840b 624 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 110:165afa46840b 625 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 110:165afa46840b 626 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 110:165afa46840b 627 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 110:165afa46840b 628 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 110:165afa46840b 629 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 110:165afa46840b 630
Kojto 110:165afa46840b 631 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 110:165afa46840b 632 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 110:165afa46840b 633 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 110:165afa46840b 634 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 110:165afa46840b 635 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 110:165afa46840b 636 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 110:165afa46840b 637 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 110:165afa46840b 638 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 110:165afa46840b 639 /**
Kojto 110:165afa46840b 640 * @}
Kojto 110:165afa46840b 641 */
Kojto 110:165afa46840b 642
Kojto 110:165afa46840b 643 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 110:165afa46840b 644 * @brief Force or release APB2 peripheral reset.
Kojto 110:165afa46840b 645 * @{
Kojto 110:165afa46840b 646 */
Kojto 110:165afa46840b 647 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 110:165afa46840b 648 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 110:165afa46840b 649 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 110:165afa46840b 650 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 110:165afa46840b 651 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 110:165afa46840b 652 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 110:165afa46840b 653 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 110:165afa46840b 654 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 110:165afa46840b 655 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 110:165afa46840b 656
Kojto 110:165afa46840b 657 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 110:165afa46840b 658 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 110:165afa46840b 659 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 110:165afa46840b 660 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 110:165afa46840b 661 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 110:165afa46840b 662 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 110:165afa46840b 663 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 110:165afa46840b 664 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 110:165afa46840b 665 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 110:165afa46840b 666 /**
Kojto 110:165afa46840b 667 * @}
Kojto 110:165afa46840b 668 */
Kojto 110:165afa46840b 669
Kojto 110:165afa46840b 670 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 110:165afa46840b 671 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 110:165afa46840b 672 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 110:165afa46840b 673 * power consumption.
Kojto 110:165afa46840b 674 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 110:165afa46840b 675 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 110:165afa46840b 676 * @{
Kojto 110:165afa46840b 677 */
Kojto 110:165afa46840b 678 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 110:165afa46840b 679 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 110:165afa46840b 680 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 110:165afa46840b 681 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 110:165afa46840b 682 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 110:165afa46840b 683 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Kojto 110:165afa46840b 684
Kojto 110:165afa46840b 685 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 110:165afa46840b 686 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 110:165afa46840b 687 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 110:165afa46840b 688 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 110:165afa46840b 689 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 110:165afa46840b 690 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 110:165afa46840b 691 /**
Kojto 110:165afa46840b 692 * @}
Kojto 110:165afa46840b 693 */
Kojto 110:165afa46840b 694
Kojto 110:165afa46840b 695 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 110:165afa46840b 696 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 110:165afa46840b 697 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 110:165afa46840b 698 * power consumption.
Kojto 110:165afa46840b 699 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 110:165afa46840b 700 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 110:165afa46840b 701 * @{
Kojto 110:165afa46840b 702 */
Kojto 110:165afa46840b 703 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 110:165afa46840b 704 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 110:165afa46840b 705 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 110:165afa46840b 706 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 110:165afa46840b 707 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 110:165afa46840b 708 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 110:165afa46840b 709 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
Kojto 110:165afa46840b 710
Kojto 110:165afa46840b 711 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 110:165afa46840b 712 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 110:165afa46840b 713 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 110:165afa46840b 714 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 110:165afa46840b 715 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 110:165afa46840b 716 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 110:165afa46840b 717 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 110:165afa46840b 718 /**
Kojto 110:165afa46840b 719 * @}
Kojto 110:165afa46840b 720 */
Kojto 110:165afa46840b 721
Kojto 110:165afa46840b 722 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 110:165afa46840b 723 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 110:165afa46840b 724 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 110:165afa46840b 725 * power consumption.
Kojto 110:165afa46840b 726 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 110:165afa46840b 727 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 110:165afa46840b 728 * @{
Kojto 110:165afa46840b 729 */
Kojto 110:165afa46840b 730 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 110:165afa46840b 731 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 110:165afa46840b 732 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 110:165afa46840b 733 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 110:165afa46840b 734 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 110:165afa46840b 735 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 110:165afa46840b 736 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 110:165afa46840b 737 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Kojto 110:165afa46840b 738
Kojto 110:165afa46840b 739 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 110:165afa46840b 740 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 110:165afa46840b 741 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 110:165afa46840b 742 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 110:165afa46840b 743 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 110:165afa46840b 744 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 110:165afa46840b 745 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 110:165afa46840b 746 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 110:165afa46840b 747 /**
Kojto 110:165afa46840b 748 * @}
Kojto 110:165afa46840b 749 */
Kojto 110:165afa46840b 750
Kojto 110:165afa46840b 751 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 110:165afa46840b 752 * @{
Kojto 110:165afa46840b 753 */
Kojto 110:165afa46840b 754
Kojto 110:165afa46840b 755 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 110:165afa46840b 756 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 110:165afa46840b 757 * It is used (enabled by hardware) as system clock source after startup
Kojto 110:165afa46840b 758 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
Kojto 110:165afa46840b 759 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 110:165afa46840b 760 * Security System CSS is enabled).
Kojto 110:165afa46840b 761 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 110:165afa46840b 762 * you have to select another source of the system clock then stop the HSI.
Kojto 110:165afa46840b 763 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 110:165afa46840b 764 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 110:165afa46840b 765 * system clock source.
Kojto 110:165afa46840b 766 * This parameter can be: ENABLE or DISABLE.
Kojto 110:165afa46840b 767 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 110:165afa46840b 768 * clock cycles.
Kojto 110:165afa46840b 769 */
Kojto 110:165afa46840b 770 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 110:165afa46840b 771 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
Kojto 110:165afa46840b 772
Kojto 110:165afa46840b 773 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 110:165afa46840b 774 * @note The calibration is used to compensate for the variations in voltage
Kojto 110:165afa46840b 775 * and temperature that influence the frequency of the internal HSI RC.
Kojto 110:165afa46840b 776 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 110:165afa46840b 777 * This parameter must be a number between 0 and 0x1F.
Kojto 110:165afa46840b 778 */
Kojto 110:165afa46840b 779 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Kojto 110:165afa46840b 780 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 110:165afa46840b 781 /**
Kojto 110:165afa46840b 782 * @}
Kojto 110:165afa46840b 783 */
Kojto 110:165afa46840b 784
Kojto 110:165afa46840b 785 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 110:165afa46840b 786 * @{
Kojto 110:165afa46840b 787 */
Kojto 110:165afa46840b 788
Kojto 110:165afa46840b 789 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 110:165afa46840b 790 * @note After enabling the LSI, the application software should wait on
Kojto 110:165afa46840b 791 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 110:165afa46840b 792 * be used to clock the IWDG and/or the RTC.
Kojto 110:165afa46840b 793 * @note LSI can not be disabled if the IWDG is running.
Kojto 110:165afa46840b 794 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 110:165afa46840b 795 * clock cycles.
Kojto 110:165afa46840b 796 */
Kojto 110:165afa46840b 797 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 110:165afa46840b 798 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 110:165afa46840b 799 /**
Kojto 110:165afa46840b 800 * @}
Kojto 110:165afa46840b 801 */
Kojto 110:165afa46840b 802
Kojto 110:165afa46840b 803 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 110:165afa46840b 804 * @{
Kojto 110:165afa46840b 805 */
Kojto 110:165afa46840b 806
Kojto 110:165afa46840b 807 /**
Kojto 110:165afa46840b 808 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 110:165afa46840b 809 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 110:165afa46840b 810 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Kojto 110:165afa46840b 811 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 110:165afa46840b 812 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 110:165afa46840b 813 * is stable and can be used to clock the PLL and/or system clock.
Kojto 110:165afa46840b 814 * @note HSE state can not be changed if it is used directly or through the
Kojto 110:165afa46840b 815 * PLL as system clock. In this case, you have to select another source
Kojto 110:165afa46840b 816 * of the system clock then change the HSE state (ex. disable it).
Kojto 110:165afa46840b 817 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 110:165afa46840b 818 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 110:165afa46840b 819 * was previously enabled you have to enable it again after calling this
Kojto 110:165afa46840b 820 * function.
Kojto 110:165afa46840b 821 * @param __STATE__: specifies the new state of the HSE.
Kojto 110:165afa46840b 822 * This parameter can be one of the following values:
Kojto 110:165afa46840b 823 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 110:165afa46840b 824 * 6 HSE oscillator clock cycles.
Kojto 110:165afa46840b 825 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto 110:165afa46840b 826 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto 110:165afa46840b 827 */
Kojto 110:165afa46840b 828 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 110:165afa46840b 829 /**
Kojto 110:165afa46840b 830 * @}
Kojto 110:165afa46840b 831 */
Kojto 110:165afa46840b 832
Kojto 110:165afa46840b 833 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 110:165afa46840b 834 * @{
Kojto 110:165afa46840b 835 */
Kojto 110:165afa46840b 836
Kojto 110:165afa46840b 837 /**
Kojto 110:165afa46840b 838 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 110:165afa46840b 839 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 110:165afa46840b 840 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto 110:165afa46840b 841 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 110:165afa46840b 842 * this domain after reset, you have to enable write access using
Kojto 110:165afa46840b 843 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 110:165afa46840b 844 * (to be done once after reset).
Kojto 110:165afa46840b 845 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 110:165afa46840b 846 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 110:165afa46840b 847 * is stable and can be used to clock the RTC.
Kojto 110:165afa46840b 848 * @param __STATE__: specifies the new state of the LSE.
Kojto 110:165afa46840b 849 * This parameter can be one of the following values:
Kojto 110:165afa46840b 850 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 110:165afa46840b 851 * 6 LSE oscillator clock cycles.
Kojto 110:165afa46840b 852 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto 110:165afa46840b 853 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto 110:165afa46840b 854 */
Kojto 110:165afa46840b 855 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 110:165afa46840b 856
Kojto 110:165afa46840b 857 /**
Kojto 110:165afa46840b 858 * @}
Kojto 110:165afa46840b 859 */
Kojto 110:165afa46840b 860
Kojto 110:165afa46840b 861 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 110:165afa46840b 862 * @{
Kojto 110:165afa46840b 863 */
Kojto 110:165afa46840b 864
Kojto 110:165afa46840b 865 /** @brief Macros to enable or disable the RTC clock.
Kojto 110:165afa46840b 866 * @note These macros must be used only after the RTC clock source was selected.
Kojto 110:165afa46840b 867 */
Kojto 110:165afa46840b 868 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 110:165afa46840b 869 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Kojto 110:165afa46840b 870
Kojto 110:165afa46840b 871 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 110:165afa46840b 872 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 110:165afa46840b 873 * access is denied to this domain after reset, you have to enable write
Kojto 110:165afa46840b 874 * access using the Power Backup Access macro before to configure
Kojto 110:165afa46840b 875 * the RTC clock source (to be done once after reset).
Kojto 110:165afa46840b 876 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 110:165afa46840b 877 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 110:165afa46840b 878 * a Power On Reset (POR).
Kojto 110:165afa46840b 879 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 110:165afa46840b 880 * This parameter can be one of the following values:
Kojto 110:165afa46840b 881 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto 110:165afa46840b 882 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto 110:165afa46840b 883 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto 110:165afa46840b 884 * as RTC clock, where x:[2,31]
Kojto 110:165afa46840b 885 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 110:165afa46840b 886 * work in STOP and STANDBY modes, and can be used as wake-up source.
Kojto 110:165afa46840b 887 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 110:165afa46840b 888 * cannot be used in STOP and STANDBY modes.
Kojto 110:165afa46840b 889 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 110:165afa46840b 890 * RTC clock source).
Kojto 110:165afa46840b 891 */
Kojto 110:165afa46840b 892 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 110:165afa46840b 893 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto 110:165afa46840b 894
Kojto 110:165afa46840b 895 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 110:165afa46840b 896 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto 110:165afa46840b 897 } while (0)
Kojto 110:165afa46840b 898
Kojto 110:165afa46840b 899 /** @brief Macros to force or release the Backup domain reset.
Kojto 110:165afa46840b 900 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 110:165afa46840b 901 * and the RTC clock source selection in RCC_CSR register.
Kojto 110:165afa46840b 902 * @note The BKPSRAM is not affected by this reset.
Kojto 110:165afa46840b 903 */
Kojto 110:165afa46840b 904 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 110:165afa46840b 905 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 110:165afa46840b 906 /**
Kojto 110:165afa46840b 907 * @}
Kojto 110:165afa46840b 908 */
Kojto 110:165afa46840b 909
Kojto 110:165afa46840b 910 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 110:165afa46840b 911 * @{
Kojto 110:165afa46840b 912 */
Kojto 110:165afa46840b 913
Kojto 110:165afa46840b 914 /** @brief Macros to enable or disable the main PLL.
Kojto 110:165afa46840b 915 * @note After enabling the main PLL, the application software should wait on
Kojto 110:165afa46840b 916 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 110:165afa46840b 917 * be used as system clock source.
Kojto 110:165afa46840b 918 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 110:165afa46840b 919 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 110:165afa46840b 920 */
Kojto 110:165afa46840b 921 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 110:165afa46840b 922 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Kojto 110:165afa46840b 923
Kojto 110:165afa46840b 924 /** @brief Macro to configure the PLL clock source.
Kojto 110:165afa46840b 925 * @note This function must be used only when the main PLL is disabled.
Kojto 110:165afa46840b 926 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 110:165afa46840b 927 * This parameter can be one of the following values:
Kojto 110:165afa46840b 928 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 110:165afa46840b 929 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 110:165afa46840b 930 *
Kojto 110:165afa46840b 931 */
Kojto 110:165afa46840b 932 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 110:165afa46840b 933
Kojto 110:165afa46840b 934 /** @brief Macro to configure the PLL multiplication factor.
Kojto 110:165afa46840b 935 * @note This function must be used only when the main PLL is disabled.
Kojto 110:165afa46840b 936 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 110:165afa46840b 937 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 110:165afa46840b 938 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 110:165afa46840b 939 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 110:165afa46840b 940 * of 2 MHz to limit PLL jitter.
Kojto 110:165afa46840b 941 *
Kojto 110:165afa46840b 942 */
Kojto 110:165afa46840b 943 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 110:165afa46840b 944 /**
Kojto 110:165afa46840b 945 * @}
Kojto 110:165afa46840b 946 */
Kojto 110:165afa46840b 947
Kojto 110:165afa46840b 948 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 110:165afa46840b 949 * @{
Kojto 110:165afa46840b 950 */
Kojto 110:165afa46840b 951 /**
Kojto 110:165afa46840b 952 * @brief Macro to configure the system clock source.
Kojto 110:165afa46840b 953 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 110:165afa46840b 954 * This parameter can be one of the following values:
Kojto 110:165afa46840b 955 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 110:165afa46840b 956 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 110:165afa46840b 957 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 110:165afa46840b 958 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto 110:165afa46840b 959 */
Kojto 110:165afa46840b 960 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto 110:165afa46840b 961
Kojto 110:165afa46840b 962 /** @brief Macro to get the clock source used as system clock.
Kojto 110:165afa46840b 963 * @retval The clock source used as system clock. The returned value can be one
Kojto 110:165afa46840b 964 * of the following:
Kojto 110:165afa46840b 965 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 110:165afa46840b 966 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 110:165afa46840b 967 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 110:165afa46840b 968 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
Kojto 110:165afa46840b 969 */
Kojto 110:165afa46840b 970 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 110:165afa46840b 971
Kojto 110:165afa46840b 972 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 110:165afa46840b 973 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 110:165afa46840b 974 * of the following:
Kojto 110:165afa46840b 975 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 110:165afa46840b 976 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 110:165afa46840b 977 */
Kojto 110:165afa46840b 978 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 110:165afa46840b 979 /**
Kojto 110:165afa46840b 980 * @}
Kojto 110:165afa46840b 981 */
Kojto 110:165afa46840b 982
Kojto 110:165afa46840b 983 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 110:165afa46840b 984 * @{
Kojto 110:165afa46840b 985 */
Kojto 110:165afa46840b 986
Kojto 110:165afa46840b 987 /** @brief Macro to configure the MCO1 clock.
Kojto 110:165afa46840b 988 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 989 * This parameter can be one of the following values:
Kojto 110:165afa46840b 990 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto 110:165afa46840b 991 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto 110:165afa46840b 992 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto 110:165afa46840b 993 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto 110:165afa46840b 994 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 995 * This parameter can be one of the following values:
Kojto 110:165afa46840b 996 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 997 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 998 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 999 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1000 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 110:165afa46840b 1001 */
Kojto 110:165afa46840b 1002
Kojto 110:165afa46840b 1003 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 110:165afa46840b 1004 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 110:165afa46840b 1005
Kojto 110:165afa46840b 1006 /** @brief Macro to configure the MCO2 clock.
Kojto 110:165afa46840b 1007 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 1008 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1009 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto 110:165afa46840b 1010 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto 110:165afa46840b 1011 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto 110:165afa46840b 1012 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto 110:165afa46840b 1013 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto 110:165afa46840b 1014 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 1015 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1016 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 1017 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 1018 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 1019 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1020 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 110:165afa46840b 1021 * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
Kojto 110:165afa46840b 1022 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto 110:165afa46840b 1023 */
Kojto 110:165afa46840b 1024
Kojto 110:165afa46840b 1025 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 110:165afa46840b 1026 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ | (__MCODIV__ << 3)));
Kojto 110:165afa46840b 1027 /**
Kojto 110:165afa46840b 1028 * @}
Kojto 110:165afa46840b 1029 */
Kojto 110:165afa46840b 1030
Kojto 110:165afa46840b 1031 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 110:165afa46840b 1032 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 110:165afa46840b 1033 * @{
Kojto 110:165afa46840b 1034 */
Kojto 110:165afa46840b 1035
Kojto 110:165afa46840b 1036 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 110:165afa46840b 1037 * the selected interrupts).
Kojto 110:165afa46840b 1038 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 110:165afa46840b 1039 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1040 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 110:165afa46840b 1041 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 110:165afa46840b 1042 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 110:165afa46840b 1043 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 110:165afa46840b 1044 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 110:165afa46840b 1045 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 110:165afa46840b 1046 */
Kojto 110:165afa46840b 1047 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 110:165afa46840b 1048
Kojto 110:165afa46840b 1049 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 110:165afa46840b 1050 * the selected interrupts).
Kojto 110:165afa46840b 1051 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 110:165afa46840b 1052 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1053 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 110:165afa46840b 1054 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 110:165afa46840b 1055 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 110:165afa46840b 1056 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 110:165afa46840b 1057 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 110:165afa46840b 1058 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 110:165afa46840b 1059 */
Kojto 110:165afa46840b 1060 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 110:165afa46840b 1061
Kojto 110:165afa46840b 1062 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 110:165afa46840b 1063 * bits to clear the selected interrupt pending bits.
Kojto 110:165afa46840b 1064 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 110:165afa46840b 1065 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1066 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 110:165afa46840b 1067 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 110:165afa46840b 1068 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 110:165afa46840b 1069 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 110:165afa46840b 1070 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 110:165afa46840b 1071 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 110:165afa46840b 1072 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 110:165afa46840b 1073 */
Kojto 110:165afa46840b 1074 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto 110:165afa46840b 1075
Kojto 110:165afa46840b 1076 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 110:165afa46840b 1077 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 110:165afa46840b 1078 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1079 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 110:165afa46840b 1080 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 110:165afa46840b 1081 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 110:165afa46840b 1082 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 110:165afa46840b 1083 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 110:165afa46840b 1084 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 110:165afa46840b 1085 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 110:165afa46840b 1086 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 110:165afa46840b 1087 */
Kojto 110:165afa46840b 1088 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 110:165afa46840b 1089
Kojto 110:165afa46840b 1090 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto 110:165afa46840b 1091 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 110:165afa46840b 1092 */
Kojto 110:165afa46840b 1093 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 110:165afa46840b 1094
Kojto 110:165afa46840b 1095 /** @brief Check RCC flag is set or not.
Kojto 110:165afa46840b 1096 * @param __FLAG__: specifies the flag to check.
Kojto 110:165afa46840b 1097 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1098 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto 110:165afa46840b 1099 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto 110:165afa46840b 1100 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto 110:165afa46840b 1101 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto 110:165afa46840b 1102 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto 110:165afa46840b 1103 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto 110:165afa46840b 1104 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto 110:165afa46840b 1105 * @arg RCC_FLAG_PINRST: Pin reset.
Kojto 110:165afa46840b 1106 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto 110:165afa46840b 1107 * @arg RCC_FLAG_SFTRST: Software reset.
Kojto 110:165afa46840b 1108 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto 110:165afa46840b 1109 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto 110:165afa46840b 1110 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto 110:165afa46840b 1111 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 110:165afa46840b 1112 */
Kojto 110:165afa46840b 1113 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 110:165afa46840b 1114 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto 110:165afa46840b 1115
Kojto 110:165afa46840b 1116 /**
Kojto 110:165afa46840b 1117 * @}
Kojto 110:165afa46840b 1118 */
Kojto 110:165afa46840b 1119
Kojto 110:165afa46840b 1120 /**
Kojto 110:165afa46840b 1121 * @}
Kojto 110:165afa46840b 1122 */
Kojto 110:165afa46840b 1123
Kojto 110:165afa46840b 1124 /* Exported functions --------------------------------------------------------*/
Kojto 110:165afa46840b 1125 /** @addtogroup RCC_Exported_Functions
Kojto 110:165afa46840b 1126 * @{
Kojto 110:165afa46840b 1127 */
Kojto 110:165afa46840b 1128
Kojto 110:165afa46840b 1129 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 110:165afa46840b 1130 * @{
Kojto 110:165afa46840b 1131 */
Kojto 110:165afa46840b 1132 /* Initialization and de-initialization functions ******************************/
Kojto 110:165afa46840b 1133 void HAL_RCC_DeInit(void);
Kojto 110:165afa46840b 1134 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 110:165afa46840b 1135 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 110:165afa46840b 1136 /**
Kojto 110:165afa46840b 1137 * @}
Kojto 110:165afa46840b 1138 */
Kojto 110:165afa46840b 1139
Kojto 110:165afa46840b 1140 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 110:165afa46840b 1141 * @{
Kojto 110:165afa46840b 1142 */
Kojto 110:165afa46840b 1143 /* Peripheral Control functions ************************************************/
Kojto 110:165afa46840b 1144 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 110:165afa46840b 1145 void HAL_RCC_EnableCSS(void);
Kojto 110:165afa46840b 1146 void HAL_RCC_DisableCSS(void);
Kojto 110:165afa46840b 1147 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 110:165afa46840b 1148 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 110:165afa46840b 1149 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 110:165afa46840b 1150 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 110:165afa46840b 1151 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 110:165afa46840b 1152 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 110:165afa46840b 1153
Kojto 110:165afa46840b 1154 /* CSS NMI IRQ handler */
Kojto 110:165afa46840b 1155 void HAL_RCC_NMI_IRQHandler(void);
Kojto 110:165afa46840b 1156
Kojto 110:165afa46840b 1157 /* User Callbacks in non blocking mode (IT mode) */
Kojto 110:165afa46840b 1158 void HAL_RCC_CSSCallback(void);
Kojto 110:165afa46840b 1159
Kojto 110:165afa46840b 1160 /**
Kojto 110:165afa46840b 1161 * @}
Kojto 110:165afa46840b 1162 */
Kojto 110:165afa46840b 1163
Kojto 110:165afa46840b 1164 /**
Kojto 110:165afa46840b 1165 * @}
Kojto 110:165afa46840b 1166 */
Kojto 110:165afa46840b 1167
Kojto 110:165afa46840b 1168 /* Private types -------------------------------------------------------------*/
Kojto 110:165afa46840b 1169 /* Private variables ---------------------------------------------------------*/
Kojto 110:165afa46840b 1170 /* Private constants ---------------------------------------------------------*/
Kojto 110:165afa46840b 1171 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 110:165afa46840b 1172 * @{
Kojto 110:165afa46840b 1173 */
Kojto 110:165afa46840b 1174
Kojto 110:165afa46840b 1175 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 110:165afa46840b 1176 * @brief RCC registers bit address in the alias region
Kojto 110:165afa46840b 1177 * @{
Kojto 110:165afa46840b 1178 */
Kojto 110:165afa46840b 1179 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 110:165afa46840b 1180 /* --- CR Register ---*/
Kojto 110:165afa46840b 1181 /* Alias word address of HSION bit */
Kojto 110:165afa46840b 1182 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 110:165afa46840b 1183 #define RCC_HSION_BIT_NUMBER 0x00
Kojto 110:165afa46840b 1184 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
Kojto 110:165afa46840b 1185 /* Alias word address of CSSON bit */
Kojto 110:165afa46840b 1186 #define RCC_CSSON_BIT_NUMBER 0x13
Kojto 110:165afa46840b 1187 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
Kojto 110:165afa46840b 1188 /* Alias word address of PLLON bit */
Kojto 110:165afa46840b 1189 #define RCC_PLLON_BIT_NUMBER 0x18
Kojto 110:165afa46840b 1190 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
Kojto 110:165afa46840b 1191
Kojto 110:165afa46840b 1192 /* --- BDCR Register ---*/
Kojto 110:165afa46840b 1193 /* Alias word address of RTCEN bit */
Kojto 110:165afa46840b 1194 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto 110:165afa46840b 1195 #define RCC_RTCEN_BIT_NUMBER 0x0F
Kojto 110:165afa46840b 1196 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
Kojto 110:165afa46840b 1197 /* Alias word address of BDRST bit */
Kojto 110:165afa46840b 1198 #define RCC_BDRST_BIT_NUMBER 0x10
Kojto 110:165afa46840b 1199 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
Kojto 110:165afa46840b 1200
Kojto 110:165afa46840b 1201 /* --- CSR Register ---*/
Kojto 110:165afa46840b 1202 /* Alias word address of LSION bit */
Kojto 110:165afa46840b 1203 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto 110:165afa46840b 1204 #define RCC_LSION_BIT_NUMBER 0x00
Kojto 110:165afa46840b 1205 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
Kojto 110:165afa46840b 1206
Kojto 110:165afa46840b 1207 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 110:165afa46840b 1208 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto 110:165afa46840b 1209
Kojto 110:165afa46840b 1210 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 110:165afa46840b 1211 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto 110:165afa46840b 1212
Kojto 110:165afa46840b 1213 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 110:165afa46840b 1214 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto 110:165afa46840b 1215
Kojto 110:165afa46840b 1216 /* BDCR register base address */
Kojto 110:165afa46840b 1217 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 110:165afa46840b 1218
Kojto 110:165afa46840b 1219 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 110:165afa46840b 1220 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 110:165afa46840b 1221
Kojto 110:165afa46840b 1222 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 110:165afa46840b 1223 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 110:165afa46840b 1224 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 110:165afa46840b 1225
Kojto 110:165afa46840b 1226 /**
Kojto 110:165afa46840b 1227 * @}
Kojto 110:165afa46840b 1228 */
Kojto 110:165afa46840b 1229
Kojto 110:165afa46840b 1230 /**
Kojto 110:165afa46840b 1231 * @}
Kojto 110:165afa46840b 1232 */
Kojto 110:165afa46840b 1233
Kojto 110:165afa46840b 1234 /* Private macros ------------------------------------------------------------*/
Kojto 110:165afa46840b 1235 /** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto 110:165afa46840b 1236 * @{
Kojto 110:165afa46840b 1237 */
Kojto 110:165afa46840b 1238
Kojto 110:165afa46840b 1239 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 110:165afa46840b 1240 * @{
Kojto 110:165afa46840b 1241 */
Kojto 110:165afa46840b 1242 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto 110:165afa46840b 1243
Kojto 110:165afa46840b 1244 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 110:165afa46840b 1245 ((HSE) == RCC_HSE_BYPASS))
Kojto 110:165afa46840b 1246
Kojto 110:165afa46840b 1247 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 110:165afa46840b 1248 ((LSE) == RCC_LSE_BYPASS))
Kojto 110:165afa46840b 1249
Kojto 110:165afa46840b 1250 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 110:165afa46840b 1251
Kojto 110:165afa46840b 1252 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 110:165afa46840b 1253
Kojto 110:165afa46840b 1254 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 110:165afa46840b 1255
Kojto 110:165afa46840b 1256 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 110:165afa46840b 1257 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 110:165afa46840b 1258
Kojto 110:165afa46840b 1259 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 110:165afa46840b 1260 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 110:165afa46840b 1261 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 110:165afa46840b 1262 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 110:165afa46840b 1263
Kojto 110:165afa46840b 1264 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 110:165afa46840b 1265
Kojto 110:165afa46840b 1266 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 110:165afa46840b 1267
Kojto 110:165afa46840b 1268 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
Kojto 110:165afa46840b 1269
Kojto 110:165afa46840b 1270 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto 110:165afa46840b 1271
Kojto 110:165afa46840b 1272 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 110:165afa46840b 1273 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 110:165afa46840b 1274 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 110:165afa46840b 1275 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 110:165afa46840b 1276 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 110:165afa46840b 1277
Kojto 110:165afa46840b 1278 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto 110:165afa46840b 1279
Kojto 110:165afa46840b 1280 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 110:165afa46840b 1281 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 110:165afa46840b 1282 ((PCLK) == RCC_HCLK_DIV16))
Kojto 110:165afa46840b 1283
Kojto 110:165afa46840b 1284 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 110:165afa46840b 1285
Kojto 110:165afa46840b 1286 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 110:165afa46840b 1287 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 110:165afa46840b 1288
Kojto 110:165afa46840b 1289 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 110:165afa46840b 1290 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 110:165afa46840b 1291 ((DIV) == RCC_MCODIV_5))
Kojto 110:165afa46840b 1292 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 110:165afa46840b 1293
Kojto 110:165afa46840b 1294 /**
Kojto 110:165afa46840b 1295 * @}
Kojto 110:165afa46840b 1296 */
Kojto 110:165afa46840b 1297
Kojto 110:165afa46840b 1298 /**
Kojto 110:165afa46840b 1299 * @}
Kojto 110:165afa46840b 1300 */
Kojto 110:165afa46840b 1301
Kojto 110:165afa46840b 1302 /**
Kojto 110:165afa46840b 1303 * @}
Kojto 110:165afa46840b 1304 */
Kojto 110:165afa46840b 1305
Kojto 110:165afa46840b 1306 /**
Kojto 110:165afa46840b 1307 * @}
Kojto 110:165afa46840b 1308 */
Kojto 110:165afa46840b 1309
Kojto 110:165afa46840b 1310 #ifdef __cplusplus
Kojto 110:165afa46840b 1311 }
Kojto 110:165afa46840b 1312 #endif
Kojto 110:165afa46840b 1313
Kojto 110:165afa46840b 1314 #endif /* __STM32F4xx_HAL_RCC_H */
Kojto 110:165afa46840b 1315
Kojto 110:165afa46840b 1316 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/