Jason Garner / ARM

same stuff from mbed trunk (LPC17xx.h, etc.) but nothing else

Dependents:   registers-example test test Tweeting_Machine_HelloWorld_WIZwiki-W750

same as the mbed trunk dated december 20th, 2012

(latest version is here: http://mbed.org/projects/libraries/svn/mbed/trunk/LPC1768/ARM)

core_cm3.h@0:f86e6135dcbc, 2012-12-21 (annotated)

Committer:
elevatorguy
Date:
Fri Dec 21 01:54:37 2012 +0000
Revision:
0:f86e6135dcbc
standard library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elevatorguy 0:f86e6135dcbc 1 /**************************************************************************//**
elevatorguy 0:f86e6135dcbc 2 * @file core_cm3.h
elevatorguy 0:f86e6135dcbc 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
elevatorguy 0:f86e6135dcbc 4 * @version V3.01
elevatorguy 0:f86e6135dcbc 5 * @date 06. March 2012
elevatorguy 0:f86e6135dcbc 6 *
elevatorguy 0:f86e6135dcbc 7 * @note
elevatorguy 0:f86e6135dcbc 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
elevatorguy 0:f86e6135dcbc 9 *
elevatorguy 0:f86e6135dcbc 10 * @par
elevatorguy 0:f86e6135dcbc 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
elevatorguy 0:f86e6135dcbc 12 * processor based microcontrollers. This file can be freely distributed
elevatorguy 0:f86e6135dcbc 13 * within development tools that are supporting such ARM based processors.
elevatorguy 0:f86e6135dcbc 14 *
elevatorguy 0:f86e6135dcbc 15 * @par
elevatorguy 0:f86e6135dcbc 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elevatorguy 0:f86e6135dcbc 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elevatorguy 0:f86e6135dcbc 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elevatorguy 0:f86e6135dcbc 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
elevatorguy 0:f86e6135dcbc 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elevatorguy 0:f86e6135dcbc 21 *
elevatorguy 0:f86e6135dcbc 22 ******************************************************************************/
elevatorguy 0:f86e6135dcbc 23 #if defined ( __ICCARM__ )
elevatorguy 0:f86e6135dcbc 24 #pragma system_include /* treat file as system include file for MISRA check */
elevatorguy 0:f86e6135dcbc 25 #endif
elevatorguy 0:f86e6135dcbc 26
elevatorguy 0:f86e6135dcbc 27 #ifdef __cplusplus
elevatorguy 0:f86e6135dcbc 28 extern "C" {
elevatorguy 0:f86e6135dcbc 29 #endif
elevatorguy 0:f86e6135dcbc 30
elevatorguy 0:f86e6135dcbc 31 #ifndef __CORE_CM3_H_GENERIC
elevatorguy 0:f86e6135dcbc 32 #define __CORE_CM3_H_GENERIC
elevatorguy 0:f86e6135dcbc 33
elevatorguy 0:f86e6135dcbc 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
elevatorguy 0:f86e6135dcbc 35 CMSIS violates the following MISRA-C:2004 rules:
elevatorguy 0:f86e6135dcbc 36
elevatorguy 0:f86e6135dcbc 37 \li Required Rule 8.5, object/function definition in header file.<br>
elevatorguy 0:f86e6135dcbc 38 Function definitions in header files are used to allow 'inlining'.
elevatorguy 0:f86e6135dcbc 39
elevatorguy 0:f86e6135dcbc 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
elevatorguy 0:f86e6135dcbc 41 Unions are used for effective representation of core registers.
elevatorguy 0:f86e6135dcbc 42
elevatorguy 0:f86e6135dcbc 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
elevatorguy 0:f86e6135dcbc 44 Function-like macros are used to allow more efficient code.
elevatorguy 0:f86e6135dcbc 45 */
elevatorguy 0:f86e6135dcbc 46
elevatorguy 0:f86e6135dcbc 47
elevatorguy 0:f86e6135dcbc 48 /*******************************************************************************
elevatorguy 0:f86e6135dcbc 49 * CMSIS definitions
elevatorguy 0:f86e6135dcbc 50 ******************************************************************************/
elevatorguy 0:f86e6135dcbc 51 /** \ingroup Cortex_M3
elevatorguy 0:f86e6135dcbc 52 @{
elevatorguy 0:f86e6135dcbc 53 */
elevatorguy 0:f86e6135dcbc 54
elevatorguy 0:f86e6135dcbc 55 /* CMSIS CM3 definitions */
elevatorguy 0:f86e6135dcbc 56 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
elevatorguy 0:f86e6135dcbc 57 #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
elevatorguy 0:f86e6135dcbc 58 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
elevatorguy 0:f86e6135dcbc 59 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
elevatorguy 0:f86e6135dcbc 60
elevatorguy 0:f86e6135dcbc 61 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
elevatorguy 0:f86e6135dcbc 62
elevatorguy 0:f86e6135dcbc 63
elevatorguy 0:f86e6135dcbc 64 #if defined ( __CC_ARM )
elevatorguy 0:f86e6135dcbc 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
elevatorguy 0:f86e6135dcbc 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
elevatorguy 0:f86e6135dcbc 67 #define __STATIC_INLINE static __inline
elevatorguy 0:f86e6135dcbc 68
elevatorguy 0:f86e6135dcbc 69 #elif defined ( __ICCARM__ )
elevatorguy 0:f86e6135dcbc 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
elevatorguy 0:f86e6135dcbc 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
elevatorguy 0:f86e6135dcbc 72 #define __STATIC_INLINE static inline
elevatorguy 0:f86e6135dcbc 73
elevatorguy 0:f86e6135dcbc 74 #elif defined ( __TMS470__ )
elevatorguy 0:f86e6135dcbc 75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
elevatorguy 0:f86e6135dcbc 76 #define __STATIC_INLINE static inline
elevatorguy 0:f86e6135dcbc 77
elevatorguy 0:f86e6135dcbc 78 #elif defined ( __GNUC__ )
elevatorguy 0:f86e6135dcbc 79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
elevatorguy 0:f86e6135dcbc 80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
elevatorguy 0:f86e6135dcbc 81 #define __STATIC_INLINE static inline
elevatorguy 0:f86e6135dcbc 82
elevatorguy 0:f86e6135dcbc 83 #elif defined ( __TASKING__ )
elevatorguy 0:f86e6135dcbc 84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
elevatorguy 0:f86e6135dcbc 85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
elevatorguy 0:f86e6135dcbc 86 #define __STATIC_INLINE static inline
elevatorguy 0:f86e6135dcbc 87
elevatorguy 0:f86e6135dcbc 88 #endif
elevatorguy 0:f86e6135dcbc 89
elevatorguy 0:f86e6135dcbc 90 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
elevatorguy 0:f86e6135dcbc 91 */
elevatorguy 0:f86e6135dcbc 92 #define __FPU_USED 0
elevatorguy 0:f86e6135dcbc 93
elevatorguy 0:f86e6135dcbc 94 #if defined ( __CC_ARM )
elevatorguy 0:f86e6135dcbc 95 #if defined __TARGET_FPU_VFP
elevatorguy 0:f86e6135dcbc 96 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elevatorguy 0:f86e6135dcbc 97 #endif
elevatorguy 0:f86e6135dcbc 98
elevatorguy 0:f86e6135dcbc 99 #elif defined ( __ICCARM__ )
elevatorguy 0:f86e6135dcbc 100 #if defined __ARMVFP__
elevatorguy 0:f86e6135dcbc 101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elevatorguy 0:f86e6135dcbc 102 #endif
elevatorguy 0:f86e6135dcbc 103
elevatorguy 0:f86e6135dcbc 104 #elif defined ( __TMS470__ )
elevatorguy 0:f86e6135dcbc 105 #if defined __TI__VFP_SUPPORT____
elevatorguy 0:f86e6135dcbc 106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elevatorguy 0:f86e6135dcbc 107 #endif
elevatorguy 0:f86e6135dcbc 108
elevatorguy 0:f86e6135dcbc 109 #elif defined ( __GNUC__ )
elevatorguy 0:f86e6135dcbc 110 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
elevatorguy 0:f86e6135dcbc 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
elevatorguy 0:f86e6135dcbc 112 #endif
elevatorguy 0:f86e6135dcbc 113
elevatorguy 0:f86e6135dcbc 114 #elif defined ( __TASKING__ )
elevatorguy 0:f86e6135dcbc 115 /* add preprocessor checks */
elevatorguy 0:f86e6135dcbc 116 #endif
elevatorguy 0:f86e6135dcbc 117
elevatorguy 0:f86e6135dcbc 118 #include <stdint.h> /* standard types definitions */
elevatorguy 0:f86e6135dcbc 119 #include <core_cmInstr.h> /* Core Instruction Access */
elevatorguy 0:f86e6135dcbc 120 #include <core_cmFunc.h> /* Core Function Access */
elevatorguy 0:f86e6135dcbc 121
elevatorguy 0:f86e6135dcbc 122 #endif /* __CORE_CM3_H_GENERIC */
elevatorguy 0:f86e6135dcbc 123
elevatorguy 0:f86e6135dcbc 124 #ifndef __CMSIS_GENERIC
elevatorguy 0:f86e6135dcbc 125
elevatorguy 0:f86e6135dcbc 126 #ifndef __CORE_CM3_H_DEPENDANT
elevatorguy 0:f86e6135dcbc 127 #define __CORE_CM3_H_DEPENDANT
elevatorguy 0:f86e6135dcbc 128
elevatorguy 0:f86e6135dcbc 129 /* check device defines and use defaults */
elevatorguy 0:f86e6135dcbc 130 #if defined __CHECK_DEVICE_DEFINES
elevatorguy 0:f86e6135dcbc 131 #ifndef __CM3_REV
elevatorguy 0:f86e6135dcbc 132 #define __CM3_REV 0x0200
elevatorguy 0:f86e6135dcbc 133 #warning "__CM3_REV not defined in device header file; using default!"
elevatorguy 0:f86e6135dcbc 134 #endif
elevatorguy 0:f86e6135dcbc 135
elevatorguy 0:f86e6135dcbc 136 #ifndef __MPU_PRESENT
elevatorguy 0:f86e6135dcbc 137 #define __MPU_PRESENT 0
elevatorguy 0:f86e6135dcbc 138 #warning "__MPU_PRESENT not defined in device header file; using default!"
elevatorguy 0:f86e6135dcbc 139 #endif
elevatorguy 0:f86e6135dcbc 140
elevatorguy 0:f86e6135dcbc 141 #ifndef __NVIC_PRIO_BITS
elevatorguy 0:f86e6135dcbc 142 #define __NVIC_PRIO_BITS 4
elevatorguy 0:f86e6135dcbc 143 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
elevatorguy 0:f86e6135dcbc 144 #endif
elevatorguy 0:f86e6135dcbc 145
elevatorguy 0:f86e6135dcbc 146 #ifndef __Vendor_SysTickConfig
elevatorguy 0:f86e6135dcbc 147 #define __Vendor_SysTickConfig 0
elevatorguy 0:f86e6135dcbc 148 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
elevatorguy 0:f86e6135dcbc 149 #endif
elevatorguy 0:f86e6135dcbc 150 #endif
elevatorguy 0:f86e6135dcbc 151
elevatorguy 0:f86e6135dcbc 152 /* IO definitions (access restrictions to peripheral registers) */
elevatorguy 0:f86e6135dcbc 153 /**
elevatorguy 0:f86e6135dcbc 154 \defgroup CMSIS_glob_defs CMSIS Global Defines
elevatorguy 0:f86e6135dcbc 155
elevatorguy 0:f86e6135dcbc 156 <strong>IO Type Qualifiers</strong> are used
elevatorguy 0:f86e6135dcbc 157 \li to specify the access to peripheral variables.
elevatorguy 0:f86e6135dcbc 158 \li for automatic generation of peripheral register debug information.
elevatorguy 0:f86e6135dcbc 159 */
elevatorguy 0:f86e6135dcbc 160 #ifdef __cplusplus
elevatorguy 0:f86e6135dcbc 161 #define __I volatile /*!< Defines 'read only' permissions */
elevatorguy 0:f86e6135dcbc 162 #else
elevatorguy 0:f86e6135dcbc 163 #define __I volatile const /*!< Defines 'read only' permissions */
elevatorguy 0:f86e6135dcbc 164 #endif
elevatorguy 0:f86e6135dcbc 165 #define __O volatile /*!< Defines 'write only' permissions */
elevatorguy 0:f86e6135dcbc 166 #define __IO volatile /*!< Defines 'read / write' permissions */
elevatorguy 0:f86e6135dcbc 167
elevatorguy 0:f86e6135dcbc 168 /*@} end of group Cortex_M3 */
elevatorguy 0:f86e6135dcbc 169
elevatorguy 0:f86e6135dcbc 170
elevatorguy 0:f86e6135dcbc 171
elevatorguy 0:f86e6135dcbc 172 /*******************************************************************************
elevatorguy 0:f86e6135dcbc 173 * Register Abstraction
elevatorguy 0:f86e6135dcbc 174 Core Register contain:
elevatorguy 0:f86e6135dcbc 175 - Core Register
elevatorguy 0:f86e6135dcbc 176 - Core NVIC Register
elevatorguy 0:f86e6135dcbc 177 - Core SCB Register
elevatorguy 0:f86e6135dcbc 178 - Core SysTick Register
elevatorguy 0:f86e6135dcbc 179 - Core Debug Register
elevatorguy 0:f86e6135dcbc 180 - Core MPU Register
elevatorguy 0:f86e6135dcbc 181 ******************************************************************************/
elevatorguy 0:f86e6135dcbc 182 /** \defgroup CMSIS_core_register Defines and Type Definitions
elevatorguy 0:f86e6135dcbc 183 \brief Type definitions and defines for Cortex-M processor based devices.
elevatorguy 0:f86e6135dcbc 184 */
elevatorguy 0:f86e6135dcbc 185
elevatorguy 0:f86e6135dcbc 186 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 187 \defgroup CMSIS_CORE Status and Control Registers
elevatorguy 0:f86e6135dcbc 188 \brief Core Register type definitions.
elevatorguy 0:f86e6135dcbc 189 @{
elevatorguy 0:f86e6135dcbc 190 */
elevatorguy 0:f86e6135dcbc 191
elevatorguy 0:f86e6135dcbc 192 /** \brief Union type to access the Application Program Status Register (APSR).
elevatorguy 0:f86e6135dcbc 193 */
elevatorguy 0:f86e6135dcbc 194 typedef union
elevatorguy 0:f86e6135dcbc 195 {
elevatorguy 0:f86e6135dcbc 196 struct
elevatorguy 0:f86e6135dcbc 197 {
elevatorguy 0:f86e6135dcbc 198 #if (__CORTEX_M != 0x04)
elevatorguy 0:f86e6135dcbc 199 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
elevatorguy 0:f86e6135dcbc 200 #else
elevatorguy 0:f86e6135dcbc 201 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
elevatorguy 0:f86e6135dcbc 202 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
elevatorguy 0:f86e6135dcbc 203 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
elevatorguy 0:f86e6135dcbc 204 #endif
elevatorguy 0:f86e6135dcbc 205 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
elevatorguy 0:f86e6135dcbc 206 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elevatorguy 0:f86e6135dcbc 207 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elevatorguy 0:f86e6135dcbc 208 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elevatorguy 0:f86e6135dcbc 209 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elevatorguy 0:f86e6135dcbc 210 } b; /*!< Structure used for bit access */
elevatorguy 0:f86e6135dcbc 211 uint32_t w; /*!< Type used for word access */
elevatorguy 0:f86e6135dcbc 212 } APSR_Type;
elevatorguy 0:f86e6135dcbc 213
elevatorguy 0:f86e6135dcbc 214
elevatorguy 0:f86e6135dcbc 215 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
elevatorguy 0:f86e6135dcbc 216 */
elevatorguy 0:f86e6135dcbc 217 typedef union
elevatorguy 0:f86e6135dcbc 218 {
elevatorguy 0:f86e6135dcbc 219 struct
elevatorguy 0:f86e6135dcbc 220 {
elevatorguy 0:f86e6135dcbc 221 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elevatorguy 0:f86e6135dcbc 222 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
elevatorguy 0:f86e6135dcbc 223 } b; /*!< Structure used for bit access */
elevatorguy 0:f86e6135dcbc 224 uint32_t w; /*!< Type used for word access */
elevatorguy 0:f86e6135dcbc 225 } IPSR_Type;
elevatorguy 0:f86e6135dcbc 226
elevatorguy 0:f86e6135dcbc 227
elevatorguy 0:f86e6135dcbc 228 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
elevatorguy 0:f86e6135dcbc 229 */
elevatorguy 0:f86e6135dcbc 230 typedef union
elevatorguy 0:f86e6135dcbc 231 {
elevatorguy 0:f86e6135dcbc 232 struct
elevatorguy 0:f86e6135dcbc 233 {
elevatorguy 0:f86e6135dcbc 234 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
elevatorguy 0:f86e6135dcbc 235 #if (__CORTEX_M != 0x04)
elevatorguy 0:f86e6135dcbc 236 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
elevatorguy 0:f86e6135dcbc 237 #else
elevatorguy 0:f86e6135dcbc 238 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
elevatorguy 0:f86e6135dcbc 239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
elevatorguy 0:f86e6135dcbc 240 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
elevatorguy 0:f86e6135dcbc 241 #endif
elevatorguy 0:f86e6135dcbc 242 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
elevatorguy 0:f86e6135dcbc 243 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
elevatorguy 0:f86e6135dcbc 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
elevatorguy 0:f86e6135dcbc 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
elevatorguy 0:f86e6135dcbc 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
elevatorguy 0:f86e6135dcbc 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
elevatorguy 0:f86e6135dcbc 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
elevatorguy 0:f86e6135dcbc 249 } b; /*!< Structure used for bit access */
elevatorguy 0:f86e6135dcbc 250 uint32_t w; /*!< Type used for word access */
elevatorguy 0:f86e6135dcbc 251 } xPSR_Type;
elevatorguy 0:f86e6135dcbc 252
elevatorguy 0:f86e6135dcbc 253
elevatorguy 0:f86e6135dcbc 254 /** \brief Union type to access the Control Registers (CONTROL).
elevatorguy 0:f86e6135dcbc 255 */
elevatorguy 0:f86e6135dcbc 256 typedef union
elevatorguy 0:f86e6135dcbc 257 {
elevatorguy 0:f86e6135dcbc 258 struct
elevatorguy 0:f86e6135dcbc 259 {
elevatorguy 0:f86e6135dcbc 260 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
elevatorguy 0:f86e6135dcbc 261 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
elevatorguy 0:f86e6135dcbc 262 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
elevatorguy 0:f86e6135dcbc 263 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
elevatorguy 0:f86e6135dcbc 264 } b; /*!< Structure used for bit access */
elevatorguy 0:f86e6135dcbc 265 uint32_t w; /*!< Type used for word access */
elevatorguy 0:f86e6135dcbc 266 } CONTROL_Type;
elevatorguy 0:f86e6135dcbc 267
elevatorguy 0:f86e6135dcbc 268 /*@} end of group CMSIS_CORE */
elevatorguy 0:f86e6135dcbc 269
elevatorguy 0:f86e6135dcbc 270
elevatorguy 0:f86e6135dcbc 271 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 272 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
elevatorguy 0:f86e6135dcbc 273 \brief Type definitions for the NVIC Registers
elevatorguy 0:f86e6135dcbc 274 @{
elevatorguy 0:f86e6135dcbc 275 */
elevatorguy 0:f86e6135dcbc 276
elevatorguy 0:f86e6135dcbc 277 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
elevatorguy 0:f86e6135dcbc 278 */
elevatorguy 0:f86e6135dcbc 279 typedef struct
elevatorguy 0:f86e6135dcbc 280 {
elevatorguy 0:f86e6135dcbc 281 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
elevatorguy 0:f86e6135dcbc 282 uint32_t RESERVED0[24];
elevatorguy 0:f86e6135dcbc 283 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
elevatorguy 0:f86e6135dcbc 284 uint32_t RSERVED1[24];
elevatorguy 0:f86e6135dcbc 285 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
elevatorguy 0:f86e6135dcbc 286 uint32_t RESERVED2[24];
elevatorguy 0:f86e6135dcbc 287 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
elevatorguy 0:f86e6135dcbc 288 uint32_t RESERVED3[24];
elevatorguy 0:f86e6135dcbc 289 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
elevatorguy 0:f86e6135dcbc 290 uint32_t RESERVED4[56];
elevatorguy 0:f86e6135dcbc 291 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
elevatorguy 0:f86e6135dcbc 292 uint32_t RESERVED5[644];
elevatorguy 0:f86e6135dcbc 293 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
elevatorguy 0:f86e6135dcbc 294 } NVIC_Type;
elevatorguy 0:f86e6135dcbc 295
elevatorguy 0:f86e6135dcbc 296 /* Software Triggered Interrupt Register Definitions */
elevatorguy 0:f86e6135dcbc 297 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
elevatorguy 0:f86e6135dcbc 298 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
elevatorguy 0:f86e6135dcbc 299
elevatorguy 0:f86e6135dcbc 300 /*@} end of group CMSIS_NVIC */
elevatorguy 0:f86e6135dcbc 301
elevatorguy 0:f86e6135dcbc 302
elevatorguy 0:f86e6135dcbc 303 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 304 \defgroup CMSIS_SCB System Control Block (SCB)
elevatorguy 0:f86e6135dcbc 305 \brief Type definitions for the System Control Block Registers
elevatorguy 0:f86e6135dcbc 306 @{
elevatorguy 0:f86e6135dcbc 307 */
elevatorguy 0:f86e6135dcbc 308
elevatorguy 0:f86e6135dcbc 309 /** \brief Structure type to access the System Control Block (SCB).
elevatorguy 0:f86e6135dcbc 310 */
elevatorguy 0:f86e6135dcbc 311 typedef struct
elevatorguy 0:f86e6135dcbc 312 {
elevatorguy 0:f86e6135dcbc 313 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
elevatorguy 0:f86e6135dcbc 314 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
elevatorguy 0:f86e6135dcbc 315 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
elevatorguy 0:f86e6135dcbc 316 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
elevatorguy 0:f86e6135dcbc 317 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
elevatorguy 0:f86e6135dcbc 318 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
elevatorguy 0:f86e6135dcbc 319 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
elevatorguy 0:f86e6135dcbc 320 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
elevatorguy 0:f86e6135dcbc 321 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
elevatorguy 0:f86e6135dcbc 322 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
elevatorguy 0:f86e6135dcbc 323 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
elevatorguy 0:f86e6135dcbc 324 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
elevatorguy 0:f86e6135dcbc 325 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
elevatorguy 0:f86e6135dcbc 326 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
elevatorguy 0:f86e6135dcbc 327 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
elevatorguy 0:f86e6135dcbc 328 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
elevatorguy 0:f86e6135dcbc 329 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
elevatorguy 0:f86e6135dcbc 330 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
elevatorguy 0:f86e6135dcbc 331 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
elevatorguy 0:f86e6135dcbc 332 uint32_t RESERVED0[5];
elevatorguy 0:f86e6135dcbc 333 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
elevatorguy 0:f86e6135dcbc 334 } SCB_Type;
elevatorguy 0:f86e6135dcbc 335
elevatorguy 0:f86e6135dcbc 336 /* SCB CPUID Register Definitions */
elevatorguy 0:f86e6135dcbc 337 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
elevatorguy 0:f86e6135dcbc 338 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
elevatorguy 0:f86e6135dcbc 339
elevatorguy 0:f86e6135dcbc 340 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
elevatorguy 0:f86e6135dcbc 341 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
elevatorguy 0:f86e6135dcbc 342
elevatorguy 0:f86e6135dcbc 343 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
elevatorguy 0:f86e6135dcbc 344 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
elevatorguy 0:f86e6135dcbc 345
elevatorguy 0:f86e6135dcbc 346 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
elevatorguy 0:f86e6135dcbc 347 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
elevatorguy 0:f86e6135dcbc 348
elevatorguy 0:f86e6135dcbc 349 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
elevatorguy 0:f86e6135dcbc 350 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
elevatorguy 0:f86e6135dcbc 351
elevatorguy 0:f86e6135dcbc 352 /* SCB Interrupt Control State Register Definitions */
elevatorguy 0:f86e6135dcbc 353 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
elevatorguy 0:f86e6135dcbc 354 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
elevatorguy 0:f86e6135dcbc 355
elevatorguy 0:f86e6135dcbc 356 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
elevatorguy 0:f86e6135dcbc 357 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
elevatorguy 0:f86e6135dcbc 358
elevatorguy 0:f86e6135dcbc 359 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
elevatorguy 0:f86e6135dcbc 360 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
elevatorguy 0:f86e6135dcbc 361
elevatorguy 0:f86e6135dcbc 362 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
elevatorguy 0:f86e6135dcbc 363 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
elevatorguy 0:f86e6135dcbc 364
elevatorguy 0:f86e6135dcbc 365 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
elevatorguy 0:f86e6135dcbc 366 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
elevatorguy 0:f86e6135dcbc 367
elevatorguy 0:f86e6135dcbc 368 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
elevatorguy 0:f86e6135dcbc 369 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
elevatorguy 0:f86e6135dcbc 370
elevatorguy 0:f86e6135dcbc 371 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
elevatorguy 0:f86e6135dcbc 372 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
elevatorguy 0:f86e6135dcbc 373
elevatorguy 0:f86e6135dcbc 374 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
elevatorguy 0:f86e6135dcbc 375 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
elevatorguy 0:f86e6135dcbc 376
elevatorguy 0:f86e6135dcbc 377 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
elevatorguy 0:f86e6135dcbc 378 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
elevatorguy 0:f86e6135dcbc 379
elevatorguy 0:f86e6135dcbc 380 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
elevatorguy 0:f86e6135dcbc 381 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
elevatorguy 0:f86e6135dcbc 382
elevatorguy 0:f86e6135dcbc 383 /* SCB Vector Table Offset Register Definitions */
elevatorguy 0:f86e6135dcbc 384 #if (__CM3_REV < 0x0201) /* core r2p1 */
elevatorguy 0:f86e6135dcbc 385 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
elevatorguy 0:f86e6135dcbc 386 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
elevatorguy 0:f86e6135dcbc 387
elevatorguy 0:f86e6135dcbc 388 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
elevatorguy 0:f86e6135dcbc 389 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
elevatorguy 0:f86e6135dcbc 390 #else
elevatorguy 0:f86e6135dcbc 391 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
elevatorguy 0:f86e6135dcbc 392 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
elevatorguy 0:f86e6135dcbc 393 #endif
elevatorguy 0:f86e6135dcbc 394
elevatorguy 0:f86e6135dcbc 395 /* SCB Application Interrupt and Reset Control Register Definitions */
elevatorguy 0:f86e6135dcbc 396 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
elevatorguy 0:f86e6135dcbc 397 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
elevatorguy 0:f86e6135dcbc 398
elevatorguy 0:f86e6135dcbc 399 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
elevatorguy 0:f86e6135dcbc 400 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
elevatorguy 0:f86e6135dcbc 401
elevatorguy 0:f86e6135dcbc 402 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
elevatorguy 0:f86e6135dcbc 403 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
elevatorguy 0:f86e6135dcbc 404
elevatorguy 0:f86e6135dcbc 405 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
elevatorguy 0:f86e6135dcbc 406 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
elevatorguy 0:f86e6135dcbc 407
elevatorguy 0:f86e6135dcbc 408 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
elevatorguy 0:f86e6135dcbc 409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
elevatorguy 0:f86e6135dcbc 410
elevatorguy 0:f86e6135dcbc 411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
elevatorguy 0:f86e6135dcbc 412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
elevatorguy 0:f86e6135dcbc 413
elevatorguy 0:f86e6135dcbc 414 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
elevatorguy 0:f86e6135dcbc 415 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
elevatorguy 0:f86e6135dcbc 416
elevatorguy 0:f86e6135dcbc 417 /* SCB System Control Register Definitions */
elevatorguy 0:f86e6135dcbc 418 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
elevatorguy 0:f86e6135dcbc 419 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
elevatorguy 0:f86e6135dcbc 420
elevatorguy 0:f86e6135dcbc 421 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
elevatorguy 0:f86e6135dcbc 422 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
elevatorguy 0:f86e6135dcbc 423
elevatorguy 0:f86e6135dcbc 424 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
elevatorguy 0:f86e6135dcbc 425 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
elevatorguy 0:f86e6135dcbc 426
elevatorguy 0:f86e6135dcbc 427 /* SCB Configuration Control Register Definitions */
elevatorguy 0:f86e6135dcbc 428 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
elevatorguy 0:f86e6135dcbc 429 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
elevatorguy 0:f86e6135dcbc 430
elevatorguy 0:f86e6135dcbc 431 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
elevatorguy 0:f86e6135dcbc 432 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
elevatorguy 0:f86e6135dcbc 433
elevatorguy 0:f86e6135dcbc 434 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
elevatorguy 0:f86e6135dcbc 435 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
elevatorguy 0:f86e6135dcbc 436
elevatorguy 0:f86e6135dcbc 437 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
elevatorguy 0:f86e6135dcbc 438 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
elevatorguy 0:f86e6135dcbc 439
elevatorguy 0:f86e6135dcbc 440 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
elevatorguy 0:f86e6135dcbc 441 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
elevatorguy 0:f86e6135dcbc 442
elevatorguy 0:f86e6135dcbc 443 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
elevatorguy 0:f86e6135dcbc 444 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
elevatorguy 0:f86e6135dcbc 445
elevatorguy 0:f86e6135dcbc 446 /* SCB System Handler Control and State Register Definitions */
elevatorguy 0:f86e6135dcbc 447 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
elevatorguy 0:f86e6135dcbc 448 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
elevatorguy 0:f86e6135dcbc 449
elevatorguy 0:f86e6135dcbc 450 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
elevatorguy 0:f86e6135dcbc 451 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
elevatorguy 0:f86e6135dcbc 452
elevatorguy 0:f86e6135dcbc 453 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
elevatorguy 0:f86e6135dcbc 454 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
elevatorguy 0:f86e6135dcbc 455
elevatorguy 0:f86e6135dcbc 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
elevatorguy 0:f86e6135dcbc 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
elevatorguy 0:f86e6135dcbc 458
elevatorguy 0:f86e6135dcbc 459 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
elevatorguy 0:f86e6135dcbc 460 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
elevatorguy 0:f86e6135dcbc 461
elevatorguy 0:f86e6135dcbc 462 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
elevatorguy 0:f86e6135dcbc 463 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
elevatorguy 0:f86e6135dcbc 464
elevatorguy 0:f86e6135dcbc 465 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
elevatorguy 0:f86e6135dcbc 466 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
elevatorguy 0:f86e6135dcbc 467
elevatorguy 0:f86e6135dcbc 468 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
elevatorguy 0:f86e6135dcbc 469 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
elevatorguy 0:f86e6135dcbc 470
elevatorguy 0:f86e6135dcbc 471 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
elevatorguy 0:f86e6135dcbc 472 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
elevatorguy 0:f86e6135dcbc 473
elevatorguy 0:f86e6135dcbc 474 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
elevatorguy 0:f86e6135dcbc 475 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
elevatorguy 0:f86e6135dcbc 476
elevatorguy 0:f86e6135dcbc 477 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
elevatorguy 0:f86e6135dcbc 478 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
elevatorguy 0:f86e6135dcbc 479
elevatorguy 0:f86e6135dcbc 480 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
elevatorguy 0:f86e6135dcbc 481 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
elevatorguy 0:f86e6135dcbc 482
elevatorguy 0:f86e6135dcbc 483 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
elevatorguy 0:f86e6135dcbc 484 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
elevatorguy 0:f86e6135dcbc 485
elevatorguy 0:f86e6135dcbc 486 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
elevatorguy 0:f86e6135dcbc 487 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
elevatorguy 0:f86e6135dcbc 488
elevatorguy 0:f86e6135dcbc 489 /* SCB Configurable Fault Status Registers Definitions */
elevatorguy 0:f86e6135dcbc 490 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
elevatorguy 0:f86e6135dcbc 491 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
elevatorguy 0:f86e6135dcbc 492
elevatorguy 0:f86e6135dcbc 493 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
elevatorguy 0:f86e6135dcbc 494 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
elevatorguy 0:f86e6135dcbc 495
elevatorguy 0:f86e6135dcbc 496 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
elevatorguy 0:f86e6135dcbc 497 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
elevatorguy 0:f86e6135dcbc 498
elevatorguy 0:f86e6135dcbc 499 /* SCB Hard Fault Status Registers Definitions */
elevatorguy 0:f86e6135dcbc 500 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
elevatorguy 0:f86e6135dcbc 501 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
elevatorguy 0:f86e6135dcbc 502
elevatorguy 0:f86e6135dcbc 503 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
elevatorguy 0:f86e6135dcbc 504 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
elevatorguy 0:f86e6135dcbc 505
elevatorguy 0:f86e6135dcbc 506 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
elevatorguy 0:f86e6135dcbc 507 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
elevatorguy 0:f86e6135dcbc 508
elevatorguy 0:f86e6135dcbc 509 /* SCB Debug Fault Status Register Definitions */
elevatorguy 0:f86e6135dcbc 510 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
elevatorguy 0:f86e6135dcbc 511 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
elevatorguy 0:f86e6135dcbc 512
elevatorguy 0:f86e6135dcbc 513 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
elevatorguy 0:f86e6135dcbc 514 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
elevatorguy 0:f86e6135dcbc 515
elevatorguy 0:f86e6135dcbc 516 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
elevatorguy 0:f86e6135dcbc 517 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
elevatorguy 0:f86e6135dcbc 518
elevatorguy 0:f86e6135dcbc 519 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
elevatorguy 0:f86e6135dcbc 520 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
elevatorguy 0:f86e6135dcbc 521
elevatorguy 0:f86e6135dcbc 522 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
elevatorguy 0:f86e6135dcbc 523 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
elevatorguy 0:f86e6135dcbc 524
elevatorguy 0:f86e6135dcbc 525 /*@} end of group CMSIS_SCB */
elevatorguy 0:f86e6135dcbc 526
elevatorguy 0:f86e6135dcbc 527
elevatorguy 0:f86e6135dcbc 528 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 529 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
elevatorguy 0:f86e6135dcbc 530 \brief Type definitions for the System Control and ID Register not in the SCB
elevatorguy 0:f86e6135dcbc 531 @{
elevatorguy 0:f86e6135dcbc 532 */
elevatorguy 0:f86e6135dcbc 533
elevatorguy 0:f86e6135dcbc 534 /** \brief Structure type to access the System Control and ID Register not in the SCB.
elevatorguy 0:f86e6135dcbc 535 */
elevatorguy 0:f86e6135dcbc 536 typedef struct
elevatorguy 0:f86e6135dcbc 537 {
elevatorguy 0:f86e6135dcbc 538 uint32_t RESERVED0[1];
elevatorguy 0:f86e6135dcbc 539 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
elevatorguy 0:f86e6135dcbc 540 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
elevatorguy 0:f86e6135dcbc 541 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
elevatorguy 0:f86e6135dcbc 542 #else
elevatorguy 0:f86e6135dcbc 543 uint32_t RESERVED1[1];
elevatorguy 0:f86e6135dcbc 544 #endif
elevatorguy 0:f86e6135dcbc 545 } SCnSCB_Type;
elevatorguy 0:f86e6135dcbc 546
elevatorguy 0:f86e6135dcbc 547 /* Interrupt Controller Type Register Definitions */
elevatorguy 0:f86e6135dcbc 548 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
elevatorguy 0:f86e6135dcbc 549 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
elevatorguy 0:f86e6135dcbc 550
elevatorguy 0:f86e6135dcbc 551 /* Auxiliary Control Register Definitions */
elevatorguy 0:f86e6135dcbc 552
elevatorguy 0:f86e6135dcbc 553 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
elevatorguy 0:f86e6135dcbc 554 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
elevatorguy 0:f86e6135dcbc 555
elevatorguy 0:f86e6135dcbc 556 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
elevatorguy 0:f86e6135dcbc 557 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
elevatorguy 0:f86e6135dcbc 558
elevatorguy 0:f86e6135dcbc 559 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
elevatorguy 0:f86e6135dcbc 560 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
elevatorguy 0:f86e6135dcbc 561
elevatorguy 0:f86e6135dcbc 562 /*@} end of group CMSIS_SCnotSCB */
elevatorguy 0:f86e6135dcbc 563
elevatorguy 0:f86e6135dcbc 564
elevatorguy 0:f86e6135dcbc 565 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 566 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
elevatorguy 0:f86e6135dcbc 567 \brief Type definitions for the System Timer Registers.
elevatorguy 0:f86e6135dcbc 568 @{
elevatorguy 0:f86e6135dcbc 569 */
elevatorguy 0:f86e6135dcbc 570
elevatorguy 0:f86e6135dcbc 571 /** \brief Structure type to access the System Timer (SysTick).
elevatorguy 0:f86e6135dcbc 572 */
elevatorguy 0:f86e6135dcbc 573 typedef struct
elevatorguy 0:f86e6135dcbc 574 {
elevatorguy 0:f86e6135dcbc 575 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
elevatorguy 0:f86e6135dcbc 576 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
elevatorguy 0:f86e6135dcbc 577 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
elevatorguy 0:f86e6135dcbc 578 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
elevatorguy 0:f86e6135dcbc 579 } SysTick_Type;
elevatorguy 0:f86e6135dcbc 580
elevatorguy 0:f86e6135dcbc 581 /* SysTick Control / Status Register Definitions */
elevatorguy 0:f86e6135dcbc 582 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
elevatorguy 0:f86e6135dcbc 583 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
elevatorguy 0:f86e6135dcbc 584
elevatorguy 0:f86e6135dcbc 585 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
elevatorguy 0:f86e6135dcbc 586 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
elevatorguy 0:f86e6135dcbc 587
elevatorguy 0:f86e6135dcbc 588 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
elevatorguy 0:f86e6135dcbc 589 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
elevatorguy 0:f86e6135dcbc 590
elevatorguy 0:f86e6135dcbc 591 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
elevatorguy 0:f86e6135dcbc 592 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
elevatorguy 0:f86e6135dcbc 593
elevatorguy 0:f86e6135dcbc 594 /* SysTick Reload Register Definitions */
elevatorguy 0:f86e6135dcbc 595 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
elevatorguy 0:f86e6135dcbc 596 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
elevatorguy 0:f86e6135dcbc 597
elevatorguy 0:f86e6135dcbc 598 /* SysTick Current Register Definitions */
elevatorguy 0:f86e6135dcbc 599 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
elevatorguy 0:f86e6135dcbc 600 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
elevatorguy 0:f86e6135dcbc 601
elevatorguy 0:f86e6135dcbc 602 /* SysTick Calibration Register Definitions */
elevatorguy 0:f86e6135dcbc 603 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
elevatorguy 0:f86e6135dcbc 604 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
elevatorguy 0:f86e6135dcbc 605
elevatorguy 0:f86e6135dcbc 606 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
elevatorguy 0:f86e6135dcbc 607 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
elevatorguy 0:f86e6135dcbc 608
elevatorguy 0:f86e6135dcbc 609 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
elevatorguy 0:f86e6135dcbc 610 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
elevatorguy 0:f86e6135dcbc 611
elevatorguy 0:f86e6135dcbc 612 /*@} end of group CMSIS_SysTick */
elevatorguy 0:f86e6135dcbc 613
elevatorguy 0:f86e6135dcbc 614
elevatorguy 0:f86e6135dcbc 615 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 616 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
elevatorguy 0:f86e6135dcbc 617 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
elevatorguy 0:f86e6135dcbc 618 @{
elevatorguy 0:f86e6135dcbc 619 */
elevatorguy 0:f86e6135dcbc 620
elevatorguy 0:f86e6135dcbc 621 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
elevatorguy 0:f86e6135dcbc 622 */
elevatorguy 0:f86e6135dcbc 623 typedef struct
elevatorguy 0:f86e6135dcbc 624 {
elevatorguy 0:f86e6135dcbc 625 __O union
elevatorguy 0:f86e6135dcbc 626 {
elevatorguy 0:f86e6135dcbc 627 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
elevatorguy 0:f86e6135dcbc 628 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
elevatorguy 0:f86e6135dcbc 629 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
elevatorguy 0:f86e6135dcbc 630 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
elevatorguy 0:f86e6135dcbc 631 uint32_t RESERVED0[864];
elevatorguy 0:f86e6135dcbc 632 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
elevatorguy 0:f86e6135dcbc 633 uint32_t RESERVED1[15];
elevatorguy 0:f86e6135dcbc 634 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
elevatorguy 0:f86e6135dcbc 635 uint32_t RESERVED2[15];
elevatorguy 0:f86e6135dcbc 636 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
elevatorguy 0:f86e6135dcbc 637 } ITM_Type;
elevatorguy 0:f86e6135dcbc 638
elevatorguy 0:f86e6135dcbc 639 /* ITM Trace Privilege Register Definitions */
elevatorguy 0:f86e6135dcbc 640 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
elevatorguy 0:f86e6135dcbc 641 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
elevatorguy 0:f86e6135dcbc 642
elevatorguy 0:f86e6135dcbc 643 /* ITM Trace Control Register Definitions */
elevatorguy 0:f86e6135dcbc 644 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
elevatorguy 0:f86e6135dcbc 645 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
elevatorguy 0:f86e6135dcbc 646
elevatorguy 0:f86e6135dcbc 647 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
elevatorguy 0:f86e6135dcbc 648 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
elevatorguy 0:f86e6135dcbc 649
elevatorguy 0:f86e6135dcbc 650 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
elevatorguy 0:f86e6135dcbc 651 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
elevatorguy 0:f86e6135dcbc 652
elevatorguy 0:f86e6135dcbc 653 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
elevatorguy 0:f86e6135dcbc 654 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
elevatorguy 0:f86e6135dcbc 655
elevatorguy 0:f86e6135dcbc 656 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
elevatorguy 0:f86e6135dcbc 657 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
elevatorguy 0:f86e6135dcbc 658
elevatorguy 0:f86e6135dcbc 659 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
elevatorguy 0:f86e6135dcbc 660 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
elevatorguy 0:f86e6135dcbc 661
elevatorguy 0:f86e6135dcbc 662 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
elevatorguy 0:f86e6135dcbc 663 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
elevatorguy 0:f86e6135dcbc 664
elevatorguy 0:f86e6135dcbc 665 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
elevatorguy 0:f86e6135dcbc 666 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
elevatorguy 0:f86e6135dcbc 667
elevatorguy 0:f86e6135dcbc 668 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
elevatorguy 0:f86e6135dcbc 669 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
elevatorguy 0:f86e6135dcbc 670
elevatorguy 0:f86e6135dcbc 671 /*@}*/ /* end of group CMSIS_ITM */
elevatorguy 0:f86e6135dcbc 672
elevatorguy 0:f86e6135dcbc 673
elevatorguy 0:f86e6135dcbc 674 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 675 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
elevatorguy 0:f86e6135dcbc 676 \brief Type definitions for the Data Watchpoint and Trace (DWT)
elevatorguy 0:f86e6135dcbc 677 @{
elevatorguy 0:f86e6135dcbc 678 */
elevatorguy 0:f86e6135dcbc 679
elevatorguy 0:f86e6135dcbc 680 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
elevatorguy 0:f86e6135dcbc 681 */
elevatorguy 0:f86e6135dcbc 682 typedef struct
elevatorguy 0:f86e6135dcbc 683 {
elevatorguy 0:f86e6135dcbc 684 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
elevatorguy 0:f86e6135dcbc 685 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
elevatorguy 0:f86e6135dcbc 686 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
elevatorguy 0:f86e6135dcbc 687 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
elevatorguy 0:f86e6135dcbc 688 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
elevatorguy 0:f86e6135dcbc 689 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
elevatorguy 0:f86e6135dcbc 690 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
elevatorguy 0:f86e6135dcbc 691 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
elevatorguy 0:f86e6135dcbc 692 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
elevatorguy 0:f86e6135dcbc 693 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
elevatorguy 0:f86e6135dcbc 694 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
elevatorguy 0:f86e6135dcbc 695 uint32_t RESERVED0[1];
elevatorguy 0:f86e6135dcbc 696 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
elevatorguy 0:f86e6135dcbc 697 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
elevatorguy 0:f86e6135dcbc 698 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
elevatorguy 0:f86e6135dcbc 699 uint32_t RESERVED1[1];
elevatorguy 0:f86e6135dcbc 700 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
elevatorguy 0:f86e6135dcbc 701 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
elevatorguy 0:f86e6135dcbc 702 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
elevatorguy 0:f86e6135dcbc 703 uint32_t RESERVED2[1];
elevatorguy 0:f86e6135dcbc 704 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
elevatorguy 0:f86e6135dcbc 705 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
elevatorguy 0:f86e6135dcbc 706 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
elevatorguy 0:f86e6135dcbc 707 } DWT_Type;
elevatorguy 0:f86e6135dcbc 708
elevatorguy 0:f86e6135dcbc 709 /* DWT Control Register Definitions */
elevatorguy 0:f86e6135dcbc 710 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
elevatorguy 0:f86e6135dcbc 711 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
elevatorguy 0:f86e6135dcbc 712
elevatorguy 0:f86e6135dcbc 713 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
elevatorguy 0:f86e6135dcbc 714 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
elevatorguy 0:f86e6135dcbc 715
elevatorguy 0:f86e6135dcbc 716 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
elevatorguy 0:f86e6135dcbc 717 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
elevatorguy 0:f86e6135dcbc 718
elevatorguy 0:f86e6135dcbc 719 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
elevatorguy 0:f86e6135dcbc 720 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
elevatorguy 0:f86e6135dcbc 721
elevatorguy 0:f86e6135dcbc 722 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
elevatorguy 0:f86e6135dcbc 723 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
elevatorguy 0:f86e6135dcbc 724
elevatorguy 0:f86e6135dcbc 725 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
elevatorguy 0:f86e6135dcbc 726 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
elevatorguy 0:f86e6135dcbc 727
elevatorguy 0:f86e6135dcbc 728 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
elevatorguy 0:f86e6135dcbc 729 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
elevatorguy 0:f86e6135dcbc 730
elevatorguy 0:f86e6135dcbc 731 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
elevatorguy 0:f86e6135dcbc 732 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
elevatorguy 0:f86e6135dcbc 733
elevatorguy 0:f86e6135dcbc 734 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
elevatorguy 0:f86e6135dcbc 735 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
elevatorguy 0:f86e6135dcbc 736
elevatorguy 0:f86e6135dcbc 737 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
elevatorguy 0:f86e6135dcbc 738 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
elevatorguy 0:f86e6135dcbc 739
elevatorguy 0:f86e6135dcbc 740 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
elevatorguy 0:f86e6135dcbc 741 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
elevatorguy 0:f86e6135dcbc 742
elevatorguy 0:f86e6135dcbc 743 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
elevatorguy 0:f86e6135dcbc 744 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
elevatorguy 0:f86e6135dcbc 745
elevatorguy 0:f86e6135dcbc 746 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
elevatorguy 0:f86e6135dcbc 747 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
elevatorguy 0:f86e6135dcbc 748
elevatorguy 0:f86e6135dcbc 749 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
elevatorguy 0:f86e6135dcbc 750 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
elevatorguy 0:f86e6135dcbc 751
elevatorguy 0:f86e6135dcbc 752 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
elevatorguy 0:f86e6135dcbc 753 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
elevatorguy 0:f86e6135dcbc 754
elevatorguy 0:f86e6135dcbc 755 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
elevatorguy 0:f86e6135dcbc 756 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
elevatorguy 0:f86e6135dcbc 757
elevatorguy 0:f86e6135dcbc 758 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
elevatorguy 0:f86e6135dcbc 759 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
elevatorguy 0:f86e6135dcbc 760
elevatorguy 0:f86e6135dcbc 761 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
elevatorguy 0:f86e6135dcbc 762 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
elevatorguy 0:f86e6135dcbc 763
elevatorguy 0:f86e6135dcbc 764 /* DWT CPI Count Register Definitions */
elevatorguy 0:f86e6135dcbc 765 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
elevatorguy 0:f86e6135dcbc 766 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
elevatorguy 0:f86e6135dcbc 767
elevatorguy 0:f86e6135dcbc 768 /* DWT Exception Overhead Count Register Definitions */
elevatorguy 0:f86e6135dcbc 769 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
elevatorguy 0:f86e6135dcbc 770 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
elevatorguy 0:f86e6135dcbc 771
elevatorguy 0:f86e6135dcbc 772 /* DWT Sleep Count Register Definitions */
elevatorguy 0:f86e6135dcbc 773 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
elevatorguy 0:f86e6135dcbc 774 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
elevatorguy 0:f86e6135dcbc 775
elevatorguy 0:f86e6135dcbc 776 /* DWT LSU Count Register Definitions */
elevatorguy 0:f86e6135dcbc 777 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
elevatorguy 0:f86e6135dcbc 778 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
elevatorguy 0:f86e6135dcbc 779
elevatorguy 0:f86e6135dcbc 780 /* DWT Folded-instruction Count Register Definitions */
elevatorguy 0:f86e6135dcbc 781 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
elevatorguy 0:f86e6135dcbc 782 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
elevatorguy 0:f86e6135dcbc 783
elevatorguy 0:f86e6135dcbc 784 /* DWT Comparator Mask Register Definitions */
elevatorguy 0:f86e6135dcbc 785 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
elevatorguy 0:f86e6135dcbc 786 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
elevatorguy 0:f86e6135dcbc 787
elevatorguy 0:f86e6135dcbc 788 /* DWT Comparator Function Register Definitions */
elevatorguy 0:f86e6135dcbc 789 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
elevatorguy 0:f86e6135dcbc 790 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
elevatorguy 0:f86e6135dcbc 791
elevatorguy 0:f86e6135dcbc 792 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
elevatorguy 0:f86e6135dcbc 793 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
elevatorguy 0:f86e6135dcbc 794
elevatorguy 0:f86e6135dcbc 795 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
elevatorguy 0:f86e6135dcbc 796 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
elevatorguy 0:f86e6135dcbc 797
elevatorguy 0:f86e6135dcbc 798 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
elevatorguy 0:f86e6135dcbc 799 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
elevatorguy 0:f86e6135dcbc 800
elevatorguy 0:f86e6135dcbc 801 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
elevatorguy 0:f86e6135dcbc 802 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
elevatorguy 0:f86e6135dcbc 803
elevatorguy 0:f86e6135dcbc 804 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
elevatorguy 0:f86e6135dcbc 805 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
elevatorguy 0:f86e6135dcbc 806
elevatorguy 0:f86e6135dcbc 807 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
elevatorguy 0:f86e6135dcbc 808 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
elevatorguy 0:f86e6135dcbc 809
elevatorguy 0:f86e6135dcbc 810 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
elevatorguy 0:f86e6135dcbc 811 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
elevatorguy 0:f86e6135dcbc 812
elevatorguy 0:f86e6135dcbc 813 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
elevatorguy 0:f86e6135dcbc 814 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
elevatorguy 0:f86e6135dcbc 815
elevatorguy 0:f86e6135dcbc 816 /*@}*/ /* end of group CMSIS_DWT */
elevatorguy 0:f86e6135dcbc 817
elevatorguy 0:f86e6135dcbc 818
elevatorguy 0:f86e6135dcbc 819 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 820 \defgroup CMSIS_TPI Trace Port Interface (TPI)
elevatorguy 0:f86e6135dcbc 821 \brief Type definitions for the Trace Port Interface (TPI)
elevatorguy 0:f86e6135dcbc 822 @{
elevatorguy 0:f86e6135dcbc 823 */
elevatorguy 0:f86e6135dcbc 824
elevatorguy 0:f86e6135dcbc 825 /** \brief Structure type to access the Trace Port Interface Register (TPI).
elevatorguy 0:f86e6135dcbc 826 */
elevatorguy 0:f86e6135dcbc 827 typedef struct
elevatorguy 0:f86e6135dcbc 828 {
elevatorguy 0:f86e6135dcbc 829 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
elevatorguy 0:f86e6135dcbc 830 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
elevatorguy 0:f86e6135dcbc 831 uint32_t RESERVED0[2];
elevatorguy 0:f86e6135dcbc 832 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
elevatorguy 0:f86e6135dcbc 833 uint32_t RESERVED1[55];
elevatorguy 0:f86e6135dcbc 834 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
elevatorguy 0:f86e6135dcbc 835 uint32_t RESERVED2[131];
elevatorguy 0:f86e6135dcbc 836 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
elevatorguy 0:f86e6135dcbc 837 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
elevatorguy 0:f86e6135dcbc 838 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
elevatorguy 0:f86e6135dcbc 839 uint32_t RESERVED3[759];
elevatorguy 0:f86e6135dcbc 840 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
elevatorguy 0:f86e6135dcbc 841 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
elevatorguy 0:f86e6135dcbc 842 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
elevatorguy 0:f86e6135dcbc 843 uint32_t RESERVED4[1];
elevatorguy 0:f86e6135dcbc 844 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
elevatorguy 0:f86e6135dcbc 845 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
elevatorguy 0:f86e6135dcbc 846 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
elevatorguy 0:f86e6135dcbc 847 uint32_t RESERVED5[39];
elevatorguy 0:f86e6135dcbc 848 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
elevatorguy 0:f86e6135dcbc 849 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
elevatorguy 0:f86e6135dcbc 850 uint32_t RESERVED7[8];
elevatorguy 0:f86e6135dcbc 851 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
elevatorguy 0:f86e6135dcbc 852 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
elevatorguy 0:f86e6135dcbc 853 } TPI_Type;
elevatorguy 0:f86e6135dcbc 854
elevatorguy 0:f86e6135dcbc 855 /* TPI Asynchronous Clock Prescaler Register Definitions */
elevatorguy 0:f86e6135dcbc 856 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
elevatorguy 0:f86e6135dcbc 857 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
elevatorguy 0:f86e6135dcbc 858
elevatorguy 0:f86e6135dcbc 859 /* TPI Selected Pin Protocol Register Definitions */
elevatorguy 0:f86e6135dcbc 860 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
elevatorguy 0:f86e6135dcbc 861 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
elevatorguy 0:f86e6135dcbc 862
elevatorguy 0:f86e6135dcbc 863 /* TPI Formatter and Flush Status Register Definitions */
elevatorguy 0:f86e6135dcbc 864 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
elevatorguy 0:f86e6135dcbc 865 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
elevatorguy 0:f86e6135dcbc 866
elevatorguy 0:f86e6135dcbc 867 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
elevatorguy 0:f86e6135dcbc 868 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
elevatorguy 0:f86e6135dcbc 869
elevatorguy 0:f86e6135dcbc 870 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
elevatorguy 0:f86e6135dcbc 871 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
elevatorguy 0:f86e6135dcbc 872
elevatorguy 0:f86e6135dcbc 873 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
elevatorguy 0:f86e6135dcbc 874 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
elevatorguy 0:f86e6135dcbc 875
elevatorguy 0:f86e6135dcbc 876 /* TPI Formatter and Flush Control Register Definitions */
elevatorguy 0:f86e6135dcbc 877 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
elevatorguy 0:f86e6135dcbc 878 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
elevatorguy 0:f86e6135dcbc 879
elevatorguy 0:f86e6135dcbc 880 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
elevatorguy 0:f86e6135dcbc 881 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
elevatorguy 0:f86e6135dcbc 882
elevatorguy 0:f86e6135dcbc 883 /* TPI TRIGGER Register Definitions */
elevatorguy 0:f86e6135dcbc 884 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
elevatorguy 0:f86e6135dcbc 885 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
elevatorguy 0:f86e6135dcbc 886
elevatorguy 0:f86e6135dcbc 887 /* TPI Integration ETM Data Register Definitions (FIFO0) */
elevatorguy 0:f86e6135dcbc 888 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
elevatorguy 0:f86e6135dcbc 889 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
elevatorguy 0:f86e6135dcbc 890
elevatorguy 0:f86e6135dcbc 891 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
elevatorguy 0:f86e6135dcbc 892 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
elevatorguy 0:f86e6135dcbc 893
elevatorguy 0:f86e6135dcbc 894 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
elevatorguy 0:f86e6135dcbc 895 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
elevatorguy 0:f86e6135dcbc 896
elevatorguy 0:f86e6135dcbc 897 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
elevatorguy 0:f86e6135dcbc 898 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
elevatorguy 0:f86e6135dcbc 899
elevatorguy 0:f86e6135dcbc 900 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
elevatorguy 0:f86e6135dcbc 901 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
elevatorguy 0:f86e6135dcbc 902
elevatorguy 0:f86e6135dcbc 903 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
elevatorguy 0:f86e6135dcbc 904 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
elevatorguy 0:f86e6135dcbc 905
elevatorguy 0:f86e6135dcbc 906 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
elevatorguy 0:f86e6135dcbc 907 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
elevatorguy 0:f86e6135dcbc 908
elevatorguy 0:f86e6135dcbc 909 /* TPI ITATBCTR2 Register Definitions */
elevatorguy 0:f86e6135dcbc 910 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
elevatorguy 0:f86e6135dcbc 911 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
elevatorguy 0:f86e6135dcbc 912
elevatorguy 0:f86e6135dcbc 913 /* TPI Integration ITM Data Register Definitions (FIFO1) */
elevatorguy 0:f86e6135dcbc 914 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
elevatorguy 0:f86e6135dcbc 915 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
elevatorguy 0:f86e6135dcbc 916
elevatorguy 0:f86e6135dcbc 917 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
elevatorguy 0:f86e6135dcbc 918 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
elevatorguy 0:f86e6135dcbc 919
elevatorguy 0:f86e6135dcbc 920 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
elevatorguy 0:f86e6135dcbc 921 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
elevatorguy 0:f86e6135dcbc 922
elevatorguy 0:f86e6135dcbc 923 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
elevatorguy 0:f86e6135dcbc 924 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
elevatorguy 0:f86e6135dcbc 925
elevatorguy 0:f86e6135dcbc 926 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
elevatorguy 0:f86e6135dcbc 927 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
elevatorguy 0:f86e6135dcbc 928
elevatorguy 0:f86e6135dcbc 929 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
elevatorguy 0:f86e6135dcbc 930 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
elevatorguy 0:f86e6135dcbc 931
elevatorguy 0:f86e6135dcbc 932 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
elevatorguy 0:f86e6135dcbc 933 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
elevatorguy 0:f86e6135dcbc 934
elevatorguy 0:f86e6135dcbc 935 /* TPI ITATBCTR0 Register Definitions */
elevatorguy 0:f86e6135dcbc 936 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
elevatorguy 0:f86e6135dcbc 937 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
elevatorguy 0:f86e6135dcbc 938
elevatorguy 0:f86e6135dcbc 939 /* TPI Integration Mode Control Register Definitions */
elevatorguy 0:f86e6135dcbc 940 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
elevatorguy 0:f86e6135dcbc 941 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
elevatorguy 0:f86e6135dcbc 942
elevatorguy 0:f86e6135dcbc 943 /* TPI DEVID Register Definitions */
elevatorguy 0:f86e6135dcbc 944 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
elevatorguy 0:f86e6135dcbc 945 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
elevatorguy 0:f86e6135dcbc 946
elevatorguy 0:f86e6135dcbc 947 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
elevatorguy 0:f86e6135dcbc 948 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
elevatorguy 0:f86e6135dcbc 949
elevatorguy 0:f86e6135dcbc 950 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
elevatorguy 0:f86e6135dcbc 951 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
elevatorguy 0:f86e6135dcbc 952
elevatorguy 0:f86e6135dcbc 953 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
elevatorguy 0:f86e6135dcbc 954 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
elevatorguy 0:f86e6135dcbc 955
elevatorguy 0:f86e6135dcbc 956 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
elevatorguy 0:f86e6135dcbc 957 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
elevatorguy 0:f86e6135dcbc 958
elevatorguy 0:f86e6135dcbc 959 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
elevatorguy 0:f86e6135dcbc 960 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
elevatorguy 0:f86e6135dcbc 961
elevatorguy 0:f86e6135dcbc 962 /* TPI DEVTYPE Register Definitions */
elevatorguy 0:f86e6135dcbc 963 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
elevatorguy 0:f86e6135dcbc 964 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
elevatorguy 0:f86e6135dcbc 965
elevatorguy 0:f86e6135dcbc 966 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
elevatorguy 0:f86e6135dcbc 967 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
elevatorguy 0:f86e6135dcbc 968
elevatorguy 0:f86e6135dcbc 969 /*@}*/ /* end of group CMSIS_TPI */
elevatorguy 0:f86e6135dcbc 970
elevatorguy 0:f86e6135dcbc 971
elevatorguy 0:f86e6135dcbc 972 #if (__MPU_PRESENT == 1)
elevatorguy 0:f86e6135dcbc 973 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 974 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
elevatorguy 0:f86e6135dcbc 975 \brief Type definitions for the Memory Protection Unit (MPU)
elevatorguy 0:f86e6135dcbc 976 @{
elevatorguy 0:f86e6135dcbc 977 */
elevatorguy 0:f86e6135dcbc 978
elevatorguy 0:f86e6135dcbc 979 /** \brief Structure type to access the Memory Protection Unit (MPU).
elevatorguy 0:f86e6135dcbc 980 */
elevatorguy 0:f86e6135dcbc 981 typedef struct
elevatorguy 0:f86e6135dcbc 982 {
elevatorguy 0:f86e6135dcbc 983 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
elevatorguy 0:f86e6135dcbc 984 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
elevatorguy 0:f86e6135dcbc 985 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
elevatorguy 0:f86e6135dcbc 986 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
elevatorguy 0:f86e6135dcbc 987 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
elevatorguy 0:f86e6135dcbc 988 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
elevatorguy 0:f86e6135dcbc 989 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
elevatorguy 0:f86e6135dcbc 990 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
elevatorguy 0:f86e6135dcbc 991 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
elevatorguy 0:f86e6135dcbc 992 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
elevatorguy 0:f86e6135dcbc 993 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
elevatorguy 0:f86e6135dcbc 994 } MPU_Type;
elevatorguy 0:f86e6135dcbc 995
elevatorguy 0:f86e6135dcbc 996 /* MPU Type Register */
elevatorguy 0:f86e6135dcbc 997 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
elevatorguy 0:f86e6135dcbc 998 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
elevatorguy 0:f86e6135dcbc 999
elevatorguy 0:f86e6135dcbc 1000 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
elevatorguy 0:f86e6135dcbc 1001 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
elevatorguy 0:f86e6135dcbc 1002
elevatorguy 0:f86e6135dcbc 1003 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
elevatorguy 0:f86e6135dcbc 1004 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
elevatorguy 0:f86e6135dcbc 1005
elevatorguy 0:f86e6135dcbc 1006 /* MPU Control Register */
elevatorguy 0:f86e6135dcbc 1007 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
elevatorguy 0:f86e6135dcbc 1008 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
elevatorguy 0:f86e6135dcbc 1009
elevatorguy 0:f86e6135dcbc 1010 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
elevatorguy 0:f86e6135dcbc 1011 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
elevatorguy 0:f86e6135dcbc 1012
elevatorguy 0:f86e6135dcbc 1013 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
elevatorguy 0:f86e6135dcbc 1014 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
elevatorguy 0:f86e6135dcbc 1015
elevatorguy 0:f86e6135dcbc 1016 /* MPU Region Number Register */
elevatorguy 0:f86e6135dcbc 1017 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
elevatorguy 0:f86e6135dcbc 1018 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
elevatorguy 0:f86e6135dcbc 1019
elevatorguy 0:f86e6135dcbc 1020 /* MPU Region Base Address Register */
elevatorguy 0:f86e6135dcbc 1021 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
elevatorguy 0:f86e6135dcbc 1022 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
elevatorguy 0:f86e6135dcbc 1023
elevatorguy 0:f86e6135dcbc 1024 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
elevatorguy 0:f86e6135dcbc 1025 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
elevatorguy 0:f86e6135dcbc 1026
elevatorguy 0:f86e6135dcbc 1027 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
elevatorguy 0:f86e6135dcbc 1028 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
elevatorguy 0:f86e6135dcbc 1029
elevatorguy 0:f86e6135dcbc 1030 /* MPU Region Attribute and Size Register */
elevatorguy 0:f86e6135dcbc 1031 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
elevatorguy 0:f86e6135dcbc 1032 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
elevatorguy 0:f86e6135dcbc 1033
elevatorguy 0:f86e6135dcbc 1034 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
elevatorguy 0:f86e6135dcbc 1035 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
elevatorguy 0:f86e6135dcbc 1036
elevatorguy 0:f86e6135dcbc 1037 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
elevatorguy 0:f86e6135dcbc 1038 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
elevatorguy 0:f86e6135dcbc 1039
elevatorguy 0:f86e6135dcbc 1040 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
elevatorguy 0:f86e6135dcbc 1041 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
elevatorguy 0:f86e6135dcbc 1042
elevatorguy 0:f86e6135dcbc 1043 /*@} end of group CMSIS_MPU */
elevatorguy 0:f86e6135dcbc 1044 #endif
elevatorguy 0:f86e6135dcbc 1045
elevatorguy 0:f86e6135dcbc 1046
elevatorguy 0:f86e6135dcbc 1047 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 1048 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
elevatorguy 0:f86e6135dcbc 1049 \brief Type definitions for the Core Debug Registers
elevatorguy 0:f86e6135dcbc 1050 @{
elevatorguy 0:f86e6135dcbc 1051 */
elevatorguy 0:f86e6135dcbc 1052
elevatorguy 0:f86e6135dcbc 1053 /** \brief Structure type to access the Core Debug Register (CoreDebug).
elevatorguy 0:f86e6135dcbc 1054 */
elevatorguy 0:f86e6135dcbc 1055 typedef struct
elevatorguy 0:f86e6135dcbc 1056 {
elevatorguy 0:f86e6135dcbc 1057 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
elevatorguy 0:f86e6135dcbc 1058 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
elevatorguy 0:f86e6135dcbc 1059 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
elevatorguy 0:f86e6135dcbc 1060 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
elevatorguy 0:f86e6135dcbc 1061 } CoreDebug_Type;
elevatorguy 0:f86e6135dcbc 1062
elevatorguy 0:f86e6135dcbc 1063 /* Debug Halting Control and Status Register */
elevatorguy 0:f86e6135dcbc 1064 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
elevatorguy 0:f86e6135dcbc 1065 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
elevatorguy 0:f86e6135dcbc 1066
elevatorguy 0:f86e6135dcbc 1067 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
elevatorguy 0:f86e6135dcbc 1068 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
elevatorguy 0:f86e6135dcbc 1069
elevatorguy 0:f86e6135dcbc 1070 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
elevatorguy 0:f86e6135dcbc 1071 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
elevatorguy 0:f86e6135dcbc 1072
elevatorguy 0:f86e6135dcbc 1073 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
elevatorguy 0:f86e6135dcbc 1074 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
elevatorguy 0:f86e6135dcbc 1075
elevatorguy 0:f86e6135dcbc 1076 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
elevatorguy 0:f86e6135dcbc 1077 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
elevatorguy 0:f86e6135dcbc 1078
elevatorguy 0:f86e6135dcbc 1079 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
elevatorguy 0:f86e6135dcbc 1080 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
elevatorguy 0:f86e6135dcbc 1081
elevatorguy 0:f86e6135dcbc 1082 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
elevatorguy 0:f86e6135dcbc 1083 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
elevatorguy 0:f86e6135dcbc 1084
elevatorguy 0:f86e6135dcbc 1085 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
elevatorguy 0:f86e6135dcbc 1086 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
elevatorguy 0:f86e6135dcbc 1087
elevatorguy 0:f86e6135dcbc 1088 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
elevatorguy 0:f86e6135dcbc 1089 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
elevatorguy 0:f86e6135dcbc 1090
elevatorguy 0:f86e6135dcbc 1091 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
elevatorguy 0:f86e6135dcbc 1092 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
elevatorguy 0:f86e6135dcbc 1093
elevatorguy 0:f86e6135dcbc 1094 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
elevatorguy 0:f86e6135dcbc 1095 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
elevatorguy 0:f86e6135dcbc 1096
elevatorguy 0:f86e6135dcbc 1097 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
elevatorguy 0:f86e6135dcbc 1098 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
elevatorguy 0:f86e6135dcbc 1099
elevatorguy 0:f86e6135dcbc 1100 /* Debug Core Register Selector Register */
elevatorguy 0:f86e6135dcbc 1101 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
elevatorguy 0:f86e6135dcbc 1102 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
elevatorguy 0:f86e6135dcbc 1103
elevatorguy 0:f86e6135dcbc 1104 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
elevatorguy 0:f86e6135dcbc 1105 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
elevatorguy 0:f86e6135dcbc 1106
elevatorguy 0:f86e6135dcbc 1107 /* Debug Exception and Monitor Control Register */
elevatorguy 0:f86e6135dcbc 1108 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
elevatorguy 0:f86e6135dcbc 1109 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
elevatorguy 0:f86e6135dcbc 1110
elevatorguy 0:f86e6135dcbc 1111 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
elevatorguy 0:f86e6135dcbc 1112 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
elevatorguy 0:f86e6135dcbc 1113
elevatorguy 0:f86e6135dcbc 1114 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
elevatorguy 0:f86e6135dcbc 1115 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
elevatorguy 0:f86e6135dcbc 1116
elevatorguy 0:f86e6135dcbc 1117 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
elevatorguy 0:f86e6135dcbc 1118 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
elevatorguy 0:f86e6135dcbc 1119
elevatorguy 0:f86e6135dcbc 1120 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
elevatorguy 0:f86e6135dcbc 1121 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
elevatorguy 0:f86e6135dcbc 1122
elevatorguy 0:f86e6135dcbc 1123 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
elevatorguy 0:f86e6135dcbc 1124 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
elevatorguy 0:f86e6135dcbc 1125
elevatorguy 0:f86e6135dcbc 1126 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
elevatorguy 0:f86e6135dcbc 1127 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
elevatorguy 0:f86e6135dcbc 1128
elevatorguy 0:f86e6135dcbc 1129 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
elevatorguy 0:f86e6135dcbc 1130 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
elevatorguy 0:f86e6135dcbc 1131
elevatorguy 0:f86e6135dcbc 1132 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
elevatorguy 0:f86e6135dcbc 1133 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
elevatorguy 0:f86e6135dcbc 1134
elevatorguy 0:f86e6135dcbc 1135 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
elevatorguy 0:f86e6135dcbc 1136 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
elevatorguy 0:f86e6135dcbc 1137
elevatorguy 0:f86e6135dcbc 1138 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
elevatorguy 0:f86e6135dcbc 1139 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
elevatorguy 0:f86e6135dcbc 1140
elevatorguy 0:f86e6135dcbc 1141 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
elevatorguy 0:f86e6135dcbc 1142 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
elevatorguy 0:f86e6135dcbc 1143
elevatorguy 0:f86e6135dcbc 1144 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
elevatorguy 0:f86e6135dcbc 1145 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
elevatorguy 0:f86e6135dcbc 1146
elevatorguy 0:f86e6135dcbc 1147 /*@} end of group CMSIS_CoreDebug */
elevatorguy 0:f86e6135dcbc 1148
elevatorguy 0:f86e6135dcbc 1149
elevatorguy 0:f86e6135dcbc 1150 /** \ingroup CMSIS_core_register
elevatorguy 0:f86e6135dcbc 1151 \defgroup CMSIS_core_base Core Definitions
elevatorguy 0:f86e6135dcbc 1152 \brief Definitions for base addresses, unions, and structures.
elevatorguy 0:f86e6135dcbc 1153 @{
elevatorguy 0:f86e6135dcbc 1154 */
elevatorguy 0:f86e6135dcbc 1155
elevatorguy 0:f86e6135dcbc 1156 /* Memory mapping of Cortex-M3 Hardware */
elevatorguy 0:f86e6135dcbc 1157 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
elevatorguy 0:f86e6135dcbc 1158 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
elevatorguy 0:f86e6135dcbc 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
elevatorguy 0:f86e6135dcbc 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
elevatorguy 0:f86e6135dcbc 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
elevatorguy 0:f86e6135dcbc 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
elevatorguy 0:f86e6135dcbc 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
elevatorguy 0:f86e6135dcbc 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
elevatorguy 0:f86e6135dcbc 1165
elevatorguy 0:f86e6135dcbc 1166 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
elevatorguy 0:f86e6135dcbc 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
elevatorguy 0:f86e6135dcbc 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
elevatorguy 0:f86e6135dcbc 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
elevatorguy 0:f86e6135dcbc 1170 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
elevatorguy 0:f86e6135dcbc 1171 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
elevatorguy 0:f86e6135dcbc 1172 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
elevatorguy 0:f86e6135dcbc 1173 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
elevatorguy 0:f86e6135dcbc 1174
elevatorguy 0:f86e6135dcbc 1175 #if (__MPU_PRESENT == 1)
elevatorguy 0:f86e6135dcbc 1176 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
elevatorguy 0:f86e6135dcbc 1177 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
elevatorguy 0:f86e6135dcbc 1178 #endif
elevatorguy 0:f86e6135dcbc 1179
elevatorguy 0:f86e6135dcbc 1180 /*@} */
elevatorguy 0:f86e6135dcbc 1181
elevatorguy 0:f86e6135dcbc 1182
elevatorguy 0:f86e6135dcbc 1183
elevatorguy 0:f86e6135dcbc 1184 /*******************************************************************************
elevatorguy 0:f86e6135dcbc 1185 * Hardware Abstraction Layer
elevatorguy 0:f86e6135dcbc 1186 Core Function Interface contains:
elevatorguy 0:f86e6135dcbc 1187 - Core NVIC Functions
elevatorguy 0:f86e6135dcbc 1188 - Core SysTick Functions
elevatorguy 0:f86e6135dcbc 1189 - Core Debug Functions
elevatorguy 0:f86e6135dcbc 1190 - Core Register Access Functions
elevatorguy 0:f86e6135dcbc 1191 ******************************************************************************/
elevatorguy 0:f86e6135dcbc 1192 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
elevatorguy 0:f86e6135dcbc 1193 */
elevatorguy 0:f86e6135dcbc 1194
elevatorguy 0:f86e6135dcbc 1195
elevatorguy 0:f86e6135dcbc 1196
elevatorguy 0:f86e6135dcbc 1197 /* ########################## NVIC functions #################################### */
elevatorguy 0:f86e6135dcbc 1198 /** \ingroup CMSIS_Core_FunctionInterface
elevatorguy 0:f86e6135dcbc 1199 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
elevatorguy 0:f86e6135dcbc 1200 \brief Functions that manage interrupts and exceptions via the NVIC.
elevatorguy 0:f86e6135dcbc 1201 @{
elevatorguy 0:f86e6135dcbc 1202 */
elevatorguy 0:f86e6135dcbc 1203
elevatorguy 0:f86e6135dcbc 1204 /** \brief Set Priority Grouping
elevatorguy 0:f86e6135dcbc 1205
elevatorguy 0:f86e6135dcbc 1206 The function sets the priority grouping field using the required unlock sequence.
elevatorguy 0:f86e6135dcbc 1207 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
elevatorguy 0:f86e6135dcbc 1208 Only values from 0..7 are used.
elevatorguy 0:f86e6135dcbc 1209 In case of a conflict between priority grouping and available
elevatorguy 0:f86e6135dcbc 1210 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
elevatorguy 0:f86e6135dcbc 1211
elevatorguy 0:f86e6135dcbc 1212 \param [in] PriorityGroup Priority grouping field.
elevatorguy 0:f86e6135dcbc 1213 */
elevatorguy 0:f86e6135dcbc 1214 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
elevatorguy 0:f86e6135dcbc 1215 {
elevatorguy 0:f86e6135dcbc 1216 uint32_t reg_value;
elevatorguy 0:f86e6135dcbc 1217 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
elevatorguy 0:f86e6135dcbc 1218
elevatorguy 0:f86e6135dcbc 1219 reg_value = SCB->AIRCR; /* read old register configuration */
elevatorguy 0:f86e6135dcbc 1220 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
elevatorguy 0:f86e6135dcbc 1221 reg_value = (reg_value |
elevatorguy 0:f86e6135dcbc 1222 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
elevatorguy 0:f86e6135dcbc 1223 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
elevatorguy 0:f86e6135dcbc 1224 SCB->AIRCR = reg_value;
elevatorguy 0:f86e6135dcbc 1225 }
elevatorguy 0:f86e6135dcbc 1226
elevatorguy 0:f86e6135dcbc 1227
elevatorguy 0:f86e6135dcbc 1228 /** \brief Get Priority Grouping
elevatorguy 0:f86e6135dcbc 1229
elevatorguy 0:f86e6135dcbc 1230 The function reads the priority grouping field from the NVIC Interrupt Controller.
elevatorguy 0:f86e6135dcbc 1231
elevatorguy 0:f86e6135dcbc 1232 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
elevatorguy 0:f86e6135dcbc 1233 */
elevatorguy 0:f86e6135dcbc 1234 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
elevatorguy 0:f86e6135dcbc 1235 {
elevatorguy 0:f86e6135dcbc 1236 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
elevatorguy 0:f86e6135dcbc 1237 }
elevatorguy 0:f86e6135dcbc 1238
elevatorguy 0:f86e6135dcbc 1239
elevatorguy 0:f86e6135dcbc 1240 /** \brief Enable External Interrupt
elevatorguy 0:f86e6135dcbc 1241
elevatorguy 0:f86e6135dcbc 1242 The function enables a device-specific interrupt in the NVIC interrupt controller.
elevatorguy 0:f86e6135dcbc 1243
elevatorguy 0:f86e6135dcbc 1244 \param [in] IRQn External interrupt number. Value cannot be negative.
elevatorguy 0:f86e6135dcbc 1245 */
elevatorguy 0:f86e6135dcbc 1246 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1247 {
elevatorguy 0:f86e6135dcbc 1248 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
elevatorguy 0:f86e6135dcbc 1249 }
elevatorguy 0:f86e6135dcbc 1250
elevatorguy 0:f86e6135dcbc 1251
elevatorguy 0:f86e6135dcbc 1252 /** \brief Disable External Interrupt
elevatorguy 0:f86e6135dcbc 1253
elevatorguy 0:f86e6135dcbc 1254 The function disables a device-specific interrupt in the NVIC interrupt controller.
elevatorguy 0:f86e6135dcbc 1255
elevatorguy 0:f86e6135dcbc 1256 \param [in] IRQn External interrupt number. Value cannot be negative.
elevatorguy 0:f86e6135dcbc 1257 */
elevatorguy 0:f86e6135dcbc 1258 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1259 {
elevatorguy 0:f86e6135dcbc 1260 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
elevatorguy 0:f86e6135dcbc 1261 }
elevatorguy 0:f86e6135dcbc 1262
elevatorguy 0:f86e6135dcbc 1263
elevatorguy 0:f86e6135dcbc 1264 /** \brief Get Pending Interrupt
elevatorguy 0:f86e6135dcbc 1265
elevatorguy 0:f86e6135dcbc 1266 The function reads the pending register in the NVIC and returns the pending bit
elevatorguy 0:f86e6135dcbc 1267 for the specified interrupt.
elevatorguy 0:f86e6135dcbc 1268
elevatorguy 0:f86e6135dcbc 1269 \param [in] IRQn Interrupt number.
elevatorguy 0:f86e6135dcbc 1270
elevatorguy 0:f86e6135dcbc 1271 \return 0 Interrupt status is not pending.
elevatorguy 0:f86e6135dcbc 1272 \return 1 Interrupt status is pending.
elevatorguy 0:f86e6135dcbc 1273 */
elevatorguy 0:f86e6135dcbc 1274 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1275 {
elevatorguy 0:f86e6135dcbc 1276 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
elevatorguy 0:f86e6135dcbc 1277 }
elevatorguy 0:f86e6135dcbc 1278
elevatorguy 0:f86e6135dcbc 1279
elevatorguy 0:f86e6135dcbc 1280 /** \brief Set Pending Interrupt
elevatorguy 0:f86e6135dcbc 1281
elevatorguy 0:f86e6135dcbc 1282 The function sets the pending bit of an external interrupt.
elevatorguy 0:f86e6135dcbc 1283
elevatorguy 0:f86e6135dcbc 1284 \param [in] IRQn Interrupt number. Value cannot be negative.
elevatorguy 0:f86e6135dcbc 1285 */
elevatorguy 0:f86e6135dcbc 1286 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1287 {
elevatorguy 0:f86e6135dcbc 1288 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
elevatorguy 0:f86e6135dcbc 1289 }
elevatorguy 0:f86e6135dcbc 1290
elevatorguy 0:f86e6135dcbc 1291
elevatorguy 0:f86e6135dcbc 1292 /** \brief Clear Pending Interrupt
elevatorguy 0:f86e6135dcbc 1293
elevatorguy 0:f86e6135dcbc 1294 The function clears the pending bit of an external interrupt.
elevatorguy 0:f86e6135dcbc 1295
elevatorguy 0:f86e6135dcbc 1296 \param [in] IRQn External interrupt number. Value cannot be negative.
elevatorguy 0:f86e6135dcbc 1297 */
elevatorguy 0:f86e6135dcbc 1298 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1299 {
elevatorguy 0:f86e6135dcbc 1300 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
elevatorguy 0:f86e6135dcbc 1301 }
elevatorguy 0:f86e6135dcbc 1302
elevatorguy 0:f86e6135dcbc 1303
elevatorguy 0:f86e6135dcbc 1304 /** \brief Get Active Interrupt
elevatorguy 0:f86e6135dcbc 1305
elevatorguy 0:f86e6135dcbc 1306 The function reads the active register in NVIC and returns the active bit.
elevatorguy 0:f86e6135dcbc 1307
elevatorguy 0:f86e6135dcbc 1308 \param [in] IRQn Interrupt number.
elevatorguy 0:f86e6135dcbc 1309
elevatorguy 0:f86e6135dcbc 1310 \return 0 Interrupt status is not active.
elevatorguy 0:f86e6135dcbc 1311 \return 1 Interrupt status is active.
elevatorguy 0:f86e6135dcbc 1312 */
elevatorguy 0:f86e6135dcbc 1313 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1314 {
elevatorguy 0:f86e6135dcbc 1315 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
elevatorguy 0:f86e6135dcbc 1316 }
elevatorguy 0:f86e6135dcbc 1317
elevatorguy 0:f86e6135dcbc 1318
elevatorguy 0:f86e6135dcbc 1319 /** \brief Set Interrupt Priority
elevatorguy 0:f86e6135dcbc 1320
elevatorguy 0:f86e6135dcbc 1321 The function sets the priority of an interrupt.
elevatorguy 0:f86e6135dcbc 1322
elevatorguy 0:f86e6135dcbc 1323 \note The priority cannot be set for every core interrupt.
elevatorguy 0:f86e6135dcbc 1324
elevatorguy 0:f86e6135dcbc 1325 \param [in] IRQn Interrupt number.
elevatorguy 0:f86e6135dcbc 1326 \param [in] priority Priority to set.
elevatorguy 0:f86e6135dcbc 1327 */
elevatorguy 0:f86e6135dcbc 1328 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
elevatorguy 0:f86e6135dcbc 1329 {
elevatorguy 0:f86e6135dcbc 1330 if(IRQn < 0) {
elevatorguy 0:f86e6135dcbc 1331 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
elevatorguy 0:f86e6135dcbc 1332 else {
elevatorguy 0:f86e6135dcbc 1333 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
elevatorguy 0:f86e6135dcbc 1334 }
elevatorguy 0:f86e6135dcbc 1335
elevatorguy 0:f86e6135dcbc 1336
elevatorguy 0:f86e6135dcbc 1337 /** \brief Get Interrupt Priority
elevatorguy 0:f86e6135dcbc 1338
elevatorguy 0:f86e6135dcbc 1339 The function reads the priority of an interrupt. The interrupt
elevatorguy 0:f86e6135dcbc 1340 number can be positive to specify an external (device specific)
elevatorguy 0:f86e6135dcbc 1341 interrupt, or negative to specify an internal (core) interrupt.
elevatorguy 0:f86e6135dcbc 1342
elevatorguy 0:f86e6135dcbc 1343
elevatorguy 0:f86e6135dcbc 1344 \param [in] IRQn Interrupt number.
elevatorguy 0:f86e6135dcbc 1345 \return Interrupt Priority. Value is aligned automatically to the implemented
elevatorguy 0:f86e6135dcbc 1346 priority bits of the microcontroller.
elevatorguy 0:f86e6135dcbc 1347 */
elevatorguy 0:f86e6135dcbc 1348 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
elevatorguy 0:f86e6135dcbc 1349 {
elevatorguy 0:f86e6135dcbc 1350
elevatorguy 0:f86e6135dcbc 1351 if(IRQn < 0) {
elevatorguy 0:f86e6135dcbc 1352 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
elevatorguy 0:f86e6135dcbc 1353 else {
elevatorguy 0:f86e6135dcbc 1354 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
elevatorguy 0:f86e6135dcbc 1355 }
elevatorguy 0:f86e6135dcbc 1356
elevatorguy 0:f86e6135dcbc 1357
elevatorguy 0:f86e6135dcbc 1358 /** \brief Encode Priority
elevatorguy 0:f86e6135dcbc 1359
elevatorguy 0:f86e6135dcbc 1360 The function encodes the priority for an interrupt with the given priority group,
elevatorguy 0:f86e6135dcbc 1361 preemptive priority value, and subpriority value.
elevatorguy 0:f86e6135dcbc 1362 In case of a conflict between priority grouping and available
elevatorguy 0:f86e6135dcbc 1363 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
elevatorguy 0:f86e6135dcbc 1364
elevatorguy 0:f86e6135dcbc 1365 \param [in] PriorityGroup Used priority group.
elevatorguy 0:f86e6135dcbc 1366 \param [in] PreemptPriority Preemptive priority value (starting from 0).
elevatorguy 0:f86e6135dcbc 1367 \param [in] SubPriority Subpriority value (starting from 0).
elevatorguy 0:f86e6135dcbc 1368 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
elevatorguy 0:f86e6135dcbc 1369 */
elevatorguy 0:f86e6135dcbc 1370 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
elevatorguy 0:f86e6135dcbc 1371 {
elevatorguy 0:f86e6135dcbc 1372 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
elevatorguy 0:f86e6135dcbc 1373 uint32_t PreemptPriorityBits;
elevatorguy 0:f86e6135dcbc 1374 uint32_t SubPriorityBits;
elevatorguy 0:f86e6135dcbc 1375
elevatorguy 0:f86e6135dcbc 1376 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
elevatorguy 0:f86e6135dcbc 1377 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
elevatorguy 0:f86e6135dcbc 1378
elevatorguy 0:f86e6135dcbc 1379 return (
elevatorguy 0:f86e6135dcbc 1380 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
elevatorguy 0:f86e6135dcbc 1381 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
elevatorguy 0:f86e6135dcbc 1382 );
elevatorguy 0:f86e6135dcbc 1383 }
elevatorguy 0:f86e6135dcbc 1384
elevatorguy 0:f86e6135dcbc 1385
elevatorguy 0:f86e6135dcbc 1386 /** \brief Decode Priority
elevatorguy 0:f86e6135dcbc 1387
elevatorguy 0:f86e6135dcbc 1388 The function decodes an interrupt priority value with a given priority group to
elevatorguy 0:f86e6135dcbc 1389 preemptive priority value and subpriority value.
elevatorguy 0:f86e6135dcbc 1390 In case of a conflict between priority grouping and available
elevatorguy 0:f86e6135dcbc 1391 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
elevatorguy 0:f86e6135dcbc 1392
elevatorguy 0:f86e6135dcbc 1393 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
elevatorguy 0:f86e6135dcbc 1394 \param [in] PriorityGroup Used priority group.
elevatorguy 0:f86e6135dcbc 1395 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
elevatorguy 0:f86e6135dcbc 1396 \param [out] pSubPriority Subpriority value (starting from 0).
elevatorguy 0:f86e6135dcbc 1397 */
elevatorguy 0:f86e6135dcbc 1398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
elevatorguy 0:f86e6135dcbc 1399 {
elevatorguy 0:f86e6135dcbc 1400 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
elevatorguy 0:f86e6135dcbc 1401 uint32_t PreemptPriorityBits;
elevatorguy 0:f86e6135dcbc 1402 uint32_t SubPriorityBits;
elevatorguy 0:f86e6135dcbc 1403
elevatorguy 0:f86e6135dcbc 1404 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
elevatorguy 0:f86e6135dcbc 1405 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
elevatorguy 0:f86e6135dcbc 1406
elevatorguy 0:f86e6135dcbc 1407 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
elevatorguy 0:f86e6135dcbc 1408 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
elevatorguy 0:f86e6135dcbc 1409 }
elevatorguy 0:f86e6135dcbc 1410
elevatorguy 0:f86e6135dcbc 1411
elevatorguy 0:f86e6135dcbc 1412 /** \brief System Reset
elevatorguy 0:f86e6135dcbc 1413
elevatorguy 0:f86e6135dcbc 1414 The function initiates a system reset request to reset the MCU.
elevatorguy 0:f86e6135dcbc 1415 */
elevatorguy 0:f86e6135dcbc 1416 __STATIC_INLINE void NVIC_SystemReset(void)
elevatorguy 0:f86e6135dcbc 1417 {
elevatorguy 0:f86e6135dcbc 1418 __DSB(); /* Ensure all outstanding memory accesses included
elevatorguy 0:f86e6135dcbc 1419 buffered write are completed before reset */
elevatorguy 0:f86e6135dcbc 1420 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
elevatorguy 0:f86e6135dcbc 1421 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
elevatorguy 0:f86e6135dcbc 1422 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
elevatorguy 0:f86e6135dcbc 1423 __DSB(); /* Ensure completion of memory access */
elevatorguy 0:f86e6135dcbc 1424 while(1); /* wait until reset */
elevatorguy 0:f86e6135dcbc 1425 }
elevatorguy 0:f86e6135dcbc 1426
elevatorguy 0:f86e6135dcbc 1427 /*@} end of CMSIS_Core_NVICFunctions */
elevatorguy 0:f86e6135dcbc 1428
elevatorguy 0:f86e6135dcbc 1429
elevatorguy 0:f86e6135dcbc 1430
elevatorguy 0:f86e6135dcbc 1431 /* ################################## SysTick function ############################################ */
elevatorguy 0:f86e6135dcbc 1432 /** \ingroup CMSIS_Core_FunctionInterface
elevatorguy 0:f86e6135dcbc 1433 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
elevatorguy 0:f86e6135dcbc 1434 \brief Functions that configure the System.
elevatorguy 0:f86e6135dcbc 1435 @{
elevatorguy 0:f86e6135dcbc 1436 */
elevatorguy 0:f86e6135dcbc 1437
elevatorguy 0:f86e6135dcbc 1438 #if (__Vendor_SysTickConfig == 0)
elevatorguy 0:f86e6135dcbc 1439
elevatorguy 0:f86e6135dcbc 1440 /** \brief System Tick Configuration
elevatorguy 0:f86e6135dcbc 1441
elevatorguy 0:f86e6135dcbc 1442 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
elevatorguy 0:f86e6135dcbc 1443 Counter is in free running mode to generate periodic interrupts.
elevatorguy 0:f86e6135dcbc 1444
elevatorguy 0:f86e6135dcbc 1445 \param [in] ticks Number of ticks between two interrupts.
elevatorguy 0:f86e6135dcbc 1446
elevatorguy 0:f86e6135dcbc 1447 \return 0 Function succeeded.
elevatorguy 0:f86e6135dcbc 1448 \return 1 Function failed.
elevatorguy 0:f86e6135dcbc 1449
elevatorguy 0:f86e6135dcbc 1450 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
elevatorguy 0:f86e6135dcbc 1451 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
elevatorguy 0:f86e6135dcbc 1452 must contain a vendor-specific implementation of this function.
elevatorguy 0:f86e6135dcbc 1453
elevatorguy 0:f86e6135dcbc 1454 */
elevatorguy 0:f86e6135dcbc 1455 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
elevatorguy 0:f86e6135dcbc 1456 {
elevatorguy 0:f86e6135dcbc 1457 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
elevatorguy 0:f86e6135dcbc 1458
elevatorguy 0:f86e6135dcbc 1459 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
elevatorguy 0:f86e6135dcbc 1460 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
elevatorguy 0:f86e6135dcbc 1461 SysTick->VAL = 0; /* Load the SysTick Counter Value */
elevatorguy 0:f86e6135dcbc 1462 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
elevatorguy 0:f86e6135dcbc 1463 SysTick_CTRL_TICKINT_Msk |
elevatorguy 0:f86e6135dcbc 1464 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
elevatorguy 0:f86e6135dcbc 1465 return (0); /* Function successful */
elevatorguy 0:f86e6135dcbc 1466 }
elevatorguy 0:f86e6135dcbc 1467
elevatorguy 0:f86e6135dcbc 1468 #endif
elevatorguy 0:f86e6135dcbc 1469
elevatorguy 0:f86e6135dcbc 1470 /*@} end of CMSIS_Core_SysTickFunctions */
elevatorguy 0:f86e6135dcbc 1471
elevatorguy 0:f86e6135dcbc 1472
elevatorguy 0:f86e6135dcbc 1473
elevatorguy 0:f86e6135dcbc 1474 /* ##################################### Debug In/Output function ########################################### */
elevatorguy 0:f86e6135dcbc 1475 /** \ingroup CMSIS_Core_FunctionInterface
elevatorguy 0:f86e6135dcbc 1476 \defgroup CMSIS_core_DebugFunctions ITM Functions
elevatorguy 0:f86e6135dcbc 1477 \brief Functions that access the ITM debug interface.
elevatorguy 0:f86e6135dcbc 1478 @{
elevatorguy 0:f86e6135dcbc 1479 */
elevatorguy 0:f86e6135dcbc 1480
elevatorguy 0:f86e6135dcbc 1481 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
elevatorguy 0:f86e6135dcbc 1482 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
elevatorguy 0:f86e6135dcbc 1483
elevatorguy 0:f86e6135dcbc 1484
elevatorguy 0:f86e6135dcbc 1485 /** \brief ITM Send Character
elevatorguy 0:f86e6135dcbc 1486
elevatorguy 0:f86e6135dcbc 1487 The function transmits a character via the ITM channel 0, and
elevatorguy 0:f86e6135dcbc 1488 \li Just returns when no debugger is connected that has booked the output.
elevatorguy 0:f86e6135dcbc 1489 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
elevatorguy 0:f86e6135dcbc 1490
elevatorguy 0:f86e6135dcbc 1491 \param [in] ch Character to transmit.
elevatorguy 0:f86e6135dcbc 1492
elevatorguy 0:f86e6135dcbc 1493 \returns Character to transmit.
elevatorguy 0:f86e6135dcbc 1494 */
elevatorguy 0:f86e6135dcbc 1495 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
elevatorguy 0:f86e6135dcbc 1496 {
elevatorguy 0:f86e6135dcbc 1497 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
elevatorguy 0:f86e6135dcbc 1498 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
elevatorguy 0:f86e6135dcbc 1499 {
elevatorguy 0:f86e6135dcbc 1500 while (ITM->PORT[0].u32 == 0);
elevatorguy 0:f86e6135dcbc 1501 ITM->PORT[0].u8 = (uint8_t) ch;
elevatorguy 0:f86e6135dcbc 1502 }
elevatorguy 0:f86e6135dcbc 1503 return (ch);
elevatorguy 0:f86e6135dcbc 1504 }
elevatorguy 0:f86e6135dcbc 1505
elevatorguy 0:f86e6135dcbc 1506
elevatorguy 0:f86e6135dcbc 1507 /** \brief ITM Receive Character
elevatorguy 0:f86e6135dcbc 1508
elevatorguy 0:f86e6135dcbc 1509 The function inputs a character via the external variable \ref ITM_RxBuffer.
elevatorguy 0:f86e6135dcbc 1510
elevatorguy 0:f86e6135dcbc 1511 \return Received character.
elevatorguy 0:f86e6135dcbc 1512 \return -1 No character pending.
elevatorguy 0:f86e6135dcbc 1513 */
elevatorguy 0:f86e6135dcbc 1514 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
elevatorguy 0:f86e6135dcbc 1515 int32_t ch = -1; /* no character available */
elevatorguy 0:f86e6135dcbc 1516
elevatorguy 0:f86e6135dcbc 1517 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
elevatorguy 0:f86e6135dcbc 1518 ch = ITM_RxBuffer;
elevatorguy 0:f86e6135dcbc 1519 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
elevatorguy 0:f86e6135dcbc 1520 }
elevatorguy 0:f86e6135dcbc 1521
elevatorguy 0:f86e6135dcbc 1522 return (ch);
elevatorguy 0:f86e6135dcbc 1523 }
elevatorguy 0:f86e6135dcbc 1524
elevatorguy 0:f86e6135dcbc 1525
elevatorguy 0:f86e6135dcbc 1526 /** \brief ITM Check Character
elevatorguy 0:f86e6135dcbc 1527
elevatorguy 0:f86e6135dcbc 1528 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
elevatorguy 0:f86e6135dcbc 1529
elevatorguy 0:f86e6135dcbc 1530 \return 0 No character available.
elevatorguy 0:f86e6135dcbc 1531 \return 1 Character available.
elevatorguy 0:f86e6135dcbc 1532 */
elevatorguy 0:f86e6135dcbc 1533 __STATIC_INLINE int32_t ITM_CheckChar (void) {
elevatorguy 0:f86e6135dcbc 1534
elevatorguy 0:f86e6135dcbc 1535 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
elevatorguy 0:f86e6135dcbc 1536 return (0); /* no character available */
elevatorguy 0:f86e6135dcbc 1537 } else {
elevatorguy 0:f86e6135dcbc 1538 return (1); /* character available */
elevatorguy 0:f86e6135dcbc 1539 }
elevatorguy 0:f86e6135dcbc 1540 }
elevatorguy 0:f86e6135dcbc 1541
elevatorguy 0:f86e6135dcbc 1542 /*@} end of CMSIS_core_DebugFunctions */
elevatorguy 0:f86e6135dcbc 1543
elevatorguy 0:f86e6135dcbc 1544 #endif /* __CORE_CM3_H_DEPENDANT */
elevatorguy 0:f86e6135dcbc 1545
elevatorguy 0:f86e6135dcbc 1546 #endif /* __CMSIS_GENERIC */
elevatorguy 0:f86e6135dcbc 1547
elevatorguy 0:f86e6135dcbc 1548 #ifdef __cplusplus
elevatorguy 0:f86e6135dcbc 1549 }
elevatorguy 0:f86e6135dcbc 1550 #endif