mbed os with nrf51 internal bandgap enabled to read battery level
Dependents: BLE_file_test BLE_Blink ExternalEncoder
Diff: tools/export/codered_lpc4330_m4_cproject.tmpl
- Revision:
- 0:f269e3021894
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/export/codered_lpc4330_m4_cproject.tmpl Sun Oct 23 15:10:02 2016 +0000 @@ -0,0 +1,1924 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?> + +<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="com.crt.advproject.config.exe.debug.2019491857"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.2019491857" moduleId="org.eclipse.cdt.core.settings" name="Debug"> + <externalSettings/> + <extensions> + <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> + <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension 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blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/> +<peripheralInstance derived_from="LPC43_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/> +<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/> +<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/> +<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;0x1" id="TIMER3" location="0x40094000"/> +<peripheralInstance derived_from="LPC43_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;0x1" id="RIT" location="0x400B0000"/> +<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO0" location="0x2009C000"/> +<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/> +<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/> +<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/> +<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/> +<peripheralInstance derived_from="LPC43_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/> +<peripheralInstance derived_from="LPC43_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/> +<peripheralInstance derived_from="LPC43_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/> +<peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/> +<peripheralInstance derived_from="LPC43xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/> +<peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/> +<peripheralInstance derived_from="LPC43xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/> +<peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/> +<peripheralInstance derived_from="LPC43_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/> +<peripheralInstance derived_from="LPC43_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/> +<peripheralInstance derived_from="LPC43_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/> +<peripheralInstance derived_from="LPC43_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/> +<peripheralInstance derived_from="LPC43_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/> +<peripheralInstance derived_from="LPC43_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/> +<peripheralInstance derived_from="LPC43_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/> +<peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/> +<peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/> +<peripheralInstance derived_from="LPC43_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/> +<peripheralInstance derived_from="LPC43_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/> +<peripheralInstance derived_from="LPC43_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/> +<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> +<peripheralInstance derived_from="LPC43_PCB" determined="infoFile" id="PCB" location="0x4002c000"/> +<peripheralInstance derived_from="LPC43_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/> +<peripheralInstance derived_from="LPC43_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/> +<peripheralInstance derived_from="LPC43_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/> +<peripheralInstance derived_from="LPC43_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/> +<peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/> +<peripheralInstance derived_from="LPC4x_WDT" determined="infoFile" id="WDT" location="0x40000000"/> +<peripheralInstance derived_from="LPC43_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/> +<peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/> +<peripheralInstance derived_from="LPC43_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/> +<peripheralInstance derived_from="LPC43_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/> +<peripheralInstance derived_from="LPC43_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/> +<peripheralInstance derived_from="LPC43_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/> +<peripheralInstance derived_from="LPC43_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/> +<peripheralInstance derived_from="LPC43_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;0x1" id="MCPWM" location="0x400B8000"/> +</chip> +<processor> +<name gcc_name="cortex-m4">Cortex-M4</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig></projectStorage> + </storageModule> +</cproject>