Diff: tools/export/codered_lpc1549_cproject.tmpl

Revision:

0:f269e3021894

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/export/codered_lpc1549_cproject.tmpl	Sun Oct 23 15:10:02 2016 +0000
@@ -0,0 +1,69 @@
+{% extends "codered_cproject_cortexm3_common.tmpl" %}
+
+{% block startup_file %}cr_startup_lpc15xx.c{% endblock %}
+
+{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?>
+<TargetConfig>
+<Properties property_0="" property_2="LPC15xx_256K.cfx" property_3="NXP" property_4="LPC1549" property_count="5" version="70200"/>
+<infoList vendor="NXP">
+<info chip="LPC1549" connectscript="LPC15RunBootRomConnect.scp" flash_driver="LPC15xx_256K.cfx" match_id="0x0" name="LPC1549" resetscript="LPC15RunBootRomReset.scp" stub="crt_emu_cm3_gen">
+<chip>
+<name>LPC1549</name>
+<family>LPC15xx</family>
+<vendor>NXP (formerly Philips)</vendor>
+<reset board="None" core="Real" sys="Real"/>
+<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
+<memory id="RAM" type="RAM"/>
+<memory id="Periph" is_volatile="true" type="Peripheral"/>
+<memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/>
+<memoryInstance derived_from="RAM" id="Ram0_16" location="0x2000000" size="0x4000"/>
+<memoryInstance derived_from="RAM" id="Ram1_16" location="0x2004000" size="0x4000"/>
+<memoryInstance derived_from="RAM" id="Ram2_4" location="0x2008000" size="0x1000"/>
+<peripheralInstance derived_from="LPC15_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/>
+<peripheralInstance derived_from="LPC15_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/>
+<peripheralInstance derived_from="LPC15_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/>
+<peripheralInstance derived_from="LPC15_ITM" determined="infoFile" id="ITM" location="0xe0000000"/>
+<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x1c000000"/>
+<peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x1c004000"/>
+<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x1c00c000"/>
+<peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x1c010000"/>
+<peripheralInstance derived_from="SCT0" determined="infoFile" id="SCT0" location="0x1c018000"/>
+<peripheralInstance derived_from="SCT1" determined="infoFile" id="SCT1" location="0x1c01c000"/>
+<peripheralInstance derived_from="SCT2" determined="infoFile" id="SCT2" location="0x1c020000"/>
+<peripheralInstance derived_from="SCT3" determined="infoFile" id="SCT3" location="0x1c024000"/>
+<peripheralInstance derived_from="ADC0" determined="infoFile" id="ADC0" location="0x40000000"/>
+<peripheralInstance derived_from="DAC" determined="infoFile" id="DAC" location="0x40004000"/>
+<peripheralInstance derived_from="ACMP" determined="infoFile" id="ACMP" location="0x40008000"/>
+<peripheralInstance derived_from="INMUX" determined="infoFile" id="INMUX" location="0x40014000"/>
+<peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40028000"/>
+<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x4002c000"/>
+<peripheralInstance derived_from="SWM" determined="infoFile" id="SWM" location="0x40038000"/>
+<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x4003c000"/>
+<peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40040000"/>
+<peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x40044000"/>
+<peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40048000"/>
+<peripheralInstance derived_from="SPI1" determined="infoFile" id="SPI1" location="0x4004c000"/>
+<peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40050000"/>
+<peripheralInstance derived_from="QEI" determined="infoFile" id="QEI" location="0x40058000"/>
+<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40074000"/>
+<peripheralInstance derived_from="ADC1" determined="infoFile" id="ADC1" location="0x40080000"/>
+<peripheralInstance derived_from="MRT" determined="infoFile" id="MRT" location="0x400a0000"/>
+<peripheralInstance derived_from="PINT" determined="infoFile" id="PINT" location="0x400a4000"/>
+<peripheralInstance derived_from="GINT0" determined="infoFile" id="GINT0" location="0x400a8000"/>
+<peripheralInstance derived_from="GINT1" determined="infoFile" id="GINT1" location="0x400ac000"/>
+<peripheralInstance derived_from="RIT" determined="infoFile" id="RIT" location="0x400b4000"/>
+<peripheralInstance derived_from="SCTIPU" determined="infoFile" id="SCTIPU" location="0x400b8000"/>
+<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x400bc000"/>
+<peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x400c0000"/>
+<peripheralInstance derived_from="C-CAN0" determined="infoFile" id="C-CAN0" location="0x400f0000"/>
+<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x400f8000"/>
+</chip>
+<processor>
+<name gcc_name="cortex-m3">Cortex-M3</name>
+<family>Cortex-M</family>
+</processor>
+<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
+</info>
+</infoList>
+</TargetConfig>{% endblock %}