erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

targets/TARGET_STM/stm_spi_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 *******************************************************************************
elessair 0:f269e3021894 3 * Copyright (c) 2015, STMicroelectronics
elessair 0:f269e3021894 4 * All rights reserved.
elessair 0:f269e3021894 5 *
elessair 0:f269e3021894 6 * Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 7 * modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 * 1. Redistributions of source code must retain the above copyright notice,
elessair 0:f269e3021894 10 * this list of conditions and the following disclaimer.
elessair 0:f269e3021894 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
elessair 0:f269e3021894 12 * this list of conditions and the following disclaimer in the documentation
elessair 0:f269e3021894 13 * and/or other materials provided with the distribution.
elessair 0:f269e3021894 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elessair 0:f269e3021894 15 * may be used to endorse or promote products derived from this software
elessair 0:f269e3021894 16 * without specific prior written permission.
elessair 0:f269e3021894 17 *
elessair 0:f269e3021894 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elessair 0:f269e3021894 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elessair 0:f269e3021894 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elessair 0:f269e3021894 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elessair 0:f269e3021894 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elessair 0:f269e3021894 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elessair 0:f269e3021894 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elessair 0:f269e3021894 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 28 *******************************************************************************
elessair 0:f269e3021894 29 */
elessair 0:f269e3021894 30 #include "mbed_assert.h"
elessair 0:f269e3021894 31 #include "mbed_error.h"
elessair 0:f269e3021894 32 #include "spi_api.h"
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 #if DEVICE_SPI
elessair 0:f269e3021894 35 #include <stdbool.h>
elessair 0:f269e3021894 36 #include <math.h>
elessair 0:f269e3021894 37 #include <string.h>
elessair 0:f269e3021894 38 #include "cmsis.h"
elessair 0:f269e3021894 39 #include "pinmap.h"
elessair 0:f269e3021894 40 #include "PeripheralPins.h"
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #if DEVICE_SPI_ASYNCH
elessair 0:f269e3021894 43 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
elessair 0:f269e3021894 44 #else
elessair 0:f269e3021894 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
elessair 0:f269e3021894 46 #endif
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 #if DEVICE_SPI_ASYNCH
elessair 0:f269e3021894 49 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
elessair 0:f269e3021894 50 #else
elessair 0:f269e3021894 51 #define SPI_S(obj) (( struct spi_s *)(obj))
elessair 0:f269e3021894 52 #endif
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54 #ifndef DEBUG_STDIO
elessair 0:f269e3021894 55 # define DEBUG_STDIO 0
elessair 0:f269e3021894 56 #endif
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 #if DEBUG_STDIO
elessair 0:f269e3021894 59 # include <stdio.h>
elessair 0:f269e3021894 60 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
elessair 0:f269e3021894 61 #else
elessair 0:f269e3021894 62 # define DEBUG_PRINTF(...) {}
elessair 0:f269e3021894 63 #endif
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 void init_spi(spi_t *obj)
elessair 0:f269e3021894 66 {
elessair 0:f269e3021894 67 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 68 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 __HAL_SPI_DISABLE(handle);
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
elessair 0:f269e3021894 73 if (HAL_SPI_Init(handle) != HAL_OK) {
elessair 0:f269e3021894 74 error("Cannot initialize SPI");
elessair 0:f269e3021894 75 }
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 __HAL_SPI_ENABLE(handle);
elessair 0:f269e3021894 78 }
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
elessair 0:f269e3021894 81 {
elessair 0:f269e3021894 82 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 83 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 // Determine the SPI to use
elessair 0:f269e3021894 86 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
elessair 0:f269e3021894 87 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
elessair 0:f269e3021894 88 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
elessair 0:f269e3021894 89 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
elessair 0:f269e3021894 90
elessair 0:f269e3021894 91 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
elessair 0:f269e3021894 92 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
elessair 0:f269e3021894 95 MBED_ASSERT(spiobj->spi != (SPIName)NC);
elessair 0:f269e3021894 96
elessair 0:f269e3021894 97 #if defined SPI1_BASE
elessair 0:f269e3021894 98 // Enable SPI clock
elessair 0:f269e3021894 99 if (spiobj->spi == SPI_1) {
elessair 0:f269e3021894 100 __HAL_RCC_SPI1_CLK_ENABLE();
elessair 0:f269e3021894 101 spiobj->spiIRQ = SPI1_IRQn;
elessair 0:f269e3021894 102 }
elessair 0:f269e3021894 103 #endif
elessair 0:f269e3021894 104
elessair 0:f269e3021894 105 #if defined SPI2_BASE
elessair 0:f269e3021894 106 if (spiobj->spi == SPI_2) {
elessair 0:f269e3021894 107 __HAL_RCC_SPI2_CLK_ENABLE();
elessair 0:f269e3021894 108 spiobj->spiIRQ = SPI2_IRQn;
elessair 0:f269e3021894 109 }
elessair 0:f269e3021894 110 #endif
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 #if defined SPI3_BASE
elessair 0:f269e3021894 113 if (spiobj->spi == SPI_3) {
elessair 0:f269e3021894 114 __HAL_RCC_SPI3_CLK_ENABLE();
elessair 0:f269e3021894 115 spiobj->spiIRQ = SPI3_IRQn;
elessair 0:f269e3021894 116 }
elessair 0:f269e3021894 117 #endif
elessair 0:f269e3021894 118
elessair 0:f269e3021894 119 #if defined SPI4_BASE
elessair 0:f269e3021894 120 if (spiobj->spi == SPI_4) {
elessair 0:f269e3021894 121 __HAL_RCC_SPI4_CLK_ENABLE();
elessair 0:f269e3021894 122 spiobj->spiIRQ = SPI4_IRQn;
elessair 0:f269e3021894 123 }
elessair 0:f269e3021894 124 #endif
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 #if defined SPI5_BASE
elessair 0:f269e3021894 127 if (spiobj->spi == SPI_5) {
elessair 0:f269e3021894 128 __HAL_RCC_SPI5_CLK_ENABLE();
elessair 0:f269e3021894 129 spiobj->spiIRQ = SPI5_IRQn;
elessair 0:f269e3021894 130 }
elessair 0:f269e3021894 131 #endif
elessair 0:f269e3021894 132
elessair 0:f269e3021894 133 #if defined SPI6_BASE
elessair 0:f269e3021894 134 if (spiobj->spi == SPI_6) {
elessair 0:f269e3021894 135 __HAL_RCC_SPI6_CLK_ENABLE();
elessair 0:f269e3021894 136 spiobj->spiIRQ = SPI6_IRQn;
elessair 0:f269e3021894 137 }
elessair 0:f269e3021894 138 #endif
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 // Configure the SPI pins
elessair 0:f269e3021894 141 pinmap_pinout(mosi, PinMap_SPI_MOSI);
elessair 0:f269e3021894 142 pinmap_pinout(miso, PinMap_SPI_MISO);
elessair 0:f269e3021894 143 pinmap_pinout(sclk, PinMap_SPI_SCLK);
elessair 0:f269e3021894 144 spiobj->pin_miso = miso;
elessair 0:f269e3021894 145 spiobj->pin_mosi = mosi;
elessair 0:f269e3021894 146 spiobj->pin_sclk = sclk;
elessair 0:f269e3021894 147 spiobj->pin_ssel = ssel;
elessair 0:f269e3021894 148 if (ssel != NC) {
elessair 0:f269e3021894 149 pinmap_pinout(ssel, PinMap_SPI_SSEL);
elessair 0:f269e3021894 150 } else {
elessair 0:f269e3021894 151 handle->Init.NSS = SPI_NSS_SOFT;
elessair 0:f269e3021894 152 }
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 /* Fill default value */
elessair 0:f269e3021894 155 handle->Instance = SPI_INST(obj);
elessair 0:f269e3021894 156 handle->Init.Mode = SPI_MODE_MASTER;
elessair 0:f269e3021894 157 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
elessair 0:f269e3021894 158 handle->Init.Direction = SPI_DIRECTION_2LINES;
elessair 0:f269e3021894 159 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
elessair 0:f269e3021894 160 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
elessair 0:f269e3021894 161 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
elessair 0:f269e3021894 162 handle->Init.CRCPolynomial = 7;
elessair 0:f269e3021894 163 handle->Init.DataSize = SPI_DATASIZE_8BIT;
elessair 0:f269e3021894 164 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
elessair 0:f269e3021894 165 handle->Init.TIMode = SPI_TIMODE_DISABLED;
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 init_spi(obj);
elessair 0:f269e3021894 168 }
elessair 0:f269e3021894 169
elessair 0:f269e3021894 170 void spi_free(spi_t *obj)
elessair 0:f269e3021894 171 {
elessair 0:f269e3021894 172 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 173 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175 DEBUG_PRINTF("spi_free\r\n");
elessair 0:f269e3021894 176
elessair 0:f269e3021894 177 __HAL_SPI_DISABLE(handle);
elessair 0:f269e3021894 178 HAL_SPI_DeInit(handle);
elessair 0:f269e3021894 179
elessair 0:f269e3021894 180 #if defined SPI1_BASE
elessair 0:f269e3021894 181 // Reset SPI and disable clock
elessair 0:f269e3021894 182 if (spiobj->spi == SPI_1) {
elessair 0:f269e3021894 183 __HAL_RCC_SPI1_FORCE_RESET();
elessair 0:f269e3021894 184 __HAL_RCC_SPI1_RELEASE_RESET();
elessair 0:f269e3021894 185 __HAL_RCC_SPI1_CLK_DISABLE();
elessair 0:f269e3021894 186 }
elessair 0:f269e3021894 187 #endif
elessair 0:f269e3021894 188 #if defined SPI2_BASE
elessair 0:f269e3021894 189 if (spiobj->spi == SPI_2) {
elessair 0:f269e3021894 190 __HAL_RCC_SPI2_FORCE_RESET();
elessair 0:f269e3021894 191 __HAL_RCC_SPI2_RELEASE_RESET();
elessair 0:f269e3021894 192 __HAL_RCC_SPI2_CLK_DISABLE();
elessair 0:f269e3021894 193 }
elessair 0:f269e3021894 194 #endif
elessair 0:f269e3021894 195
elessair 0:f269e3021894 196 #if defined SPI3_BASE
elessair 0:f269e3021894 197 if (spiobj->spi == SPI_3) {
elessair 0:f269e3021894 198 __HAL_RCC_SPI3_FORCE_RESET();
elessair 0:f269e3021894 199 __HAL_RCC_SPI3_RELEASE_RESET();
elessair 0:f269e3021894 200 __HAL_RCC_SPI3_CLK_DISABLE();
elessair 0:f269e3021894 201 }
elessair 0:f269e3021894 202 #endif
elessair 0:f269e3021894 203
elessair 0:f269e3021894 204 #if defined SPI4_BASE
elessair 0:f269e3021894 205 if (spiobj->spi == SPI_4) {
elessair 0:f269e3021894 206 __HAL_RCC_SPI4_FORCE_RESET();
elessair 0:f269e3021894 207 __HAL_RCC_SPI4_RELEASE_RESET();
elessair 0:f269e3021894 208 __HAL_RCC_SPI4_CLK_DISABLE();
elessair 0:f269e3021894 209 }
elessair 0:f269e3021894 210 #endif
elessair 0:f269e3021894 211
elessair 0:f269e3021894 212 #if defined SPI5_BASE
elessair 0:f269e3021894 213 if (spiobj->spi == SPI_5) {
elessair 0:f269e3021894 214 __HAL_RCC_SPI5_FORCE_RESET();
elessair 0:f269e3021894 215 __HAL_RCC_SPI5_RELEASE_RESET();
elessair 0:f269e3021894 216 __HAL_RCC_SPI5_CLK_DISABLE();
elessair 0:f269e3021894 217 }
elessair 0:f269e3021894 218 #endif
elessair 0:f269e3021894 219
elessair 0:f269e3021894 220 #if defined SPI6_BASE
elessair 0:f269e3021894 221 if (spiobj->spi == SPI_6) {
elessair 0:f269e3021894 222 __HAL_RCC_SPI6_FORCE_RESET();
elessair 0:f269e3021894 223 __HAL_RCC_SPI6_RELEASE_RESET();
elessair 0:f269e3021894 224 __HAL_RCC_SPI6_CLK_DISABLE();
elessair 0:f269e3021894 225 }
elessair 0:f269e3021894 226 #endif
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 // Configure GPIOs
elessair 0:f269e3021894 229 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elessair 0:f269e3021894 230 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elessair 0:f269e3021894 231 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elessair 0:f269e3021894 232 if (handle->Init.NSS != SPI_NSS_SOFT) {
elessair 0:f269e3021894 233 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
elessair 0:f269e3021894 234 }
elessair 0:f269e3021894 235 }
elessair 0:f269e3021894 236
elessair 0:f269e3021894 237 void spi_format(spi_t *obj, int bits, int mode, int slave)
elessair 0:f269e3021894 238 {
elessair 0:f269e3021894 239 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 240 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 241
elessair 0:f269e3021894 242 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
elessair 0:f269e3021894 243
elessair 0:f269e3021894 244 // Save new values
elessair 0:f269e3021894 245 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
elessair 0:f269e3021894 246
elessair 0:f269e3021894 247 switch (mode) {
elessair 0:f269e3021894 248 case 0:
elessair 0:f269e3021894 249 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
elessair 0:f269e3021894 250 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
elessair 0:f269e3021894 251 break;
elessair 0:f269e3021894 252 case 1:
elessair 0:f269e3021894 253 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
elessair 0:f269e3021894 254 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
elessair 0:f269e3021894 255 break;
elessair 0:f269e3021894 256 case 2:
elessair 0:f269e3021894 257 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
elessair 0:f269e3021894 258 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
elessair 0:f269e3021894 259 break;
elessair 0:f269e3021894 260 default:
elessair 0:f269e3021894 261 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
elessair 0:f269e3021894 262 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
elessair 0:f269e3021894 263 break;
elessair 0:f269e3021894 264 }
elessair 0:f269e3021894 265
elessair 0:f269e3021894 266 if (handle->Init.NSS != SPI_NSS_SOFT) {
elessair 0:f269e3021894 267 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
elessair 0:f269e3021894 268 }
elessair 0:f269e3021894 269
elessair 0:f269e3021894 270 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
elessair 0:f269e3021894 271
elessair 0:f269e3021894 272 init_spi(obj);
elessair 0:f269e3021894 273 }
elessair 0:f269e3021894 274
elessair 0:f269e3021894 275 /*
elessair 0:f269e3021894 276 * Only the IP clock input is family dependant so it computed
elessair 0:f269e3021894 277 * separately in spi_get_clock_freq
elessair 0:f269e3021894 278 */
elessair 0:f269e3021894 279 extern int spi_get_clock_freq(spi_t *obj);
elessair 0:f269e3021894 280
elessair 0:f269e3021894 281 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
elessair 0:f269e3021894 282 SPI_BAUDRATEPRESCALER_4,
elessair 0:f269e3021894 283 SPI_BAUDRATEPRESCALER_8,
elessair 0:f269e3021894 284 SPI_BAUDRATEPRESCALER_16,
elessair 0:f269e3021894 285 SPI_BAUDRATEPRESCALER_32,
elessair 0:f269e3021894 286 SPI_BAUDRATEPRESCALER_64,
elessair 0:f269e3021894 287 SPI_BAUDRATEPRESCALER_128,
elessair 0:f269e3021894 288 SPI_BAUDRATEPRESCALER_256};
elessair 0:f269e3021894 289
elessair 0:f269e3021894 290 void spi_frequency(spi_t *obj, int hz) {
elessair 0:f269e3021894 291 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 292 int spi_hz = 0;
elessair 0:f269e3021894 293 uint8_t prescaler_rank = 0;
elessair 0:f269e3021894 294 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 295
elessair 0:f269e3021894 296 /* Get the clock of the peripheral */
elessair 0:f269e3021894 297 spi_hz = spi_get_clock_freq(obj);
elessair 0:f269e3021894 298
elessair 0:f269e3021894 299 /* Define pre-scaler in order to get highest available frequency below requested frequency */
elessair 0:f269e3021894 300 while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
elessair 0:f269e3021894 301 spi_hz = spi_hz / 2;
elessair 0:f269e3021894 302 prescaler_rank++;
elessair 0:f269e3021894 303 }
elessair 0:f269e3021894 304
elessair 0:f269e3021894 305 if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
elessair 0:f269e3021894 306 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
elessair 0:f269e3021894 307 } else {
elessair 0:f269e3021894 308 error("Couldn't setup requested SPI frequency");
elessair 0:f269e3021894 309 }
elessair 0:f269e3021894 310
elessair 0:f269e3021894 311 init_spi(obj);
elessair 0:f269e3021894 312 }
elessair 0:f269e3021894 313
elessair 0:f269e3021894 314 static inline int ssp_readable(spi_t *obj)
elessair 0:f269e3021894 315 {
elessair 0:f269e3021894 316 int status;
elessair 0:f269e3021894 317 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 318 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 319
elessair 0:f269e3021894 320 // Check if data is received
elessair 0:f269e3021894 321 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
elessair 0:f269e3021894 322 return status;
elessair 0:f269e3021894 323 }
elessair 0:f269e3021894 324
elessair 0:f269e3021894 325 static inline int ssp_writeable(spi_t *obj)
elessair 0:f269e3021894 326 {
elessair 0:f269e3021894 327 int status;
elessair 0:f269e3021894 328 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 329 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 330
elessair 0:f269e3021894 331 // Check if data is transmitted
elessair 0:f269e3021894 332 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
elessair 0:f269e3021894 333 return status;
elessair 0:f269e3021894 334 }
elessair 0:f269e3021894 335
elessair 0:f269e3021894 336 static inline int ssp_busy(spi_t *obj)
elessair 0:f269e3021894 337 {
elessair 0:f269e3021894 338 int status;
elessair 0:f269e3021894 339 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 340 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 341 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
elessair 0:f269e3021894 342 return status;
elessair 0:f269e3021894 343 }
elessair 0:f269e3021894 344
elessair 0:f269e3021894 345 int spi_master_write(spi_t *obj, int value)
elessair 0:f269e3021894 346 {
elessair 0:f269e3021894 347 uint16_t size, Rx, ret;
elessair 0:f269e3021894 348 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 349 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 350
elessair 0:f269e3021894 351 size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1;
elessair 0:f269e3021894 352
elessair 0:f269e3021894 353 /* Use 10ms timeout */
elessair 0:f269e3021894 354 ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10);
elessair 0:f269e3021894 355
elessair 0:f269e3021894 356 if(ret == HAL_OK) {
elessair 0:f269e3021894 357 return Rx;
elessair 0:f269e3021894 358 } else {
elessair 0:f269e3021894 359 DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance);
elessair 0:f269e3021894 360 return -1;
elessair 0:f269e3021894 361 }
elessair 0:f269e3021894 362 }
elessair 0:f269e3021894 363
elessair 0:f269e3021894 364 int spi_slave_receive(spi_t *obj)
elessair 0:f269e3021894 365 {
elessair 0:f269e3021894 366 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
elessair 0:f269e3021894 367 };
elessair 0:f269e3021894 368
elessair 0:f269e3021894 369 int spi_slave_read(spi_t *obj)
elessair 0:f269e3021894 370 {
elessair 0:f269e3021894 371 SPI_TypeDef *spi = SPI_INST(obj);
elessair 0:f269e3021894 372 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 373 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 374 while (!ssp_readable(obj));
elessair 0:f269e3021894 375 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
elessair 0:f269e3021894 376 // Force 8-bit access to the data register
elessair 0:f269e3021894 377 uint8_t *p_spi_dr = 0;
elessair 0:f269e3021894 378 p_spi_dr = (uint8_t *) & (spi->DR);
elessair 0:f269e3021894 379 return (int)(*p_spi_dr);
elessair 0:f269e3021894 380 } else {
elessair 0:f269e3021894 381 return (int)spi->DR;
elessair 0:f269e3021894 382 }
elessair 0:f269e3021894 383 }
elessair 0:f269e3021894 384
elessair 0:f269e3021894 385 void spi_slave_write(spi_t *obj, int value)
elessair 0:f269e3021894 386 {
elessair 0:f269e3021894 387 SPI_TypeDef *spi = SPI_INST(obj);
elessair 0:f269e3021894 388 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 389 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 390 while (!ssp_writeable(obj));
elessair 0:f269e3021894 391 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
elessair 0:f269e3021894 392 // Force 8-bit access to the data register
elessair 0:f269e3021894 393 uint8_t *p_spi_dr = 0;
elessair 0:f269e3021894 394 p_spi_dr = (uint8_t *) & (spi->DR);
elessair 0:f269e3021894 395 *p_spi_dr = (uint8_t)value;
elessair 0:f269e3021894 396 } else { // SPI_DATASIZE_16BIT
elessair 0:f269e3021894 397 spi->DR = (uint16_t)value;
elessair 0:f269e3021894 398 }
elessair 0:f269e3021894 399 }
elessair 0:f269e3021894 400
elessair 0:f269e3021894 401 int spi_busy(spi_t *obj)
elessair 0:f269e3021894 402 {
elessair 0:f269e3021894 403 return ssp_busy(obj);
elessair 0:f269e3021894 404 }
elessair 0:f269e3021894 405
elessair 0:f269e3021894 406 #ifdef DEVICE_SPI_ASYNCH
elessair 0:f269e3021894 407 typedef enum {
elessair 0:f269e3021894 408 SPI_TRANSFER_TYPE_NONE = 0,
elessair 0:f269e3021894 409 SPI_TRANSFER_TYPE_TX = 1,
elessair 0:f269e3021894 410 SPI_TRANSFER_TYPE_RX = 2,
elessair 0:f269e3021894 411 SPI_TRANSFER_TYPE_TXRX = 3,
elessair 0:f269e3021894 412 } transfer_type_t;
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414
elessair 0:f269e3021894 415 /// @returns the number of bytes transferred, or `0` if nothing transferred
elessair 0:f269e3021894 416 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
elessair 0:f269e3021894 417 {
elessair 0:f269e3021894 418 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 419 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 420 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
elessair 0:f269e3021894 421 // the HAL expects number of transfers instead of number of bytes
elessair 0:f269e3021894 422 // so for 16 bit transfer width the count needs to be halved
elessair 0:f269e3021894 423 size_t words;
elessair 0:f269e3021894 424
elessair 0:f269e3021894 425 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
elessair 0:f269e3021894 426
elessair 0:f269e3021894 427 obj->spi.transfer_type = transfer_type;
elessair 0:f269e3021894 428
elessair 0:f269e3021894 429 if (is16bit) {
elessair 0:f269e3021894 430 words = length / 2;
elessair 0:f269e3021894 431 } else {
elessair 0:f269e3021894 432 words = length;
elessair 0:f269e3021894 433 }
elessair 0:f269e3021894 434
elessair 0:f269e3021894 435 // enable the interrupt
elessair 0:f269e3021894 436 IRQn_Type irq_n = spiobj->spiIRQ;
elessair 0:f269e3021894 437 NVIC_ClearPendingIRQ(irq_n);
elessair 0:f269e3021894 438 NVIC_DisableIRQ(irq_n);
elessair 0:f269e3021894 439 NVIC_SetPriority(irq_n, 1);
elessair 0:f269e3021894 440 NVIC_EnableIRQ(irq_n);
elessair 0:f269e3021894 441
elessair 0:f269e3021894 442 // enable the right hal transfer
elessair 0:f269e3021894 443 int rc = 0;
elessair 0:f269e3021894 444 switch(transfer_type) {
elessair 0:f269e3021894 445 case SPI_TRANSFER_TYPE_TXRX:
elessair 0:f269e3021894 446 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
elessair 0:f269e3021894 447 break;
elessair 0:f269e3021894 448 case SPI_TRANSFER_TYPE_TX:
elessair 0:f269e3021894 449 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
elessair 0:f269e3021894 450 break;
elessair 0:f269e3021894 451 case SPI_TRANSFER_TYPE_RX:
elessair 0:f269e3021894 452 // the receive function also "transmits" the receive buffer so in order
elessair 0:f269e3021894 453 // to guarantee that 0xff is on the line, we explicitly memset it here
elessair 0:f269e3021894 454 memset(rx, SPI_FILL_WORD, length);
elessair 0:f269e3021894 455 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
elessair 0:f269e3021894 456 break;
elessair 0:f269e3021894 457 default:
elessair 0:f269e3021894 458 length = 0;
elessair 0:f269e3021894 459 }
elessair 0:f269e3021894 460
elessair 0:f269e3021894 461 if (rc) {
elessair 0:f269e3021894 462 DEBUG_PRINTF("SPI: RC=%u\n", rc);
elessair 0:f269e3021894 463 length = 0;
elessair 0:f269e3021894 464 }
elessair 0:f269e3021894 465
elessair 0:f269e3021894 466 return length;
elessair 0:f269e3021894 467 }
elessair 0:f269e3021894 468
elessair 0:f269e3021894 469 // asynchronous API
elessair 0:f269e3021894 470 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
elessair 0:f269e3021894 471 {
elessair 0:f269e3021894 472 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 473 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 474
elessair 0:f269e3021894 475 // TODO: DMA usage is currently ignored
elessair 0:f269e3021894 476 (void) hint;
elessair 0:f269e3021894 477
elessair 0:f269e3021894 478 // check which use-case we have
elessair 0:f269e3021894 479 bool use_tx = (tx != NULL && tx_length > 0);
elessair 0:f269e3021894 480 bool use_rx = (rx != NULL && rx_length > 0);
elessair 0:f269e3021894 481 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
elessair 0:f269e3021894 482
elessair 0:f269e3021894 483 // don't do anything, if the buffers aren't valid
elessair 0:f269e3021894 484 if (!use_tx && !use_rx)
elessair 0:f269e3021894 485 return;
elessair 0:f269e3021894 486
elessair 0:f269e3021894 487 // copy the buffers to the SPI object
elessair 0:f269e3021894 488 obj->tx_buff.buffer = (void *) tx;
elessair 0:f269e3021894 489 obj->tx_buff.length = tx_length;
elessair 0:f269e3021894 490 obj->tx_buff.pos = 0;
elessair 0:f269e3021894 491 obj->tx_buff.width = is16bit ? 16 : 8;
elessair 0:f269e3021894 492
elessair 0:f269e3021894 493 obj->rx_buff.buffer = rx;
elessair 0:f269e3021894 494 obj->rx_buff.length = rx_length;
elessair 0:f269e3021894 495 obj->rx_buff.pos = 0;
elessair 0:f269e3021894 496 obj->rx_buff.width = obj->tx_buff.width;
elessair 0:f269e3021894 497
elessair 0:f269e3021894 498 obj->spi.event = event;
elessair 0:f269e3021894 499
elessair 0:f269e3021894 500 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
elessair 0:f269e3021894 501
elessair 0:f269e3021894 502 // register the thunking handler
elessair 0:f269e3021894 503 IRQn_Type irq_n = spiobj->spiIRQ;
elessair 0:f269e3021894 504 NVIC_SetVector(irq_n, (uint32_t)handler);
elessair 0:f269e3021894 505
elessair 0:f269e3021894 506 // enable the right hal transfer
elessair 0:f269e3021894 507 if (use_tx && use_rx) {
elessair 0:f269e3021894 508 // we cannot manage different rx / tx sizes, let's use smaller one
elessair 0:f269e3021894 509 size_t size = (tx_length < rx_length)? tx_length : rx_length;
elessair 0:f269e3021894 510 if(tx_length != rx_length) {
elessair 0:f269e3021894 511 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
elessair 0:f269e3021894 512 obj->tx_buff.length = size;
elessair 0:f269e3021894 513 obj->rx_buff.length = size;
elessair 0:f269e3021894 514 }
elessair 0:f269e3021894 515 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
elessair 0:f269e3021894 516 } else if (use_tx) {
elessair 0:f269e3021894 517 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
elessair 0:f269e3021894 518 } else if (use_rx) {
elessair 0:f269e3021894 519 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
elessair 0:f269e3021894 520 }
elessair 0:f269e3021894 521 }
elessair 0:f269e3021894 522
elessair 0:f269e3021894 523 uint32_t spi_irq_handler_asynch(spi_t *obj)
elessair 0:f269e3021894 524 {
elessair 0:f269e3021894 525 // use the right instance
elessair 0:f269e3021894 526 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 527 SPI_HandleTypeDef *handle = &spiobj->handle;
elessair 0:f269e3021894 528 int event = 0;
elessair 0:f269e3021894 529
elessair 0:f269e3021894 530 // call the CubeF4 handler, this will update the handle
elessair 0:f269e3021894 531 HAL_SPI_IRQHandler(handle);
elessair 0:f269e3021894 532
elessair 0:f269e3021894 533 if (HAL_SPI_GetState(handle) == HAL_SPI_STATE_READY) {
elessair 0:f269e3021894 534 // When HAL SPI is back to READY state, check if there was an error
elessair 0:f269e3021894 535 int error = HAL_SPI_GetError(handle);
elessair 0:f269e3021894 536 if(error != HAL_SPI_ERROR_NONE) {
elessair 0:f269e3021894 537 // something went wrong and the transfer has definitely completed
elessair 0:f269e3021894 538 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
elessair 0:f269e3021894 539
elessair 0:f269e3021894 540 if (error & HAL_SPI_ERROR_OVR) {
elessair 0:f269e3021894 541 // buffer overrun
elessair 0:f269e3021894 542 event |= SPI_EVENT_RX_OVERFLOW;
elessair 0:f269e3021894 543 }
elessair 0:f269e3021894 544 } else {
elessair 0:f269e3021894 545 // else we're done
elessair 0:f269e3021894 546 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
elessair 0:f269e3021894 547 }
elessair 0:f269e3021894 548 }
elessair 0:f269e3021894 549
elessair 0:f269e3021894 550 if (event) DEBUG_PRINTF("SPI: Event: 0x%x\n", event);
elessair 0:f269e3021894 551
elessair 0:f269e3021894 552 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
elessair 0:f269e3021894 553 }
elessair 0:f269e3021894 554
elessair 0:f269e3021894 555 uint8_t spi_active(spi_t *obj)
elessair 0:f269e3021894 556 {
elessair 0:f269e3021894 557 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 558 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 559 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
elessair 0:f269e3021894 560
elessair 0:f269e3021894 561 switch(state) {
elessair 0:f269e3021894 562 case HAL_SPI_STATE_RESET:
elessair 0:f269e3021894 563 case HAL_SPI_STATE_READY:
elessair 0:f269e3021894 564 case HAL_SPI_STATE_ERROR:
elessair 0:f269e3021894 565 return 0;
elessair 0:f269e3021894 566 default:
elessair 0:f269e3021894 567 return 1;
elessair 0:f269e3021894 568 }
elessair 0:f269e3021894 569 }
elessair 0:f269e3021894 570
elessair 0:f269e3021894 571 void spi_abort_asynch(spi_t *obj)
elessair 0:f269e3021894 572 {
elessair 0:f269e3021894 573 struct spi_s *spiobj = SPI_S(obj);
elessair 0:f269e3021894 574 SPI_HandleTypeDef *handle = &(spiobj->handle);
elessair 0:f269e3021894 575
elessair 0:f269e3021894 576 // disable interrupt
elessair 0:f269e3021894 577 IRQn_Type irq_n = spiobj->spiIRQ;
elessair 0:f269e3021894 578 NVIC_ClearPendingIRQ(irq_n);
elessair 0:f269e3021894 579 NVIC_DisableIRQ(irq_n);
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 // clean-up
elessair 0:f269e3021894 582 __HAL_SPI_DISABLE(handle);
elessair 0:f269e3021894 583 HAL_SPI_DeInit(handle);
elessair 0:f269e3021894 584 HAL_SPI_Init(handle);
elessair 0:f269e3021894 585 __HAL_SPI_ENABLE(handle);
elessair 0:f269e3021894 586 }
elessair 0:f269e3021894 587
elessair 0:f269e3021894 588 #endif //DEVICE_SPI_ASYNCH
elessair 0:f269e3021894 589
elessair 0:f269e3021894 590 #endif