erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #include "mbed_assert.h"
elessair 0:f269e3021894 17 #include <math.h>
elessair 0:f269e3021894 18 #include "spi_api.h"
elessair 0:f269e3021894 19 #include "cmsis.h"
elessair 0:f269e3021894 20 #include "pinmap.h"
elessair 0:f269e3021894 21 #include "mbed_error.h"
elessair 0:f269e3021894 22 #include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform
elessair 0:f269e3021894 23
elessair 0:f269e3021894 24 static inline int ssp_disable(spi_t *obj);
elessair 0:f269e3021894 25 static inline int ssp_enable(spi_t *obj);
elessair 0:f269e3021894 26
elessair 0:f269e3021894 27 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
elessair 0:f269e3021894 28 // determine the SPI to use
elessair 0:f269e3021894 29 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
elessair 0:f269e3021894 30 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
elessair 0:f269e3021894 31 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
elessair 0:f269e3021894 32 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
elessair 0:f269e3021894 33 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
elessair 0:f269e3021894 34 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
elessair 0:f269e3021894 35
elessair 0:f269e3021894 36 obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
elessair 0:f269e3021894 37 MBED_ASSERT((int)obj->spi != NC);
elessair 0:f269e3021894 38
elessair 0:f269e3021894 39 // enable power and clocking
elessair 0:f269e3021894 40 switch ((int)obj->spi) {
elessair 0:f269e3021894 41 case SPI_0:
elessair 0:f269e3021894 42 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
elessair 0:f269e3021894 43 LPC_SYSCON->SSP0CLKDIV = 0x01;
elessair 0:f269e3021894 44 LPC_SYSCON->PRESETCTRL |= 1 << 0;
elessair 0:f269e3021894 45 break;
elessair 0:f269e3021894 46 case SPI_1:
elessair 0:f269e3021894 47 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
elessair 0:f269e3021894 48 LPC_SYSCON->SSP1CLKDIV = 0x01;
elessair 0:f269e3021894 49 LPC_SYSCON->PRESETCTRL |= 1 << 2;
elessair 0:f269e3021894 50 break;
elessair 0:f269e3021894 51 }
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 // pin out the spi pins
elessair 0:f269e3021894 54 pinmap_pinout(mosi, PinMap_SPI_MOSI);
elessair 0:f269e3021894 55 pinmap_pinout(miso, PinMap_SPI_MISO);
elessair 0:f269e3021894 56 pinmap_pinout(sclk, PinMap_SPI_SCLK);
elessair 0:f269e3021894 57 if (ssel != NC) {
elessair 0:f269e3021894 58 pinmap_pinout(ssel, PinMap_SPI_SSEL);
elessair 0:f269e3021894 59 }
elessair 0:f269e3021894 60 }
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 void spi_free(spi_t *obj) {}
elessair 0:f269e3021894 63
elessair 0:f269e3021894 64 void spi_format(spi_t *obj, int bits, int mode, int slave) {
elessair 0:f269e3021894 65 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 ssp_disable(obj);
elessair 0:f269e3021894 68
elessair 0:f269e3021894 69 int polarity = (mode & 0x2) ? 1 : 0;
elessair 0:f269e3021894 70 int phase = (mode & 0x1) ? 1 : 0;
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 // set it up
elessair 0:f269e3021894 73 int DSS = bits - 1; // DSS (data select size)
elessair 0:f269e3021894 74 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
elessair 0:f269e3021894 75 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 int FRF = 0; // FRF (frame format) = SPI
elessair 0:f269e3021894 78 uint32_t tmp = obj->spi->CR0;
elessair 0:f269e3021894 79 tmp &= ~(0xFFFF);
elessair 0:f269e3021894 80 tmp |= DSS << 0
elessair 0:f269e3021894 81 | FRF << 4
elessair 0:f269e3021894 82 | SPO << 6
elessair 0:f269e3021894 83 | SPH << 7;
elessair 0:f269e3021894 84 obj->spi->CR0 = tmp;
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 tmp = obj->spi->CR1;
elessair 0:f269e3021894 87 tmp &= ~(0xD);
elessair 0:f269e3021894 88 tmp |= 0 << 0 // LBM - loop back mode - off
elessair 0:f269e3021894 89 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
elessair 0:f269e3021894 90 | 0 << 3; // SOD - slave output disable - na
elessair 0:f269e3021894 91 obj->spi->CR1 = tmp;
elessair 0:f269e3021894 92
elessair 0:f269e3021894 93 ssp_enable(obj);
elessair 0:f269e3021894 94 }
elessair 0:f269e3021894 95
elessair 0:f269e3021894 96 void spi_frequency(spi_t *obj, int hz) {
elessair 0:f269e3021894 97 ssp_disable(obj);
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 uint32_t PCLK = SystemCoreClock;
elessair 0:f269e3021894 100
elessair 0:f269e3021894 101 int prescaler;
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
elessair 0:f269e3021894 104 int prescale_hz = PCLK / prescaler;
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 // calculate the divider
elessair 0:f269e3021894 107 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 // check we can support the divider
elessair 0:f269e3021894 110 if (divider < 256) {
elessair 0:f269e3021894 111 // prescaler
elessair 0:f269e3021894 112 obj->spi->CPSR = prescaler;
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 // divider
elessair 0:f269e3021894 115 obj->spi->CR0 &= ~(0xFFFF << 8);
elessair 0:f269e3021894 116 obj->spi->CR0 |= (divider - 1) << 8;
elessair 0:f269e3021894 117 ssp_enable(obj);
elessair 0:f269e3021894 118 return;
elessair 0:f269e3021894 119 }
elessair 0:f269e3021894 120 }
elessair 0:f269e3021894 121 error("Couldn't setup requested SPI frequency");
elessair 0:f269e3021894 122 }
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 static inline int ssp_disable(spi_t *obj) {
elessair 0:f269e3021894 125 return obj->spi->CR1 &= ~(1 << 1);
elessair 0:f269e3021894 126 }
elessair 0:f269e3021894 127
elessair 0:f269e3021894 128 static inline int ssp_enable(spi_t *obj) {
elessair 0:f269e3021894 129 return obj->spi->CR1 |= (1 << 1);
elessair 0:f269e3021894 130 }
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 static inline int ssp_readable(spi_t *obj) {
elessair 0:f269e3021894 133 return obj->spi->SR & (1 << 2);
elessair 0:f269e3021894 134 }
elessair 0:f269e3021894 135
elessair 0:f269e3021894 136 static inline int ssp_writeable(spi_t *obj) {
elessair 0:f269e3021894 137 return obj->spi->SR & (1 << 1);
elessair 0:f269e3021894 138 }
elessair 0:f269e3021894 139
elessair 0:f269e3021894 140 static inline void ssp_write(spi_t *obj, int value) {
elessair 0:f269e3021894 141 while (!ssp_writeable(obj));
elessair 0:f269e3021894 142 obj->spi->DR = value;
elessair 0:f269e3021894 143 }
elessair 0:f269e3021894 144
elessair 0:f269e3021894 145 static inline int ssp_read(spi_t *obj) {
elessair 0:f269e3021894 146 while (!ssp_readable(obj));
elessair 0:f269e3021894 147 return obj->spi->DR;
elessair 0:f269e3021894 148 }
elessair 0:f269e3021894 149
elessair 0:f269e3021894 150 static inline int ssp_busy(spi_t *obj) {
elessair 0:f269e3021894 151 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
elessair 0:f269e3021894 152 }
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 int spi_master_write(spi_t *obj, int value) {
elessair 0:f269e3021894 155 ssp_write(obj, value);
elessair 0:f269e3021894 156 return ssp_read(obj);
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 int spi_slave_receive(spi_t *obj) {
elessair 0:f269e3021894 160 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
elessair 0:f269e3021894 161 }
elessair 0:f269e3021894 162
elessair 0:f269e3021894 163 int spi_slave_read(spi_t *obj) {
elessair 0:f269e3021894 164 return obj->spi->DR;
elessair 0:f269e3021894 165 }
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 void spi_slave_write(spi_t *obj, int value) {
elessair 0:f269e3021894 168 while (ssp_writeable(obj) == 0) ;
elessair 0:f269e3021894 169 obj->spi->DR = value;
elessair 0:f269e3021894 170 }
elessair 0:f269e3021894 171
elessair 0:f269e3021894 172 int spi_busy(spi_t *obj) {
elessair 0:f269e3021894 173 return ssp_busy(obj);
elessair 0:f269e3021894 174 }