erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2015-2016 Nuvoton
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16
elessair 0:f269e3021894 17 #include "serial_api.h"
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #if DEVICE_SERIAL
elessair 0:f269e3021894 20
elessair 0:f269e3021894 21 #include "cmsis.h"
elessair 0:f269e3021894 22 #include "mbed_error.h"
elessair 0:f269e3021894 23 #include "mbed_assert.h"
elessair 0:f269e3021894 24 #include "PeripheralPins.h"
elessair 0:f269e3021894 25 #include "nu_modutil.h"
elessair 0:f269e3021894 26 #include "nu_bitutil.h"
elessair 0:f269e3021894 27
elessair 0:f269e3021894 28 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 29 #include "dma_api.h"
elessair 0:f269e3021894 30 #include "dma.h"
elessair 0:f269e3021894 31 #endif
elessair 0:f269e3021894 32
elessair 0:f269e3021894 33 struct nu_uart_var {
elessair 0:f269e3021894 34 serial_t * obj;
elessair 0:f269e3021894 35 uint32_t fifo_size_tx;
elessair 0:f269e3021894 36 uint32_t fifo_size_rx;
elessair 0:f269e3021894 37 void (*vec)(void);
elessair 0:f269e3021894 38 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 39 void (*vec_async)(void);
elessair 0:f269e3021894 40 uint8_t pdma_perp_tx;
elessair 0:f269e3021894 41 uint8_t pdma_perp_rx;
elessair 0:f269e3021894 42 #endif
elessair 0:f269e3021894 43 };
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 static void uart0_vec(void);
elessair 0:f269e3021894 46 static void uart1_vec(void);
elessair 0:f269e3021894 47 static void uart2_vec(void);
elessair 0:f269e3021894 48 static void uart3_vec(void);
elessair 0:f269e3021894 49 static void uart_irq(serial_t *obj);
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 52 static void uart0_vec_async(void);
elessair 0:f269e3021894 53 static void uart1_vec_async(void);
elessair 0:f269e3021894 54 static void uart2_vec_async(void);
elessair 0:f269e3021894 55 static void uart3_vec_async(void);
elessair 0:f269e3021894 56 static void uart_irq_async(serial_t *obj);
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
elessair 0:f269e3021894 59 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
elessair 0:f269e3021894 60
elessair 0:f269e3021894 61 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
elessair 0:f269e3021894 62 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
elessair 0:f269e3021894 63 static int serial_write_async(serial_t *obj);
elessair 0:f269e3021894 64 static int serial_read_async(serial_t *obj);
elessair 0:f269e3021894 65
elessair 0:f269e3021894 66 static uint32_t serial_rx_event_check(serial_t *obj);
elessair 0:f269e3021894 67 static uint32_t serial_tx_event_check(serial_t *obj);
elessair 0:f269e3021894 68
elessair 0:f269e3021894 69 static int serial_is_tx_complete(serial_t *obj);
elessair 0:f269e3021894 70 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
elessair 0:f269e3021894 73 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
elessair 0:f269e3021894 74 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
elessair 0:f269e3021894 75 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
elessair 0:f269e3021894 76 static int serial_is_rx_complete(serial_t *obj);
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
elessair 0:f269e3021894 79 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
elessair 0:f269e3021894 80 #endif
elessair 0:f269e3021894 81
elessair 0:f269e3021894 82 static struct nu_uart_var uart0_var = {
elessair 0:f269e3021894 83 .obj = NULL,
elessair 0:f269e3021894 84 .fifo_size_tx = 16,
elessair 0:f269e3021894 85 .fifo_size_rx = 16,
elessair 0:f269e3021894 86 .vec = uart0_vec,
elessair 0:f269e3021894 87 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 88 .vec_async = uart0_vec_async,
elessair 0:f269e3021894 89 .pdma_perp_tx = PDMA_UART0_TX,
elessair 0:f269e3021894 90 .pdma_perp_rx = PDMA_UART0_RX
elessair 0:f269e3021894 91 #endif
elessair 0:f269e3021894 92 };
elessair 0:f269e3021894 93 static struct nu_uart_var uart1_var = {
elessair 0:f269e3021894 94 .obj = NULL,
elessair 0:f269e3021894 95 .fifo_size_tx = 16,
elessair 0:f269e3021894 96 .fifo_size_rx = 16,
elessair 0:f269e3021894 97 .vec = uart1_vec,
elessair 0:f269e3021894 98 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 99 .vec_async = uart1_vec_async,
elessair 0:f269e3021894 100 .pdma_perp_tx = PDMA_UART1_TX,
elessair 0:f269e3021894 101 .pdma_perp_rx = PDMA_UART1_RX
elessair 0:f269e3021894 102 #endif
elessair 0:f269e3021894 103 };
elessair 0:f269e3021894 104 static struct nu_uart_var uart2_var = {
elessair 0:f269e3021894 105 .obj = NULL,
elessair 0:f269e3021894 106 .fifo_size_tx = 16,
elessair 0:f269e3021894 107 .fifo_size_rx = 16,
elessair 0:f269e3021894 108 .vec = uart2_vec,
elessair 0:f269e3021894 109 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 110 .vec_async = uart2_vec_async,
elessair 0:f269e3021894 111 .pdma_perp_tx = PDMA_UART2_TX,
elessair 0:f269e3021894 112 .pdma_perp_rx = PDMA_UART2_RX
elessair 0:f269e3021894 113 #endif
elessair 0:f269e3021894 114 };
elessair 0:f269e3021894 115 static struct nu_uart_var uart3_var = {
elessair 0:f269e3021894 116 .obj = NULL,
elessair 0:f269e3021894 117 .fifo_size_tx = 16,
elessair 0:f269e3021894 118 .fifo_size_rx = 16,
elessair 0:f269e3021894 119 .vec = uart3_vec,
elessair 0:f269e3021894 120 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 121 .vec_async = uart3_vec_async,
elessair 0:f269e3021894 122 .pdma_perp_tx = PDMA_UART3_TX,
elessair 0:f269e3021894 123 .pdma_perp_rx = PDMA_UART3_RX
elessair 0:f269e3021894 124 #endif
elessair 0:f269e3021894 125 };
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127
elessair 0:f269e3021894 128 int stdio_uart_inited = 0;
elessair 0:f269e3021894 129 serial_t stdio_uart;
elessair 0:f269e3021894 130 static uint32_t uart_modinit_mask = 0;
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 static const struct nu_modinit_s uart_modinit_tab[] = {
elessair 0:f269e3021894 133 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
elessair 0:f269e3021894 134 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
elessair 0:f269e3021894 135 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
elessair 0:f269e3021894 136 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
elessair 0:f269e3021894 139 };
elessair 0:f269e3021894 140
elessair 0:f269e3021894 141 extern void mbed_sdk_init(void);
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143 void serial_init(serial_t *obj, PinName tx, PinName rx)
elessair 0:f269e3021894 144 {
elessair 0:f269e3021894 145 // NOTE: serial_init() gets called from _sys_open() timing of which is before main()/mbed_hal_init().
elessair 0:f269e3021894 146 mbed_sdk_init();
elessair 0:f269e3021894 147
elessair 0:f269e3021894 148 // Determine which UART_x the pins are used for
elessair 0:f269e3021894 149 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
elessair 0:f269e3021894 150 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
elessair 0:f269e3021894 151 // Get the peripheral name (UART_x) from the pins and assign it to the object
elessair 0:f269e3021894 152 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
elessair 0:f269e3021894 153 MBED_ASSERT((int)obj->serial.uart != NC);
elessair 0:f269e3021894 154
elessair 0:f269e3021894 155 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 156 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 157 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 // Reset this module
elessair 0:f269e3021894 160 SYS_ResetModule(modinit->rsetidx);
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 // Select IP clock source
elessair 0:f269e3021894 163 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
elessair 0:f269e3021894 164 // Enable IP clock
elessair 0:f269e3021894 165 CLK_EnableModuleClock(modinit->clkidx);
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 168 pinmap_pinout(rx, PinMap_UART_RX);
elessair 0:f269e3021894 169 // FIXME: Why PullUp?
elessair 0:f269e3021894 170 //if (tx != NC) {
elessair 0:f269e3021894 171 // pin_mode(tx, PullUp);
elessair 0:f269e3021894 172 //}
elessair 0:f269e3021894 173 //if (rx != NC) {
elessair 0:f269e3021894 174 // pin_mode(rx, PullUp);
elessair 0:f269e3021894 175 //}
elessair 0:f269e3021894 176 obj->serial.pin_tx = tx;
elessair 0:f269e3021894 177 obj->serial.pin_rx = rx;
elessair 0:f269e3021894 178
elessair 0:f269e3021894 179 // Configure the UART module and set its baudrate
elessair 0:f269e3021894 180 serial_baud(obj, 9600);
elessair 0:f269e3021894 181 // Configure data bits, parity, and stop bits
elessair 0:f269e3021894 182 serial_format(obj, 8, ParityNone, 1);
elessair 0:f269e3021894 183
elessair 0:f269e3021894 184 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
elessair 0:f269e3021894 185
elessair 0:f269e3021894 186 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 187 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
elessair 0:f269e3021894 188 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
elessair 0:f269e3021894 189 obj->serial.event = 0;
elessair 0:f269e3021894 190 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 191 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 192 #endif
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 // For stdio management
elessair 0:f269e3021894 195 if (obj == &stdio_uart) {
elessair 0:f269e3021894 196 stdio_uart_inited = 1;
elessair 0:f269e3021894 197 /* NOTE: Not required anymore because stdio_uart will be manually initialized in mbed-drivers/source/retarget.cpp from mbed beta */
elessair 0:f269e3021894 198 //memcpy(&stdio_uart, obj, sizeof(serial_t));
elessair 0:f269e3021894 199 }
elessair 0:f269e3021894 200
elessair 0:f269e3021894 201 // Mark this module to be inited.
elessair 0:f269e3021894 202 int i = modinit - uart_modinit_tab;
elessair 0:f269e3021894 203 uart_modinit_mask |= 1 << i;
elessair 0:f269e3021894 204 }
elessair 0:f269e3021894 205
elessair 0:f269e3021894 206 void serial_free(serial_t *obj)
elessair 0:f269e3021894 207 {
elessair 0:f269e3021894 208 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 209 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 210 dma_channel_free(obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 211 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 212 }
elessair 0:f269e3021894 213 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 214 dma_channel_free(obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 215 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 216 }
elessair 0:f269e3021894 217 #endif
elessair 0:f269e3021894 218
elessair 0:f269e3021894 219 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
elessair 0:f269e3021894 220
elessair 0:f269e3021894 221 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 222 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 223 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 224
elessair 0:f269e3021894 225 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 226 NVIC_DisableIRQ(modinit->irq_n);
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 // Disable IP clock
elessair 0:f269e3021894 229 CLK_DisableModuleClock(modinit->clkidx);
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 ((struct nu_uart_var *) modinit->var)->obj = NULL;
elessair 0:f269e3021894 232
elessair 0:f269e3021894 233 if (obj == &stdio_uart) {
elessair 0:f269e3021894 234 stdio_uart_inited = 0;
elessair 0:f269e3021894 235 }
elessair 0:f269e3021894 236
elessair 0:f269e3021894 237 // Mark this module to be deinited.
elessair 0:f269e3021894 238 int i = modinit - uart_modinit_tab;
elessair 0:f269e3021894 239 uart_modinit_mask &= ~(1 << i);
elessair 0:f269e3021894 240 }
elessair 0:f269e3021894 241
elessair 0:f269e3021894 242 void serial_baud(serial_t *obj, int baudrate) {
elessair 0:f269e3021894 243 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 244 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 245
elessair 0:f269e3021894 246 obj->serial.baudrate = baudrate;
elessair 0:f269e3021894 247 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
elessair 0:f269e3021894 248 }
elessair 0:f269e3021894 249
elessair 0:f269e3021894 250 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
elessair 0:f269e3021894 251 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 252 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 253
elessair 0:f269e3021894 254 // TODO: Assert for not supported parity and data bits
elessair 0:f269e3021894 255 obj->serial.databits = data_bits;
elessair 0:f269e3021894 256 obj->serial.parity = parity;
elessair 0:f269e3021894 257 obj->serial.stopbits = stop_bits;
elessair 0:f269e3021894 258
elessair 0:f269e3021894 259 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
elessair 0:f269e3021894 260 (data_bits == 6) ? UART_WORD_LEN_6 :
elessair 0:f269e3021894 261 (data_bits == 7) ? UART_WORD_LEN_7 :
elessair 0:f269e3021894 262 UART_WORD_LEN_8;
elessair 0:f269e3021894 263 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
elessair 0:f269e3021894 264 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
elessair 0:f269e3021894 265 UART_PARITY_NONE;
elessair 0:f269e3021894 266 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
elessair 0:f269e3021894 267 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
elessair 0:f269e3021894 268 0, // Don't change baudrate
elessair 0:f269e3021894 269 databits_intern,
elessair 0:f269e3021894 270 parity_intern,
elessair 0:f269e3021894 271 stopbits_intern);
elessair 0:f269e3021894 272 }
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 #if DEVICE_SERIAL_FC
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
elessair 0:f269e3021894 277 {
elessair 0:f269e3021894 278 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 279
elessair 0:f269e3021894 280 // First, disable flow control completely.
elessair 0:f269e3021894 281 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
elessair 0:f269e3021894 282
elessair 0:f269e3021894 283 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
elessair 0:f269e3021894 284 // Check if RTS pin matches.
elessair 0:f269e3021894 285 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
elessair 0:f269e3021894 286 MBED_ASSERT(uart_rts == obj->serial.uart);
elessair 0:f269e3021894 287 // Enable the pin for RTS function
elessair 0:f269e3021894 288 pinmap_pinout(rxflow, PinMap_UART_RTS);
elessair 0:f269e3021894 289 // nRTS pin output is high level active
elessair 0:f269e3021894 290 uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk);
elessair 0:f269e3021894 291 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
elessair 0:f269e3021894 292 // Enable RTS
elessair 0:f269e3021894 293 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
elessair 0:f269e3021894 294 }
elessair 0:f269e3021894 295
elessair 0:f269e3021894 296 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
elessair 0:f269e3021894 297 // Check if CTS pin matches.
elessair 0:f269e3021894 298 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
elessair 0:f269e3021894 299 MBED_ASSERT(uart_cts == obj->serial.uart);
elessair 0:f269e3021894 300 // Enable the pin for CTS function
elessair 0:f269e3021894 301 pinmap_pinout(txflow, PinMap_UART_CTS);
elessair 0:f269e3021894 302 // nCTS pin input is high level active
elessair 0:f269e3021894 303 uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk);
elessair 0:f269e3021894 304 // Enable CTS
elessair 0:f269e3021894 305 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
elessair 0:f269e3021894 306 }
elessair 0:f269e3021894 307 }
elessair 0:f269e3021894 308
elessair 0:f269e3021894 309 #endif //DEVICE_SERIAL_FC
elessair 0:f269e3021894 310
elessair 0:f269e3021894 311 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
elessair 0:f269e3021894 312 {
elessair 0:f269e3021894 313 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 314 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 315
elessair 0:f269e3021894 316 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 317 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 318 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 319
elessair 0:f269e3021894 320 ((struct nu_uart_var *) modinit->var)->obj = obj;
elessair 0:f269e3021894 321 obj->serial.irq_handler = (uint32_t) handler;
elessair 0:f269e3021894 322 obj->serial.irq_id = id;
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 // Restore sync-mode vector
elessair 0:f269e3021894 325 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
elessair 0:f269e3021894 326 }
elessair 0:f269e3021894 327
elessair 0:f269e3021894 328 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
elessair 0:f269e3021894 329 {
elessair 0:f269e3021894 330 if (enable) {
elessair 0:f269e3021894 331 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 332 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 333 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 334
elessair 0:f269e3021894 335 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
elessair 0:f269e3021894 336 NVIC_EnableIRQ(modinit->irq_n);
elessair 0:f269e3021894 337
elessair 0:f269e3021894 338 switch (irq) {
elessair 0:f269e3021894 339 // NOTE: Setting inten_msk first to avoid race condition
elessair 0:f269e3021894 340 case RxIrq:
elessair 0:f269e3021894 341 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elessair 0:f269e3021894 342 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 343 break;
elessair 0:f269e3021894 344 case TxIrq:
elessair 0:f269e3021894 345 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
elessair 0:f269e3021894 346 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 347 break;
elessair 0:f269e3021894 348 }
elessair 0:f269e3021894 349 } else { // disable
elessair 0:f269e3021894 350 switch (irq) {
elessair 0:f269e3021894 351 case RxIrq:
elessair 0:f269e3021894 352 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 353 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elessair 0:f269e3021894 354 break;
elessair 0:f269e3021894 355 case TxIrq:
elessair 0:f269e3021894 356 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 357 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
elessair 0:f269e3021894 358 break;
elessair 0:f269e3021894 359 }
elessair 0:f269e3021894 360 }
elessair 0:f269e3021894 361 }
elessair 0:f269e3021894 362
elessair 0:f269e3021894 363 int serial_getc(serial_t *obj)
elessair 0:f269e3021894 364 {
elessair 0:f269e3021894 365 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
elessair 0:f269e3021894 366 while (! serial_readable(obj));
elessair 0:f269e3021894 367 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 368
elessair 0:f269e3021894 369 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 370 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elessair 0:f269e3021894 371 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 372 }
elessair 0:f269e3021894 373
elessair 0:f269e3021894 374 return c;
elessair 0:f269e3021894 375 }
elessair 0:f269e3021894 376
elessair 0:f269e3021894 377 void serial_putc(serial_t *obj, int c)
elessair 0:f269e3021894 378 {
elessair 0:f269e3021894 379 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
elessair 0:f269e3021894 380 while (! serial_writable(obj));
elessair 0:f269e3021894 381 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
elessair 0:f269e3021894 382
elessair 0:f269e3021894 383 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 384 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elessair 0:f269e3021894 385 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 386 }
elessair 0:f269e3021894 387 }
elessair 0:f269e3021894 388
elessair 0:f269e3021894 389 int serial_readable(serial_t *obj)
elessair 0:f269e3021894 390 {
elessair 0:f269e3021894 391 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 392 return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 393 }
elessair 0:f269e3021894 394
elessair 0:f269e3021894 395 int serial_writable(serial_t *obj)
elessair 0:f269e3021894 396 {
elessair 0:f269e3021894 397 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 398 }
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 void serial_pinout_tx(PinName tx)
elessair 0:f269e3021894 401 {
elessair 0:f269e3021894 402 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 403 }
elessair 0:f269e3021894 404
elessair 0:f269e3021894 405 void serial_break_set(serial_t *obj)
elessair 0:f269e3021894 406 {
elessair 0:f269e3021894 407 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
elessair 0:f269e3021894 408 }
elessair 0:f269e3021894 409
elessair 0:f269e3021894 410 void serial_break_clear(serial_t *obj)
elessair 0:f269e3021894 411 {
elessair 0:f269e3021894 412 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
elessair 0:f269e3021894 413 }
elessair 0:f269e3021894 414
elessair 0:f269e3021894 415 static void uart0_vec(void)
elessair 0:f269e3021894 416 {
elessair 0:f269e3021894 417 uart_irq(uart0_var.obj);
elessair 0:f269e3021894 418 }
elessair 0:f269e3021894 419
elessair 0:f269e3021894 420 static void uart1_vec(void)
elessair 0:f269e3021894 421 {
elessair 0:f269e3021894 422 uart_irq(uart1_var.obj);
elessair 0:f269e3021894 423 }
elessair 0:f269e3021894 424
elessair 0:f269e3021894 425 static void uart2_vec(void)
elessair 0:f269e3021894 426 {
elessair 0:f269e3021894 427 uart_irq(uart2_var.obj);
elessair 0:f269e3021894 428 }
elessair 0:f269e3021894 429
elessair 0:f269e3021894 430 static void uart3_vec(void)
elessair 0:f269e3021894 431 {
elessair 0:f269e3021894 432 uart_irq(uart3_var.obj);
elessair 0:f269e3021894 433 }
elessair 0:f269e3021894 434
elessair 0:f269e3021894 435 static void uart_irq(serial_t *obj)
elessair 0:f269e3021894 436 {
elessair 0:f269e3021894 437 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 438
elessair 0:f269e3021894 439 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
elessair 0:f269e3021894 440 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
elessair 0:f269e3021894 441 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 442 if (obj->serial.irq_handler) {
elessair 0:f269e3021894 443 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
elessair 0:f269e3021894 444 }
elessair 0:f269e3021894 445 }
elessair 0:f269e3021894 446
elessair 0:f269e3021894 447 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
elessair 0:f269e3021894 448 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
elessair 0:f269e3021894 449 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 450 if (obj->serial.irq_handler) {
elessair 0:f269e3021894 451 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
elessair 0:f269e3021894 452 }
elessair 0:f269e3021894 453 }
elessair 0:f269e3021894 454
elessair 0:f269e3021894 455 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
elessair 0:f269e3021894 456 uart_base->INTSTS = uart_base->INTSTS;
elessair 0:f269e3021894 457 uart_base->FIFOSTS = uart_base->FIFOSTS;
elessair 0:f269e3021894 458 }
elessair 0:f269e3021894 459
elessair 0:f269e3021894 460
elessair 0:f269e3021894 461 #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 462 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
elessair 0:f269e3021894 463 {
elessair 0:f269e3021894 464 // NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
elessair 0:f269e3021894 465 tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
elessair 0:f269e3021894 466
elessair 0:f269e3021894 467 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
elessair 0:f269e3021894 468
elessair 0:f269e3021894 469 obj->serial.dma_usage_tx = hint;
elessair 0:f269e3021894 470 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 471
elessair 0:f269e3021894 472 // UART IRQ is necessary for both interrupt way and DMA way
elessair 0:f269e3021894 473 serial_tx_enable_event(obj, event, 1);
elessair 0:f269e3021894 474 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
elessair 0:f269e3021894 475 //UART_HAL_DisableTransmitter(obj->serial.address);
elessair 0:f269e3021894 476 //UART_HAL_FlushTxFifo(obj->serial.address);
elessair 0:f269e3021894 477 //UART_HAL_EnableTransmitter(obj->serial.address);
elessair 0:f269e3021894 478
elessair 0:f269e3021894 479 int n_word = 0;
elessair 0:f269e3021894 480 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 481 // Interrupt way
elessair 0:f269e3021894 482 n_word = serial_write_async(obj);
elessair 0:f269e3021894 483 serial_tx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 484 } else {
elessair 0:f269e3021894 485 // DMA way
elessair 0:f269e3021894 486 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 487 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 488 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 489
elessair 0:f269e3021894 490 PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
elessair 0:f269e3021894 491 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 492 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
elessair 0:f269e3021894 493 0, // Scatter-gather disabled
elessair 0:f269e3021894 494 0); // Scatter-gather descriptor address
elessair 0:f269e3021894 495 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 496 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
elessair 0:f269e3021894 497 tx_length);
elessair 0:f269e3021894 498 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 499 (uint32_t) tx, // NOTE:
elessair 0:f269e3021894 500 // NUC472: End of source address
elessair 0:f269e3021894 501 // M451: Start of source address
elessair 0:f269e3021894 502 PDMA_SAR_INC, // Source address incremental
elessair 0:f269e3021894 503 (uint32_t) obj->serial.uart, // Destination address
elessair 0:f269e3021894 504 PDMA_DAR_FIX); // Destination address fixed
elessair 0:f269e3021894 505 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 506 PDMA_REQ_SINGLE, // Single mode
elessair 0:f269e3021894 507 0); // Burst size
elessair 0:f269e3021894 508 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
elessair 0:f269e3021894 509 PDMA_INT_TRANS_DONE); // Interrupt type
elessair 0:f269e3021894 510 // Register DMA event handler
elessair 0:f269e3021894 511 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
elessair 0:f269e3021894 512 serial_tx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 513 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
elessair 0:f269e3021894 514 }
elessair 0:f269e3021894 515
elessair 0:f269e3021894 516 return n_word;
elessair 0:f269e3021894 517 }
elessair 0:f269e3021894 518
elessair 0:f269e3021894 519 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
elessair 0:f269e3021894 520 {
elessair 0:f269e3021894 521 // NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
elessair 0:f269e3021894 522 rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
elessair 0:f269e3021894 525
elessair 0:f269e3021894 526 obj->serial.dma_usage_rx = hint;
elessair 0:f269e3021894 527 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 528 // DMA doesn't support char match, so fall back to IRQ if it is requested.
elessair 0:f269e3021894 529 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
elessair 0:f269e3021894 530 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
elessair 0:f269e3021894 531 char_match != SERIAL_RESERVED_CHAR_MATCH) {
elessair 0:f269e3021894 532 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
elessair 0:f269e3021894 533 dma_channel_free(obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 534 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 535 }
elessair 0:f269e3021894 536
elessair 0:f269e3021894 537 // UART IRQ is necessary for both interrupt way and DMA way
elessair 0:f269e3021894 538 serial_rx_enable_event(obj, event, 1);
elessair 0:f269e3021894 539 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
elessair 0:f269e3021894 540 serial_rx_set_char_match(obj, char_match);
elessair 0:f269e3021894 541 //UART_HAL_DisableReceiver(obj->serial.address);
elessair 0:f269e3021894 542 //UART_HAL_FlushRxFifo(obj->serial.address);
elessair 0:f269e3021894 543 //UART_HAL_EnableReceiver(obj->serial.address);
elessair 0:f269e3021894 544
elessair 0:f269e3021894 545 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 546 // Interrupt way
elessair 0:f269e3021894 547 serial_rx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 548 } else {
elessair 0:f269e3021894 549 // DMA way
elessair 0:f269e3021894 550 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 551 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 552 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 553
elessair 0:f269e3021894 554 PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
elessair 0:f269e3021894 555 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 556 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
elessair 0:f269e3021894 557 0, // Scatter-gather disabled
elessair 0:f269e3021894 558 0); // Scatter-gather descriptor address
elessair 0:f269e3021894 559 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 560 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
elessair 0:f269e3021894 561 rx_length);
elessair 0:f269e3021894 562 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 563 (uint32_t) obj->serial.uart, // Source address
elessair 0:f269e3021894 564 PDMA_SAR_FIX, // Source address fixed
elessair 0:f269e3021894 565 (uint32_t) rx, // NOTE:
elessair 0:f269e3021894 566 // NUC472: End of destination address
elessair 0:f269e3021894 567 // M451: Start of destination address
elessair 0:f269e3021894 568 PDMA_DAR_INC); // Destination address incremental
elessair 0:f269e3021894 569 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 570 PDMA_REQ_SINGLE, // Single mode
elessair 0:f269e3021894 571 0); // Burst size
elessair 0:f269e3021894 572 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
elessair 0:f269e3021894 573 PDMA_INT_TRANS_DONE); // Interrupt type
elessair 0:f269e3021894 574 // Register DMA event handler
elessair 0:f269e3021894 575 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
elessair 0:f269e3021894 576 serial_rx_enable_interrupt(obj, handler, 1);
elessair 0:f269e3021894 577 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
elessair 0:f269e3021894 578 }
elessair 0:f269e3021894 579 }
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 void serial_tx_abort_asynch(serial_t *obj)
elessair 0:f269e3021894 582 {
elessair 0:f269e3021894 583 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
elessair 0:f269e3021894 584 while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
elessair 0:f269e3021894 585
elessair 0:f269e3021894 586 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
elessair 0:f269e3021894 587 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 588 PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
elessair 0:f269e3021894 589 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
elessair 0:f269e3021894 590 //PDMA_STOP(obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 591 PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
elessair 0:f269e3021894 592 }
elessair 0:f269e3021894 593 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
elessair 0:f269e3021894 594 }
elessair 0:f269e3021894 595
elessair 0:f269e3021894 596 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 597 serial_irq_set(obj, TxIrq, 0);
elessair 0:f269e3021894 598 // FIXME: more complete abort operation
elessair 0:f269e3021894 599 //UART_HAL_DisableTransmitter(obj->serial.serial.address);
elessair 0:f269e3021894 600 //UART_HAL_FlushTxFifo(obj->serial.serial.address);
elessair 0:f269e3021894 601 }
elessair 0:f269e3021894 602
elessair 0:f269e3021894 603 void serial_rx_abort_asynch(serial_t *obj)
elessair 0:f269e3021894 604 {
elessair 0:f269e3021894 605 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
elessair 0:f269e3021894 606 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 607 PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
elessair 0:f269e3021894 608 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
elessair 0:f269e3021894 609 //PDMA_STOP(obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 610 PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
elessair 0:f269e3021894 611 }
elessair 0:f269e3021894 612 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
elessair 0:f269e3021894 613 }
elessair 0:f269e3021894 614
elessair 0:f269e3021894 615 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 616 serial_irq_set(obj, RxIrq, 0);
elessair 0:f269e3021894 617 // FIXME: more complete abort operation
elessair 0:f269e3021894 618 //UART_HAL_DisableReceiver(obj->serial.serial.address);
elessair 0:f269e3021894 619 //UART_HAL_FlushRxFifo(obj->serial.serial.address);
elessair 0:f269e3021894 620 }
elessair 0:f269e3021894 621
elessair 0:f269e3021894 622 uint8_t serial_tx_active(serial_t *obj)
elessair 0:f269e3021894 623 {
elessair 0:f269e3021894 624 return serial_is_irq_en(obj, TxIrq);
elessair 0:f269e3021894 625 }
elessair 0:f269e3021894 626
elessair 0:f269e3021894 627 uint8_t serial_rx_active(serial_t *obj)
elessair 0:f269e3021894 628 {
elessair 0:f269e3021894 629 return serial_is_irq_en(obj, RxIrq);
elessair 0:f269e3021894 630 }
elessair 0:f269e3021894 631
elessair 0:f269e3021894 632 int serial_irq_handler_asynch(serial_t *obj)
elessair 0:f269e3021894 633 {
elessair 0:f269e3021894 634 int event_rx = 0;
elessair 0:f269e3021894 635 int event_tx = 0;
elessair 0:f269e3021894 636
elessair 0:f269e3021894 637 // Necessary for both interrup way and DMA way
elessair 0:f269e3021894 638 if (serial_is_irq_en(obj, RxIrq)) {
elessair 0:f269e3021894 639 event_rx = serial_rx_event_check(obj);
elessair 0:f269e3021894 640 if (event_rx) {
elessair 0:f269e3021894 641 serial_rx_abort_asynch(obj);
elessair 0:f269e3021894 642 }
elessair 0:f269e3021894 643 }
elessair 0:f269e3021894 644
elessair 0:f269e3021894 645 if (serial_is_irq_en(obj, TxIrq)) {
elessair 0:f269e3021894 646 event_tx = serial_tx_event_check(obj);
elessair 0:f269e3021894 647 if (event_tx) {
elessair 0:f269e3021894 648 serial_tx_abort_asynch(obj);
elessair 0:f269e3021894 649 }
elessair 0:f269e3021894 650 }
elessair 0:f269e3021894 651
elessair 0:f269e3021894 652 return (obj->serial.event & (event_rx | event_tx));
elessair 0:f269e3021894 653 }
elessair 0:f269e3021894 654
elessair 0:f269e3021894 655 int serial_allow_powerdown(void)
elessair 0:f269e3021894 656 {
elessair 0:f269e3021894 657 uint32_t modinit_mask = uart_modinit_mask;
elessair 0:f269e3021894 658 while (modinit_mask) {
elessair 0:f269e3021894 659 int uart_idx = nu_ctz(modinit_mask);
elessair 0:f269e3021894 660 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
elessair 0:f269e3021894 661 if (modinit->modname != NC) {
elessair 0:f269e3021894 662 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
elessair 0:f269e3021894 663 // Disallow entering power-down mode if Tx FIFO has data to flush
elessair 0:f269e3021894 664 if (! UART_IS_TX_EMPTY((uart_base))) {
elessair 0:f269e3021894 665 return 0;
elessair 0:f269e3021894 666 }
elessair 0:f269e3021894 667 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
elessair 0:f269e3021894 668 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elessair 0:f269e3021894 669 return 0;
elessair 0:f269e3021894 670 }
elessair 0:f269e3021894 671 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
elessair 0:f269e3021894 672 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
elessair 0:f269e3021894 673 return 0;
elessair 0:f269e3021894 674 }
elessair 0:f269e3021894 675 }
elessair 0:f269e3021894 676 modinit_mask &= ~(1 << uart_idx);
elessair 0:f269e3021894 677 }
elessair 0:f269e3021894 678
elessair 0:f269e3021894 679 return 1;
elessair 0:f269e3021894 680 }
elessair 0:f269e3021894 681
elessair 0:f269e3021894 682 static void uart0_vec_async(void)
elessair 0:f269e3021894 683 {
elessair 0:f269e3021894 684 uart_irq_async(uart0_var.obj);
elessair 0:f269e3021894 685 }
elessair 0:f269e3021894 686
elessair 0:f269e3021894 687 static void uart1_vec_async(void)
elessair 0:f269e3021894 688 {
elessair 0:f269e3021894 689 uart_irq_async(uart1_var.obj);
elessair 0:f269e3021894 690 }
elessair 0:f269e3021894 691
elessair 0:f269e3021894 692 static void uart2_vec_async(void)
elessair 0:f269e3021894 693 {
elessair 0:f269e3021894 694 uart_irq_async(uart2_var.obj);
elessair 0:f269e3021894 695 }
elessair 0:f269e3021894 696
elessair 0:f269e3021894 697 static void uart3_vec_async(void)
elessair 0:f269e3021894 698 {
elessair 0:f269e3021894 699 uart_irq_async(uart3_var.obj);
elessair 0:f269e3021894 700 }
elessair 0:f269e3021894 701
elessair 0:f269e3021894 702 static void uart_irq_async(serial_t *obj)
elessair 0:f269e3021894 703 {
elessair 0:f269e3021894 704 if (serial_is_irq_en(obj, RxIrq)) {
elessair 0:f269e3021894 705 (*obj->serial.irq_handler_rx_async)();
elessair 0:f269e3021894 706 }
elessair 0:f269e3021894 707 if (serial_is_irq_en(obj, TxIrq)) {
elessair 0:f269e3021894 708 (*obj->serial.irq_handler_tx_async)();
elessair 0:f269e3021894 709 }
elessair 0:f269e3021894 710 }
elessair 0:f269e3021894 711
elessair 0:f269e3021894 712 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
elessair 0:f269e3021894 713 {
elessair 0:f269e3021894 714 obj->char_match = char_match;
elessair 0:f269e3021894 715 obj->char_found = 0;
elessair 0:f269e3021894 716 }
elessair 0:f269e3021894 717
elessair 0:f269e3021894 718 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
elessair 0:f269e3021894 719 {
elessair 0:f269e3021894 720 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
elessair 0:f269e3021894 721 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
elessair 0:f269e3021894 722
elessair 0:f269e3021894 723 //if (event & SERIAL_EVENT_TX_COMPLETE) {
elessair 0:f269e3021894 724 //}
elessair 0:f269e3021894 725 }
elessair 0:f269e3021894 726
elessair 0:f269e3021894 727 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
elessair 0:f269e3021894 728 {
elessair 0:f269e3021894 729 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
elessair 0:f269e3021894 730 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
elessair 0:f269e3021894 731
elessair 0:f269e3021894 732 //if (event & SERIAL_EVENT_RX_COMPLETE) {
elessair 0:f269e3021894 733 //}
elessair 0:f269e3021894 734 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
elessair 0:f269e3021894 735 //}
elessair 0:f269e3021894 736 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
elessair 0:f269e3021894 737 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
elessair 0:f269e3021894 738 }
elessair 0:f269e3021894 739 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
elessair 0:f269e3021894 740 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
elessair 0:f269e3021894 741 }
elessair 0:f269e3021894 742 if (event & SERIAL_EVENT_RX_OVERFLOW) {
elessair 0:f269e3021894 743 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
elessair 0:f269e3021894 744 }
elessair 0:f269e3021894 745 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
elessair 0:f269e3021894 746 //}
elessair 0:f269e3021894 747 }
elessair 0:f269e3021894 748
elessair 0:f269e3021894 749 static int serial_is_tx_complete(serial_t *obj)
elessair 0:f269e3021894 750 {
elessair 0:f269e3021894 751 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
elessair 0:f269e3021894 752 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 753 // FIXME: Premature abort???
elessair 0:f269e3021894 754 return (obj->tx_buff.pos == obj->tx_buff.length);
elessair 0:f269e3021894 755 }
elessair 0:f269e3021894 756
elessair 0:f269e3021894 757 static int serial_is_rx_complete(serial_t *obj)
elessair 0:f269e3021894 758 {
elessair 0:f269e3021894 759 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 760 return (obj->rx_buff.pos == obj->rx_buff.length);
elessair 0:f269e3021894 761 }
elessair 0:f269e3021894 762
elessair 0:f269e3021894 763 static uint32_t serial_tx_event_check(serial_t *obj)
elessair 0:f269e3021894 764 {
elessair 0:f269e3021894 765 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 766
elessair 0:f269e3021894 767 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
elessair 0:f269e3021894 768 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
elessair 0:f269e3021894 769 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 770 }
elessair 0:f269e3021894 771
elessair 0:f269e3021894 772 uint32_t event = 0;
elessair 0:f269e3021894 773
elessair 0:f269e3021894 774 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 775 serial_write_async(obj);
elessair 0:f269e3021894 776 }
elessair 0:f269e3021894 777
elessair 0:f269e3021894 778 if (serial_is_tx_complete(obj)) {
elessair 0:f269e3021894 779 event |= SERIAL_EVENT_TX_COMPLETE;
elessair 0:f269e3021894 780 }
elessair 0:f269e3021894 781
elessair 0:f269e3021894 782 return event;
elessair 0:f269e3021894 783 }
elessair 0:f269e3021894 784
elessair 0:f269e3021894 785 static uint32_t serial_rx_event_check(serial_t *obj)
elessair 0:f269e3021894 786 {
elessair 0:f269e3021894 787 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 788
elessair 0:f269e3021894 789 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
elessair 0:f269e3021894 790 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
elessair 0:f269e3021894 791 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 792 }
elessair 0:f269e3021894 793
elessair 0:f269e3021894 794 uint32_t event = 0;
elessair 0:f269e3021894 795
elessair 0:f269e3021894 796 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
elessair 0:f269e3021894 797 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
elessair 0:f269e3021894 798 }
elessair 0:f269e3021894 799 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
elessair 0:f269e3021894 800 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
elessair 0:f269e3021894 801 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
elessair 0:f269e3021894 802 }
elessair 0:f269e3021894 803 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
elessair 0:f269e3021894 804 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
elessair 0:f269e3021894 805 event |= SERIAL_EVENT_RX_PARITY_ERROR;
elessair 0:f269e3021894 806 }
elessair 0:f269e3021894 807
elessair 0:f269e3021894 808 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
elessair 0:f269e3021894 809 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
elessair 0:f269e3021894 810 event |= SERIAL_EVENT_RX_OVERFLOW;
elessair 0:f269e3021894 811 }
elessair 0:f269e3021894 812
elessair 0:f269e3021894 813 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
elessair 0:f269e3021894 814 serial_read_async(obj);
elessair 0:f269e3021894 815 }
elessair 0:f269e3021894 816
elessair 0:f269e3021894 817 if (serial_is_rx_complete(obj)) {
elessair 0:f269e3021894 818 event |= SERIAL_EVENT_RX_COMPLETE;
elessair 0:f269e3021894 819 }
elessair 0:f269e3021894 820 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
elessair 0:f269e3021894 821 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
elessair 0:f269e3021894 822 // FIXME: Timing to reset char_found?
elessair 0:f269e3021894 823 //obj->char_found = 0;
elessair 0:f269e3021894 824 }
elessair 0:f269e3021894 825
elessair 0:f269e3021894 826 return event;
elessair 0:f269e3021894 827 }
elessair 0:f269e3021894 828
elessair 0:f269e3021894 829 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
elessair 0:f269e3021894 830 {
elessair 0:f269e3021894 831 serial_t *obj = (serial_t *) id;
elessair 0:f269e3021894 832
elessair 0:f269e3021894 833 // FIXME: Pass this error to caller
elessair 0:f269e3021894 834 if (event_dma & DMA_EVENT_ABORT) {
elessair 0:f269e3021894 835 }
elessair 0:f269e3021894 836 // Expect UART IRQ will catch this transfer done event
elessair 0:f269e3021894 837 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
elessair 0:f269e3021894 838 obj->tx_buff.pos = obj->tx_buff.length;
elessair 0:f269e3021894 839 }
elessair 0:f269e3021894 840 // FIXME: Pass this error to caller
elessair 0:f269e3021894 841 if (event_dma & DMA_EVENT_TIMEOUT) {
elessair 0:f269e3021894 842 }
elessair 0:f269e3021894 843
elessair 0:f269e3021894 844 uart_irq_async(obj);
elessair 0:f269e3021894 845 }
elessair 0:f269e3021894 846
elessair 0:f269e3021894 847 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
elessair 0:f269e3021894 848 {
elessair 0:f269e3021894 849 serial_t *obj = (serial_t *) id;
elessair 0:f269e3021894 850
elessair 0:f269e3021894 851 // FIXME: Pass this error to caller
elessair 0:f269e3021894 852 if (event_dma & DMA_EVENT_ABORT) {
elessair 0:f269e3021894 853 }
elessair 0:f269e3021894 854 // Expect UART IRQ will catch this transfer done event
elessair 0:f269e3021894 855 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
elessair 0:f269e3021894 856 obj->rx_buff.pos = obj->rx_buff.length;
elessair 0:f269e3021894 857 }
elessair 0:f269e3021894 858 // FIXME: Pass this error to caller
elessair 0:f269e3021894 859 if (event_dma & DMA_EVENT_TIMEOUT) {
elessair 0:f269e3021894 860 }
elessair 0:f269e3021894 861
elessair 0:f269e3021894 862 uart_irq_async(obj);
elessair 0:f269e3021894 863 }
elessair 0:f269e3021894 864
elessair 0:f269e3021894 865 static int serial_write_async(serial_t *obj)
elessair 0:f269e3021894 866 {
elessair 0:f269e3021894 867 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 868 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 869 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 870
elessair 0:f269e3021894 871 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
elessair 0:f269e3021894 872
elessair 0:f269e3021894 873 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
elessair 0:f269e3021894 874 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
elessair 0:f269e3021894 875 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
elessair 0:f269e3021894 876 tx_fifo_busy = tx_fifo_max;
elessair 0:f269e3021894 877 }
elessair 0:f269e3021894 878 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
elessair 0:f269e3021894 879 if (tx_fifo_free == 0) {
elessair 0:f269e3021894 880 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 881 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elessair 0:f269e3021894 882 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 883 }
elessair 0:f269e3021894 884 return 0;
elessair 0:f269e3021894 885 }
elessair 0:f269e3021894 886
elessair 0:f269e3021894 887 uint32_t bytes_per_word = obj->tx_buff.width / 8;
elessair 0:f269e3021894 888
elessair 0:f269e3021894 889 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
elessair 0:f269e3021894 890 int n_words = 0;
elessair 0:f269e3021894 891 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
elessair 0:f269e3021894 892 switch (bytes_per_word) {
elessair 0:f269e3021894 893 case 4:
elessair 0:f269e3021894 894 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 895 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 896 case 2:
elessair 0:f269e3021894 897 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 898 case 1:
elessair 0:f269e3021894 899 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
elessair 0:f269e3021894 900 }
elessair 0:f269e3021894 901
elessair 0:f269e3021894 902 n_words ++;
elessair 0:f269e3021894 903 tx_fifo_free -= bytes_per_word;
elessair 0:f269e3021894 904 obj->tx_buff.pos ++;
elessair 0:f269e3021894 905 }
elessair 0:f269e3021894 906
elessair 0:f269e3021894 907 if (n_words) {
elessair 0:f269e3021894 908 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 909 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
elessair 0:f269e3021894 910 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
elessair 0:f269e3021894 911 }
elessair 0:f269e3021894 912 }
elessair 0:f269e3021894 913
elessair 0:f269e3021894 914 return n_words;
elessair 0:f269e3021894 915 }
elessair 0:f269e3021894 916
elessair 0:f269e3021894 917 static int serial_read_async(serial_t *obj)
elessair 0:f269e3021894 918 {
elessair 0:f269e3021894 919 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 920 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 921 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 922
elessair 0:f269e3021894 923 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
elessair 0:f269e3021894 924 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
elessair 0:f269e3021894 925 //if (rx_fifo_free == 0) {
elessair 0:f269e3021894 926 // return 0;
elessair 0:f269e3021894 927 //}
elessair 0:f269e3021894 928
elessair 0:f269e3021894 929 uint32_t bytes_per_word = obj->rx_buff.width / 8;
elessair 0:f269e3021894 930
elessair 0:f269e3021894 931 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
elessair 0:f269e3021894 932 int n_words = 0;
elessair 0:f269e3021894 933 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
elessair 0:f269e3021894 934 switch (bytes_per_word) {
elessair 0:f269e3021894 935 case 4:
elessair 0:f269e3021894 936 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 937 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 938 case 2:
elessair 0:f269e3021894 939 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 940 case 1:
elessair 0:f269e3021894 941 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
elessair 0:f269e3021894 942 }
elessair 0:f269e3021894 943
elessair 0:f269e3021894 944 n_words ++;
elessair 0:f269e3021894 945 rx_fifo_busy -= bytes_per_word;
elessair 0:f269e3021894 946 obj->rx_buff.pos ++;
elessair 0:f269e3021894 947
elessair 0:f269e3021894 948 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
elessair 0:f269e3021894 949 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
elessair 0:f269e3021894 950 uint8_t *rx_cmp = rx;
elessair 0:f269e3021894 951 switch (bytes_per_word) {
elessair 0:f269e3021894 952 case 4:
elessair 0:f269e3021894 953 rx_cmp -= 2;
elessair 0:f269e3021894 954 case 2:
elessair 0:f269e3021894 955 rx_cmp --;
elessair 0:f269e3021894 956 case 1:
elessair 0:f269e3021894 957 rx_cmp --;
elessair 0:f269e3021894 958 }
elessair 0:f269e3021894 959 if (*rx_cmp == obj->char_match) {
elessair 0:f269e3021894 960 obj->char_found = 1;
elessair 0:f269e3021894 961 break;
elessair 0:f269e3021894 962 }
elessair 0:f269e3021894 963 }
elessair 0:f269e3021894 964 }
elessair 0:f269e3021894 965
elessair 0:f269e3021894 966 if (n_words) {
elessair 0:f269e3021894 967 // Simulate clear of the interrupt flag
elessair 0:f269e3021894 968 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
elessair 0:f269e3021894 969 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
elessair 0:f269e3021894 970 }
elessair 0:f269e3021894 971 }
elessair 0:f269e3021894 972
elessair 0:f269e3021894 973 return n_words;
elessair 0:f269e3021894 974 }
elessair 0:f269e3021894 975
elessair 0:f269e3021894 976 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
elessair 0:f269e3021894 977 {
elessair 0:f269e3021894 978 obj->tx_buff.buffer = (void *) tx;
elessair 0:f269e3021894 979 obj->tx_buff.length = length;
elessair 0:f269e3021894 980 obj->tx_buff.pos = 0;
elessair 0:f269e3021894 981 obj->tx_buff.width = width;
elessair 0:f269e3021894 982 }
elessair 0:f269e3021894 983
elessair 0:f269e3021894 984 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
elessair 0:f269e3021894 985 {
elessair 0:f269e3021894 986 obj->rx_buff.buffer = rx;
elessair 0:f269e3021894 987 obj->rx_buff.length = length;
elessair 0:f269e3021894 988 obj->rx_buff.pos = 0;
elessair 0:f269e3021894 989 obj->rx_buff.width = width;
elessair 0:f269e3021894 990 }
elessair 0:f269e3021894 991
elessair 0:f269e3021894 992 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
elessair 0:f269e3021894 993 {
elessair 0:f269e3021894 994 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 995 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 996 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 997
elessair 0:f269e3021894 998 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 999 ((struct nu_uart_var *) modinit->var)->obj = obj;
elessair 0:f269e3021894 1000 // With our own async vector, tx/rx handlers can be different.
elessair 0:f269e3021894 1001 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async;
elessair 0:f269e3021894 1002 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
elessair 0:f269e3021894 1003 serial_irq_set(obj, TxIrq, enable);
elessair 0:f269e3021894 1004 }
elessair 0:f269e3021894 1005
elessair 0:f269e3021894 1006 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
elessair 0:f269e3021894 1007 {
elessair 0:f269e3021894 1008 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
elessair 0:f269e3021894 1009 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 1010 MBED_ASSERT(modinit->modname == obj->serial.uart);
elessair 0:f269e3021894 1011
elessair 0:f269e3021894 1012 // Necessary for both interrupt way and DMA way
elessair 0:f269e3021894 1013 ((struct nu_uart_var *) modinit->var)->obj = obj;
elessair 0:f269e3021894 1014 // With our own async vector, tx/rx handlers can be different.
elessair 0:f269e3021894 1015 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async;
elessair 0:f269e3021894 1016 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
elessair 0:f269e3021894 1017 serial_irq_set(obj, RxIrq, enable);
elessair 0:f269e3021894 1018 }
elessair 0:f269e3021894 1019
elessair 0:f269e3021894 1020 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
elessair 0:f269e3021894 1021 {
elessair 0:f269e3021894 1022 if (*dma_usage != DMA_USAGE_NEVER) {
elessair 0:f269e3021894 1023 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 1024 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
elessair 0:f269e3021894 1025 }
elessair 0:f269e3021894 1026 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
elessair 0:f269e3021894 1027 *dma_usage = DMA_USAGE_NEVER;
elessair 0:f269e3021894 1028 }
elessair 0:f269e3021894 1029 }
elessair 0:f269e3021894 1030 else {
elessair 0:f269e3021894 1031 dma_channel_free(*dma_ch);
elessair 0:f269e3021894 1032 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
elessair 0:f269e3021894 1033 }
elessair 0:f269e3021894 1034 }
elessair 0:f269e3021894 1035
elessair 0:f269e3021894 1036 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
elessair 0:f269e3021894 1037 {
elessair 0:f269e3021894 1038 int inten_msk = 0;
elessair 0:f269e3021894 1039
elessair 0:f269e3021894 1040 switch (irq) {
elessair 0:f269e3021894 1041 case RxIrq:
elessair 0:f269e3021894 1042 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
elessair 0:f269e3021894 1043 break;
elessair 0:f269e3021894 1044 case TxIrq:
elessair 0:f269e3021894 1045 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
elessair 0:f269e3021894 1046 break;
elessair 0:f269e3021894 1047 }
elessair 0:f269e3021894 1048
elessair 0:f269e3021894 1049 return !! inten_msk;
elessair 0:f269e3021894 1050 }
elessair 0:f269e3021894 1051
elessair 0:f269e3021894 1052 #endif // #if DEVICE_SERIAL_ASYNCH
elessair 0:f269e3021894 1053 #endif // #if DEVICE_SERIAL