erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #include <stddef.h>
elessair 0:f269e3021894 17 #include "us_ticker_api.h"
elessair 0:f269e3021894 18 #include "PeripheralNames.h"
elessair 0:f269e3021894 19 #include "clk_freqs.h"
elessair 0:f269e3021894 20
elessair 0:f269e3021894 21 static void pit_init(void);
elessair 0:f269e3021894 22 static void lptmr_init(void);
elessair 0:f269e3021894 23
elessair 0:f269e3021894 24 static int us_ticker_inited = 0;
elessair 0:f269e3021894 25
elessair 0:f269e3021894 26 void us_ticker_init(void) {
elessair 0:f269e3021894 27 if (us_ticker_inited) return;
elessair 0:f269e3021894 28 us_ticker_inited = 1;
elessair 0:f269e3021894 29
elessair 0:f269e3021894 30 pit_init();
elessair 0:f269e3021894 31 lptmr_init();
elessair 0:f269e3021894 32 }
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 /******************************************************************************
elessair 0:f269e3021894 35 * Timer for us timing.
elessair 0:f269e3021894 36 ******************************************************************************/
elessair 0:f269e3021894 37 static void pit_init(void) {
elessair 0:f269e3021894 38 SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
elessair 0:f269e3021894 39 PIT->MCR = 0; // Enable PIT
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 // Channel 1
elessair 0:f269e3021894 42 PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
elessair 0:f269e3021894 43 PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK; // Chain to timer 0, disable Interrupts
elessair 0:f269e3021894 44 PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
elessair 0:f269e3021894 45
elessair 0:f269e3021894 46 // Use channel 0 as a prescaler for channel 1
elessair 0:f269e3021894 47 PIT->CHANNEL[0].LDVAL = (bus_frequency() + 500000) / 1000000 - 1;
elessair 0:f269e3021894 48 PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
elessair 0:f269e3021894 49 }
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 uint32_t us_ticker_read() {
elessair 0:f269e3021894 52 if (!us_ticker_inited)
elessair 0:f269e3021894 53 us_ticker_init();
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 // The PIT is a countdown timer
elessair 0:f269e3021894 56 return ~(PIT->CHANNEL[1].CVAL);
elessair 0:f269e3021894 57 }
elessair 0:f269e3021894 58
elessair 0:f269e3021894 59 /******************************************************************************
elessair 0:f269e3021894 60 * Timer Event
elessair 0:f269e3021894 61 *
elessair 0:f269e3021894 62 * It schedules interrupts at given (32bit)us interval of time.
elessair 0:f269e3021894 63 * It is implemented used the 16bit Low Power Timer that remains powered in all
elessair 0:f269e3021894 64 * power modes.
elessair 0:f269e3021894 65 ******************************************************************************/
elessair 0:f269e3021894 66 static void lptmr_isr(void);
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68 static void lptmr_init(void) {
elessair 0:f269e3021894 69 uint32_t extosc;
elessair 0:f269e3021894 70
elessair 0:f269e3021894 71 /* Clock the timer */
elessair 0:f269e3021894 72 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
elessair 0:f269e3021894 73
elessair 0:f269e3021894 74 /* Reset */
elessair 0:f269e3021894 75 LPTMR0->CSR = 0;
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 #if defined(TARGET_KL43Z)
elessair 0:f269e3021894 78 /* Set interrupt handler */
elessair 0:f269e3021894 79 NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
elessair 0:f269e3021894 80 NVIC_EnableIRQ(LPTMR0_IRQn);
elessair 0:f269e3021894 81
elessair 0:f269e3021894 82
elessair 0:f269e3021894 83 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
elessair 0:f269e3021894 84 extosc = mcgirc_frequency();
elessair 0:f269e3021894 85 #else
elessair 0:f269e3021894 86 /* Set interrupt handler */
elessair 0:f269e3021894 87 NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
elessair 0:f269e3021894 88 NVIC_EnableIRQ(LPTimer_IRQn);
elessair 0:f269e3021894 89
elessair 0:f269e3021894 90 /* Clock at (1)MHz -> (1)tick/us */
elessair 0:f269e3021894 91 /* Check if the external oscillator can be divided to 1MHz */
elessair 0:f269e3021894 92 extosc = extosc_frequency();
elessair 0:f269e3021894 93 #endif
elessair 0:f269e3021894 94 if (extosc != 0) { //If external oscillator found
elessair 0:f269e3021894 95 if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
elessair 0:f269e3021894 96 extosc /= 1000000;
elessair 0:f269e3021894 97 if (extosc == 1) { //1MHz, set timerprescaler in bypass mode
elessair 0:f269e3021894 98 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK;
elessair 0:f269e3021894 99 return;
elessair 0:f269e3021894 100 } else { //See if we can divide it to 1MHz
elessair 0:f269e3021894 101 uint32_t divider = 0;
elessair 0:f269e3021894 102 extosc >>= 1;
elessair 0:f269e3021894 103 while (1) {
elessair 0:f269e3021894 104 if (extosc == 1) {
elessair 0:f269e3021894 105 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider);
elessair 0:f269e3021894 106 return;
elessair 0:f269e3021894 107 }
elessair 0:f269e3021894 108 if (extosc % 2 != 0) //If we can't divide by two anymore
elessair 0:f269e3021894 109 break;
elessair 0:f269e3021894 110 divider++;
elessair 0:f269e3021894 111 extosc >>= 1;
elessair 0:f269e3021894 112 }
elessair 0:f269e3021894 113 }
elessair 0:f269e3021894 114 }
elessair 0:f269e3021894 115 }
elessair 0:f269e3021894 116 #if defined(TARGET_KL43Z)
elessair 0:f269e3021894 117 //No suitable actual IRC oscillator clock -> Set it to (8MHz / divider)
elessair 0:f269e3021894 118 MCG->SC &= ~MCG_SC_FCRDIV_MASK;
elessair 0:f269e3021894 119 MCG->MC &= ~MCG->MC & MCG_MC_LIRC_DIV2_MASK;
elessair 0:f269e3021894 120 LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(2);
elessair 0:f269e3021894 121 #else
elessair 0:f269e3021894 122 //No suitable external oscillator clock -> Use fast internal oscillator (4MHz / divider)
elessair 0:f269e3021894 123 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
elessair 0:f269e3021894 124 MCG->C2 |= MCG_C2_IRCS_MASK;
elessair 0:f269e3021894 125 LPTMR0->PSR = LPTMR_PSR_PCS(0);
elessair 0:f269e3021894 126 switch (MCG->SC & MCG_SC_FCRDIV_MASK) {
elessair 0:f269e3021894 127 case MCG_SC_FCRDIV(0): //4MHz
elessair 0:f269e3021894 128 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(1);
elessair 0:f269e3021894 129 break;
elessair 0:f269e3021894 130 case MCG_SC_FCRDIV(1): //2MHz
elessair 0:f269e3021894 131 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(0);
elessair 0:f269e3021894 132 break;
elessair 0:f269e3021894 133 default: //1MHz or anything else, in which case we put it on 1MHz
elessair 0:f269e3021894 134 MCG->SC &= ~MCG_SC_FCRDIV_MASK;
elessair 0:f269e3021894 135 MCG->SC |= MCG_SC_FCRDIV(2);
elessair 0:f269e3021894 136 LPTMR0->PSR |= LPTMR_PSR_PBYP_MASK;
elessair 0:f269e3021894 137 }
elessair 0:f269e3021894 138 #endif
elessair 0:f269e3021894 139 }
elessair 0:f269e3021894 140
elessair 0:f269e3021894 141 void us_ticker_disable_interrupt(void) {
elessair 0:f269e3021894 142 LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
elessair 0:f269e3021894 143 }
elessair 0:f269e3021894 144
elessair 0:f269e3021894 145 void us_ticker_clear_interrupt(void) {
elessair 0:f269e3021894 146 // we already clear interrupt in lptmr_isr
elessair 0:f269e3021894 147 }
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 static uint32_t us_ticker_int_counter = 0;
elessair 0:f269e3021894 150 static uint16_t us_ticker_int_remainder = 0;
elessair 0:f269e3021894 151
elessair 0:f269e3021894 152 static void lptmr_set(unsigned short count) {
elessair 0:f269e3021894 153 /* Reset */
elessair 0:f269e3021894 154 LPTMR0->CSR = 0;
elessair 0:f269e3021894 155
elessair 0:f269e3021894 156 /* Set the compare register */
elessair 0:f269e3021894 157 LPTMR0->CMR = count;
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 /* Enable interrupt */
elessair 0:f269e3021894 160 LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 /* Start the timer */
elessair 0:f269e3021894 163 LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
elessair 0:f269e3021894 164 }
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166 static void lptmr_isr(void) {
elessair 0:f269e3021894 167 // write 1 to TCF to clear the LPT timer compare flag
elessair 0:f269e3021894 168 LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
elessair 0:f269e3021894 169
elessair 0:f269e3021894 170 if (us_ticker_int_counter > 0) {
elessair 0:f269e3021894 171 lptmr_set(0xFFFF);
elessair 0:f269e3021894 172 us_ticker_int_counter--;
elessair 0:f269e3021894 173
elessair 0:f269e3021894 174 } else {
elessair 0:f269e3021894 175 if (us_ticker_int_remainder > 0) {
elessair 0:f269e3021894 176 lptmr_set(us_ticker_int_remainder);
elessair 0:f269e3021894 177 us_ticker_int_remainder = 0;
elessair 0:f269e3021894 178
elessair 0:f269e3021894 179 } else {
elessair 0:f269e3021894 180 // This function is going to disable the interrupts if there are
elessair 0:f269e3021894 181 // no other events in the queue
elessair 0:f269e3021894 182 us_ticker_irq_handler();
elessair 0:f269e3021894 183 }
elessair 0:f269e3021894 184 }
elessair 0:f269e3021894 185 }
elessair 0:f269e3021894 186
elessair 0:f269e3021894 187 void us_ticker_set_interrupt(timestamp_t timestamp) {
elessair 0:f269e3021894 188 int delta = (int)((uint32_t)timestamp - us_ticker_read());
elessair 0:f269e3021894 189 if (delta <= 0) {
elessair 0:f269e3021894 190 // This event was in the past:
elessair 0:f269e3021894 191 us_ticker_irq_handler();
elessair 0:f269e3021894 192 return;
elessair 0:f269e3021894 193 }
elessair 0:f269e3021894 194
elessair 0:f269e3021894 195 us_ticker_int_counter = (uint32_t)(delta >> 16);
elessair 0:f269e3021894 196 us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
elessair 0:f269e3021894 197 if (us_ticker_int_counter > 0) {
elessair 0:f269e3021894 198 lptmr_set(0xFFFF);
elessair 0:f269e3021894 199 us_ticker_int_counter--;
elessair 0:f269e3021894 200 } else {
elessair 0:f269e3021894 201 lptmr_set(us_ticker_int_remainder);
elessair 0:f269e3021894 202 us_ticker_int_remainder = 0;
elessair 0:f269e3021894 203 }
elessair 0:f269e3021894 204 }