erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

targets/TARGET_Freescale/TARGET_KLXX/sleep.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2013 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #include "sleep_api.h"
elessair 0:f269e3021894 17 #include "cmsis.h"
elessair 0:f269e3021894 18 #include "PeripheralPins.h"
elessair 0:f269e3021894 19
elessair 0:f269e3021894 20 //Normal wait mode
elessair 0:f269e3021894 21 void sleep(void)
elessair 0:f269e3021894 22 {
elessair 0:f269e3021894 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
elessair 0:f269e3021894 24
elessair 0:f269e3021894 25 //Normal sleep mode for ARM core:
elessair 0:f269e3021894 26 SCB->SCR = 0;
elessair 0:f269e3021894 27 __WFI();
elessair 0:f269e3021894 28 }
elessair 0:f269e3021894 29
elessair 0:f269e3021894 30 //Very low-power stop mode
elessair 0:f269e3021894 31 void deepsleep(void)
elessair 0:f269e3021894 32 {
elessair 0:f269e3021894 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
elessair 0:f269e3021894 34 uint8_t ADC_HSC = 0;
elessair 0:f269e3021894 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
elessair 0:f269e3021894 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
elessair 0:f269e3021894 37 ADC_HSC = 1;
elessair 0:f269e3021894 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
elessair 0:f269e3021894 39 }
elessair 0:f269e3021894 40 }
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #if ! defined(TARGET_KL43Z)
elessair 0:f269e3021894 43 //Check if PLL/FLL is enabled:
elessair 0:f269e3021894 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
elessair 0:f269e3021894 45 #endif
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
elessair 0:f269e3021894 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
elessair 0:f269e3021894 49
elessair 0:f269e3021894 50 //Deep sleep for ARM core:
elessair 0:f269e3021894 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 __WFI();
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 #if ! defined(TARGET_KL43Z)
elessair 0:f269e3021894 56 //Switch back to PLL as clock source if needed
elessair 0:f269e3021894 57 //The interrupt that woke up the device will run at reduced speed
elessair 0:f269e3021894 58 if (PLL_FLL_en) {
elessair 0:f269e3021894 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
elessair 0:f269e3021894 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
elessair 0:f269e3021894 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
elessair 0:f269e3021894 62 #endif
elessair 0:f269e3021894 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
elessair 0:f269e3021894 64 }
elessair 0:f269e3021894 65 #endif
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 if (ADC_HSC) {
elessair 0:f269e3021894 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
elessair 0:f269e3021894 69 }
elessair 0:f269e3021894 70 }