mbed os with nrf51 internal bandgap enabled to read battery level
Dependents: BLE_file_test BLE_Blink ExternalEncoder
targets/TARGET_Freescale/TARGET_KLXX/analogin_api.c@0:f269e3021894, 2016-10-23 (annotated)
- Committer:
- elessair
- Date:
- Sun Oct 23 15:10:02 2016 +0000
- Revision:
- 0:f269e3021894
Initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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elessair | 0:f269e3021894 | 1 | /* mbed Microcontroller Library |
elessair | 0:f269e3021894 | 2 | * Copyright (c) 2006-2013 ARM Limited |
elessair | 0:f269e3021894 | 3 | * |
elessair | 0:f269e3021894 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
elessair | 0:f269e3021894 | 5 | * you may not use this file except in compliance with the License. |
elessair | 0:f269e3021894 | 6 | * You may obtain a copy of the License at |
elessair | 0:f269e3021894 | 7 | * |
elessair | 0:f269e3021894 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
elessair | 0:f269e3021894 | 9 | * |
elessair | 0:f269e3021894 | 10 | * Unless required by applicable law or agreed to in writing, software |
elessair | 0:f269e3021894 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
elessair | 0:f269e3021894 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
elessair | 0:f269e3021894 | 13 | * See the License for the specific language governing permissions and |
elessair | 0:f269e3021894 | 14 | * limitations under the License. |
elessair | 0:f269e3021894 | 15 | */ |
elessair | 0:f269e3021894 | 16 | #include "mbed_assert.h" |
elessair | 0:f269e3021894 | 17 | #include "analogin_api.h" |
elessair | 0:f269e3021894 | 18 | |
elessair | 0:f269e3021894 | 19 | #include "cmsis.h" |
elessair | 0:f269e3021894 | 20 | #include "pinmap.h" |
elessair | 0:f269e3021894 | 21 | #include "clk_freqs.h" |
elessair | 0:f269e3021894 | 22 | #include "PeripheralPins.h" |
elessair | 0:f269e3021894 | 23 | |
elessair | 0:f269e3021894 | 24 | #define MAX_FADC 6000000 |
elessair | 0:f269e3021894 | 25 | #define CHANNELS_A_SHIFT 5 |
elessair | 0:f269e3021894 | 26 | |
elessair | 0:f269e3021894 | 27 | |
elessair | 0:f269e3021894 | 28 | void analogin_init(analogin_t *obj, PinName pin) { |
elessair | 0:f269e3021894 | 29 | obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); |
elessair | 0:f269e3021894 | 30 | MBED_ASSERT(obj->adc != (ADCName)NC); |
elessair | 0:f269e3021894 | 31 | |
elessair | 0:f269e3021894 | 32 | SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK; |
elessair | 0:f269e3021894 | 33 | |
elessair | 0:f269e3021894 | 34 | uint32_t port = (uint32_t)pin >> PORT_SHIFT; |
elessair | 0:f269e3021894 | 35 | SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); |
elessair | 0:f269e3021894 | 36 | |
elessair | 0:f269e3021894 | 37 | uint32_t cfg2_muxsel = ADC_CFG2_MUXSEL_MASK; |
elessair | 0:f269e3021894 | 38 | if (obj->adc & (1 << CHANNELS_A_SHIFT)) { |
elessair | 0:f269e3021894 | 39 | cfg2_muxsel = 0; |
elessair | 0:f269e3021894 | 40 | } |
elessair | 0:f269e3021894 | 41 | |
elessair | 0:f269e3021894 | 42 | // bus clk |
elessair | 0:f269e3021894 | 43 | uint32_t PCLK = bus_frequency(); |
elessair | 0:f269e3021894 | 44 | uint32_t clkdiv; |
elessair | 0:f269e3021894 | 45 | for (clkdiv = 0; clkdiv < 4; clkdiv++) { |
elessair | 0:f269e3021894 | 46 | if ((PCLK >> clkdiv) <= MAX_FADC) |
elessair | 0:f269e3021894 | 47 | break; |
elessair | 0:f269e3021894 | 48 | } |
elessair | 0:f269e3021894 | 49 | if (clkdiv == 4) //Set max div |
elessair | 0:f269e3021894 | 50 | clkdiv = 0x7; |
elessair | 0:f269e3021894 | 51 | |
elessair | 0:f269e3021894 | 52 | ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc & ~(1 << CHANNELS_A_SHIFT)); |
elessair | 0:f269e3021894 | 53 | |
elessair | 0:f269e3021894 | 54 | ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration |
elessair | 0:f269e3021894 | 55 | | ADC_CFG1_ADIV(clkdiv & 0x3) // Clock Divide Select: (Input Clock)/8 |
elessair | 0:f269e3021894 | 56 | | ADC_CFG1_ADLSMP_MASK // Long Sample Time |
elessair | 0:f269e3021894 | 57 | | ADC_CFG1_MODE(3) // (16)bits Resolution |
elessair | 0:f269e3021894 | 58 | | ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock: (Bus Clock)/2 |
elessair | 0:f269e3021894 | 59 | |
elessair | 0:f269e3021894 | 60 | ADC0->CFG2 = cfg2_muxsel // ADxxb or ADxxa channels |
elessair | 0:f269e3021894 | 61 | | ADC_CFG2_ADHSC_MASK // High-Speed Configuration |
elessair | 0:f269e3021894 | 62 | | ADC_CFG2_ADLSTS(0); // Long Sample Time Select |
elessair | 0:f269e3021894 | 63 | |
elessair | 0:f269e3021894 | 64 | ADC0->SC2 = ADC_SC2_REFSEL(0); // Default Voltage Reference |
elessair | 0:f269e3021894 | 65 | |
elessair | 0:f269e3021894 | 66 | ADC0->SC3 = ADC_SC3_AVGE_MASK // Hardware Average Enable |
elessair | 0:f269e3021894 | 67 | | ADC_SC3_AVGS(0); // 4 Samples Averaged |
elessair | 0:f269e3021894 | 68 | |
elessair | 0:f269e3021894 | 69 | pinmap_pinout(pin, PinMap_ADC); |
elessair | 0:f269e3021894 | 70 | } |
elessair | 0:f269e3021894 | 71 | |
elessair | 0:f269e3021894 | 72 | uint16_t analogin_read_u16(analogin_t *obj) { |
elessair | 0:f269e3021894 | 73 | // start conversion |
elessair | 0:f269e3021894 | 74 | ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc & ~(1 << CHANNELS_A_SHIFT)); |
elessair | 0:f269e3021894 | 75 | |
elessair | 0:f269e3021894 | 76 | // Wait Conversion Complete |
elessair | 0:f269e3021894 | 77 | while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK); |
elessair | 0:f269e3021894 | 78 | |
elessair | 0:f269e3021894 | 79 | // Return value |
elessair | 0:f269e3021894 | 80 | return (uint16_t)ADC0->R[0]; |
elessair | 0:f269e3021894 | 81 | } |
elessair | 0:f269e3021894 | 82 | |
elessair | 0:f269e3021894 | 83 | float analogin_read(analogin_t *obj) { |
elessair | 0:f269e3021894 | 84 | uint16_t value = analogin_read_u16(obj); |
elessair | 0:f269e3021894 | 85 | return (float)value * (1.0f / (float)0xFFFF); |
elessair | 0:f269e3021894 | 86 | } |
elessair | 0:f269e3021894 | 87 |