erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

rtos/rtx/TARGET_ARM7/rt_HAL_CM.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /*----------------------------------------------------------------------------
elessair 0:f269e3021894 2 * RL-ARM - RTX
elessair 0:f269e3021894 3 *----------------------------------------------------------------------------
elessair 0:f269e3021894 4 * Name: RT_HAL_CM.H
elessair 0:f269e3021894 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
elessair 0:f269e3021894 6 * Rev.: V4.60
elessair 0:f269e3021894 7 *----------------------------------------------------------------------------
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
elessair 0:f269e3021894 10 * All rights reserved.
elessair 0:f269e3021894 11 * Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 12 * modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 13 * - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 14 * notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 15 * - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 16 * notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 17 * documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 18 * - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 19 * to endorse or promote products derived from this software without
elessair 0:f269e3021894 20 * specific prior written permission.
elessair 0:f269e3021894 21 *
elessair 0:f269e3021894 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 32 * POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 33 *---------------------------------------------------------------------------*/
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 #include "cmsis.h"
elessair 0:f269e3021894 36 /* Definitions */
elessair 0:f269e3021894 37 #define INITIAL_xPSR 0x10000000
elessair 0:f269e3021894 38 #define DEMCR_TRCENA 0x01000000
elessair 0:f269e3021894 39 #define ITM_ITMENA 0x00000001
elessair 0:f269e3021894 40 #define MAGIC_WORD 0xE25A2EA5
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #define SYS_TICK_IRQn TIMER0_IRQn
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 extern void rt_set_PSP (U32 stack);
elessair 0:f269e3021894 45 extern U32 rt_get_PSP (void);
elessair 0:f269e3021894 46 extern void os_set_env (void);
elessair 0:f269e3021894 47 extern void SysTick_Handler (void);
elessair 0:f269e3021894 48 extern void *_alloc_box (void *box_mem);
elessair 0:f269e3021894 49 extern int _free_box (void *box_mem, void *box);
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
elessair 0:f269e3021894 52 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
elessair 0:f269e3021894 53 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 extern void dbg_init (void);
elessair 0:f269e3021894 56 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
elessair 0:f269e3021894 57 extern void dbg_task_switch (U32 task_id);
elessair 0:f269e3021894 58
elessair 0:f269e3021894 59
elessair 0:f269e3021894 60 #if defined (__CC_ARM) /* ARM Compiler */
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
elessair 0:f269e3021894 63 #define __USE_EXCLUSIVE_ACCESS
elessair 0:f269e3021894 64 #else
elessair 0:f269e3021894 65 #undef __USE_EXCLUSIVE_ACCESS
elessair 0:f269e3021894 66 #endif
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68 #elif defined (__GNUC__) /* GNU Compiler */
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 #undef __USE_EXCLUSIVE_ACCESS
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
elessair 0:f269e3021894 73 #define __TARGET_ARCH_6S_M 1
elessair 0:f269e3021894 74 #else
elessair 0:f269e3021894 75 #define __TARGET_ARCH_6S_M 0
elessair 0:f269e3021894 76 #endif
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
elessair 0:f269e3021894 79 #define __TARGET_FPU_VFP 1
elessair 0:f269e3021894 80 #else
elessair 0:f269e3021894 81 #define __TARGET_FPU_VFP 0
elessair 0:f269e3021894 82 #endif
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 #define __inline inline
elessair 0:f269e3021894 85 #define __weak __attribute__((weak))
elessair 0:f269e3021894 86
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 #elif defined (__ICCARM__) /* IAR Compiler */
elessair 0:f269e3021894 89
elessair 0:f269e3021894 90 #undef __USE_EXCLUSIVE_ACCESS
elessair 0:f269e3021894 91
elessair 0:f269e3021894 92 #if (__CORE__ == __ARM6M__)
elessair 0:f269e3021894 93 #define __TARGET_ARCH_6S_M 1
elessair 0:f269e3021894 94 #else
elessair 0:f269e3021894 95 #define __TARGET_ARCH_6S_M 0
elessair 0:f269e3021894 96 #endif
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 #if defined __ARMVFP__
elessair 0:f269e3021894 99 #define __TARGET_FPU_VFP 1
elessair 0:f269e3021894 100 #else
elessair 0:f269e3021894 101 #define __TARGET_FPU_VFP 0
elessair 0:f269e3021894 102 #endif
elessair 0:f269e3021894 103
elessair 0:f269e3021894 104 #define __inline inline
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 #endif
elessair 0:f269e3021894 107
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 /* NVIC registers */
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 #define OS_PEND_IRQ() NVIC_PendIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 112 #define OS_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 113 #define OS_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 114 #define OS_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 115 #define OS_LOCK() NVIC_DisableIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 116 #define OS_UNLOCK() NVIC_EnableIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 #define OS_X_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 119 #define OS_X_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 120 #define OS_X_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
elessair 0:f269e3021894 121
elessair 0:f269e3021894 122 #define OS_X_INIT(n) NVIC_EnableIRQ(n)
elessair 0:f269e3021894 123 #define OS_X_LOCK(n) NVIC_DisableIRQ(n)
elessair 0:f269e3021894 124 #define OS_X_UNLOCK(n) NVIC_EnableIRQ(n)
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 /* Variables */
elessair 0:f269e3021894 127 extern BIT dbg_msg;
elessair 0:f269e3021894 128
elessair 0:f269e3021894 129 /* Functions */
elessair 0:f269e3021894 130 #ifdef __USE_EXCLUSIVE_ACCESS
elessair 0:f269e3021894 131 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
elessair 0:f269e3021894 132 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
elessair 0:f269e3021894 133 #else
elessair 0:f269e3021894 134 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
elessair 0:f269e3021894 135 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
elessair 0:f269e3021894 136 #endif
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
elessair 0:f269e3021894 139 U32 cnt,c2;
elessair 0:f269e3021894 140 #ifdef __USE_EXCLUSIVE_ACCESS
elessair 0:f269e3021894 141 do {
elessair 0:f269e3021894 142 if ((cnt = __ldrex(count)) == size) {
elessair 0:f269e3021894 143 __clrex();
elessair 0:f269e3021894 144 return (cnt); }
elessair 0:f269e3021894 145 } while (__strex(cnt+1, count));
elessair 0:f269e3021894 146 do {
elessair 0:f269e3021894 147 c2 = (cnt = __ldrex(first)) + 1;
elessair 0:f269e3021894 148 if (c2 == size) c2 = 0;
elessair 0:f269e3021894 149 } while (__strex(c2, first));
elessair 0:f269e3021894 150 #else
elessair 0:f269e3021894 151 __disable_irq();
elessair 0:f269e3021894 152 if ((cnt = *count) < size) {
elessair 0:f269e3021894 153 *count = cnt+1;
elessair 0:f269e3021894 154 c2 = (cnt = *first) + 1;
elessair 0:f269e3021894 155 if (c2 == size) c2 = 0;
elessair 0:f269e3021894 156 *first = c2;
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158 __enable_irq ();
elessair 0:f269e3021894 159 #endif
elessair 0:f269e3021894 160 return (cnt);
elessair 0:f269e3021894 161 }
elessair 0:f269e3021894 162
elessair 0:f269e3021894 163 __inline static void rt_systick_init (void) {
elessair 0:f269e3021894 164 #if SYS_TICK_IRQn == TIMER0_IRQn
elessair 0:f269e3021894 165 #define SYS_TICK_TIMER LPC_TIM0
elessair 0:f269e3021894 166 LPC_SC->PCONP |= (1 << PCTIM0);
elessair 0:f269e3021894 167 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<3))) | (1<<2); //PCLK == CPUCLK
elessair 0:f269e3021894 168 #elif SYS_TICK_IRQn == TIMER1_IRQn
elessair 0:f269e3021894 169 #define SYS_TICK_TIMER LPC_TIM1
elessair 0:f269e3021894 170 LPC_SC->PCONP |= (1 << PCTIM1);
elessair 0:f269e3021894 171 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<5))) | (1<<4); //PCLK == CPUCLK
elessair 0:f269e3021894 172 #elif SYS_TICK_IRQn == TIMER2_IRQn
elessair 0:f269e3021894 173 #define SYS_TICK_TIMER LPC_TIM2
elessair 0:f269e3021894 174 LPC_SC->PCONP |= (1 << PCTIM2);
elessair 0:f269e3021894 175 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<13))) | (1<<12); //PCLK == CPUCLK
elessair 0:f269e3021894 176 #else
elessair 0:f269e3021894 177 #define SYS_TICK_TIMER LPC_TIM3
elessair 0:f269e3021894 178 LPC_SC->PCONP |= (1 << PCTIM3);
elessair 0:f269e3021894 179 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<15))) | (1<<14); //PCLK == CPUCLK
elessair 0:f269e3021894 180 #endif
elessair 0:f269e3021894 181
elessair 0:f269e3021894 182 // setup Timer to count forever
elessair 0:f269e3021894 183 //interrupt_reg
elessair 0:f269e3021894 184 SYS_TICK_TIMER->TCR = 2; // reset & disable timer 0
elessair 0:f269e3021894 185 SYS_TICK_TIMER->TC = os_trv;
elessair 0:f269e3021894 186 SYS_TICK_TIMER->PR = 0; // set the prescale divider
elessair 0:f269e3021894 187 //Reset of TC and Interrupt when MR3 MR2 matches TC
elessair 0:f269e3021894 188 SYS_TICK_TIMER->MCR = (1 << 9) |(1 << 10); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk
elessair 0:f269e3021894 189 SYS_TICK_TIMER->MR3 = os_trv; // match registers
elessair 0:f269e3021894 190 SYS_TICK_TIMER->CCR = 0; // disable compare registers
elessair 0:f269e3021894 191 SYS_TICK_TIMER->EMR = 0; // disable external match register
elessair 0:f269e3021894 192 // initialize the interrupt vector
elessair 0:f269e3021894 193 NVIC_SetVector(SYS_TICK_IRQn, (uint32_t)&SysTick_Handler);
elessair 0:f269e3021894 194 SYS_TICK_TIMER->TCR = 1; // enable timer 0
elessair 0:f269e3021894 195 }
elessair 0:f269e3021894 196
elessair 0:f269e3021894 197 __inline static void rt_svc_init (void) {
elessair 0:f269e3021894 198 // TODO: add svcInit
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200 }
elessair 0:f269e3021894 201
elessair 0:f269e3021894 202 #ifdef DBG_MSG
elessair 0:f269e3021894 203 #define DBG_INIT() dbg_init()
elessair 0:f269e3021894 204 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
elessair 0:f269e3021894 205 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
elessair 0:f269e3021894 206 dbg_task_switch(task_id)
elessair 0:f269e3021894 207 #else
elessair 0:f269e3021894 208 #define DBG_INIT()
elessair 0:f269e3021894 209 #define DBG_TASK_NOTIFY(p_tcb,create)
elessair 0:f269e3021894 210 #define DBG_TASK_SWITCH(task_id)
elessair 0:f269e3021894 211 #endif
elessair 0:f269e3021894 212
elessair 0:f269e3021894 213 /*----------------------------------------------------------------------------
elessair 0:f269e3021894 214 * end of file
elessair 0:f269e3021894 215 *---------------------------------------------------------------------------*/
elessair 0:f269e3021894 216