erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

rtos/rtx/TARGET_ARM7/HAL_CM.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /*----------------------------------------------------------------------------
elessair 0:f269e3021894 2 * RL-ARM - RTX
elessair 0:f269e3021894 3 *----------------------------------------------------------------------------
elessair 0:f269e3021894 4 * Name: HAL_CM.C
elessair 0:f269e3021894 5 * Purpose: Hardware Abstraction Layer for ARM7TDMI
elessair 0:f269e3021894 6 * Rev.: V1.0
elessair 0:f269e3021894 7 *----------------------------------------------------------------------------
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
elessair 0:f269e3021894 10 * All rights reserved.
elessair 0:f269e3021894 11 * Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 12 * modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 13 * - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 14 * notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 15 * - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 16 * notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 17 * documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 18 * - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 19 * to endorse or promote products derived from this software without
elessair 0:f269e3021894 20 * specific prior written permission.
elessair 0:f269e3021894 21 *
elessair 0:f269e3021894 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 32 * POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 33 *---------------------------------------------------------------------------*/
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 #include "rt_TypeDef.h"
elessair 0:f269e3021894 36 #include "RTX_Conf.h"
elessair 0:f269e3021894 37 #include "rt_HAL_CM.h"
elessair 0:f269e3021894 38
elessair 0:f269e3021894 39
elessair 0:f269e3021894 40 /*----------------------------------------------------------------------------
elessair 0:f269e3021894 41 * Global Variables
elessair 0:f269e3021894 42 *---------------------------------------------------------------------------*/
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 #ifdef DBG_MSG
elessair 0:f269e3021894 45 BIT dbg_msg;
elessair 0:f269e3021894 46 #endif
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 /*----------------------------------------------------------------------------
elessair 0:f269e3021894 49 * Functions
elessair 0:f269e3021894 50 *---------------------------------------------------------------------------*/
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 /*--------------------------- rt_init_stack ---------------------------------*/
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
elessair 0:f269e3021894 56 /* Prepare TCB and saved context for a first time start of a task. */
elessair 0:f269e3021894 57 U32 *stk,i,size;
elessair 0:f269e3021894 58
elessair 0:f269e3021894 59 /* Prepare a complete interrupt frame for first task start */
elessair 0:f269e3021894 60 size = p_TCB->priv_stack >> 2;
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 /* Write to the top of stack. */
elessair 0:f269e3021894 63 stk = &p_TCB->stack[size];
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 /* Auto correct to 8-byte ARM stack alignment. */
elessair 0:f269e3021894 66 if ((U32)stk & 0x04) {
elessair 0:f269e3021894 67 stk--;
elessair 0:f269e3021894 68 }
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 stk -= 16;
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 /* Default xPSR and initial PC */
elessair 0:f269e3021894 73 stk[15] = (U32)task_body + 4; /* add 4 byte offset because SUB PC, LR - 4 */
elessair 0:f269e3021894 74 stk[0] = INITIAL_xPSR;
elessair 0:f269e3021894 75
elessair 0:f269e3021894 76 /* Clear R0-R13/LR registers. */
elessair 0:f269e3021894 77 for (i = 1; i < 14; i++) {
elessair 0:f269e3021894 78 stk[i] = 0;
elessair 0:f269e3021894 79 }
elessair 0:f269e3021894 80
elessair 0:f269e3021894 81 /* Assign a void pointer to R0. */
elessair 0:f269e3021894 82 stk[TCB_STACK_R0_OFFSET_DWORDS] = (U32)p_TCB->msg;
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 /* Initial Task stack pointer. */
elessair 0:f269e3021894 85 p_TCB->tsk_stack = (U32)stk;
elessair 0:f269e3021894 86
elessair 0:f269e3021894 87 /* Task entry point. */
elessair 0:f269e3021894 88 p_TCB->ptask = task_body;
elessair 0:f269e3021894 89
elessair 0:f269e3021894 90 /* Set a magic word for checking of stack overflow.
elessair 0:f269e3021894 91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
elessair 0:f269e3021894 92 heap, therefore the last word of the stack is a moving target.
elessair 0:f269e3021894 93 We want to do stack/heap collision detection instead.
elessair 0:f269e3021894 94 */
elessair 0:f269e3021894 95 if (p_TCB->task_id != 0x01)
elessair 0:f269e3021894 96 p_TCB->stack[0] = MAGIC_WORD;
elessair 0:f269e3021894 97 }
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99
elessair 0:f269e3021894 100 /*--------------------------- rt_ret_val ----------------------------------*/
elessair 0:f269e3021894 101
elessair 0:f269e3021894 102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
elessair 0:f269e3021894 103 /* Get pointer to task return value registers (R0..R3) in Stack */
elessair 0:f269e3021894 104
elessair 0:f269e3021894 105 /* Stack Frame: CPSR,R0-R13,PC */
elessair 0:f269e3021894 106 return (U32 *)(p_TCB->tsk_stack + TCB_STACK_R0_OFFSET_BYTES);
elessair 0:f269e3021894 107 }
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 void rt_ret_val (P_TCB p_TCB, U32 v0) {
elessair 0:f269e3021894 110 U32 *ret;
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 ret = rt_ret_regs(p_TCB);
elessair 0:f269e3021894 113 ret[0] = v0;
elessair 0:f269e3021894 114 }
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
elessair 0:f269e3021894 117 U32 *ret;
elessair 0:f269e3021894 118
elessair 0:f269e3021894 119 ret = rt_ret_regs(p_TCB);
elessair 0:f269e3021894 120 ret[0] = v0;
elessair 0:f269e3021894 121 ret[1] = v1;
elessair 0:f269e3021894 122 }
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124
elessair 0:f269e3021894 125 /*--------------------------- dbg_init --------------------------------------*/
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 #ifdef DBG_MSG
elessair 0:f269e3021894 128 void dbg_init (void) {
elessair 0:f269e3021894 129 if ((DEMCR & DEMCR_TRCENA) &&
elessair 0:f269e3021894 130 (ITM_CONTROL & ITM_ITMENA) &&
elessair 0:f269e3021894 131 (ITM_ENABLE & (1UL << 31))) {
elessair 0:f269e3021894 132 dbg_msg = __TRUE;
elessair 0:f269e3021894 133 }
elessair 0:f269e3021894 134 }
elessair 0:f269e3021894 135 #endif
elessair 0:f269e3021894 136
elessair 0:f269e3021894 137 /*--------------------------- dbg_task_notify -------------------------------*/
elessair 0:f269e3021894 138
elessair 0:f269e3021894 139 #ifdef DBG_MSG
elessair 0:f269e3021894 140 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
elessair 0:f269e3021894 141 while (ITM_PORT31_U32 == 0);
elessair 0:f269e3021894 142 ITM_PORT31_U32 = (U32)p_tcb->ptask;
elessair 0:f269e3021894 143 while (ITM_PORT31_U32 == 0);
elessair 0:f269e3021894 144 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
elessair 0:f269e3021894 145 }
elessair 0:f269e3021894 146 #endif
elessair 0:f269e3021894 147
elessair 0:f269e3021894 148 /*--------------------------- dbg_task_switch -------------------------------*/
elessair 0:f269e3021894 149
elessair 0:f269e3021894 150 #ifdef DBG_MSG
elessair 0:f269e3021894 151 void dbg_task_switch (U32 task_id) {
elessair 0:f269e3021894 152 while (ITM_PORT31_U32 == 0);
elessair 0:f269e3021894 153 ITM_PORT31_U8 = task_id;
elessair 0:f269e3021894 154 }
elessair 0:f269e3021894 155 #endif
elessair 0:f269e3021894 156
elessair 0:f269e3021894 157
elessair 0:f269e3021894 158 /*----------------------------------------------------------------------------
elessair 0:f269e3021894 159 * end of file
elessair 0:f269e3021894 160 *---------------------------------------------------------------------------*/
elessair 0:f269e3021894 161