erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

cmsis/core_caFunc.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /**************************************************************************//**
elessair 0:f269e3021894 2 * @file core_caFunc.h
elessair 0:f269e3021894 3 * @brief CMSIS Cortex-A Core Function Access Header File
elessair 0:f269e3021894 4 * @version V3.10
elessair 0:f269e3021894 5 * @date 30 Oct 2013
elessair 0:f269e3021894 6 *
elessair 0:f269e3021894 7 * @note
elessair 0:f269e3021894 8 *
elessair 0:f269e3021894 9 ******************************************************************************/
elessair 0:f269e3021894 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
elessair 0:f269e3021894 11
elessair 0:f269e3021894 12 All rights reserved.
elessair 0:f269e3021894 13 Redistribution and use in source and binary forms, with or without
elessair 0:f269e3021894 14 modification, are permitted provided that the following conditions are met:
elessair 0:f269e3021894 15 - Redistributions of source code must retain the above copyright
elessair 0:f269e3021894 16 notice, this list of conditions and the following disclaimer.
elessair 0:f269e3021894 17 - Redistributions in binary form must reproduce the above copyright
elessair 0:f269e3021894 18 notice, this list of conditions and the following disclaimer in the
elessair 0:f269e3021894 19 documentation and/or other materials provided with the distribution.
elessair 0:f269e3021894 20 - Neither the name of ARM nor the names of its contributors may be used
elessair 0:f269e3021894 21 to endorse or promote products derived from this software without
elessair 0:f269e3021894 22 specific prior written permission.
elessair 0:f269e3021894 23 *
elessair 0:f269e3021894 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair 0:f269e3021894 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair 0:f269e3021894 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
elessair 0:f269e3021894 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
elessair 0:f269e3021894 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
elessair 0:f269e3021894 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
elessair 0:f269e3021894 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
elessair 0:f269e3021894 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
elessair 0:f269e3021894 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
elessair 0:f269e3021894 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
elessair 0:f269e3021894 34 POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 35 ---------------------------------------------------------------------------*/
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #ifndef __CORE_CAFUNC_H__
elessair 0:f269e3021894 39 #define __CORE_CAFUNC_H__
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 /* ########################### Core Function Access ########################### */
elessair 0:f269e3021894 43 /** \ingroup CMSIS_Core_FunctionInterface
elessair 0:f269e3021894 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
elessair 0:f269e3021894 45 @{
elessair 0:f269e3021894 46 */
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
elessair 0:f269e3021894 49 /* ARM armcc specific functions */
elessair 0:f269e3021894 50
elessair 0:f269e3021894 51 #if (__ARMCC_VERSION < 400677)
elessair 0:f269e3021894 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
elessair 0:f269e3021894 53 #endif
elessair 0:f269e3021894 54
elessair 0:f269e3021894 55 #define MODE_USR 0x10
elessair 0:f269e3021894 56 #define MODE_FIQ 0x11
elessair 0:f269e3021894 57 #define MODE_IRQ 0x12
elessair 0:f269e3021894 58 #define MODE_SVC 0x13
elessair 0:f269e3021894 59 #define MODE_MON 0x16
elessair 0:f269e3021894 60 #define MODE_ABT 0x17
elessair 0:f269e3021894 61 #define MODE_HYP 0x1A
elessair 0:f269e3021894 62 #define MODE_UND 0x1B
elessair 0:f269e3021894 63 #define MODE_SYS 0x1F
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 /** \brief Get APSR Register
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 This function returns the content of the APSR Register.
elessair 0:f269e3021894 68
elessair 0:f269e3021894 69 \return APSR Register value
elessair 0:f269e3021894 70 */
elessair 0:f269e3021894 71 __STATIC_INLINE uint32_t __get_APSR(void)
elessair 0:f269e3021894 72 {
elessair 0:f269e3021894 73 register uint32_t __regAPSR __ASM("apsr");
elessair 0:f269e3021894 74 return(__regAPSR);
elessair 0:f269e3021894 75 }
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 /** \brief Get CPSR Register
elessair 0:f269e3021894 79
elessair 0:f269e3021894 80 This function returns the content of the CPSR Register.
elessair 0:f269e3021894 81
elessair 0:f269e3021894 82 \return CPSR Register value
elessair 0:f269e3021894 83 */
elessair 0:f269e3021894 84 __STATIC_INLINE uint32_t __get_CPSR(void)
elessair 0:f269e3021894 85 {
elessair 0:f269e3021894 86 register uint32_t __regCPSR __ASM("cpsr");
elessair 0:f269e3021894 87 return(__regCPSR);
elessair 0:f269e3021894 88 }
elessair 0:f269e3021894 89
elessair 0:f269e3021894 90 /** \brief Set Stack Pointer
elessair 0:f269e3021894 91
elessair 0:f269e3021894 92 This function assigns the given value to the current stack pointer.
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 \param [in] topOfStack Stack Pointer value to set
elessair 0:f269e3021894 95 */
elessair 0:f269e3021894 96 register uint32_t __regSP __ASM("sp");
elessair 0:f269e3021894 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
elessair 0:f269e3021894 98 {
elessair 0:f269e3021894 99 __regSP = topOfStack;
elessair 0:f269e3021894 100 }
elessair 0:f269e3021894 101
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 /** \brief Get link register
elessair 0:f269e3021894 104
elessair 0:f269e3021894 105 This function returns the value of the link register
elessair 0:f269e3021894 106
elessair 0:f269e3021894 107 \return Value of link register
elessair 0:f269e3021894 108 */
elessair 0:f269e3021894 109 register uint32_t __reglr __ASM("lr");
elessair 0:f269e3021894 110 __STATIC_INLINE uint32_t __get_LR(void)
elessair 0:f269e3021894 111 {
elessair 0:f269e3021894 112 return(__reglr);
elessair 0:f269e3021894 113 }
elessair 0:f269e3021894 114
elessair 0:f269e3021894 115 /** \brief Set link register
elessair 0:f269e3021894 116
elessair 0:f269e3021894 117 This function sets the value of the link register
elessair 0:f269e3021894 118
elessair 0:f269e3021894 119 \param [in] lr LR value to set
elessair 0:f269e3021894 120 */
elessair 0:f269e3021894 121 __STATIC_INLINE void __set_LR(uint32_t lr)
elessair 0:f269e3021894 122 {
elessair 0:f269e3021894 123 __reglr = lr;
elessair 0:f269e3021894 124 }
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 /** \brief Set Process Stack Pointer
elessair 0:f269e3021894 127
elessair 0:f269e3021894 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
elessair 0:f269e3021894 131 */
elessair 0:f269e3021894 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
elessair 0:f269e3021894 133 {
elessair 0:f269e3021894 134 ARM
elessair 0:f269e3021894 135 PRESERVE8
elessair 0:f269e3021894 136
elessair 0:f269e3021894 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
elessair 0:f269e3021894 138 MRS R1, CPSR
elessair 0:f269e3021894 139 CPS #MODE_SYS ;no effect in USR mode
elessair 0:f269e3021894 140 MOV SP, R0
elessair 0:f269e3021894 141 MSR CPSR_c, R1 ;no effect in USR mode
elessair 0:f269e3021894 142 ISB
elessair 0:f269e3021894 143 BX LR
elessair 0:f269e3021894 144
elessair 0:f269e3021894 145 }
elessair 0:f269e3021894 146
elessair 0:f269e3021894 147 /** \brief Set User Mode
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 This function changes the processor state to User Mode
elessair 0:f269e3021894 150 */
elessair 0:f269e3021894 151 __STATIC_ASM void __set_CPS_USR(void)
elessair 0:f269e3021894 152 {
elessair 0:f269e3021894 153 ARM
elessair 0:f269e3021894 154
elessair 0:f269e3021894 155 CPS #MODE_USR
elessair 0:f269e3021894 156 BX LR
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159
elessair 0:f269e3021894 160 /** \brief Enable FIQ
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
elessair 0:f269e3021894 163 Can only be executed in Privileged modes.
elessair 0:f269e3021894 164 */
elessair 0:f269e3021894 165 #define __enable_fault_irq __enable_fiq
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167
elessair 0:f269e3021894 168 /** \brief Disable FIQ
elessair 0:f269e3021894 169
elessair 0:f269e3021894 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
elessair 0:f269e3021894 171 Can only be executed in Privileged modes.
elessair 0:f269e3021894 172 */
elessair 0:f269e3021894 173 #define __disable_fault_irq __disable_fiq
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 /** \brief Get FPSCR
elessair 0:f269e3021894 177
elessair 0:f269e3021894 178 This function returns the current value of the Floating Point Status/Control register.
elessair 0:f269e3021894 179
elessair 0:f269e3021894 180 \return Floating Point Status/Control register value
elessair 0:f269e3021894 181 */
elessair 0:f269e3021894 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
elessair 0:f269e3021894 183 {
elessair 0:f269e3021894 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 185 register uint32_t __regfpscr __ASM("fpscr");
elessair 0:f269e3021894 186 return(__regfpscr);
elessair 0:f269e3021894 187 #else
elessair 0:f269e3021894 188 return(0);
elessair 0:f269e3021894 189 #endif
elessair 0:f269e3021894 190 }
elessair 0:f269e3021894 191
elessair 0:f269e3021894 192
elessair 0:f269e3021894 193 /** \brief Set FPSCR
elessair 0:f269e3021894 194
elessair 0:f269e3021894 195 This function assigns the given value to the Floating Point Status/Control register.
elessair 0:f269e3021894 196
elessair 0:f269e3021894 197 \param [in] fpscr Floating Point Status/Control value to set
elessair 0:f269e3021894 198 */
elessair 0:f269e3021894 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
elessair 0:f269e3021894 200 {
elessair 0:f269e3021894 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 202 register uint32_t __regfpscr __ASM("fpscr");
elessair 0:f269e3021894 203 __regfpscr = (fpscr);
elessair 0:f269e3021894 204 #endif
elessair 0:f269e3021894 205 }
elessair 0:f269e3021894 206
elessair 0:f269e3021894 207 /** \brief Get FPEXC
elessair 0:f269e3021894 208
elessair 0:f269e3021894 209 This function returns the current value of the Floating Point Exception Control register.
elessair 0:f269e3021894 210
elessair 0:f269e3021894 211 \return Floating Point Exception Control register value
elessair 0:f269e3021894 212 */
elessair 0:f269e3021894 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
elessair 0:f269e3021894 214 {
elessair 0:f269e3021894 215 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 216 register uint32_t __regfpexc __ASM("fpexc");
elessair 0:f269e3021894 217 return(__regfpexc);
elessair 0:f269e3021894 218 #else
elessair 0:f269e3021894 219 return(0);
elessair 0:f269e3021894 220 #endif
elessair 0:f269e3021894 221 }
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223
elessair 0:f269e3021894 224 /** \brief Set FPEXC
elessair 0:f269e3021894 225
elessair 0:f269e3021894 226 This function assigns the given value to the Floating Point Exception Control register.
elessair 0:f269e3021894 227
elessair 0:f269e3021894 228 \param [in] fpscr Floating Point Exception Control value to set
elessair 0:f269e3021894 229 */
elessair 0:f269e3021894 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
elessair 0:f269e3021894 231 {
elessair 0:f269e3021894 232 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 233 register uint32_t __regfpexc __ASM("fpexc");
elessair 0:f269e3021894 234 __regfpexc = (fpexc);
elessair 0:f269e3021894 235 #endif
elessair 0:f269e3021894 236 }
elessair 0:f269e3021894 237
elessair 0:f269e3021894 238 /** \brief Get CPACR
elessair 0:f269e3021894 239
elessair 0:f269e3021894 240 This function returns the current value of the Coprocessor Access Control register.
elessair 0:f269e3021894 241
elessair 0:f269e3021894 242 \return Coprocessor Access Control register value
elessair 0:f269e3021894 243 */
elessair 0:f269e3021894 244 __STATIC_INLINE uint32_t __get_CPACR(void)
elessair 0:f269e3021894 245 {
elessair 0:f269e3021894 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
elessair 0:f269e3021894 247 return __regCPACR;
elessair 0:f269e3021894 248 }
elessair 0:f269e3021894 249
elessair 0:f269e3021894 250 /** \brief Set CPACR
elessair 0:f269e3021894 251
elessair 0:f269e3021894 252 This function assigns the given value to the Coprocessor Access Control register.
elessair 0:f269e3021894 253
elessair 0:f269e3021894 254 \param [in] cpacr Coprocessor Acccess Control value to set
elessair 0:f269e3021894 255 */
elessair 0:f269e3021894 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
elessair 0:f269e3021894 257 {
elessair 0:f269e3021894 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
elessair 0:f269e3021894 259 __regCPACR = cpacr;
elessair 0:f269e3021894 260 __ISB();
elessair 0:f269e3021894 261 }
elessair 0:f269e3021894 262
elessair 0:f269e3021894 263 /** \brief Get CBAR
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 This function returns the value of the Configuration Base Address register.
elessair 0:f269e3021894 266
elessair 0:f269e3021894 267 \return Configuration Base Address register value
elessair 0:f269e3021894 268 */
elessair 0:f269e3021894 269 __STATIC_INLINE uint32_t __get_CBAR() {
elessair 0:f269e3021894 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
elessair 0:f269e3021894 271 return(__regCBAR);
elessair 0:f269e3021894 272 }
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 /** \brief Get TTBR0
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 This function returns the value of the Translation Table Base Register 0.
elessair 0:f269e3021894 277
elessair 0:f269e3021894 278 \return Translation Table Base Register 0 value
elessair 0:f269e3021894 279 */
elessair 0:f269e3021894 280 __STATIC_INLINE uint32_t __get_TTBR0() {
elessair 0:f269e3021894 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
elessair 0:f269e3021894 282 return(__regTTBR0);
elessair 0:f269e3021894 283 }
elessair 0:f269e3021894 284
elessair 0:f269e3021894 285 /** \brief Set TTBR0
elessair 0:f269e3021894 286
elessair 0:f269e3021894 287 This function assigns the given value to the Translation Table Base Register 0.
elessair 0:f269e3021894 288
elessair 0:f269e3021894 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
elessair 0:f269e3021894 290 */
elessair 0:f269e3021894 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
elessair 0:f269e3021894 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
elessair 0:f269e3021894 293 __regTTBR0 = ttbr0;
elessair 0:f269e3021894 294 __ISB();
elessair 0:f269e3021894 295 }
elessair 0:f269e3021894 296
elessair 0:f269e3021894 297 /** \brief Get DACR
elessair 0:f269e3021894 298
elessair 0:f269e3021894 299 This function returns the value of the Domain Access Control Register.
elessair 0:f269e3021894 300
elessair 0:f269e3021894 301 \return Domain Access Control Register value
elessair 0:f269e3021894 302 */
elessair 0:f269e3021894 303 __STATIC_INLINE uint32_t __get_DACR() {
elessair 0:f269e3021894 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
elessair 0:f269e3021894 305 return(__regDACR);
elessair 0:f269e3021894 306 }
elessair 0:f269e3021894 307
elessair 0:f269e3021894 308 /** \brief Set DACR
elessair 0:f269e3021894 309
elessair 0:f269e3021894 310 This function assigns the given value to the Domain Access Control Register.
elessair 0:f269e3021894 311
elessair 0:f269e3021894 312 \param [in] dacr Domain Access Control Register value to set
elessair 0:f269e3021894 313 */
elessair 0:f269e3021894 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
elessair 0:f269e3021894 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
elessair 0:f269e3021894 316 __regDACR = dacr;
elessair 0:f269e3021894 317 __ISB();
elessair 0:f269e3021894 318 }
elessair 0:f269e3021894 319
elessair 0:f269e3021894 320 /******************************** Cache and BTAC enable ****************************************************/
elessair 0:f269e3021894 321
elessair 0:f269e3021894 322 /** \brief Set SCTLR
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 This function assigns the given value to the System Control Register.
elessair 0:f269e3021894 325
elessair 0:f269e3021894 326 \param [in] sctlr System Control Register value to set
elessair 0:f269e3021894 327 */
elessair 0:f269e3021894 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
elessair 0:f269e3021894 329 {
elessair 0:f269e3021894 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
elessair 0:f269e3021894 331 __regSCTLR = sctlr;
elessair 0:f269e3021894 332 }
elessair 0:f269e3021894 333
elessair 0:f269e3021894 334 /** \brief Get SCTLR
elessair 0:f269e3021894 335
elessair 0:f269e3021894 336 This function returns the value of the System Control Register.
elessair 0:f269e3021894 337
elessair 0:f269e3021894 338 \return System Control Register value
elessair 0:f269e3021894 339 */
elessair 0:f269e3021894 340 __STATIC_INLINE uint32_t __get_SCTLR() {
elessair 0:f269e3021894 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
elessair 0:f269e3021894 342 return(__regSCTLR);
elessair 0:f269e3021894 343 }
elessair 0:f269e3021894 344
elessair 0:f269e3021894 345 /** \brief Enable Caches
elessair 0:f269e3021894 346
elessair 0:f269e3021894 347 Enable Caches
elessair 0:f269e3021894 348 */
elessair 0:f269e3021894 349 __STATIC_INLINE void __enable_caches(void) {
elessair 0:f269e3021894 350 // Set I bit 12 to enable I Cache
elessair 0:f269e3021894 351 // Set C bit 2 to enable D Cache
elessair 0:f269e3021894 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
elessair 0:f269e3021894 353 }
elessair 0:f269e3021894 354
elessair 0:f269e3021894 355 /** \brief Disable Caches
elessair 0:f269e3021894 356
elessair 0:f269e3021894 357 Disable Caches
elessair 0:f269e3021894 358 */
elessair 0:f269e3021894 359 __STATIC_INLINE void __disable_caches(void) {
elessair 0:f269e3021894 360 // Clear I bit 12 to disable I Cache
elessair 0:f269e3021894 361 // Clear C bit 2 to disable D Cache
elessair 0:f269e3021894 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
elessair 0:f269e3021894 363 __ISB();
elessair 0:f269e3021894 364 }
elessair 0:f269e3021894 365
elessair 0:f269e3021894 366 /** \brief Enable BTAC
elessair 0:f269e3021894 367
elessair 0:f269e3021894 368 Enable BTAC
elessair 0:f269e3021894 369 */
elessair 0:f269e3021894 370 __STATIC_INLINE void __enable_btac(void) {
elessair 0:f269e3021894 371 // Set Z bit 11 to enable branch prediction
elessair 0:f269e3021894 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
elessair 0:f269e3021894 373 __ISB();
elessair 0:f269e3021894 374 }
elessair 0:f269e3021894 375
elessair 0:f269e3021894 376 /** \brief Disable BTAC
elessair 0:f269e3021894 377
elessair 0:f269e3021894 378 Disable BTAC
elessair 0:f269e3021894 379 */
elessair 0:f269e3021894 380 __STATIC_INLINE void __disable_btac(void) {
elessair 0:f269e3021894 381 // Clear Z bit 11 to disable branch prediction
elessair 0:f269e3021894 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
elessair 0:f269e3021894 383 }
elessair 0:f269e3021894 384
elessair 0:f269e3021894 385
elessair 0:f269e3021894 386 /** \brief Enable MMU
elessair 0:f269e3021894 387
elessair 0:f269e3021894 388 Enable MMU
elessair 0:f269e3021894 389 */
elessair 0:f269e3021894 390 __STATIC_INLINE void __enable_mmu(void) {
elessair 0:f269e3021894 391 // Set M bit 0 to enable the MMU
elessair 0:f269e3021894 392 // Set AFE bit to enable simplified access permissions model
elessair 0:f269e3021894 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
elessair 0:f269e3021894 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
elessair 0:f269e3021894 395 __ISB();
elessair 0:f269e3021894 396 }
elessair 0:f269e3021894 397
elessair 0:f269e3021894 398 /** \brief Disable MMU
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 Disable MMU
elessair 0:f269e3021894 401 */
elessair 0:f269e3021894 402 __STATIC_INLINE void __disable_mmu(void) {
elessair 0:f269e3021894 403 // Clear M bit 0 to disable the MMU
elessair 0:f269e3021894 404 __set_SCTLR( __get_SCTLR() & ~1);
elessair 0:f269e3021894 405 __ISB();
elessair 0:f269e3021894 406 }
elessair 0:f269e3021894 407
elessair 0:f269e3021894 408 /******************************** TLB maintenance operations ************************************************/
elessair 0:f269e3021894 409 /** \brief Invalidate the whole tlb
elessair 0:f269e3021894 410
elessair 0:f269e3021894 411 TLBIALL. Invalidate the whole tlb
elessair 0:f269e3021894 412 */
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
elessair 0:f269e3021894 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
elessair 0:f269e3021894 416 __TLBIALL = 0;
elessair 0:f269e3021894 417 __DSB();
elessair 0:f269e3021894 418 __ISB();
elessair 0:f269e3021894 419 }
elessair 0:f269e3021894 420
elessair 0:f269e3021894 421 /******************************** BTB maintenance operations ************************************************/
elessair 0:f269e3021894 422 /** \brief Invalidate entire branch predictor array
elessair 0:f269e3021894 423
elessair 0:f269e3021894 424 BPIALL. Branch Predictor Invalidate All.
elessair 0:f269e3021894 425 */
elessair 0:f269e3021894 426
elessair 0:f269e3021894 427 __STATIC_INLINE void __v7_inv_btac(void) {
elessair 0:f269e3021894 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
elessair 0:f269e3021894 429 __BPIALL = 0;
elessair 0:f269e3021894 430 __DSB(); //ensure completion of the invalidation
elessair 0:f269e3021894 431 __ISB(); //ensure instruction fetch path sees new state
elessair 0:f269e3021894 432 }
elessair 0:f269e3021894 433
elessair 0:f269e3021894 434
elessair 0:f269e3021894 435 /******************************** L1 cache operations ******************************************************/
elessair 0:f269e3021894 436
elessair 0:f269e3021894 437 /** \brief Invalidate the whole I$
elessair 0:f269e3021894 438
elessair 0:f269e3021894 439 ICIALLU. Instruction Cache Invalidate All to PoU
elessair 0:f269e3021894 440 */
elessair 0:f269e3021894 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
elessair 0:f269e3021894 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
elessair 0:f269e3021894 443 __ICIALLU = 0;
elessair 0:f269e3021894 444 __DSB(); //ensure completion of the invalidation
elessair 0:f269e3021894 445 __ISB(); //ensure instruction fetch path sees new I cache state
elessair 0:f269e3021894 446 }
elessair 0:f269e3021894 447
elessair 0:f269e3021894 448 /** \brief Clean D$ by MVA
elessair 0:f269e3021894 449
elessair 0:f269e3021894 450 DCCMVAC. Data cache clean by MVA to PoC
elessair 0:f269e3021894 451 */
elessair 0:f269e3021894 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
elessair 0:f269e3021894 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
elessair 0:f269e3021894 454 __DCCMVAC = (uint32_t)va;
elessair 0:f269e3021894 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
elessair 0:f269e3021894 456 }
elessair 0:f269e3021894 457
elessair 0:f269e3021894 458 /** \brief Invalidate D$ by MVA
elessair 0:f269e3021894 459
elessair 0:f269e3021894 460 DCIMVAC. Data cache invalidate by MVA to PoC
elessair 0:f269e3021894 461 */
elessair 0:f269e3021894 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
elessair 0:f269e3021894 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
elessair 0:f269e3021894 464 __DCIMVAC = (uint32_t)va;
elessair 0:f269e3021894 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
elessair 0:f269e3021894 466 }
elessair 0:f269e3021894 467
elessair 0:f269e3021894 468 /** \brief Clean and Invalidate D$ by MVA
elessair 0:f269e3021894 469
elessair 0:f269e3021894 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
elessair 0:f269e3021894 471 */
elessair 0:f269e3021894 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
elessair 0:f269e3021894 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
elessair 0:f269e3021894 474 __DCCIMVAC = (uint32_t)va;
elessair 0:f269e3021894 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
elessair 0:f269e3021894 476 }
elessair 0:f269e3021894 477
elessair 0:f269e3021894 478 /** \brief Clean and Invalidate the entire data or unified cache
elessair 0:f269e3021894 479
elessair 0:f269e3021894 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
elessair 0:f269e3021894 481 */
elessair 0:f269e3021894 482 #pragma push
elessair 0:f269e3021894 483 #pragma arm
elessair 0:f269e3021894 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
elessair 0:f269e3021894 485 ARM
elessair 0:f269e3021894 486
elessair 0:f269e3021894 487 PUSH {R4-R11}
elessair 0:f269e3021894 488
elessair 0:f269e3021894 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
elessair 0:f269e3021894 490 ANDS R3, R6, #0x07000000 // Extract coherency level
elessair 0:f269e3021894 491 MOV R3, R3, LSR #23 // Total cache levels << 1
elessair 0:f269e3021894 492 BEQ Finished // If 0, no need to clean
elessair 0:f269e3021894 493
elessair 0:f269e3021894 494 MOV R10, #0 // R10 holds current cache level << 1
elessair 0:f269e3021894 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
elessair 0:f269e3021894 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
elessair 0:f269e3021894 497 AND R1, R1, #7 // Isolate those lower 3 bits
elessair 0:f269e3021894 498 CMP R1, #2
elessair 0:f269e3021894 499 BLT Skip // No cache or only instruction cache at this level
elessair 0:f269e3021894 500
elessair 0:f269e3021894 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
elessair 0:f269e3021894 502 ISB // ISB to sync the change to the CacheSizeID reg
elessair 0:f269e3021894 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
elessair 0:f269e3021894 504 AND R2, R1, #7 // Extract the line length field
elessair 0:f269e3021894 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
elessair 0:f269e3021894 506 LDR R4, =0x3FF
elessair 0:f269e3021894 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
elessair 0:f269e3021894 508 CLZ R5, R4 // R5 is the bit position of the way size increment
elessair 0:f269e3021894 509 LDR R7, =0x7FFF
elessair 0:f269e3021894 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
elessair 0:f269e3021894 511
elessair 0:f269e3021894 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
elessair 0:f269e3021894 513
elessair 0:f269e3021894 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
elessair 0:f269e3021894 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
elessair 0:f269e3021894 516 CMP R0, #0
elessair 0:f269e3021894 517 BNE Dccsw
elessair 0:f269e3021894 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
elessair 0:f269e3021894 519 B cont
elessair 0:f269e3021894 520 Dccsw CMP R0, #1
elessair 0:f269e3021894 521 BNE Dccisw
elessair 0:f269e3021894 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
elessair 0:f269e3021894 523 B cont
elessair 0:f269e3021894 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
elessair 0:f269e3021894 525 cont SUBS R9, R9, #1 // Decrement the Way number
elessair 0:f269e3021894 526 BGE Loop3
elessair 0:f269e3021894 527 SUBS R7, R7, #1 // Decrement the Set number
elessair 0:f269e3021894 528 BGE Loop2
elessair 0:f269e3021894 529 Skip ADD R10, R10, #2 // Increment the cache number
elessair 0:f269e3021894 530 CMP R3, R10
elessair 0:f269e3021894 531 BGT Loop1
elessair 0:f269e3021894 532
elessair 0:f269e3021894 533 Finished
elessair 0:f269e3021894 534 DSB
elessair 0:f269e3021894 535 POP {R4-R11}
elessair 0:f269e3021894 536 BX lr
elessair 0:f269e3021894 537
elessair 0:f269e3021894 538 }
elessair 0:f269e3021894 539 #pragma pop
elessair 0:f269e3021894 540
elessair 0:f269e3021894 541
elessair 0:f269e3021894 542 /** \brief Invalidate the whole D$
elessair 0:f269e3021894 543
elessair 0:f269e3021894 544 DCISW. Invalidate by Set/Way
elessair 0:f269e3021894 545 */
elessair 0:f269e3021894 546
elessair 0:f269e3021894 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
elessair 0:f269e3021894 548 __v7_all_cache(0);
elessair 0:f269e3021894 549 }
elessair 0:f269e3021894 550
elessair 0:f269e3021894 551 /** \brief Clean the whole D$
elessair 0:f269e3021894 552
elessair 0:f269e3021894 553 DCCSW. Clean by Set/Way
elessair 0:f269e3021894 554 */
elessair 0:f269e3021894 555
elessair 0:f269e3021894 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
elessair 0:f269e3021894 557 __v7_all_cache(1);
elessair 0:f269e3021894 558 }
elessair 0:f269e3021894 559
elessair 0:f269e3021894 560 /** \brief Clean and invalidate the whole D$
elessair 0:f269e3021894 561
elessair 0:f269e3021894 562 DCCISW. Clean and Invalidate by Set/Way
elessair 0:f269e3021894 563 */
elessair 0:f269e3021894 564
elessair 0:f269e3021894 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
elessair 0:f269e3021894 566 __v7_all_cache(2);
elessair 0:f269e3021894 567 }
elessair 0:f269e3021894 568
elessair 0:f269e3021894 569 #include "core_ca_mmu.h"
elessair 0:f269e3021894 570
elessair 0:f269e3021894 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
elessair 0:f269e3021894 572
elessair 0:f269e3021894 573 #define __inline inline
elessair 0:f269e3021894 574
elessair 0:f269e3021894 575 inline static uint32_t __disable_irq_iar() {
elessair 0:f269e3021894 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
elessair 0:f269e3021894 577 __disable_irq();
elessair 0:f269e3021894 578 return irq_dis;
elessair 0:f269e3021894 579 }
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 #define MODE_USR 0x10
elessair 0:f269e3021894 582 #define MODE_FIQ 0x11
elessair 0:f269e3021894 583 #define MODE_IRQ 0x12
elessair 0:f269e3021894 584 #define MODE_SVC 0x13
elessair 0:f269e3021894 585 #define MODE_MON 0x16
elessair 0:f269e3021894 586 #define MODE_ABT 0x17
elessair 0:f269e3021894 587 #define MODE_HYP 0x1A
elessair 0:f269e3021894 588 #define MODE_UND 0x1B
elessair 0:f269e3021894 589 #define MODE_SYS 0x1F
elessair 0:f269e3021894 590
elessair 0:f269e3021894 591 /** \brief Set Process Stack Pointer
elessair 0:f269e3021894 592
elessair 0:f269e3021894 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
elessair 0:f269e3021894 594
elessair 0:f269e3021894 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
elessair 0:f269e3021894 596 */
elessair 0:f269e3021894 597 // from rt_CMSIS.c
elessair 0:f269e3021894 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
elessair 0:f269e3021894 599 __asm(
elessair 0:f269e3021894 600 " ARM\n"
elessair 0:f269e3021894 601 // " PRESERVE8\n"
elessair 0:f269e3021894 602
elessair 0:f269e3021894 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
elessair 0:f269e3021894 604 " MRS R1, CPSR \n"
elessair 0:f269e3021894 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
elessair 0:f269e3021894 606 " MOV SP, R0 \n"
elessair 0:f269e3021894 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
elessair 0:f269e3021894 608 " ISB \n"
elessair 0:f269e3021894 609 " BX LR \n");
elessair 0:f269e3021894 610 }
elessair 0:f269e3021894 611
elessair 0:f269e3021894 612 /** \brief Set User Mode
elessair 0:f269e3021894 613
elessair 0:f269e3021894 614 This function changes the processor state to User Mode
elessair 0:f269e3021894 615 */
elessair 0:f269e3021894 616 // from rt_CMSIS.c
elessair 0:f269e3021894 617 __arm static inline void __set_CPS_USR(void) {
elessair 0:f269e3021894 618 __asm(
elessair 0:f269e3021894 619 " ARM \n"
elessair 0:f269e3021894 620
elessair 0:f269e3021894 621 " CPS #0x10 \n" // MODE_USR
elessair 0:f269e3021894 622 " BX LR\n");
elessair 0:f269e3021894 623 }
elessair 0:f269e3021894 624
elessair 0:f269e3021894 625 /** \brief Set TTBR0
elessair 0:f269e3021894 626
elessair 0:f269e3021894 627 This function assigns the given value to the Translation Table Base Register 0.
elessair 0:f269e3021894 628
elessair 0:f269e3021894 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
elessair 0:f269e3021894 630 */
elessair 0:f269e3021894 631 // from mmu_Renesas_RZ_A1.c
elessair 0:f269e3021894 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
elessair 0:f269e3021894 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
elessair 0:f269e3021894 634 __ISB();
elessair 0:f269e3021894 635 }
elessair 0:f269e3021894 636
elessair 0:f269e3021894 637 /** \brief Set DACR
elessair 0:f269e3021894 638
elessair 0:f269e3021894 639 This function assigns the given value to the Domain Access Control Register.
elessair 0:f269e3021894 640
elessair 0:f269e3021894 641 \param [in] dacr Domain Access Control Register value to set
elessair 0:f269e3021894 642 */
elessair 0:f269e3021894 643 // from mmu_Renesas_RZ_A1.c
elessair 0:f269e3021894 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
elessair 0:f269e3021894 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
elessair 0:f269e3021894 646 __ISB();
elessair 0:f269e3021894 647 }
elessair 0:f269e3021894 648
elessair 0:f269e3021894 649
elessair 0:f269e3021894 650 /******************************** Cache and BTAC enable ****************************************************/
elessair 0:f269e3021894 651 /** \brief Set SCTLR
elessair 0:f269e3021894 652
elessair 0:f269e3021894 653 This function assigns the given value to the System Control Register.
elessair 0:f269e3021894 654
elessair 0:f269e3021894 655 \param [in] sctlr System Control Register value to set
elessair 0:f269e3021894 656 */
elessair 0:f269e3021894 657 // from __enable_mmu()
elessair 0:f269e3021894 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
elessair 0:f269e3021894 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
elessair 0:f269e3021894 660 }
elessair 0:f269e3021894 661
elessair 0:f269e3021894 662 /** \brief Get SCTLR
elessair 0:f269e3021894 663
elessair 0:f269e3021894 664 This function returns the value of the System Control Register.
elessair 0:f269e3021894 665
elessair 0:f269e3021894 666 \return System Control Register value
elessair 0:f269e3021894 667 */
elessair 0:f269e3021894 668 // from __enable_mmu()
elessair 0:f269e3021894 669 __STATIC_INLINE uint32_t __get_SCTLR() {
elessair 0:f269e3021894 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
elessair 0:f269e3021894 671 return __regSCTLR;
elessair 0:f269e3021894 672 }
elessair 0:f269e3021894 673
elessair 0:f269e3021894 674 /** \brief Enable Caches
elessair 0:f269e3021894 675
elessair 0:f269e3021894 676 Enable Caches
elessair 0:f269e3021894 677 */
elessair 0:f269e3021894 678 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 679 __STATIC_INLINE void __enable_caches(void) {
elessair 0:f269e3021894 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
elessair 0:f269e3021894 681 }
elessair 0:f269e3021894 682
elessair 0:f269e3021894 683 /** \brief Enable BTAC
elessair 0:f269e3021894 684
elessair 0:f269e3021894 685 Enable BTAC
elessair 0:f269e3021894 686 */
elessair 0:f269e3021894 687 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 688 __STATIC_INLINE void __enable_btac(void) {
elessair 0:f269e3021894 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
elessair 0:f269e3021894 690 __ISB();
elessair 0:f269e3021894 691 }
elessair 0:f269e3021894 692
elessair 0:f269e3021894 693 /** \brief Enable MMU
elessair 0:f269e3021894 694
elessair 0:f269e3021894 695 Enable MMU
elessair 0:f269e3021894 696 */
elessair 0:f269e3021894 697 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 698 __STATIC_INLINE void __enable_mmu(void) {
elessair 0:f269e3021894 699 // Set M bit 0 to enable the MMU
elessair 0:f269e3021894 700 // Set AFE bit to enable simplified access permissions model
elessair 0:f269e3021894 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
elessair 0:f269e3021894 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
elessair 0:f269e3021894 703 __ISB();
elessair 0:f269e3021894 704 }
elessair 0:f269e3021894 705
elessair 0:f269e3021894 706 /******************************** TLB maintenance operations ************************************************/
elessair 0:f269e3021894 707 /** \brief Invalidate the whole tlb
elessair 0:f269e3021894 708
elessair 0:f269e3021894 709 TLBIALL. Invalidate the whole tlb
elessair 0:f269e3021894 710 */
elessair 0:f269e3021894 711 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
elessair 0:f269e3021894 713 uint32_t val = 0;
elessair 0:f269e3021894 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
elessair 0:f269e3021894 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
elessair 0:f269e3021894 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
elessair 0:f269e3021894 717 __DSB();
elessair 0:f269e3021894 718 __ISB();
elessair 0:f269e3021894 719 }
elessair 0:f269e3021894 720
elessair 0:f269e3021894 721 /******************************** BTB maintenance operations ************************************************/
elessair 0:f269e3021894 722 /** \brief Invalidate entire branch predictor array
elessair 0:f269e3021894 723
elessair 0:f269e3021894 724 BPIALL. Branch Predictor Invalidate All.
elessair 0:f269e3021894 725 */
elessair 0:f269e3021894 726 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 727 __STATIC_INLINE void __v7_inv_btac(void) {
elessair 0:f269e3021894 728 uint32_t val = 0;
elessair 0:f269e3021894 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
elessair 0:f269e3021894 730 __DSB(); //ensure completion of the invalidation
elessair 0:f269e3021894 731 __ISB(); //ensure instruction fetch path sees new state
elessair 0:f269e3021894 732 }
elessair 0:f269e3021894 733
elessair 0:f269e3021894 734
elessair 0:f269e3021894 735 /******************************** L1 cache operations ******************************************************/
elessair 0:f269e3021894 736
elessair 0:f269e3021894 737 /** \brief Invalidate the whole I$
elessair 0:f269e3021894 738
elessair 0:f269e3021894 739 ICIALLU. Instruction Cache Invalidate All to PoU
elessair 0:f269e3021894 740 */
elessair 0:f269e3021894 741 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
elessair 0:f269e3021894 743 uint32_t val = 0;
elessair 0:f269e3021894 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
elessair 0:f269e3021894 745 __DSB(); //ensure completion of the invalidation
elessair 0:f269e3021894 746 __ISB(); //ensure instruction fetch path sees new I cache state
elessair 0:f269e3021894 747 }
elessair 0:f269e3021894 748
elessair 0:f269e3021894 749 // from __v7_inv_dcache_all()
elessair 0:f269e3021894 750 __arm static inline void __v7_all_cache(uint32_t op) {
elessair 0:f269e3021894 751 __asm(
elessair 0:f269e3021894 752 " ARM \n"
elessair 0:f269e3021894 753
elessair 0:f269e3021894 754 " PUSH {R4-R11} \n"
elessair 0:f269e3021894 755
elessair 0:f269e3021894 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
elessair 0:f269e3021894 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
elessair 0:f269e3021894 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
elessair 0:f269e3021894 759 " BEQ Finished\n" // If 0, no need to clean
elessair 0:f269e3021894 760
elessair 0:f269e3021894 761 " MOV R10, #0\n" // R10 holds current cache level << 1
elessair 0:f269e3021894 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
elessair 0:f269e3021894 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
elessair 0:f269e3021894 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
elessair 0:f269e3021894 765 " CMP R1, #2 \n"
elessair 0:f269e3021894 766 " BLT Skip \n" // No cache or only instruction cache at this level
elessair 0:f269e3021894 767
elessair 0:f269e3021894 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
elessair 0:f269e3021894 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
elessair 0:f269e3021894 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
elessair 0:f269e3021894 771 " AND R2, R1, #7 \n" // Extract the line length field
elessair 0:f269e3021894 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
elessair 0:f269e3021894 773 " movw R4, #0x3FF \n"
elessair 0:f269e3021894 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
elessair 0:f269e3021894 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
elessair 0:f269e3021894 776 " movw R7, #0x7FFF \n"
elessair 0:f269e3021894 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
elessair 0:f269e3021894 778
elessair 0:f269e3021894 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
elessair 0:f269e3021894 780
elessair 0:f269e3021894 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
elessair 0:f269e3021894 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
elessair 0:f269e3021894 783 " CMP R0, #0 \n"
elessair 0:f269e3021894 784 " BNE Dccsw \n"
elessair 0:f269e3021894 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
elessair 0:f269e3021894 786 " B cont \n"
elessair 0:f269e3021894 787 "Dccsw: CMP R0, #1 \n"
elessair 0:f269e3021894 788 " BNE Dccisw \n"
elessair 0:f269e3021894 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
elessair 0:f269e3021894 790 " B cont \n"
elessair 0:f269e3021894 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
elessair 0:f269e3021894 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
elessair 0:f269e3021894 793 " BGE Loop3 \n"
elessair 0:f269e3021894 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
elessair 0:f269e3021894 795 " BGE Loop2 \n"
elessair 0:f269e3021894 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
elessair 0:f269e3021894 797 " CMP R3, R10 \n"
elessair 0:f269e3021894 798 " BGT Loop1 \n"
elessair 0:f269e3021894 799
elessair 0:f269e3021894 800 "Finished: \n"
elessair 0:f269e3021894 801 " DSB \n"
elessair 0:f269e3021894 802 " POP {R4-R11} \n"
elessair 0:f269e3021894 803 " BX lr \n" );
elessair 0:f269e3021894 804 }
elessair 0:f269e3021894 805
elessair 0:f269e3021894 806 /** \brief Invalidate the whole D$
elessair 0:f269e3021894 807
elessair 0:f269e3021894 808 DCISW. Invalidate by Set/Way
elessair 0:f269e3021894 809 */
elessair 0:f269e3021894 810 // from system_Renesas_RZ_A1.c
elessair 0:f269e3021894 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
elessair 0:f269e3021894 812 __v7_all_cache(0);
elessair 0:f269e3021894 813 }
elessair 0:f269e3021894 814 /** \brief Clean and Invalidate D$ by MVA
elessair 0:f269e3021894 815
elessair 0:f269e3021894 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
elessair 0:f269e3021894 817 */
elessair 0:f269e3021894 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
elessair 0:f269e3021894 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
elessair 0:f269e3021894 820 __DMB();
elessair 0:f269e3021894 821 }
elessair 0:f269e3021894 822
elessair 0:f269e3021894 823 #include "core_ca_mmu.h"
elessair 0:f269e3021894 824
elessair 0:f269e3021894 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
elessair 0:f269e3021894 826 /* GNU gcc specific functions */
elessair 0:f269e3021894 827
elessair 0:f269e3021894 828 #define MODE_USR 0x10
elessair 0:f269e3021894 829 #define MODE_FIQ 0x11
elessair 0:f269e3021894 830 #define MODE_IRQ 0x12
elessair 0:f269e3021894 831 #define MODE_SVC 0x13
elessair 0:f269e3021894 832 #define MODE_MON 0x16
elessair 0:f269e3021894 833 #define MODE_ABT 0x17
elessair 0:f269e3021894 834 #define MODE_HYP 0x1A
elessair 0:f269e3021894 835 #define MODE_UND 0x1B
elessair 0:f269e3021894 836 #define MODE_SYS 0x1F
elessair 0:f269e3021894 837
elessair 0:f269e3021894 838
elessair 0:f269e3021894 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
elessair 0:f269e3021894 840 {
elessair 0:f269e3021894 841 __ASM volatile ("cpsie i");
elessair 0:f269e3021894 842 }
elessair 0:f269e3021894 843
elessair 0:f269e3021894 844 /** \brief Disable IRQ Interrupts
elessair 0:f269e3021894 845
elessair 0:f269e3021894 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
elessair 0:f269e3021894 847 Can only be executed in Privileged modes.
elessair 0:f269e3021894 848 */
elessair 0:f269e3021894 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
elessair 0:f269e3021894 850 {
elessair 0:f269e3021894 851 uint32_t result;
elessair 0:f269e3021894 852
elessair 0:f269e3021894 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
elessair 0:f269e3021894 854 __ASM volatile ("cpsid i");
elessair 0:f269e3021894 855 return(result & 0x80);
elessair 0:f269e3021894 856 }
elessair 0:f269e3021894 857
elessair 0:f269e3021894 858
elessair 0:f269e3021894 859 /** \brief Get APSR Register
elessair 0:f269e3021894 860
elessair 0:f269e3021894 861 This function returns the content of the APSR Register.
elessair 0:f269e3021894 862
elessair 0:f269e3021894 863 \return APSR Register value
elessair 0:f269e3021894 864 */
elessair 0:f269e3021894 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
elessair 0:f269e3021894 866 {
elessair 0:f269e3021894 867 #if 1
elessair 0:f269e3021894 868 register uint32_t __regAPSR;
elessair 0:f269e3021894 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
elessair 0:f269e3021894 870 #else
elessair 0:f269e3021894 871 register uint32_t __regAPSR __ASM("apsr");
elessair 0:f269e3021894 872 #endif
elessair 0:f269e3021894 873 return(__regAPSR);
elessair 0:f269e3021894 874 }
elessair 0:f269e3021894 875
elessair 0:f269e3021894 876
elessair 0:f269e3021894 877 /** \brief Get CPSR Register
elessair 0:f269e3021894 878
elessair 0:f269e3021894 879 This function returns the content of the CPSR Register.
elessair 0:f269e3021894 880
elessair 0:f269e3021894 881 \return CPSR Register value
elessair 0:f269e3021894 882 */
elessair 0:f269e3021894 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
elessair 0:f269e3021894 884 {
elessair 0:f269e3021894 885 #if 1
elessair 0:f269e3021894 886 register uint32_t __regCPSR;
elessair 0:f269e3021894 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
elessair 0:f269e3021894 888 #else
elessair 0:f269e3021894 889 register uint32_t __regCPSR __ASM("cpsr");
elessair 0:f269e3021894 890 #endif
elessair 0:f269e3021894 891 return(__regCPSR);
elessair 0:f269e3021894 892 }
elessair 0:f269e3021894 893
elessair 0:f269e3021894 894 #if 0
elessair 0:f269e3021894 895 /** \brief Set Stack Pointer
elessair 0:f269e3021894 896
elessair 0:f269e3021894 897 This function assigns the given value to the current stack pointer.
elessair 0:f269e3021894 898
elessair 0:f269e3021894 899 \param [in] topOfStack Stack Pointer value to set
elessair 0:f269e3021894 900 */
elessair 0:f269e3021894 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
elessair 0:f269e3021894 902 {
elessair 0:f269e3021894 903 register uint32_t __regSP __ASM("sp");
elessair 0:f269e3021894 904 __regSP = topOfStack;
elessair 0:f269e3021894 905 }
elessair 0:f269e3021894 906 #endif
elessair 0:f269e3021894 907
elessair 0:f269e3021894 908 /** \brief Get link register
elessair 0:f269e3021894 909
elessair 0:f269e3021894 910 This function returns the value of the link register
elessair 0:f269e3021894 911
elessair 0:f269e3021894 912 \return Value of link register
elessair 0:f269e3021894 913 */
elessair 0:f269e3021894 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
elessair 0:f269e3021894 915 {
elessair 0:f269e3021894 916 register uint32_t __reglr __ASM("lr");
elessair 0:f269e3021894 917 return(__reglr);
elessair 0:f269e3021894 918 }
elessair 0:f269e3021894 919
elessair 0:f269e3021894 920 #if 0
elessair 0:f269e3021894 921 /** \brief Set link register
elessair 0:f269e3021894 922
elessair 0:f269e3021894 923 This function sets the value of the link register
elessair 0:f269e3021894 924
elessair 0:f269e3021894 925 \param [in] lr LR value to set
elessair 0:f269e3021894 926 */
elessair 0:f269e3021894 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
elessair 0:f269e3021894 928 {
elessair 0:f269e3021894 929 register uint32_t __reglr __ASM("lr");
elessair 0:f269e3021894 930 __reglr = lr;
elessair 0:f269e3021894 931 }
elessair 0:f269e3021894 932 #endif
elessair 0:f269e3021894 933
elessair 0:f269e3021894 934 /** \brief Set Process Stack Pointer
elessair 0:f269e3021894 935
elessair 0:f269e3021894 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
elessair 0:f269e3021894 937
elessair 0:f269e3021894 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
elessair 0:f269e3021894 939 */
elessair 0:f269e3021894 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
elessair 0:f269e3021894 941 {
elessair 0:f269e3021894 942 __asm__ volatile (
elessair 0:f269e3021894 943 ".ARM;"
elessair 0:f269e3021894 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
elessair 0:f269e3021894 945
elessair 0:f269e3021894 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
elessair 0:f269e3021894 947 "MRS R1, CPSR;"
elessair 0:f269e3021894 948 "CPS %0;" /* ;no effect in USR mode */
elessair 0:f269e3021894 949 "MOV SP, R0;"
elessair 0:f269e3021894 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
elessair 0:f269e3021894 951 "ISB;"
elessair 0:f269e3021894 952 //"BX LR;"
elessair 0:f269e3021894 953 :
elessair 0:f269e3021894 954 : "i"(MODE_SYS)
elessair 0:f269e3021894 955 : "r0", "r1");
elessair 0:f269e3021894 956 return;
elessair 0:f269e3021894 957 }
elessair 0:f269e3021894 958
elessair 0:f269e3021894 959 /** \brief Set User Mode
elessair 0:f269e3021894 960
elessair 0:f269e3021894 961 This function changes the processor state to User Mode
elessair 0:f269e3021894 962 */
elessair 0:f269e3021894 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
elessair 0:f269e3021894 964 {
elessair 0:f269e3021894 965 __asm__ volatile (
elessair 0:f269e3021894 966 ".ARM;"
elessair 0:f269e3021894 967
elessair 0:f269e3021894 968 "CPS %0;"
elessair 0:f269e3021894 969 //"BX LR;"
elessair 0:f269e3021894 970 :
elessair 0:f269e3021894 971 : "i"(MODE_USR)
elessair 0:f269e3021894 972 : );
elessair 0:f269e3021894 973 return;
elessair 0:f269e3021894 974 }
elessair 0:f269e3021894 975
elessair 0:f269e3021894 976
elessair 0:f269e3021894 977 /** \brief Enable FIQ
elessair 0:f269e3021894 978
elessair 0:f269e3021894 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
elessair 0:f269e3021894 980 Can only be executed in Privileged modes.
elessair 0:f269e3021894 981 */
elessair 0:f269e3021894 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
elessair 0:f269e3021894 983
elessair 0:f269e3021894 984
elessair 0:f269e3021894 985 /** \brief Disable FIQ
elessair 0:f269e3021894 986
elessair 0:f269e3021894 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
elessair 0:f269e3021894 988 Can only be executed in Privileged modes.
elessair 0:f269e3021894 989 */
elessair 0:f269e3021894 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
elessair 0:f269e3021894 991
elessair 0:f269e3021894 992
elessair 0:f269e3021894 993 /** \brief Get FPSCR
elessair 0:f269e3021894 994
elessair 0:f269e3021894 995 This function returns the current value of the Floating Point Status/Control register.
elessair 0:f269e3021894 996
elessair 0:f269e3021894 997 \return Floating Point Status/Control register value
elessair 0:f269e3021894 998 */
elessair 0:f269e3021894 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
elessair 0:f269e3021894 1000 {
elessair 0:f269e3021894 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 1002 #if 1
elessair 0:f269e3021894 1003 uint32_t result;
elessair 0:f269e3021894 1004
elessair 0:f269e3021894 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
elessair 0:f269e3021894 1006 return (result);
elessair 0:f269e3021894 1007 #else
elessair 0:f269e3021894 1008 register uint32_t __regfpscr __ASM("fpscr");
elessair 0:f269e3021894 1009 return(__regfpscr);
elessair 0:f269e3021894 1010 #endif
elessair 0:f269e3021894 1011 #else
elessair 0:f269e3021894 1012 return(0);
elessair 0:f269e3021894 1013 #endif
elessair 0:f269e3021894 1014 }
elessair 0:f269e3021894 1015
elessair 0:f269e3021894 1016
elessair 0:f269e3021894 1017 /** \brief Set FPSCR
elessair 0:f269e3021894 1018
elessair 0:f269e3021894 1019 This function assigns the given value to the Floating Point Status/Control register.
elessair 0:f269e3021894 1020
elessair 0:f269e3021894 1021 \param [in] fpscr Floating Point Status/Control value to set
elessair 0:f269e3021894 1022 */
elessair 0:f269e3021894 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
elessair 0:f269e3021894 1024 {
elessair 0:f269e3021894 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
elessair 0:f269e3021894 1026 #if 1
elessair 0:f269e3021894 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
elessair 0:f269e3021894 1028 #else
elessair 0:f269e3021894 1029 register uint32_t __regfpscr __ASM("fpscr");
elessair 0:f269e3021894 1030 __regfpscr = (fpscr);
elessair 0:f269e3021894 1031 #endif
elessair 0:f269e3021894 1032 #endif
elessair 0:f269e3021894 1033 }
elessair 0:f269e3021894 1034
elessair 0:f269e3021894 1035 /** \brief Get FPEXC
elessair 0:f269e3021894 1036
elessair 0:f269e3021894 1037 This function returns the current value of the Floating Point Exception Control register.
elessair 0:f269e3021894 1038
elessair 0:f269e3021894 1039 \return Floating Point Exception Control register value
elessair 0:f269e3021894 1040 */
elessair 0:f269e3021894 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
elessair 0:f269e3021894 1042 {
elessair 0:f269e3021894 1043 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 1044 #if 1
elessair 0:f269e3021894 1045 uint32_t result;
elessair 0:f269e3021894 1046
elessair 0:f269e3021894 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
elessair 0:f269e3021894 1048 return (result);
elessair 0:f269e3021894 1049 #else
elessair 0:f269e3021894 1050 register uint32_t __regfpexc __ASM("fpexc");
elessair 0:f269e3021894 1051 return(__regfpexc);
elessair 0:f269e3021894 1052 #endif
elessair 0:f269e3021894 1053 #else
elessair 0:f269e3021894 1054 return(0);
elessair 0:f269e3021894 1055 #endif
elessair 0:f269e3021894 1056 }
elessair 0:f269e3021894 1057
elessair 0:f269e3021894 1058
elessair 0:f269e3021894 1059 /** \brief Set FPEXC
elessair 0:f269e3021894 1060
elessair 0:f269e3021894 1061 This function assigns the given value to the Floating Point Exception Control register.
elessair 0:f269e3021894 1062
elessair 0:f269e3021894 1063 \param [in] fpscr Floating Point Exception Control value to set
elessair 0:f269e3021894 1064 */
elessair 0:f269e3021894 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
elessair 0:f269e3021894 1066 {
elessair 0:f269e3021894 1067 #if (__FPU_PRESENT == 1)
elessair 0:f269e3021894 1068 #if 1
elessair 0:f269e3021894 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
elessair 0:f269e3021894 1070 #else
elessair 0:f269e3021894 1071 register uint32_t __regfpexc __ASM("fpexc");
elessair 0:f269e3021894 1072 __regfpexc = (fpexc);
elessair 0:f269e3021894 1073 #endif
elessair 0:f269e3021894 1074 #endif
elessair 0:f269e3021894 1075 }
elessair 0:f269e3021894 1076
elessair 0:f269e3021894 1077 /** \brief Get CPACR
elessair 0:f269e3021894 1078
elessair 0:f269e3021894 1079 This function returns the current value of the Coprocessor Access Control register.
elessair 0:f269e3021894 1080
elessair 0:f269e3021894 1081 \return Coprocessor Access Control register value
elessair 0:f269e3021894 1082 */
elessair 0:f269e3021894 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
elessair 0:f269e3021894 1084 {
elessair 0:f269e3021894 1085 #if 1
elessair 0:f269e3021894 1086 register uint32_t __regCPACR;
elessair 0:f269e3021894 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
elessair 0:f269e3021894 1088 #else
elessair 0:f269e3021894 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
elessair 0:f269e3021894 1090 #endif
elessair 0:f269e3021894 1091 return __regCPACR;
elessair 0:f269e3021894 1092 }
elessair 0:f269e3021894 1093
elessair 0:f269e3021894 1094 /** \brief Set CPACR
elessair 0:f269e3021894 1095
elessair 0:f269e3021894 1096 This function assigns the given value to the Coprocessor Access Control register.
elessair 0:f269e3021894 1097
elessair 0:f269e3021894 1098 \param [in] cpacr Coprocessor Acccess Control value to set
elessair 0:f269e3021894 1099 */
elessair 0:f269e3021894 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
elessair 0:f269e3021894 1101 {
elessair 0:f269e3021894 1102 #if 1
elessair 0:f269e3021894 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
elessair 0:f269e3021894 1104 #else
elessair 0:f269e3021894 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
elessair 0:f269e3021894 1106 __regCPACR = cpacr;
elessair 0:f269e3021894 1107 #endif
elessair 0:f269e3021894 1108 __ISB();
elessair 0:f269e3021894 1109 }
elessair 0:f269e3021894 1110
elessair 0:f269e3021894 1111 /** \brief Get CBAR
elessair 0:f269e3021894 1112
elessair 0:f269e3021894 1113 This function returns the value of the Configuration Base Address register.
elessair 0:f269e3021894 1114
elessair 0:f269e3021894 1115 \return Configuration Base Address register value
elessair 0:f269e3021894 1116 */
elessair 0:f269e3021894 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
elessair 0:f269e3021894 1118 #if 1
elessair 0:f269e3021894 1119 register uint32_t __regCBAR;
elessair 0:f269e3021894 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
elessair 0:f269e3021894 1121 #else
elessair 0:f269e3021894 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
elessair 0:f269e3021894 1123 #endif
elessair 0:f269e3021894 1124 return(__regCBAR);
elessair 0:f269e3021894 1125 }
elessair 0:f269e3021894 1126
elessair 0:f269e3021894 1127 /** \brief Get TTBR0
elessair 0:f269e3021894 1128
elessair 0:f269e3021894 1129 This function returns the value of the Translation Table Base Register 0.
elessair 0:f269e3021894 1130
elessair 0:f269e3021894 1131 \return Translation Table Base Register 0 value
elessair 0:f269e3021894 1132 */
elessair 0:f269e3021894 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
elessair 0:f269e3021894 1134 #if 1
elessair 0:f269e3021894 1135 register uint32_t __regTTBR0;
elessair 0:f269e3021894 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
elessair 0:f269e3021894 1137 #else
elessair 0:f269e3021894 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
elessair 0:f269e3021894 1139 #endif
elessair 0:f269e3021894 1140 return(__regTTBR0);
elessair 0:f269e3021894 1141 }
elessair 0:f269e3021894 1142
elessair 0:f269e3021894 1143 /** \brief Set TTBR0
elessair 0:f269e3021894 1144
elessair 0:f269e3021894 1145 This function assigns the given value to the Translation Table Base Register 0.
elessair 0:f269e3021894 1146
elessair 0:f269e3021894 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
elessair 0:f269e3021894 1148 */
elessair 0:f269e3021894 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
elessair 0:f269e3021894 1150 #if 1
elessair 0:f269e3021894 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
elessair 0:f269e3021894 1152 #else
elessair 0:f269e3021894 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
elessair 0:f269e3021894 1154 __regTTBR0 = ttbr0;
elessair 0:f269e3021894 1155 #endif
elessair 0:f269e3021894 1156 __ISB();
elessair 0:f269e3021894 1157 }
elessair 0:f269e3021894 1158
elessair 0:f269e3021894 1159 /** \brief Get DACR
elessair 0:f269e3021894 1160
elessair 0:f269e3021894 1161 This function returns the value of the Domain Access Control Register.
elessair 0:f269e3021894 1162
elessair 0:f269e3021894 1163 \return Domain Access Control Register value
elessair 0:f269e3021894 1164 */
elessair 0:f269e3021894 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
elessair 0:f269e3021894 1166 #if 1
elessair 0:f269e3021894 1167 register uint32_t __regDACR;
elessair 0:f269e3021894 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
elessair 0:f269e3021894 1169 #else
elessair 0:f269e3021894 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
elessair 0:f269e3021894 1171 #endif
elessair 0:f269e3021894 1172 return(__regDACR);
elessair 0:f269e3021894 1173 }
elessair 0:f269e3021894 1174
elessair 0:f269e3021894 1175 /** \brief Set DACR
elessair 0:f269e3021894 1176
elessair 0:f269e3021894 1177 This function assigns the given value to the Domain Access Control Register.
elessair 0:f269e3021894 1178
elessair 0:f269e3021894 1179 \param [in] dacr Domain Access Control Register value to set
elessair 0:f269e3021894 1180 */
elessair 0:f269e3021894 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
elessair 0:f269e3021894 1182 #if 1
elessair 0:f269e3021894 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
elessair 0:f269e3021894 1184 #else
elessair 0:f269e3021894 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
elessair 0:f269e3021894 1186 __regDACR = dacr;
elessair 0:f269e3021894 1187 #endif
elessair 0:f269e3021894 1188 __ISB();
elessair 0:f269e3021894 1189 }
elessair 0:f269e3021894 1190
elessair 0:f269e3021894 1191 /******************************** Cache and BTAC enable ****************************************************/
elessair 0:f269e3021894 1192
elessair 0:f269e3021894 1193 /** \brief Set SCTLR
elessair 0:f269e3021894 1194
elessair 0:f269e3021894 1195 This function assigns the given value to the System Control Register.
elessair 0:f269e3021894 1196
elessair 0:f269e3021894 1197 \param [in] sctlr System Control Register value to set
elessair 0:f269e3021894 1198 */
elessair 0:f269e3021894 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
elessair 0:f269e3021894 1200 {
elessair 0:f269e3021894 1201 #if 1
elessair 0:f269e3021894 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
elessair 0:f269e3021894 1203 #else
elessair 0:f269e3021894 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
elessair 0:f269e3021894 1205 __regSCTLR = sctlr;
elessair 0:f269e3021894 1206 #endif
elessair 0:f269e3021894 1207 }
elessair 0:f269e3021894 1208
elessair 0:f269e3021894 1209 /** \brief Get SCTLR
elessair 0:f269e3021894 1210
elessair 0:f269e3021894 1211 This function returns the value of the System Control Register.
elessair 0:f269e3021894 1212
elessair 0:f269e3021894 1213 \return System Control Register value
elessair 0:f269e3021894 1214 */
elessair 0:f269e3021894 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
elessair 0:f269e3021894 1216 #if 1
elessair 0:f269e3021894 1217 register uint32_t __regSCTLR;
elessair 0:f269e3021894 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
elessair 0:f269e3021894 1219 #else
elessair 0:f269e3021894 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
elessair 0:f269e3021894 1221 #endif
elessair 0:f269e3021894 1222 return(__regSCTLR);
elessair 0:f269e3021894 1223 }
elessair 0:f269e3021894 1224
elessair 0:f269e3021894 1225 /** \brief Enable Caches
elessair 0:f269e3021894 1226
elessair 0:f269e3021894 1227 Enable Caches
elessair 0:f269e3021894 1228 */
elessair 0:f269e3021894 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
elessair 0:f269e3021894 1230 // Set I bit 12 to enable I Cache
elessair 0:f269e3021894 1231 // Set C bit 2 to enable D Cache
elessair 0:f269e3021894 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
elessair 0:f269e3021894 1233 }
elessair 0:f269e3021894 1234
elessair 0:f269e3021894 1235 /** \brief Disable Caches
elessair 0:f269e3021894 1236
elessair 0:f269e3021894 1237 Disable Caches
elessair 0:f269e3021894 1238 */
elessair 0:f269e3021894 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
elessair 0:f269e3021894 1240 // Clear I bit 12 to disable I Cache
elessair 0:f269e3021894 1241 // Clear C bit 2 to disable D Cache
elessair 0:f269e3021894 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
elessair 0:f269e3021894 1243 __ISB();
elessair 0:f269e3021894 1244 }
elessair 0:f269e3021894 1245
elessair 0:f269e3021894 1246 /** \brief Enable BTAC
elessair 0:f269e3021894 1247
elessair 0:f269e3021894 1248 Enable BTAC
elessair 0:f269e3021894 1249 */
elessair 0:f269e3021894 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
elessair 0:f269e3021894 1251 // Set Z bit 11 to enable branch prediction
elessair 0:f269e3021894 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
elessair 0:f269e3021894 1253 __ISB();
elessair 0:f269e3021894 1254 }
elessair 0:f269e3021894 1255
elessair 0:f269e3021894 1256 /** \brief Disable BTAC
elessair 0:f269e3021894 1257
elessair 0:f269e3021894 1258 Disable BTAC
elessair 0:f269e3021894 1259 */
elessair 0:f269e3021894 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
elessair 0:f269e3021894 1261 // Clear Z bit 11 to disable branch prediction
elessair 0:f269e3021894 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
elessair 0:f269e3021894 1263 }
elessair 0:f269e3021894 1264
elessair 0:f269e3021894 1265
elessair 0:f269e3021894 1266 /** \brief Enable MMU
elessair 0:f269e3021894 1267
elessair 0:f269e3021894 1268 Enable MMU
elessair 0:f269e3021894 1269 */
elessair 0:f269e3021894 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
elessair 0:f269e3021894 1271 // Set M bit 0 to enable the MMU
elessair 0:f269e3021894 1272 // Set AFE bit to enable simplified access permissions model
elessair 0:f269e3021894 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
elessair 0:f269e3021894 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
elessair 0:f269e3021894 1275 __ISB();
elessair 0:f269e3021894 1276 }
elessair 0:f269e3021894 1277
elessair 0:f269e3021894 1278 /** \brief Disable MMU
elessair 0:f269e3021894 1279
elessair 0:f269e3021894 1280 Disable MMU
elessair 0:f269e3021894 1281 */
elessair 0:f269e3021894 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
elessair 0:f269e3021894 1283 // Clear M bit 0 to disable the MMU
elessair 0:f269e3021894 1284 __set_SCTLR( __get_SCTLR() & ~1);
elessair 0:f269e3021894 1285 __ISB();
elessair 0:f269e3021894 1286 }
elessair 0:f269e3021894 1287
elessair 0:f269e3021894 1288 /******************************** TLB maintenance operations ************************************************/
elessair 0:f269e3021894 1289 /** \brief Invalidate the whole tlb
elessair 0:f269e3021894 1290
elessair 0:f269e3021894 1291 TLBIALL. Invalidate the whole tlb
elessair 0:f269e3021894 1292 */
elessair 0:f269e3021894 1293
elessair 0:f269e3021894 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
elessair 0:f269e3021894 1295 #if 1
elessair 0:f269e3021894 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
elessair 0:f269e3021894 1297 #else
elessair 0:f269e3021894 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
elessair 0:f269e3021894 1299 __TLBIALL = 0;
elessair 0:f269e3021894 1300 #endif
elessair 0:f269e3021894 1301 __DSB();
elessair 0:f269e3021894 1302 __ISB();
elessair 0:f269e3021894 1303 }
elessair 0:f269e3021894 1304
elessair 0:f269e3021894 1305 /******************************** BTB maintenance operations ************************************************/
elessair 0:f269e3021894 1306 /** \brief Invalidate entire branch predictor array
elessair 0:f269e3021894 1307
elessair 0:f269e3021894 1308 BPIALL. Branch Predictor Invalidate All.
elessair 0:f269e3021894 1309 */
elessair 0:f269e3021894 1310
elessair 0:f269e3021894 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
elessair 0:f269e3021894 1312 #if 1
elessair 0:f269e3021894 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
elessair 0:f269e3021894 1314 #else
elessair 0:f269e3021894 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
elessair 0:f269e3021894 1316 __BPIALL = 0;
elessair 0:f269e3021894 1317 #endif
elessair 0:f269e3021894 1318 __DSB(); //ensure completion of the invalidation
elessair 0:f269e3021894 1319 __ISB(); //ensure instruction fetch path sees new state
elessair 0:f269e3021894 1320 }
elessair 0:f269e3021894 1321
elessair 0:f269e3021894 1322
elessair 0:f269e3021894 1323 /******************************** L1 cache operations ******************************************************/
elessair 0:f269e3021894 1324
elessair 0:f269e3021894 1325 /** \brief Invalidate the whole I$
elessair 0:f269e3021894 1326
elessair 0:f269e3021894 1327 ICIALLU. Instruction Cache Invalidate All to PoU
elessair 0:f269e3021894 1328 */
elessair 0:f269e3021894 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
elessair 0:f269e3021894 1330 #if 1
elessair 0:f269e3021894 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
elessair 0:f269e3021894 1332 #else
elessair 0:f269e3021894 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
elessair 0:f269e3021894 1334 __ICIALLU = 0;
elessair 0:f269e3021894 1335 #endif
elessair 0:f269e3021894 1336 __DSB(); //ensure completion of the invalidation
elessair 0:f269e3021894 1337 __ISB(); //ensure instruction fetch path sees new I cache state
elessair 0:f269e3021894 1338 }
elessair 0:f269e3021894 1339
elessair 0:f269e3021894 1340 /** \brief Clean D$ by MVA
elessair 0:f269e3021894 1341
elessair 0:f269e3021894 1342 DCCMVAC. Data cache clean by MVA to PoC
elessair 0:f269e3021894 1343 */
elessair 0:f269e3021894 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
elessair 0:f269e3021894 1345 #if 1
elessair 0:f269e3021894 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
elessair 0:f269e3021894 1347 #else
elessair 0:f269e3021894 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
elessair 0:f269e3021894 1349 __DCCMVAC = (uint32_t)va;
elessair 0:f269e3021894 1350 #endif
elessair 0:f269e3021894 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
elessair 0:f269e3021894 1352 }
elessair 0:f269e3021894 1353
elessair 0:f269e3021894 1354 /** \brief Invalidate D$ by MVA
elessair 0:f269e3021894 1355
elessair 0:f269e3021894 1356 DCIMVAC. Data cache invalidate by MVA to PoC
elessair 0:f269e3021894 1357 */
elessair 0:f269e3021894 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
elessair 0:f269e3021894 1359 #if 1
elessair 0:f269e3021894 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
elessair 0:f269e3021894 1361 #else
elessair 0:f269e3021894 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
elessair 0:f269e3021894 1363 __DCIMVAC = (uint32_t)va;
elessair 0:f269e3021894 1364 #endif
elessair 0:f269e3021894 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
elessair 0:f269e3021894 1366 }
elessair 0:f269e3021894 1367
elessair 0:f269e3021894 1368 /** \brief Clean and Invalidate D$ by MVA
elessair 0:f269e3021894 1369
elessair 0:f269e3021894 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
elessair 0:f269e3021894 1371 */
elessair 0:f269e3021894 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
elessair 0:f269e3021894 1373 #if 1
elessair 0:f269e3021894 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
elessair 0:f269e3021894 1375 #else
elessair 0:f269e3021894 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
elessair 0:f269e3021894 1377 __DCCIMVAC = (uint32_t)va;
elessair 0:f269e3021894 1378 #endif
elessair 0:f269e3021894 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
elessair 0:f269e3021894 1380 }
elessair 0:f269e3021894 1381
elessair 0:f269e3021894 1382 /** \brief Clean and Invalidate the entire data or unified cache
elessair 0:f269e3021894 1383
elessair 0:f269e3021894 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
elessair 0:f269e3021894 1385 */
elessair 0:f269e3021894 1386 extern void __v7_all_cache(uint32_t op);
elessair 0:f269e3021894 1387
elessair 0:f269e3021894 1388
elessair 0:f269e3021894 1389 /** \brief Invalidate the whole D$
elessair 0:f269e3021894 1390
elessair 0:f269e3021894 1391 DCISW. Invalidate by Set/Way
elessair 0:f269e3021894 1392 */
elessair 0:f269e3021894 1393
elessair 0:f269e3021894 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
elessair 0:f269e3021894 1395 __v7_all_cache(0);
elessair 0:f269e3021894 1396 }
elessair 0:f269e3021894 1397
elessair 0:f269e3021894 1398 /** \brief Clean the whole D$
elessair 0:f269e3021894 1399
elessair 0:f269e3021894 1400 DCCSW. Clean by Set/Way
elessair 0:f269e3021894 1401 */
elessair 0:f269e3021894 1402
elessair 0:f269e3021894 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
elessair 0:f269e3021894 1404 __v7_all_cache(1);
elessair 0:f269e3021894 1405 }
elessair 0:f269e3021894 1406
elessair 0:f269e3021894 1407 /** \brief Clean and invalidate the whole D$
elessair 0:f269e3021894 1408
elessair 0:f269e3021894 1409 DCCISW. Clean and Invalidate by Set/Way
elessair 0:f269e3021894 1410 */
elessair 0:f269e3021894 1411
elessair 0:f269e3021894 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
elessair 0:f269e3021894 1413 __v7_all_cache(2);
elessair 0:f269e3021894 1414 }
elessair 0:f269e3021894 1415
elessair 0:f269e3021894 1416 #include "core_ca_mmu.h"
elessair 0:f269e3021894 1417
elessair 0:f269e3021894 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
elessair 0:f269e3021894 1419
elessair 0:f269e3021894 1420 #error TASKING Compiler support not implemented for Cortex-A
elessair 0:f269e3021894 1421
elessair 0:f269e3021894 1422 #endif
elessair 0:f269e3021894 1423
elessair 0:f269e3021894 1424 /*@} end of CMSIS_Core_RegAccFunctions */
elessair 0:f269e3021894 1425
elessair 0:f269e3021894 1426
elessair 0:f269e3021894 1427 #endif /* __CORE_CAFUNC_H__ */