L VD / SC16IS740

SC16IS740 I2C to UART Bridge, based on SC16IS750 by Wim Huiskamp https://os.mbed.com/users/wim/code/SC16IS750/

Dependents:   SC16IS740_test

SC16IS740.h@0:db4396ad001f, 2020-08-12 (annotated)

Committer:
elelthvd
Date:
Wed Aug 12 05:16:11 2020 +0000
Revision:
0:db4396ad001f
Renames for use with SC16IS740 on the Mikroe UART I2C/SPI Click board and updated Mbed OS 6 calls.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elelthvd 0:db4396ad001f 1 /* SC16IS740 I2C or SPI to UART bridge
elelthvd 0:db4396ad001f 2 * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods.
elelthvd 0:db4396ad001f 3 * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846
elelthvd 0:db4396ad001f 4 * v0.2 WH, Feb 2014, Added Doxygen Documentation, Added Hardware Reset pin methods.
elelthvd 0:db4396ad001f 5 * v0.3 WH, Dec 2014, Added support for SC16IS752 dual UART.
elelthvd 0:db4396ad001f 6 * v0.4 WH, Dec 2014, Added Repeated Start for I2C readRegister(). Set I2C clock at 100kb/s. Fixed and added some comments.
elelthvd 0:db4396ad001f 7 * v0.5 LVD, Aug 2020, Renames for use with SC16IS740 on the Mikroe UART I2C/SPI Click board and updated Mbed OS 6 calls.
elelthvd 0:db4396ad001f 8 *
elelthvd 0:db4396ad001f 9 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
elelthvd 0:db4396ad001f 10 * and associated documentation files (the "Software"), to deal in the Software without restriction,
elelthvd 0:db4396ad001f 11 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
elelthvd 0:db4396ad001f 12 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
elelthvd 0:db4396ad001f 13 * furnished to do so, subject to the following conditions:
elelthvd 0:db4396ad001f 14 *
elelthvd 0:db4396ad001f 15 * The above copyright notice and this permission notice shall be included in all copies or
elelthvd 0:db4396ad001f 16 * substantial portions of the Software.
elelthvd 0:db4396ad001f 17 *
elelthvd 0:db4396ad001f 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
elelthvd 0:db4396ad001f 19 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
elelthvd 0:db4396ad001f 20 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
elelthvd 0:db4396ad001f 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
elelthvd 0:db4396ad001f 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
elelthvd 0:db4396ad001f 23 */
elelthvd 0:db4396ad001f 24 #ifndef _SC16IS740_H
elelthvd 0:db4396ad001f 25 #define _SC16IS740_H
elelthvd 0:db4396ad001f 26
elelthvd 0:db4396ad001f 27 /**
elelthvd 0:db4396ad001f 28 * Mikroe UART I2C/SPI click
elelthvd 0:db4396ad001f 29 * Uses SC16IS740IPW,112 in SPI mode by default,
elelthvd 0:db4396ad001f 30 * Has HW reset, (740) model does not have GPIO pins
elelthvd 0:db4396ad001f 31 * 1.8432MHz connected to XTAL1
elelthvd 0:db4396ad001f 32 */
elelthvd 0:db4396ad001f 33
elelthvd 0:db4396ad001f 34 #include "mbed.h"
elelthvd 0:db4396ad001f 35 #include "Stream.h"
elelthvd 0:db4396ad001f 36 //#include <SerialBase.h>
elelthvd 0:db4396ad001f 37
elelthvd 0:db4396ad001f 38 //I2C Slaveaddresses A1 A0
elelthvd 0:db4396ad001f 39 #define SC16IS740_SA0 0x90 /* VDD VDD */
elelthvd 0:db4396ad001f 40 #define SC16IS740_SA1 0x92 /* VDD VSS */
elelthvd 0:db4396ad001f 41 #define SC16IS740_SA2 0x94 /* VDD SCL */
elelthvd 0:db4396ad001f 42 #define SC16IS740_SA3 0x95 /* VDD SDA */
elelthvd 0:db4396ad001f 43 #define SC16IS740_SA4 0x98 /* VSS VDD */
elelthvd 0:db4396ad001f 44 #define SC16IS740_SA5 0x9A /* VSS VSS */
elelthvd 0:db4396ad001f 45 #define SC16IS740_SA6 0x9C /* VSS SCL */
elelthvd 0:db4396ad001f 46 #define SC16IS740_SA7 0x9E /* VSS SDA */
elelthvd 0:db4396ad001f 47 #define SC16IS740_SA8 0xA0 /* SCL VDD */
elelthvd 0:db4396ad001f 48 #define SC16IS740_SA9 0xA2 /* SCL VSS */
elelthvd 0:db4396ad001f 49 #define SC16IS740_SA10 0xA4 /* SCL SCL */
elelthvd 0:db4396ad001f 50 #define SC16IS740_SA11 0xA6 /* SCL SDA */
elelthvd 0:db4396ad001f 51 #define SC16IS740_SA12 0xA8 /* SDA VDD */
elelthvd 0:db4396ad001f 52 #define SC16IS740_SA13 0xAA /* SDA VSS */
elelthvd 0:db4396ad001f 53 #define SC16IS740_SA14 0xAC /* SDA SCL */
elelthvd 0:db4396ad001f 54 #define SC16IS740_SA15 0xAE /* SDA SDA */
elelthvd 0:db4396ad001f 55
elelthvd 0:db4396ad001f 56 //Default I2C Slaveaddress
elelthvd 0:db4396ad001f 57 #define SC16IS740_DEFAULT_ADDR SC16IS740_SA0
elelthvd 0:db4396ad001f 58
elelthvd 0:db4396ad001f 59
elelthvd 0:db4396ad001f 60 /** See datasheet section 7.8 for configuring the
elelthvd 0:db4396ad001f 61 * "Programmable baud rate generator"
elelthvd 0:db4396ad001f 62 */
elelthvd 0:db4396ad001f 63 /* https://github.com/sparkfun/WiFly-Shield/blob/master/Libraries/Arduino/src/SpiUart.cpp*/
elelthvd 0:db4396ad001f 64 //#define SC16IS740_XTAL_FREQ 14745600UL /* On-board crystal (New mid-2010 Version) */
elelthvd 0:db4396ad001f 65 /* https://github.com/MikroElektronika/UART_I2C-SPI_click/blob/master/library/__uarti2cspi_driver.c */
elelthvd 0:db4396ad001f 66 #define SC16IS740_XTAL_FREQ 1843200UL /* On-board crystal (Mikroe UART I2C/SPI click) */
elelthvd 0:db4396ad001f 67 #define SC16IS740_PRESCALER_1 1 /* Default prescaler after reset */
elelthvd 0:db4396ad001f 68 #define SC16IS740_PRESCALER_4 4 /* Selectable by setting MCR[7] */
elelthvd 0:db4396ad001f 69 #define SC16IS740_PRESCALER SC16IS740_PRESCALER_1
elelthvd 0:db4396ad001f 70 #define SC16IS740_BAUDRATE_DIVISOR(baud) ((SC16IS740_XTAL_FREQ/SC16IS740_PRESCALER)/(baud*16UL))
elelthvd 0:db4396ad001f 71
elelthvd 0:db4396ad001f 72 //Default baudrate
elelthvd 0:db4396ad001f 73 #define SC16IS740_DEFAULT_BAUDRATE 9600
elelthvd 0:db4396ad001f 74
elelthvd 0:db4396ad001f 75
elelthvd 0:db4396ad001f 76 /** See section 8.3 of the datasheet for definitions
elelthvd 0:db4396ad001f 77 * of bits in the FIFO Control Register (FCR)
elelthvd 0:db4396ad001f 78 */
elelthvd 0:db4396ad001f 79 #define FCR_RX_IRQ_60 (3 << 6)
elelthvd 0:db4396ad001f 80 #define FCR_RX_IRQ_56 (2 << 6)
elelthvd 0:db4396ad001f 81 #define FCR_RX_IRQ_16 (1 << 6)
elelthvd 0:db4396ad001f 82 #define FCR_RX_IRQ_8 (0 << 6)
elelthvd 0:db4396ad001f 83 //TX Level only accessible when EFR[4] is set
elelthvd 0:db4396ad001f 84 #define FCR_TX_IRQ_56 (3 << 4)
elelthvd 0:db4396ad001f 85 #define FCR_TX_IRQ_32 (2 << 4)
elelthvd 0:db4396ad001f 86 #define FCR_TX_IRQ_16 (1 << 4)
elelthvd 0:db4396ad001f 87 #define FCR_TX_IRQ_8 (0 << 4)
elelthvd 0:db4396ad001f 88 //#define FCR_RESERVED (1 << 3)
elelthvd 0:db4396ad001f 89 #define FCR_TX_FIFO_RST (1 << 2)
elelthvd 0:db4396ad001f 90 #define FCR_RX_FIFO_RST (1 << 1)
elelthvd 0:db4396ad001f 91 #define FCR_ENABLE_FIFO (1 << 0)
elelthvd 0:db4396ad001f 92
elelthvd 0:db4396ad001f 93 //FIFO size
elelthvd 0:db4396ad001f 94 #define SC16IS740_FIFO_RX 64
elelthvd 0:db4396ad001f 95 #define SC16IS740_FIFO_TX 64
elelthvd 0:db4396ad001f 96
elelthvd 0:db4396ad001f 97
elelthvd 0:db4396ad001f 98 /** See section 8.4 of the datasheet for definitions
elelthvd 0:db4396ad001f 99 * of bits in the Line Control Register (LCR)
elelthvd 0:db4396ad001f 100 */
elelthvd 0:db4396ad001f 101 #define LCR_BITS5 0x00
elelthvd 0:db4396ad001f 102 #define LCR_BITS6 0x01
elelthvd 0:db4396ad001f 103 #define LCR_BITS7 0x02
elelthvd 0:db4396ad001f 104 #define LCR_BITS8 0x03
elelthvd 0:db4396ad001f 105
elelthvd 0:db4396ad001f 106 #define LCR_BITS1 0x00
elelthvd 0:db4396ad001f 107 #define LCR_BITS2 0x04
elelthvd 0:db4396ad001f 108
elelthvd 0:db4396ad001f 109 #define LCR_NONE 0x00
elelthvd 0:db4396ad001f 110 #define LCR_ODD 0x08
elelthvd 0:db4396ad001f 111 #define LCR_EVEN 0x18
elelthvd 0:db4396ad001f 112 #define LCR_FORCED1 0x28
elelthvd 0:db4396ad001f 113 #define LCR_FORCED0 0x38
elelthvd 0:db4396ad001f 114
elelthvd 0:db4396ad001f 115 #define LCR_BRK_ENA 0x40
elelthvd 0:db4396ad001f 116 #define LCR_BRK_DIS 0x00
elelthvd 0:db4396ad001f 117
elelthvd 0:db4396ad001f 118 #define LCR_ENABLE_DIV 0x80
elelthvd 0:db4396ad001f 119 #define LCR_DISABLE_DIV 0x00
elelthvd 0:db4396ad001f 120
elelthvd 0:db4396ad001f 121 #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF)
elelthvd 0:db4396ad001f 122
elelthvd 0:db4396ad001f 123
elelthvd 0:db4396ad001f 124 /** See section 8.5 of the datasheet for definitions
elelthvd 0:db4396ad001f 125 * of bits in the Line status register (LSR)
elelthvd 0:db4396ad001f 126 */
elelthvd 0:db4396ad001f 127 #define LSR_DR (0x01) /* Data ready in RX FIFO */
elelthvd 0:db4396ad001f 128 #define LSR_OE (0x02) /* Overrun error */
elelthvd 0:db4396ad001f 129 #define LSR_PE (0x04) /* Parity error */
elelthvd 0:db4396ad001f 130 #define LSR_FE (0x08) /* Framing error */
elelthvd 0:db4396ad001f 131 #define LSR_BI (0x10) /* Break interrupt */
elelthvd 0:db4396ad001f 132 #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty) */
elelthvd 0:db4396ad001f 133 #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */
elelthvd 0:db4396ad001f 134 #define LSR_FFE (0x80) /* At least one PE, FE or BI in FIFO */
elelthvd 0:db4396ad001f 135
elelthvd 0:db4396ad001f 136
elelthvd 0:db4396ad001f 137 /** See section 8.6 of the datasheet for definitions
elelthvd 0:db4396ad001f 138 * of bits in the Modem control register (MCR)
elelthvd 0:db4396ad001f 139 */
elelthvd 0:db4396ad001f 140 #define MCR_MDTR (1 << 0) /* Data Terminal Ready pin control. */
elelthvd 0:db4396ad001f 141 #define MCR_MRTS (1 << 1) /* Request to Send pin control when not in Auto RTS mode.*/
elelthvd 0:db4396ad001f 142 //MCR[2] only accessible when EFR[4] is set
elelthvd 0:db4396ad001f 143 #define MCR_ENABLE_TCR_TLR (1 << 2)
elelthvd 0:db4396ad001f 144 #define MCR_ENABLE_LOOPBACK (1 << 4)
elelthvd 0:db4396ad001f 145 //MCR[7:5] only accessible when EFR[4] is set
elelthvd 0:db4396ad001f 146 #define MCR_ENABLE_XON_ANY_CHAR (1 << 5)
elelthvd 0:db4396ad001f 147 #define MCR_ENABLE_IRDA (1 << 6)
elelthvd 0:db4396ad001f 148 #define MCR_PRESCALE_1 (0 << 7)
elelthvd 0:db4396ad001f 149 #define MCR_PRESCALE_4 (1 << 7)
elelthvd 0:db4396ad001f 150
elelthvd 0:db4396ad001f 151
elelthvd 0:db4396ad001f 152 /** See section 8.7 of the datasheet for definitions
elelthvd 0:db4396ad001f 153 * of bits in the Modem status register (MSR)
elelthvd 0:db4396ad001f 154 */
elelthvd 0:db4396ad001f 155 #define MSR_DCTS (1 << 0) /* Delta CTS - CTS Changed State */
elelthvd 0:db4396ad001f 156 #define MSR_DDSR (1 << 1) /* Delta DSR - DSR Changed State */
elelthvd 0:db4396ad001f 157 #define MSR_DDI (1 << 2) /* Delta DI - DI Changed State */
elelthvd 0:db4396ad001f 158 #define MSR_DCD (1 << 3) /* Delta CD - CD Changed State */
elelthvd 0:db4396ad001f 159 #define MSR_CTS (1 << 4) /* CTS State - Complement of NCTS pin */
elelthvd 0:db4396ad001f 160 //MSR[7:5] only accessible when GPIO[7:4] are set as modem pin
elelthvd 0:db4396ad001f 161 #define MSR_DSR (1 << 5) /* DSR State - Complement of NDSR pin */
elelthvd 0:db4396ad001f 162 #define MSR_RI (1 << 6) /* RI State - Complement of NRI pin */
elelthvd 0:db4396ad001f 163 #define MSR_CD (1 << 7) /* CD State - Complement of NCD pin */
elelthvd 0:db4396ad001f 164
elelthvd 0:db4396ad001f 165
elelthvd 0:db4396ad001f 166 /** See section 8.8 of the datasheet for definitions
elelthvd 0:db4396ad001f 167 * of bits in the Interrupt enable register (IER)
elelthvd 0:db4396ad001f 168 */
elelthvd 0:db4396ad001f 169 #define IER_ERHRI (0x01) /* Enable received data available interrupt */
elelthvd 0:db4396ad001f 170 #define IER_ETHRI (0x02) /* Enable transmitter holding register empty interrupt */
elelthvd 0:db4396ad001f 171 #define IER_ELSI (0x04) /* Enable receiver line status interrupt */
elelthvd 0:db4396ad001f 172 #define IER_EMSI (0x08) /* Enable modem status interrupt */
elelthvd 0:db4396ad001f 173 //IER[7:5] only accessible when EFR[4] is set
elelthvd 0:db4396ad001f 174 #define IER_SLEEP (0x10) /* Enable sleep mode */
elelthvd 0:db4396ad001f 175 #define IER_XOFFI (0x20) /* Enable XOFF interrupt */
elelthvd 0:db4396ad001f 176 #define IER_RTSI (0x40) /* Enable RTS interrupt */
elelthvd 0:db4396ad001f 177 #define IER_CTSI (0x80) /* Enable CTS interrupt */
elelthvd 0:db4396ad001f 178
elelthvd 0:db4396ad001f 179
elelthvd 0:db4396ad001f 180 /** See section 8.9 of the datasheet for definitions
elelthvd 0:db4396ad001f 181 * of bits in the Interrupt identification register (IIR)
elelthvd 0:db4396ad001f 182 * Bit 0 is set to 0 if an IRQ is pending.
elelthvd 0:db4396ad001f 183 * Bits 1..5 are used to identify the IRQ source.
elelthvd 0:db4396ad001f 184 */
elelthvd 0:db4396ad001f 185 #define IIR_IRQ_NOT_PENDING (0x01) /* IRQ Not Pending */
elelthvd 0:db4396ad001f 186 #define IIR_TX_EMPTY (0x02) /* THR Interrupt */
elelthvd 0:db4396ad001f 187 #define IIR_RX_DATA (0x04) /* RHR Interrupt */
elelthvd 0:db4396ad001f 188 #define IIR_RX_ERROR (0x06) /* Line Status Error Interrupt */
elelthvd 0:db4396ad001f 189 #define IIR_RX_TIMEOUT (0x0B) /* RX Timeout Interrupt */
elelthvd 0:db4396ad001f 190 #define IIR_RX_XOFF (0x10) /* RX XOff Interrupt */
elelthvd 0:db4396ad001f 191 #define IIR_DCTS_DRTS (0x20) /* Delta CTS or RTS Interrupt */
elelthvd 0:db4396ad001f 192 #define IIR_DIO (0x30) /* Delta GPIO pin Interrupt */
elelthvd 0:db4396ad001f 193
elelthvd 0:db4396ad001f 194 #define IIR_BITS_USED (0x07)
elelthvd 0:db4396ad001f 195
elelthvd 0:db4396ad001f 196
elelthvd 0:db4396ad001f 197 /** See section 8.10 of the datasheet for definitions
elelthvd 0:db4396ad001f 198 * of bits in the Enhanced Features Register (EFR)
elelthvd 0:db4396ad001f 199 */
elelthvd 0:db4396ad001f 200 #define EFR_ENABLE_CTS (1 << 7)
elelthvd 0:db4396ad001f 201 #define EFR_ENABLE_RTS (1 << 6)
elelthvd 0:db4396ad001f 202 #define EFR_ENABLE_XOFF2_CHAR_DETECT (1 << 5)
elelthvd 0:db4396ad001f 203 #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4)
elelthvd 0:db4396ad001f 204 // EFR[3:0] are used to define Software Flow Control mode
elelthvd 0:db4396ad001f 205 // See section 7.3
elelthvd 0:db4396ad001f 206 #define EFR_DISABLE_TX_FLOW_CTRL (0x0 << 2)
elelthvd 0:db4396ad001f 207 #define EFR_TX_XON2_XOFF2 (0x1 << 2)
elelthvd 0:db4396ad001f 208 #define EFR_TX_XON1_XOFF1 (0x2 << 2)
elelthvd 0:db4396ad001f 209 #define EFR_TX_XON2_1_XOFF2_1 (0x3 << 2)
elelthvd 0:db4396ad001f 210
elelthvd 0:db4396ad001f 211 #define EFR_DISABLE_RX_FLOW_CTRL (0x0 << 0)
elelthvd 0:db4396ad001f 212 #define EFR_RX_XON2_XOFF2 (0x1 << 0)
elelthvd 0:db4396ad001f 213 #define EFR_RX_XON1_XOFF1 (0x2 << 0)
elelthvd 0:db4396ad001f 214 #define EFR_RX_XON2_1_XOFF2_1 (0x3 << 0)
elelthvd 0:db4396ad001f 215
elelthvd 0:db4396ad001f 216 #define EFR_TX_XON2_XOFF2_RX_FLOW (0x1 << 2) | (0x3 << 0)
elelthvd 0:db4396ad001f 217 #define EFR_TX_XON1_XOFF1_RX_FLOW (0x2 << 2) | (0x3 << 0)
elelthvd 0:db4396ad001f 218 #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW (0x3 << 2) | (0x3 << 0)
elelthvd 0:db4396ad001f 219
elelthvd 0:db4396ad001f 220
elelthvd 0:db4396ad001f 221
elelthvd 0:db4396ad001f 222 /** See section 8.12 of the datasheet for definitions
elelthvd 0:db4396ad001f 223 * of bits in the Transmission Control Register (TCR)
elelthvd 0:db4396ad001f 224 * These levels control when RTS is asserted or de-asserted and auto RTS is enabled. Note that XON/XOFF is not supported in this lib.
elelthvd 0:db4396ad001f 225 * Trigger level to halt transmission to the device : 0..15 (meaning 0-60 with a granularity of 4)
elelthvd 0:db4396ad001f 226 * RTS is de-asserted when RX FIFO is above the set trigger level (i.e. buffer is getting full)
elelthvd 0:db4396ad001f 227 * Trigger level to resume transmission to the device : 0..15 (meaning 0-60 with a granularity of 4)
elelthvd 0:db4396ad001f 228 * RTS is asserted again when RX FIFO drops below the set trigger level (i.e. buffer has room again)
elelthvd 0:db4396ad001f 229 */
elelthvd 0:db4396ad001f 230 #define TCR_HALT_DEFAULT (0x0E)
elelthvd 0:db4396ad001f 231 #define TCR_RESUME_DEFAULT (0x08)
elelthvd 0:db4396ad001f 232
elelthvd 0:db4396ad001f 233 /** See section 8.12 of the datasheet for definitions
elelthvd 0:db4396ad001f 234 * Note: The device will stop transmissions from the TX FIFO when CTS is de-asserted by external receiver and
elelthvd 0:db4396ad001f 235 * auto CTS is enabled. Note that XON/XOFF is not supported in this lib.
elelthvd 0:db4396ad001f 236 */
elelthvd 0:db4396ad001f 237
elelthvd 0:db4396ad001f 238
elelthvd 0:db4396ad001f 239 /** See section 7.5 and 8.13 of the datasheet for definitions
elelthvd 0:db4396ad001f 240 * of bits in the Trigger Level Register (TLR) control when an IRQ is generated.
elelthvd 0:db4396ad001f 241 * Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4)
elelthvd 0:db4396ad001f 242 * IRQ when TX FIFO is above the set trigger level (i.e. buffer is getting full)
elelthvd 0:db4396ad001f 243 * Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4)
elelthvd 0:db4396ad001f 244 * IRQ when RX FIFO is above the set trigger level (i.e. data is waiting to be read)
elelthvd 0:db4396ad001f 245 */
elelthvd 0:db4396ad001f 246 #define TLR_TX_DEFAULT (0x0E)
elelthvd 0:db4396ad001f 247 #define TLR_RX_DEFAULT (0x04)
elelthvd 0:db4396ad001f 248
elelthvd 0:db4396ad001f 249
elelthvd 0:db4396ad001f 250 /**
elelthvd 0:db4396ad001f 251 * See section 8.16, 8.17, 8.18 of the datasheet for definitions
elelthvd 0:db4396ad001f 252 * of bits in the IO Direction (IODIR), IO State (IOSTATE) and IO Interrupt Enable register (IOINTENA)
elelthvd 0:db4396ad001f 253 *
elelthvd 0:db4396ad001f 254 * Basically a direct mapping of register bits to GPIO pin.
elelthvd 0:db4396ad001f 255 */
elelthvd 0:db4396ad001f 256
elelthvd 0:db4396ad001f 257
elelthvd 0:db4396ad001f 258 /**
elelthvd 0:db4396ad001f 259 * See section 8.19 of the datasheet for definitions
elelthvd 0:db4396ad001f 260 * of bits in the IO Control register (IOC)
elelthvd 0:db4396ad001f 261 *
elelthvd 0:db4396ad001f 262 * Bit 0 is set to 0 to enable latch of IO inputs.
elelthvd 0:db4396ad001f 263 * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST.
elelthvd 0:db4396ad001f 264 * Bit 2 is set to enable software reset.
elelthvd 0:db4396ad001f 265 */
elelthvd 0:db4396ad001f 266 #define IOC_ENA_LATCH (0x01)
elelthvd 0:db4396ad001f 267 #define IOC_ENA_MODEM (0x02) /* Set GPIO[7:4] pins to modem functions */
elelthvd 0:db4396ad001f 268 #define IOC_SW_RST (0x04)
elelthvd 0:db4396ad001f 269
elelthvd 0:db4396ad001f 270
elelthvd 0:db4396ad001f 271 /**
elelthvd 0:db4396ad001f 272 * See section 8.20 of the datasheet for definitions
elelthvd 0:db4396ad001f 273 * of bits in the Extra Features Control register (EFCR)
elelthvd 0:db4396ad001f 274 *
elelthvd 0:db4396ad001f 275 */
elelthvd 0:db4396ad001f 276 #define EFCR_ENA_RS485 (0x01)
elelthvd 0:db4396ad001f 277 #define EFCR_DIS_RX (0x02)
elelthvd 0:db4396ad001f 278 #define EFCR_DIS_TX (0x04)
elelthvd 0:db4396ad001f 279 #define EFCR_ENA_TX_RTS (0x10)
elelthvd 0:db4396ad001f 280 #define EFCR_INV_RTS_RS485 (0x20)
elelthvd 0:db4396ad001f 281 #define EFCR_ENA_IRDA (0x80)
elelthvd 0:db4396ad001f 282
elelthvd 0:db4396ad001f 283 // See Chapter 11 of datasheet
elelthvd 0:db4396ad001f 284 #define SPI_READ_MODE_FLAG (0x80)
elelthvd 0:db4396ad001f 285
elelthvd 0:db4396ad001f 286
elelthvd 0:db4396ad001f 287 /** Abstract class SC16IS740 for a bridge between either SPI or I2C and a Serial port
elelthvd 0:db4396ad001f 288 *
elelthvd 0:db4396ad001f 289 * Supports both SPI and I2C interfaces through derived classes
elelthvd 0:db4396ad001f 290 *
elelthvd 0:db4396ad001f 291 * @code
elelthvd 0:db4396ad001f 292 *
elelthvd 0:db4396ad001f 293 * @endcode
elelthvd 0:db4396ad001f 294 */
elelthvd 0:db4396ad001f 295 //class SC16IS740 {
elelthvd 0:db4396ad001f 296 //class SC16IS740 : public SerialBase, public Stream { // Wrong, Serialbase can not be constructed for NC,NC
elelthvd 0:db4396ad001f 297 class SC16IS740 : public Stream {
elelthvd 0:db4396ad001f 298 public:
elelthvd 0:db4396ad001f 299
elelthvd 0:db4396ad001f 300 // SC16IS740 Register definitions (shifted to align)
elelthvd 0:db4396ad001f 301 enum RegisterName {
elelthvd 0:db4396ad001f 302 /*
elelthvd 0:db4396ad001f 303 * 16750 addresses. Registers accessed when LCR[7] = 0.
elelthvd 0:db4396ad001f 304 */
elelthvd 0:db4396ad001f 305 RHR = 0x00 << 3, /* Rx buffer register - Read access */
elelthvd 0:db4396ad001f 306 THR = 0x00 << 3, /* Tx holding register - Write access */
elelthvd 0:db4396ad001f 307 IER = 0x01 << 3, /* Interrupt enable reg - RD/WR access */
elelthvd 0:db4396ad001f 308
elelthvd 0:db4396ad001f 309 /*
elelthvd 0:db4396ad001f 310 * 16750 addresses. Registers accessed when LCR[7] = 1.
elelthvd 0:db4396ad001f 311 */
elelthvd 0:db4396ad001f 312 DLL = 0x00 << 3, /* Divisor latch (LSB) - RD/WR access */
elelthvd 0:db4396ad001f 313 DLH = 0x01 << 3, /* Divisor latch (MSB) - RD/WR access */
elelthvd 0:db4396ad001f 314
elelthvd 0:db4396ad001f 315 /*
elelthvd 0:db4396ad001f 316 * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF.
elelthvd 0:db4396ad001f 317 * Bit 5 of the FCR register is accessed when LCR[7] = 1.
elelthvd 0:db4396ad001f 318 */
elelthvd 0:db4396ad001f 319 IIR = 0x02 << 3, /* Interrupt id. register - Read only */
elelthvd 0:db4396ad001f 320 FCR = 0x02 << 3, /* FIFO control register - Write only */
elelthvd 0:db4396ad001f 321 /*
elelthvd 0:db4396ad001f 322 * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF.
elelthvd 0:db4396ad001f 323 */
elelthvd 0:db4396ad001f 324 EFR = 0x02 << 3, /* Enhanced features reg - RD/WR access */
elelthvd 0:db4396ad001f 325
elelthvd 0:db4396ad001f 326 /*
elelthvd 0:db4396ad001f 327 * 16750 addresses.
elelthvd 0:db4396ad001f 328 */
elelthvd 0:db4396ad001f 329 LCR = 0x03 << 3, /* Line control register - RD/WR access */
elelthvd 0:db4396ad001f 330 /*
elelthvd 0:db4396ad001f 331 * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF.
elelthvd 0:db4396ad001f 332 * Bit 7 of the MCR register is accessed when EFR[4] = 1.
elelthvd 0:db4396ad001f 333 */
elelthvd 0:db4396ad001f 334 MCR = 0x04 << 3, /* Modem control register - RD/WR access */
elelthvd 0:db4396ad001f 335 LSR = 0x05 << 3, /* Line status register - Read only */
elelthvd 0:db4396ad001f 336
elelthvd 0:db4396ad001f 337 /*
elelthvd 0:db4396ad001f 338 * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF.
elelthvd 0:db4396ad001f 339 * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0.
elelthvd 0:db4396ad001f 340 */
elelthvd 0:db4396ad001f 341 MSR = 0x06 << 3, /* Modem status register - Read only */
elelthvd 0:db4396ad001f 342 SPR = 0x07 << 3, /* Scratchpad register - RD/WR access */
elelthvd 0:db4396ad001f 343 /*
elelthvd 0:db4396ad001f 344 * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF.
elelthvd 0:db4396ad001f 345 * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1.
elelthvd 0:db4396ad001f 346 */
elelthvd 0:db4396ad001f 347 TCR = 0x06 << 3, /* Transmission control register - RD/WR access */
elelthvd 0:db4396ad001f 348 TLR = 0x07 << 3, /* Trigger level register - RD/WR access */
elelthvd 0:db4396ad001f 349
elelthvd 0:db4396ad001f 350 /*
elelthvd 0:db4396ad001f 351 * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF.
elelthvd 0:db4396ad001f 352 */
elelthvd 0:db4396ad001f 353 XON1 = 0x04 << 3, /* XON1 register - RD/WR access */
elelthvd 0:db4396ad001f 354 XON2 = 0x05 << 3, /* XON2 register - RD/WR access */
elelthvd 0:db4396ad001f 355 XOFF1 = 0x06 << 3, /* XOFF1 register - RD/WR access */
elelthvd 0:db4396ad001f 356 XOFF2 = 0x07 << 3, /* XOFF2 register - RD/WR access */
elelthvd 0:db4396ad001f 357
elelthvd 0:db4396ad001f 358 /*
elelthvd 0:db4396ad001f 359 * 16750 addresses.
elelthvd 0:db4396ad001f 360 */
elelthvd 0:db4396ad001f 361 TXLVL = 0x08 << 3, /* TX FIFO Level register - Read only */
elelthvd 0:db4396ad001f 362 RXLVL = 0x09 << 3, /* RX FIFO Level register - Read only */
elelthvd 0:db4396ad001f 363 IODIR = 0x0A << 3, /* IO Pin Direction reg - RD/WR access */
elelthvd 0:db4396ad001f 364 IOSTATE = 0x0B << 3, /* IO Pin State reg - RD/WR access */
elelthvd 0:db4396ad001f 365 IOINTENA = 0x0C << 3, /* IO Interrupt Enable - RD/WR access */
elelthvd 0:db4396ad001f 366 // reserved = 0x0D << 3,
elelthvd 0:db4396ad001f 367 IOCTRL = 0x0E << 3, /* IO Control register - RD/WR access */
elelthvd 0:db4396ad001f 368 EFCR = 0x0F << 3, /* Extra features reg - RD/WR access */
elelthvd 0:db4396ad001f 369
elelthvd 0:db4396ad001f 370 } ;
elelthvd 0:db4396ad001f 371
elelthvd 0:db4396ad001f 372
elelthvd 0:db4396ad001f 373 // This enum used to be part of SerialBase class (access via SerialBase.h).
elelthvd 0:db4396ad001f 374 // It seems not be supported anymore. The enums for Parity have moved to Serial now..
elelthvd 0:db4396ad001f 375 enum Flow {
elelthvd 0:db4396ad001f 376 Disabled = 0,
elelthvd 0:db4396ad001f 377 RTS,
elelthvd 0:db4396ad001f 378 CTS,
elelthvd 0:db4396ad001f 379 RTSCTS
elelthvd 0:db4396ad001f 380 };
elelthvd 0:db4396ad001f 381
elelthvd 0:db4396ad001f 382 // SC16IS752 Channel definitions (shifted to align)
elelthvd 0:db4396ad001f 383 enum ChannelName {
elelthvd 0:db4396ad001f 384 Channel_A = 0x00 << 1,
elelthvd 0:db4396ad001f 385 Channel_B = 0x01 << 1
elelthvd 0:db4396ad001f 386 };
elelthvd 0:db4396ad001f 387
elelthvd 0:db4396ad001f 388 // SC16IS740 configuration register values
elelthvd 0:db4396ad001f 389 // Several configuration registers are write-only. Need to save values to allow restoring.
elelthvd 0:db4396ad001f 390 struct SC16IS740_cfg {
elelthvd 0:db4396ad001f 391 char baudrate;
elelthvd 0:db4396ad001f 392 char dataformat;
elelthvd 0:db4396ad001f 393 char flowctrl;
elelthvd 0:db4396ad001f 394 char fifoformat;
elelthvd 0:db4396ad001f 395 bool fifoenable;
elelthvd 0:db4396ad001f 396 };
elelthvd 0:db4396ad001f 397
elelthvd 0:db4396ad001f 398
elelthvd 0:db4396ad001f 399 /** Determine if there is a character available to read.
elelthvd 0:db4396ad001f 400 * This is data that's already arrived and stored in the receive
elelthvd 0:db4396ad001f 401 * buffer (which holds 64 chars).
elelthvd 0:db4396ad001f 402 *
elelthvd 0:db4396ad001f 403 * @return 1 if there is a character available to read, 0 otherwise
elelthvd 0:db4396ad001f 404 */
elelthvd 0:db4396ad001f 405 int readable();
elelthvd 0:db4396ad001f 406
elelthvd 0:db4396ad001f 407 /** Determine how many characters are available to read.
elelthvd 0:db4396ad001f 408 * This is data that's already arrived and stored in the receive
elelthvd 0:db4396ad001f 409 * buffer (which holds 64 chars).
elelthvd 0:db4396ad001f 410 *
elelthvd 0:db4396ad001f 411 * @return int Characters available to read
elelthvd 0:db4396ad001f 412 */
elelthvd 0:db4396ad001f 413 int readableCount();
elelthvd 0:db4396ad001f 414
elelthvd 0:db4396ad001f 415 /** Determine if there is space available to write a character.
elelthvd 0:db4396ad001f 416 * @return 1 if there is a space for a character to write, 0 otherwise
elelthvd 0:db4396ad001f 417 */
elelthvd 0:db4396ad001f 418 int writable();
elelthvd 0:db4396ad001f 419
elelthvd 0:db4396ad001f 420
elelthvd 0:db4396ad001f 421 /** Determine how much space available for writing characters.
elelthvd 0:db4396ad001f 422 * This considers data that's already stored in the transmit
elelthvd 0:db4396ad001f 423 * buffer (which holds 64 chars).
elelthvd 0:db4396ad001f 424 *
elelthvd 0:db4396ad001f 425 * @return int character space available to write
elelthvd 0:db4396ad001f 426 */
elelthvd 0:db4396ad001f 427 int writableCount();
elelthvd 0:db4396ad001f 428
elelthvd 0:db4396ad001f 429 /**
elelthvd 0:db4396ad001f 430 * Read char from UART Bridge.
elelthvd 0:db4396ad001f 431 * Acts in the same manner as 'Serial.read()'.
elelthvd 0:db4396ad001f 432 * @param none
elelthvd 0:db4396ad001f 433 * @return char read or -1 if no data available.
elelthvd 0:db4396ad001f 434 */
elelthvd 0:db4396ad001f 435 int getc();
elelthvd 0:db4396ad001f 436
elelthvd 0:db4396ad001f 437 /**
elelthvd 0:db4396ad001f 438 * Write char to UART Bridge. Blocking when no free space in FIFO
elelthvd 0:db4396ad001f 439 * @param value char to be written
elelthvd 0:db4396ad001f 440 * @return value written
elelthvd 0:db4396ad001f 441 */
elelthvd 0:db4396ad001f 442 int putc(int c);
elelthvd 0:db4396ad001f 443
elelthvd 0:db4396ad001f 444
elelthvd 0:db4396ad001f 445 #if DOXYGEN_ONLY
elelthvd 0:db4396ad001f 446 /** Write a formatted string to the UART Bridge. Blocking when no free space in FIFO
elelthvd 0:db4396ad001f 447 *
elelthvd 0:db4396ad001f 448 * @param format A printf-style format string, followed by the
elelthvd 0:db4396ad001f 449 * variables to use in formatting the string.
elelthvd 0:db4396ad001f 450 */
elelthvd 0:db4396ad001f 451 int printf(const char* format, ...);
elelthvd 0:db4396ad001f 452 #endif
elelthvd 0:db4396ad001f 453
elelthvd 0:db4396ad001f 454
elelthvd 0:db4396ad001f 455 /**
elelthvd 0:db4396ad001f 456 * Write char string to UART Bridge. Blocking when no free space in FIFO
elelthvd 0:db4396ad001f 457 * @param *str char string to be written
elelthvd 0:db4396ad001f 458 * @return none
elelthvd 0:db4396ad001f 459 */
elelthvd 0:db4396ad001f 460 void writeString(const char *str);
elelthvd 0:db4396ad001f 461
elelthvd 0:db4396ad001f 462
elelthvd 0:db4396ad001f 463 /**
elelthvd 0:db4396ad001f 464 * Write byte array to UART Bridge. Blocking when no free space in FIFO
elelthvd 0:db4396ad001f 465 * @param *data byte array to be written
elelthvd 0:db4396ad001f 466 * @param len number of bytes to write
elelthvd 0:db4396ad001f 467 * @return none
elelthvd 0:db4396ad001f 468 */
elelthvd 0:db4396ad001f 469 void writeBytes(const char *data, int len);
elelthvd 0:db4396ad001f 470
elelthvd 0:db4396ad001f 471 /** Set baudrate of the serial port.
elelthvd 0:db4396ad001f 472 * @param baud integer baudrate (4800, 9600 etc)
elelthvd 0:db4396ad001f 473 * @return none
elelthvd 0:db4396ad001f 474 */
elelthvd 0:db4396ad001f 475 void baud(int baudrate = SC16IS740_DEFAULT_BAUDRATE);
elelthvd 0:db4396ad001f 476
elelthvd 0:db4396ad001f 477 /** Set the transmission format used by the serial port.
elelthvd 0:db4396ad001f 478 * @param bits The number of bits in a word (5-8; default = 8)
elelthvd 0:db4396ad001f 479 * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
elelthvd 0:db4396ad001f 480 * @param stop_bits The number of stop bits (1 or 2; default = 1)
elelthvd 0:db4396ad001f 481 * @return none
elelthvd 0:db4396ad001f 482 */
elelthvd 0:db4396ad001f 483 void format(int bits=8, BufferedSerial::Parity parity=BufferedSerial::None, int stop_bits=1);
elelthvd 0:db4396ad001f 484
elelthvd 0:db4396ad001f 485 #if(0)
elelthvd 0:db4396ad001f 486 /** Attach a function to call whenever a serial interrupt is generated
elelthvd 0:db4396ad001f 487 *
elelthvd 0:db4396ad001f 488 * @param fptr A pointer to a void function, or 0 to set as none
elelthvd 0:db4396ad001f 489 * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
elelthvd 0:db4396ad001f 490 */
elelthvd 0:db4396ad001f 491 void attach(void (*fptr)(void), IrqType type=RxIrq);
elelthvd 0:db4396ad001f 492
elelthvd 0:db4396ad001f 493 /** Attach a member function to call whenever a serial interrupt is generated
elelthvd 0:db4396ad001f 494 *
elelthvd 0:db4396ad001f 495 * @param tptr pointer to the object to call the member function on
elelthvd 0:db4396ad001f 496 * @param mptr pointer to the member function to be called
elelthvd 0:db4396ad001f 497 * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
elelthvd 0:db4396ad001f 498 * @return none
elelthvd 0:db4396ad001f 499 */
elelthvd 0:db4396ad001f 500 template<typename T>
elelthvd 0:db4396ad001f 501 void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
elelthvd 0:db4396ad001f 502 if((mptr != NULL) && (tptr != NULL)) {
elelthvd 0:db4396ad001f 503 _irq[type].attach(tptr, mptr);
elelthvd 0:db4396ad001f 504 serial_irq_set(&_serial, (SerialIrq)type, 1);
elelthvd 0:db4396ad001f 505 }
elelthvd 0:db4396ad001f 506 }
elelthvd 0:db4396ad001f 507 #endif
elelthvd 0:db4396ad001f 508
elelthvd 0:db4396ad001f 509 /** Generate a break condition on the serial line
elelthvd 0:db4396ad001f 510 * @param none
elelthvd 0:db4396ad001f 511 * @return none
elelthvd 0:db4396ad001f 512 */
elelthvd 0:db4396ad001f 513 void send_break();
elelthvd 0:db4396ad001f 514
elelthvd 0:db4396ad001f 515
elelthvd 0:db4396ad001f 516 /** Set a break condition on the serial line
elelthvd 0:db4396ad001f 517 * @param enable break condition
elelthvd 0:db4396ad001f 518 * @return none
elelthvd 0:db4396ad001f 519 */
elelthvd 0:db4396ad001f 520 void set_break(bool enable=false);
elelthvd 0:db4396ad001f 521
elelthvd 0:db4396ad001f 522
elelthvd 0:db4396ad001f 523 /** Set the flow control type on the serial port
elelthvd 0:db4396ad001f 524 * Added for compatibility with Serial Class.
elelthvd 0:db4396ad001f 525 * SC16IS740 supports only Flow, Pins can not be selected.
elelthvd 0:db4396ad001f 526 * This method sets hardware flow control levels. SC16IS740 supports XON/XOFF, but this is not implemented.
elelthvd 0:db4396ad001f 527 *
elelthvd 0:db4396ad001f 528 * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
elelthvd 0:db4396ad001f 529 * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
elelthvd 0:db4396ad001f 530 * @param flow2 the second flow control pin (CTS for RTSCTS)
elelthvd 0:db4396ad001f 531 * @return none
elelthvd 0:db4396ad001f 532 */
elelthvd 0:db4396ad001f 533 void set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC);
elelthvd 0:db4396ad001f 534
elelthvd 0:db4396ad001f 535
elelthvd 0:db4396ad001f 536 /** Set the RX FIFO flow control levels
elelthvd 0:db4396ad001f 537 * This method sets hardware flow control levels. SC16IS740 supports XON/XOFF, but this is not implemented.
elelthvd 0:db4396ad001f 538 * Should be called BEFORE Auto RTS is enabled.
elelthvd 0:db4396ad001f 539 *
elelthvd 0:db4396ad001f 540 * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4)
elelthvd 0:db4396ad001f 541 * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4)
elelthvd 0:db4396ad001f 542 * @return none
elelthvd 0:db4396ad001f 543 */
elelthvd 0:db4396ad001f 544 void set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT);
elelthvd 0:db4396ad001f 545
elelthvd 0:db4396ad001f 546
elelthvd 0:db4396ad001f 547 /** Set the Modem Control register
elelthvd 0:db4396ad001f 548 * This method sets prescaler, enables TCR and TLR
elelthvd 0:db4396ad001f 549 *
elelthvd 0:db4396ad001f 550 * @param none
elelthvd 0:db4396ad001f 551 * @return none
elelthvd 0:db4396ad001f 552 */
elelthvd 0:db4396ad001f 553 void set_modem_control();
elelthvd 0:db4396ad001f 554
elelthvd 0:db4396ad001f 555
elelthvd 0:db4396ad001f 556 /**
elelthvd 0:db4396ad001f 557 * Check that UART is connected and operational.
elelthvd 0:db4396ad001f 558 * @param none
elelthvd 0:db4396ad001f 559 * @return bool true when connected, false otherwise
elelthvd 0:db4396ad001f 560 */
elelthvd 0:db4396ad001f 561 bool connected();
elelthvd 0:db4396ad001f 562
elelthvd 0:db4396ad001f 563
elelthvd 0:db4396ad001f 564
elelthvd 0:db4396ad001f 565 /** FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config
elelthvd 0:db4396ad001f 566 * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable)
elelthvd 0:db4396ad001f 567 * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set
elelthvd 0:db4396ad001f 568 * @param none
elelthvd 0:db4396ad001f 569 * @return none
elelthvd 0:db4396ad001f 570 */
elelthvd 0:db4396ad001f 571 void set_fifo_control();
elelthvd 0:db4396ad001f 572
elelthvd 0:db4396ad001f 573
elelthvd 0:db4396ad001f 574 /** Flush the UART FIFOs while maintaining current FIFO mode.
elelthvd 0:db4396ad001f 575 * @param none
elelthvd 0:db4396ad001f 576 * @return none
elelthvd 0:db4396ad001f 577 */
elelthvd 0:db4396ad001f 578 void flush();
elelthvd 0:db4396ad001f 579
elelthvd 0:db4396ad001f 580
elelthvd 0:db4396ad001f 581 /** Set direction of I/O port pins.
elelthvd 0:db4396ad001f 582 * This method is specific to the SPI-I2C UART and not found on the 16750
elelthvd 0:db4396ad001f 583 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 584 * @param bits Bitpattern for I/O (1=output, 0=input)
elelthvd 0:db4396ad001f 585 * @return none
elelthvd 0:db4396ad001f 586 */
elelthvd 0:db4396ad001f 587 void ioSetDirection(unsigned char bits);
elelthvd 0:db4396ad001f 588
elelthvd 0:db4396ad001f 589 /** Set bits of I/O port pins.
elelthvd 0:db4396ad001f 590 * This method is specific to the SPI-I2C UART and not found on the 16750
elelthvd 0:db4396ad001f 591 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 592 * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit)
elelthvd 0:db4396ad001f 593 * @return none
elelthvd 0:db4396ad001f 594 */
elelthvd 0:db4396ad001f 595 void ioSetState(unsigned char bits);
elelthvd 0:db4396ad001f 596
elelthvd 0:db4396ad001f 597 /** Get bits of I/O port pins.
elelthvd 0:db4396ad001f 598 * This method is specific to the SPI-I2C UART and not found on the 16750
elelthvd 0:db4396ad001f 599 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 600 * @param none
elelthvd 0:db4396ad001f 601 * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared)
elelthvd 0:db4396ad001f 602 */
elelthvd 0:db4396ad001f 603 unsigned char ioGetState();
elelthvd 0:db4396ad001f 604
elelthvd 0:db4396ad001f 605
elelthvd 0:db4396ad001f 606 /** Software Reset SC16IS740 device.
elelthvd 0:db4396ad001f 607 * This method is specific to the SPI-I2C UART and not found on the 16750
elelthvd 0:db4396ad001f 608 * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 609 * @param none
elelthvd 0:db4396ad001f 610 * @return none
elelthvd 0:db4396ad001f 611 */
elelthvd 0:db4396ad001f 612 void swReset();
elelthvd 0:db4396ad001f 613
elelthvd 0:db4396ad001f 614
elelthvd 0:db4396ad001f 615 /** Hardware Reset SC16IS740 device.
elelthvd 0:db4396ad001f 616 * Pure virtual, must be declared in derived class.
elelthvd 0:db4396ad001f 617 * This method is only functional when the Reset pin has been declared and is also connected
elelthvd 0:db4396ad001f 618 * @param none
elelthvd 0:db4396ad001f 619 * @return none
elelthvd 0:db4396ad001f 620 */
elelthvd 0:db4396ad001f 621 virtual void hwReset() =0;
elelthvd 0:db4396ad001f 622
elelthvd 0:db4396ad001f 623 /** Write value to internal register.
elelthvd 0:db4396ad001f 624 * Pure virtual, must be declared in derived class.
elelthvd 0:db4396ad001f 625 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 626 * @param data The 8bit value to write
elelthvd 0:db4396ad001f 627 * @return none
elelthvd 0:db4396ad001f 628 */
elelthvd 0:db4396ad001f 629 virtual void writeRegister (RegisterName register_address, char data ) =0;
elelthvd 0:db4396ad001f 630
elelthvd 0:db4396ad001f 631 /** Read value from internal register.
elelthvd 0:db4396ad001f 632 * Pure virtual, must be declared in derived class.
elelthvd 0:db4396ad001f 633 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 634 * @return char The 8bit value read from the register
elelthvd 0:db4396ad001f 635 */
elelthvd 0:db4396ad001f 636 virtual char readRegister (RegisterName register_address ) =0;
elelthvd 0:db4396ad001f 637
elelthvd 0:db4396ad001f 638 /** Write multiple datavalues to Transmitregister.
elelthvd 0:db4396ad001f 639 * More Efficient implementation than writing individual bytes
elelthvd 0:db4396ad001f 640 * Pure virtual, must be declared in derived class.
elelthvd 0:db4396ad001f 641 * @param char* databytes The pointer to the block of data
elelthvd 0:db4396ad001f 642 * @param len The number of bytes to write
elelthvd 0:db4396ad001f 643 * @return none
elelthvd 0:db4396ad001f 644 */
elelthvd 0:db4396ad001f 645 virtual void writeDataBlock (const char *data, int len ) =0;
elelthvd 0:db4396ad001f 646
elelthvd 0:db4396ad001f 647
elelthvd 0:db4396ad001f 648 /** Initialise internal registers
elelthvd 0:db4396ad001f 649 * Should be in protection section. Public for testing purposes
elelthvd 0:db4396ad001f 650 * If initialisation fails this method does not return.
elelthvd 0:db4396ad001f 651 * @param none
elelthvd 0:db4396ad001f 652 * @return none
elelthvd 0:db4396ad001f 653 */
elelthvd 0:db4396ad001f 654 void _init();
elelthvd 0:db4396ad001f 655
elelthvd 0:db4396ad001f 656 protected:
elelthvd 0:db4396ad001f 657 //protected is accessible to derived classes, but not to external users
elelthvd 0:db4396ad001f 658
elelthvd 0:db4396ad001f 659
elelthvd 0:db4396ad001f 660 /** Constructor is protected for this abstract Class
elelthvd 0:db4396ad001f 661 *
elelthvd 0:db4396ad001f 662 */
elelthvd 0:db4396ad001f 663 SC16IS740();
elelthvd 0:db4396ad001f 664
elelthvd 0:db4396ad001f 665 /** Needed to implement Stream
elelthvd 0:db4396ad001f 666 *
elelthvd 0:db4396ad001f 667 * Read char from UART Bridge.
elelthvd 0:db4396ad001f 668 * Acts in the same manner as 'Serial.read()'.
elelthvd 0:db4396ad001f 669 * @param none
elelthvd 0:db4396ad001f 670 * @return char read or -1 if no data available.
elelthvd 0:db4396ad001f 671 */
elelthvd 0:db4396ad001f 672 virtual int _getc() {
elelthvd 0:db4396ad001f 673 return getc();
elelthvd 0:db4396ad001f 674 }
elelthvd 0:db4396ad001f 675
elelthvd 0:db4396ad001f 676
elelthvd 0:db4396ad001f 677 /** Needed to implement Stream
elelthvd 0:db4396ad001f 678 *
elelthvd 0:db4396ad001f 679 * Write char to UART Bridge. Blocking when no free space in FIFO
elelthvd 0:db4396ad001f 680 * @param value char to be written
elelthvd 0:db4396ad001f 681 * @return value written
elelthvd 0:db4396ad001f 682 */
elelthvd 0:db4396ad001f 683 virtual int _putc(int c) {
elelthvd 0:db4396ad001f 684 return putc(c);
elelthvd 0:db4396ad001f 685 }
elelthvd 0:db4396ad001f 686
elelthvd 0:db4396ad001f 687 /** Needed to implement Stream
elelthvd 0:db4396ad001f 688 *
elelthvd 0:db4396ad001f 689 */
elelthvd 0:db4396ad001f 690 virtual int peek() {return 0;};
elelthvd 0:db4396ad001f 691
elelthvd 0:db4396ad001f 692
elelthvd 0:db4396ad001f 693 // Save config settings
elelthvd 0:db4396ad001f 694 SC16IS740_cfg _config;
elelthvd 0:db4396ad001f 695
elelthvd 0:db4396ad001f 696 private:
elelthvd 0:db4396ad001f 697 //private is not accessible to derived classes, nor external users
elelthvd 0:db4396ad001f 698
elelthvd 0:db4396ad001f 699 };
elelthvd 0:db4396ad001f 700
elelthvd 0:db4396ad001f 701
elelthvd 0:db4396ad001f 702
elelthvd 0:db4396ad001f 703 /** Class SC16IS740_SPI for a bridge between SPI and a Serial port
elelthvd 0:db4396ad001f 704 *
elelthvd 0:db4396ad001f 705 * @code
elelthvd 0:db4396ad001f 706 * #include "mbed.h"
elelthvd 0:db4396ad001f 707 * #include "SC16IS740.h"
elelthvd 0:db4396ad001f 708 *
elelthvd 0:db4396ad001f 709 * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK
elelthvd 0:db4396ad001f 710 * SC16IS740_SPI serial_spi(&spi, PTD0);
elelthvd 0:db4396ad001f 711 *
elelthvd 0:db4396ad001f 712 * Serial pc(USBTX,USBRX);
elelthvd 0:db4396ad001f 713 *
elelthvd 0:db4396ad001f 714 * int main() {
elelthvd 0:db4396ad001f 715 * pc.printf("\nHello World!\n");
elelthvd 0:db4396ad001f 716 *
elelthvd 0:db4396ad001f 717 * while(1) {
elelthvd 0:db4396ad001f 718 * serial_spi.ioSetState(0x00);
elelthvd 0:db4396ad001f 719 * wait(0.5);
elelthvd 0:db4396ad001f 720 * serial_spi.ioSetState(0xFF);
elelthvd 0:db4396ad001f 721 * wait(0.5);
elelthvd 0:db4396ad001f 722 * serial_spi.putc('*');
elelthvd 0:db4396ad001f 723 * pc.putc('*');
elelthvd 0:db4396ad001f 724 * }
elelthvd 0:db4396ad001f 725 * }
elelthvd 0:db4396ad001f 726 *
elelthvd 0:db4396ad001f 727 * @endcode
elelthvd 0:db4396ad001f 728 */
elelthvd 0:db4396ad001f 729 class SC16IS740_SPI : public SC16IS740 {
elelthvd 0:db4396ad001f 730 public:
elelthvd 0:db4396ad001f 731
elelthvd 0:db4396ad001f 732 /** Create an SC16IS740_SPI object using a specified SPI bus and CS
elelthvd 0:db4396ad001f 733 *
elelthvd 0:db4396ad001f 734 * @param SPI &spi the SPI port to connect to
elelthvd 0:db4396ad001f 735 * @param cs Pinname of the CS pin (active low)
elelthvd 0:db4396ad001f 736 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
elelthvd 0:db4396ad001f 737 */
elelthvd 0:db4396ad001f 738 SC16IS740_SPI(SPI *spi, PinName cs, PinName rst = NC);
elelthvd 0:db4396ad001f 739
elelthvd 0:db4396ad001f 740 /** Destruct SC16IS740_SPI bridge object
elelthvd 0:db4396ad001f 741 *
elelthvd 0:db4396ad001f 742 * @param none
elelthvd 0:db4396ad001f 743 * @return none
elelthvd 0:db4396ad001f 744 */
elelthvd 0:db4396ad001f 745 virtual ~SC16IS740_SPI();
elelthvd 0:db4396ad001f 746
elelthvd 0:db4396ad001f 747
elelthvd 0:db4396ad001f 748 /** Write value to internal register.
elelthvd 0:db4396ad001f 749 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 750 * @param data The 8bit value to write
elelthvd 0:db4396ad001f 751 * @return none
elelthvd 0:db4396ad001f 752 */
elelthvd 0:db4396ad001f 753 virtual void writeRegister(SC16IS740::RegisterName registerAddress, char data);
elelthvd 0:db4396ad001f 754
elelthvd 0:db4396ad001f 755 /** Read value from internal register.
elelthvd 0:db4396ad001f 756 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 757 * @return char The 8bit value read from the register
elelthvd 0:db4396ad001f 758 */
elelthvd 0:db4396ad001f 759 virtual char readRegister(SC16IS740::RegisterName registerAddress);
elelthvd 0:db4396ad001f 760
elelthvd 0:db4396ad001f 761 /** Write multiple datavalues to Transmitregister.
elelthvd 0:db4396ad001f 762 * More Efficient implementation than writing individual bytes
elelthvd 0:db4396ad001f 763 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
elelthvd 0:db4396ad001f 764 *
elelthvd 0:db4396ad001f 765 * @param char* databytes The pointer to the block of data
elelthvd 0:db4396ad001f 766 * @param len The number of bytes to write
elelthvd 0:db4396ad001f 767 * @return none
elelthvd 0:db4396ad001f 768 */
elelthvd 0:db4396ad001f 769 virtual void writeDataBlock (const char *data, int len );
elelthvd 0:db4396ad001f 770
elelthvd 0:db4396ad001f 771 /** Hardware Reset SC16IS740 device.
elelthvd 0:db4396ad001f 772 * This method is only functional when the Reset pin has been declared and is also connected
elelthvd 0:db4396ad001f 773 * @param none
elelthvd 0:db4396ad001f 774 * @return none
elelthvd 0:db4396ad001f 775 */
elelthvd 0:db4396ad001f 776 virtual void hwReset();
elelthvd 0:db4396ad001f 777
elelthvd 0:db4396ad001f 778
elelthvd 0:db4396ad001f 779 protected:
elelthvd 0:db4396ad001f 780 //protected is accessible to derived classes, but not to external users
elelthvd 0:db4396ad001f 781
elelthvd 0:db4396ad001f 782
elelthvd 0:db4396ad001f 783 private:
elelthvd 0:db4396ad001f 784 SPI *_spi; //SPI bus reference
elelthvd 0:db4396ad001f 785 DigitalOut _cs; //CS of SPI device (active low)
elelthvd 0:db4396ad001f 786
elelthvd 0:db4396ad001f 787 /** Optional Hardware Reset pin for the bridge device (active low)
elelthvd 0:db4396ad001f 788 * Default PinName value is NC
elelthvd 0:db4396ad001f 789 */
elelthvd 0:db4396ad001f 790 DigitalOut* _reset; //Reset the Bridge device (active low)
elelthvd 0:db4396ad001f 791
elelthvd 0:db4396ad001f 792 };
elelthvd 0:db4396ad001f 793
elelthvd 0:db4396ad001f 794
elelthvd 0:db4396ad001f 795
elelthvd 0:db4396ad001f 796 /** Class SC16IS740_I2C for a bridge between I2C and a Serial port
elelthvd 0:db4396ad001f 797 *
elelthvd 0:db4396ad001f 798 * @code
elelthvd 0:db4396ad001f 799 * #include "mbed.h"
elelthvd 0:db4396ad001f 800 * #include "SC16IS740.h"
elelthvd 0:db4396ad001f 801 *
elelthvd 0:db4396ad001f 802 * I2C i2c(PTE0, PTE1); //SDA, SCL
elelthvd 0:db4396ad001f 803 * SC16IS740_I2C serial_i2c(&i2c, SC16IS740_DEFAULT_ADDR);
elelthvd 0:db4396ad001f 804 *
elelthvd 0:db4396ad001f 805 * Serial pc(USBTX,USBRX);
elelthvd 0:db4396ad001f 806 *
elelthvd 0:db4396ad001f 807 * int main() {
elelthvd 0:db4396ad001f 808 * pc.printf("\nHello World!\n");
elelthvd 0:db4396ad001f 809 *
elelthvd 0:db4396ad001f 810 * while(1) {
elelthvd 0:db4396ad001f 811 * serial_i2c.ioSetState(0x00);
elelthvd 0:db4396ad001f 812 * wait(0.5);
elelthvd 0:db4396ad001f 813 * serial_i2c.ioSetState(0xFF);
elelthvd 0:db4396ad001f 814 * wait(0.5);
elelthvd 0:db4396ad001f 815 * serial_i2c.putc('*');
elelthvd 0:db4396ad001f 816 * pc.putc('*');
elelthvd 0:db4396ad001f 817 * }
elelthvd 0:db4396ad001f 818 * }
elelthvd 0:db4396ad001f 819 *
elelthvd 0:db4396ad001f 820 * @endcode
elelthvd 0:db4396ad001f 821 */
elelthvd 0:db4396ad001f 822 class SC16IS740_I2C : public SC16IS740 {
elelthvd 0:db4396ad001f 823 public:
elelthvd 0:db4396ad001f 824
elelthvd 0:db4396ad001f 825 /** Create an SC16IS740_I2C object using a specified I2C bus and slaveaddress
elelthvd 0:db4396ad001f 826 *
elelthvd 0:db4396ad001f 827 * @param I2C &i2c the I2C port to connect to
elelthvd 0:db4396ad001f 828 * @param char deviceAddress the address of the SC16IS740
elelthvd 0:db4396ad001f 829 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
elelthvd 0:db4396ad001f 830 */
elelthvd 0:db4396ad001f 831 SC16IS740_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS740_DEFAULT_ADDR, PinName rst = NC);
elelthvd 0:db4396ad001f 832
elelthvd 0:db4396ad001f 833
elelthvd 0:db4396ad001f 834 /** Destruct SC16IS740_I2C bridge object
elelthvd 0:db4396ad001f 835 *
elelthvd 0:db4396ad001f 836 * @param none
elelthvd 0:db4396ad001f 837 * @return none
elelthvd 0:db4396ad001f 838 */
elelthvd 0:db4396ad001f 839 virtual ~SC16IS740_I2C();
elelthvd 0:db4396ad001f 840
elelthvd 0:db4396ad001f 841
elelthvd 0:db4396ad001f 842 /** Write value to internal register.
elelthvd 0:db4396ad001f 843 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 844 * @param data The 8bit value to write
elelthvd 0:db4396ad001f 845 * @return none
elelthvd 0:db4396ad001f 846 */
elelthvd 0:db4396ad001f 847 virtual void writeRegister(SC16IS740::RegisterName register_address, char data );
elelthvd 0:db4396ad001f 848
elelthvd 0:db4396ad001f 849 /** Read value from internal register.
elelthvd 0:db4396ad001f 850 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 851 * @return char The 8bit value read from the register
elelthvd 0:db4396ad001f 852 */
elelthvd 0:db4396ad001f 853 virtual char readRegister(SC16IS740::RegisterName register_address );
elelthvd 0:db4396ad001f 854
elelthvd 0:db4396ad001f 855
elelthvd 0:db4396ad001f 856 /** Write multiple datavalues to Transmitregister.
elelthvd 0:db4396ad001f 857 * More Efficient implementation than writing individual bytes
elelthvd 0:db4396ad001f 858 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
elelthvd 0:db4396ad001f 859 * Pure virtual, must be declared in derived class.
elelthvd 0:db4396ad001f 860 * @param char* databytes The pointer to the block of data
elelthvd 0:db4396ad001f 861 * @param len The number of bytes to write
elelthvd 0:db4396ad001f 862 * @return none
elelthvd 0:db4396ad001f 863 */
elelthvd 0:db4396ad001f 864 virtual void writeDataBlock (const char *data, int len );
elelthvd 0:db4396ad001f 865
elelthvd 0:db4396ad001f 866
elelthvd 0:db4396ad001f 867 /** Hardware Reset SC16IS740 device.
elelthvd 0:db4396ad001f 868 * This method is only functional when the Reset pin has been declared and is also connected
elelthvd 0:db4396ad001f 869 * @param none
elelthvd 0:db4396ad001f 870 * @return none
elelthvd 0:db4396ad001f 871 */
elelthvd 0:db4396ad001f 872 virtual void hwReset();
elelthvd 0:db4396ad001f 873
elelthvd 0:db4396ad001f 874
elelthvd 0:db4396ad001f 875 protected:
elelthvd 0:db4396ad001f 876 //protected is accessible to derived classes, but not to external users
elelthvd 0:db4396ad001f 877
elelthvd 0:db4396ad001f 878
elelthvd 0:db4396ad001f 879 private:
elelthvd 0:db4396ad001f 880 I2C *_i2c; //I2C bus reference
elelthvd 0:db4396ad001f 881 uint8_t _slaveAddress; //I2C Slave address of device
elelthvd 0:db4396ad001f 882
elelthvd 0:db4396ad001f 883 /** Optional Hardware Reset pin for the bridge device (active low)
elelthvd 0:db4396ad001f 884 * Default PinName value is NC
elelthvd 0:db4396ad001f 885 */
elelthvd 0:db4396ad001f 886 DigitalOut* _reset; //Reset the Bridge device (active low)
elelthvd 0:db4396ad001f 887
elelthvd 0:db4396ad001f 888 };
elelthvd 0:db4396ad001f 889
elelthvd 0:db4396ad001f 890
elelthvd 0:db4396ad001f 891
elelthvd 0:db4396ad001f 892 /** Class SC16IS752_SPI for a bridge between SPI and a Serial port
elelthvd 0:db4396ad001f 893 *
elelthvd 0:db4396ad001f 894 * @code
elelthvd 0:db4396ad001f 895 * #include "mbed.h"
elelthvd 0:db4396ad001f 896 * #include "SC16IS740.h"
elelthvd 0:db4396ad001f 897 *
elelthvd 0:db4396ad001f 898 * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK
elelthvd 0:db4396ad001f 899 * SC16IS740_SPI serial_spi(&spi, PTD0, NC, SC16IS740::Channel_B);
elelthvd 0:db4396ad001f 900 *
elelthvd 0:db4396ad001f 901 * Serial pc(USBTX,USBRX);
elelthvd 0:db4396ad001f 902 *
elelthvd 0:db4396ad001f 903 * int main() {
elelthvd 0:db4396ad001f 904 * pc.printf("\nHello World!\n");
elelthvd 0:db4396ad001f 905 *
elelthvd 0:db4396ad001f 906 * while(1) {
elelthvd 0:db4396ad001f 907 * serial_spi.ioSetState(0x00);
elelthvd 0:db4396ad001f 908 * wait(0.5);
elelthvd 0:db4396ad001f 909 * serial_spi.ioSetState(0xFF);
elelthvd 0:db4396ad001f 910 * wait(0.5);
elelthvd 0:db4396ad001f 911 * serial_spi.putc('*');
elelthvd 0:db4396ad001f 912 * pc.putc('*');
elelthvd 0:db4396ad001f 913 * }
elelthvd 0:db4396ad001f 914 * }
elelthvd 0:db4396ad001f 915 *
elelthvd 0:db4396ad001f 916 * @endcode
elelthvd 0:db4396ad001f 917 */
elelthvd 0:db4396ad001f 918 class SC16IS752_SPI : public SC16IS740 {
elelthvd 0:db4396ad001f 919 public:
elelthvd 0:db4396ad001f 920
elelthvd 0:db4396ad001f 921 /** Create an SC16IS752_SPI object using a specified SPI bus and CS
elelthvd 0:db4396ad001f 922 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 923 * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 924 *
elelthvd 0:db4396ad001f 925 * @param SPI &spi the SPI port to connect to
elelthvd 0:db4396ad001f 926 * @param cs Pinname of the CS pin (active low)
elelthvd 0:db4396ad001f 927 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
elelthvd 0:db4396ad001f 928 * @param channel UART ChannelName, Default = Channel_A
elelthvd 0:db4396ad001f 929 */
elelthvd 0:db4396ad001f 930 SC16IS752_SPI(SPI *spi, PinName cs, PinName rst = NC, ChannelName channel = SC16IS740::Channel_A );
elelthvd 0:db4396ad001f 931
elelthvd 0:db4396ad001f 932 /** Destruct SC16IS752_SPI bridge object
elelthvd 0:db4396ad001f 933 *
elelthvd 0:db4396ad001f 934 * @param none
elelthvd 0:db4396ad001f 935 * @return none
elelthvd 0:db4396ad001f 936 */
elelthvd 0:db4396ad001f 937 virtual ~SC16IS752_SPI();
elelthvd 0:db4396ad001f 938
elelthvd 0:db4396ad001f 939
elelthvd 0:db4396ad001f 940 /** Write value to internal register.
elelthvd 0:db4396ad001f 941 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 942 * @param data The 8bit value to write
elelthvd 0:db4396ad001f 943 * @return none
elelthvd 0:db4396ad001f 944 */
elelthvd 0:db4396ad001f 945 virtual void writeRegister(SC16IS740::RegisterName registerAddress, char data);
elelthvd 0:db4396ad001f 946
elelthvd 0:db4396ad001f 947 /** Read value from internal register.
elelthvd 0:db4396ad001f 948 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 949 * @return char The 8bit value read from the register
elelthvd 0:db4396ad001f 950 */
elelthvd 0:db4396ad001f 951 virtual char readRegister(SC16IS740::RegisterName registerAddress);
elelthvd 0:db4396ad001f 952
elelthvd 0:db4396ad001f 953 /** Write multiple datavalues to Transmitregister.
elelthvd 0:db4396ad001f 954 * More Efficient implementation than writing individual bytes
elelthvd 0:db4396ad001f 955 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
elelthvd 0:db4396ad001f 956 *
elelthvd 0:db4396ad001f 957 * @param char* databytes The pointer to the block of data
elelthvd 0:db4396ad001f 958 * @param len The number of bytes to write
elelthvd 0:db4396ad001f 959 * @return none
elelthvd 0:db4396ad001f 960 */
elelthvd 0:db4396ad001f 961 virtual void writeDataBlock (const char *data, int len );
elelthvd 0:db4396ad001f 962
elelthvd 0:db4396ad001f 963 /** Hardware Reset SC16IS740 device.
elelthvd 0:db4396ad001f 964 * This method is only functional when the Reset pin has been declared and is also connected
elelthvd 0:db4396ad001f 965 * @param none
elelthvd 0:db4396ad001f 966 * @return none
elelthvd 0:db4396ad001f 967 */
elelthvd 0:db4396ad001f 968 virtual void hwReset();
elelthvd 0:db4396ad001f 969
elelthvd 0:db4396ad001f 970
elelthvd 0:db4396ad001f 971 protected:
elelthvd 0:db4396ad001f 972 //protected is accessible to derived classes, but not to external users
elelthvd 0:db4396ad001f 973
elelthvd 0:db4396ad001f 974
elelthvd 0:db4396ad001f 975 private:
elelthvd 0:db4396ad001f 976 SPI *_spi; //SPI bus reference
elelthvd 0:db4396ad001f 977 DigitalOut _cs; //CS of SPI device (active low)
elelthvd 0:db4396ad001f 978
elelthvd 0:db4396ad001f 979 /** Optional Hardware Reset pin for the bridge device (active low)
elelthvd 0:db4396ad001f 980 * Default PinName value is NC
elelthvd 0:db4396ad001f 981 */
elelthvd 0:db4396ad001f 982 DigitalOut* _reset; //Reset the Bridge device (active low)
elelthvd 0:db4396ad001f 983
elelthvd 0:db4396ad001f 984 // Save Channel setting
elelthvd 0:db4396ad001f 985 ChannelName _channel;
elelthvd 0:db4396ad001f 986 };
elelthvd 0:db4396ad001f 987
elelthvd 0:db4396ad001f 988
elelthvd 0:db4396ad001f 989
elelthvd 0:db4396ad001f 990 /** Class SC16IS752_I2C for a bridge between I2C and a Serial port
elelthvd 0:db4396ad001f 991 *
elelthvd 0:db4396ad001f 992 * @code
elelthvd 0:db4396ad001f 993 * #include "mbed.h"
elelthvd 0:db4396ad001f 994 * #include "SC16IS740.h"
elelthvd 0:db4396ad001f 995 *
elelthvd 0:db4396ad001f 996 * I2C i2c(PTE0, PTE1); //SDA, SCL
elelthvd 0:db4396ad001f 997 * SC16IS752_I2C serial_i2c(&i2c, SC16IS740_DEFAULT_ADDR, NC, SC16IS740::Channel_A);
elelthvd 0:db4396ad001f 998 *
elelthvd 0:db4396ad001f 999 * Serial pc(USBTX,USBRX);
elelthvd 0:db4396ad001f 1000 *
elelthvd 0:db4396ad001f 1001 * int main() {
elelthvd 0:db4396ad001f 1002 * pc.printf("\nHello World!\n");
elelthvd 0:db4396ad001f 1003 *
elelthvd 0:db4396ad001f 1004 * while(1) {
elelthvd 0:db4396ad001f 1005 * serial_i2c.ioSetState(0x00);
elelthvd 0:db4396ad001f 1006 * wait(0.5);
elelthvd 0:db4396ad001f 1007 * serial_i2c.ioSetState(0xFF);
elelthvd 0:db4396ad001f 1008 * wait(0.5);
elelthvd 0:db4396ad001f 1009 * serial_i2c.putc('*');
elelthvd 0:db4396ad001f 1010 * pc.putc('*');
elelthvd 0:db4396ad001f 1011 * }
elelthvd 0:db4396ad001f 1012 * }
elelthvd 0:db4396ad001f 1013 *
elelthvd 0:db4396ad001f 1014 * @endcode
elelthvd 0:db4396ad001f 1015 */
elelthvd 0:db4396ad001f 1016 class SC16IS752_I2C : public SC16IS740 {
elelthvd 0:db4396ad001f 1017 public:
elelthvd 0:db4396ad001f 1018
elelthvd 0:db4396ad001f 1019 /** Create an SC16IS752_I2C object using a specified I2C bus, slaveaddress and Channel
elelthvd 0:db4396ad001f 1020 * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 1021 * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B.
elelthvd 0:db4396ad001f 1022 *
elelthvd 0:db4396ad001f 1023 * @param I2C &i2c the I2C port to connect to
elelthvd 0:db4396ad001f 1024 * @param char deviceAddress the address of the SC16IS740
elelthvd 0:db4396ad001f 1025 * @param rst Pinname for Reset pin (active low) Optional, Default = NC
elelthvd 0:db4396ad001f 1026 * @param channel UART ChannelName, Default = Channel_A
elelthvd 0:db4396ad001f 1027 */
elelthvd 0:db4396ad001f 1028 SC16IS752_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS740_DEFAULT_ADDR, PinName rst = NC, ChannelName channel = SC16IS740::Channel_A);
elelthvd 0:db4396ad001f 1029
elelthvd 0:db4396ad001f 1030
elelthvd 0:db4396ad001f 1031 /** Destruct SC16IS752_I2C bridge object
elelthvd 0:db4396ad001f 1032 *
elelthvd 0:db4396ad001f 1033 * @param none
elelthvd 0:db4396ad001f 1034 * @return none
elelthvd 0:db4396ad001f 1035 */
elelthvd 0:db4396ad001f 1036 virtual ~SC16IS752_I2C();
elelthvd 0:db4396ad001f 1037
elelthvd 0:db4396ad001f 1038
elelthvd 0:db4396ad001f 1039 /** Write value to internal register.
elelthvd 0:db4396ad001f 1040 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 1041 * @param data The 8bit value to write
elelthvd 0:db4396ad001f 1042 * @return none
elelthvd 0:db4396ad001f 1043 */
elelthvd 0:db4396ad001f 1044 virtual void writeRegister(SC16IS740::RegisterName register_address, char data );
elelthvd 0:db4396ad001f 1045
elelthvd 0:db4396ad001f 1046 /** Read value from internal register.
elelthvd 0:db4396ad001f 1047 * @param registerAddress The address of the Register (enum RegisterName)
elelthvd 0:db4396ad001f 1048 * @return char The 8bit value read from the register
elelthvd 0:db4396ad001f 1049 */
elelthvd 0:db4396ad001f 1050 virtual char readRegister(SC16IS740::RegisterName register_address );
elelthvd 0:db4396ad001f 1051
elelthvd 0:db4396ad001f 1052
elelthvd 0:db4396ad001f 1053 /** Write multiple datavalues to Transmitregister.
elelthvd 0:db4396ad001f 1054 * More Efficient implementation than writing individual bytes
elelthvd 0:db4396ad001f 1055 * Assume that previous check confirmed that the FIFO has sufficient free space to store the data
elelthvd 0:db4396ad001f 1056 * Pure virtual, must be declared in derived class.
elelthvd 0:db4396ad001f 1057 * @param char* databytes The pointer to the block of data
elelthvd 0:db4396ad001f 1058 * @param len The number of bytes to write
elelthvd 0:db4396ad001f 1059 * @return none
elelthvd 0:db4396ad001f 1060 */
elelthvd 0:db4396ad001f 1061 virtual void writeDataBlock (const char *data, int len );
elelthvd 0:db4396ad001f 1062
elelthvd 0:db4396ad001f 1063
elelthvd 0:db4396ad001f 1064 /** Hardware Reset SC16IS752 device.
elelthvd 0:db4396ad001f 1065 * This method is only functional when the Reset pin has been declared and is also connected
elelthvd 0:db4396ad001f 1066 * @param none
elelthvd 0:db4396ad001f 1067 * @return none
elelthvd 0:db4396ad001f 1068 */
elelthvd 0:db4396ad001f 1069 virtual void hwReset();
elelthvd 0:db4396ad001f 1070
elelthvd 0:db4396ad001f 1071
elelthvd 0:db4396ad001f 1072 protected:
elelthvd 0:db4396ad001f 1073 //protected is accessible to derived classes, but not to external users
elelthvd 0:db4396ad001f 1074
elelthvd 0:db4396ad001f 1075
elelthvd 0:db4396ad001f 1076 private:
elelthvd 0:db4396ad001f 1077 I2C *_i2c; //I2C bus reference
elelthvd 0:db4396ad001f 1078 uint8_t _slaveAddress; //I2C Slave address of device
elelthvd 0:db4396ad001f 1079
elelthvd 0:db4396ad001f 1080 /** Optional Hardware Reset pin for the bridge device (active low)
elelthvd 0:db4396ad001f 1081 * Default PinName value is NC
elelthvd 0:db4396ad001f 1082 */
elelthvd 0:db4396ad001f 1083 DigitalOut* _reset; //Reset the Bridge device (active low)
elelthvd 0:db4396ad001f 1084
elelthvd 0:db4396ad001f 1085 // Save Channel setting
elelthvd 0:db4396ad001f 1086 ChannelName _channel;
elelthvd 0:db4396ad001f 1087
elelthvd 0:db4396ad001f 1088 };
elelthvd 0:db4396ad001f 1089
elelthvd 0:db4396ad001f 1090
elelthvd 0:db4396ad001f 1091 #endif // _SC16IS740_H