Diff: sx127x.h

Revision:

6:5d94ee847016

Parent:

5:dde68100518b

--- a/sx127x.h	Tue Jun 03 20:44:30 2014 +0000
+++ b/sx127x.h	Mon Jun 30 17:05:12 2014 +0000
@@ -50,6 +50,8 @@
 #define REG_DIOMAPPING2                             0x41
 #define REG_VERSION                                 0x42
 
+#define REG_PLL                                     0x5C    // RX PLL bandwidth
+#define REG_BSYNCTST2                               0x67
 /******************************************************************************/
 
 
@@ -156,6 +158,24 @@
     uint8_t octet;
 } RegDioMapping2_t;
 
+typedef union {
+    struct {    // sx1272 register 0x5c
+        uint8_t reserved           : 6;    // 0->5
+        uint8_t PllBandwidth       : 2;    // 6,7 
+    } bits;
+    uint8_t octet;
+} RegPll_t;
+
+typedef union {
+    struct {    // sx1272 register 0x67
+        uint8_t bsync_mode              : 3;    // 0,1,2
+        uint8_t reserved                : 1;    // 3
+        uint8_t bsync_thresh_validity   : 1;    // 4
+        uint8_t unused                  : 3;    // 5,6,7 
+    } bits;
+    uint8_t octet;
+} RegBsyncTest2_t;
+
 /***************************************************/
 
 /** FSK/LoRa radio transceiver.
@@ -261,13 +281,15 @@
         //! pin assignments
         RegDioMapping2_t RegDioMapping2;
         
+        RegPll_t RegPll;                                // 0x5C
+        RegBsyncTest2_t RegBsyncTest2;                  // 0x67
+        
         // frequency hopping table
         const uint32_t *frfs;
         
         DigitalIn dio0;
         DigitalIn dio1;
-        DigitalOut femcps;  // LF rf switch
-        DigitalOut femctx;  // HF rf switch
+
         DigitalOut m_cs;
         SPI m_spi;
         bool HF;    // sx1272 is always HF   
@@ -275,6 +297,8 @@
     private:    
         DigitalInOut reset_pin;
         //void dio0_callback(void);
+        DigitalOut femcps;  // LF rf switch
+        DigitalOut femctx;  // HF rf switch        
         
         
     protected: