Department of Electrical Eng University of Moratuwa / Mbed 2 deprecated Vibration_Analysis_Force_Control

Force controlled vibration analysis

Dependencies:   mbed

QEI_hw/qeihw.h@5:9ab19c63203e, 2019-12-03 (annotated)

Committer:
eembed
Date:
Tue Dec 03 10:40:16 2019 +0000
Revision:
5:9ab19c63203e
Parent:
0:5459cdde6298 
first commit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
eembed 0:5459cdde6298 1 /* mbed Library - QEIhw
eembed 0:5459cdde6298 2 * Copyright (c) 2010, hball
eembed 0:5459cdde6298 3 * released under MIT license http://mbed.org/licence/mit
eembed 0:5459cdde6298 4 */
eembed 0:5459cdde6298 5
eembed 0:5459cdde6298 6 /***********************************************************************//**
eembed 0:5459cdde6298 7 * @file qeihw.h
eembed 0:5459cdde6298 8 * @brief Header file for the qeihw driver. Adapted from the CMSIS
eembed 0:5459cdde6298 9 * header, lpc17xx_qei.h, v 2.0
eembed 0:5459cdde6298 10 * @version 0.0
eembed 0:5459cdde6298 11 * @date 10 Dec 2010
eembed 0:5459cdde6298 12 * @author hb
eembed 0:5459cdde6298 13 **************************************************************************/
eembed 0:5459cdde6298 14
eembed 0:5459cdde6298 15
eembed 0:5459cdde6298 16 #ifndef MBED_QEIHW_H
eembed 0:5459cdde6298 17 #define MBED_QEIHW_H
eembed 0:5459cdde6298 18
eembed 0:5459cdde6298 19 /* Includes ------------------------------------------------------------------- */
eembed 0:5459cdde6298 20 #include "mbed.h"
eembed 0:5459cdde6298 21
eembed 0:5459cdde6298 22
eembed 0:5459cdde6298 23 /* Public Types --------------------------------------------------------------- */
eembed 0:5459cdde6298 24
eembed 0:5459cdde6298 25 /* Flag Status type definition */
eembed 0:5459cdde6298 26 typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
eembed 0:5459cdde6298 27
eembed 0:5459cdde6298 28 /* Functional State Definition */
eembed 0:5459cdde6298 29 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
eembed 0:5459cdde6298 30
eembed 0:5459cdde6298 31
eembed 0:5459cdde6298 32 /* Other definitions */
eembed 0:5459cdde6298 33 #define XTAL_FREQ 12000000
eembed 0:5459cdde6298 34
eembed 0:5459cdde6298 35 /* Public Functions ----------------------------------------------------------- */
eembed 0:5459cdde6298 36 /** @defgroup QEI_Public_Functions QEI Public Functions
eembed 0:5459cdde6298 37 */
eembed 0:5459cdde6298 38
eembed 0:5459cdde6298 39 /** QEI hardware interface class
eembed 0:5459cdde6298 40 * Requires mbed hardware modification: connect
eembed 0:5459cdde6298 41 * encoder PhA to p1.20, and PhB to p1.23.
eembed 0:5459cdde6298 42 *
eembed 0:5459cdde6298 43 * Example:
eembed 0:5459cdde6298 44 * @code
eembed 0:5459cdde6298 45 * // Display changes in encoder position and direction
eembed 0:5459cdde6298 46 #include "mbed.h"
eembed 0:5459cdde6298 47 * #include "qeihw.h"
eembed 0:5459cdde6298 48 *
eembed 0:5459cdde6298 49 * DigitalOut led1(LED1);
eembed 0:5459cdde6298 50 * DigitalOut led3(LED3);
eembed 0:5459cdde6298 51 * QEIHW qei(QEI_DIRINV_NONE, QEI_SIGNALMODE_QUAD, QEI_CAPMODE_2X, QEI_INVINX_NONE );
eembed 0:5459cdde6298 52 *
eembed 0:5459cdde6298 53 * int main() {
eembed 0:5459cdde6298 54 * int32_t temp, position = 0;
eembed 0:5459cdde6298 55 * qei.SetDigiFilter(480UL);
eembed 0:5459cdde6298 56 * qei.SetMaxPosition(0xFFFFFFFF);
eembed 0:5459cdde6298 57 *
eembed 0:5459cdde6298 58 * while(1) {
eembed 0:5459cdde6298 59 * while(position == (temp = qei.GetPosition()) );
eembed 0:5459cdde6298 60 * position = temp;
eembed 0:5459cdde6298 61 * printf("New position = %d.\r\n", temp);
eembed 0:5459cdde6298 62 * led1 = qei.Direction() == SET ? 1 : 0;
eembed 0:5459cdde6298 63 * led3 = !led1;
eembed 0:5459cdde6298 64 * wait(0.1);
eembed 0:5459cdde6298 65 * }
eembed 0:5459cdde6298 66 * }
eembed 0:5459cdde6298 67 * @endcode
eembed 0:5459cdde6298 68 */
eembed 0:5459cdde6298 69
eembed 0:5459cdde6298 70 class QEIHW {
eembed 0:5459cdde6298 71 public:
eembed 0:5459cdde6298 72
eembed 0:5459cdde6298 73 /** Create a QEI object and configure it
eembed 0:5459cdde6298 74 *
eembed 0:5459cdde6298 75 * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit
eembed 0:5459cdde6298 76 * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock
eembed 0:5459cdde6298 77 * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode).
eembed 0:5459cdde6298 78 * @param _invinx Invert index. When = 1, inverts the sense of the index signal
eembed 0:5459cdde6298 79 */
eembed 0:5459cdde6298 80 QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx);
eembed 0:5459cdde6298 81
eembed 0:5459cdde6298 82 /** Resets value for each type of QEI value, such as velocity, position, etc.
eembed 0:5459cdde6298 83 *
eembed 0:5459cdde6298 84 * @param[in] ulResetType QEI Reset Type, should be one of the following:
eembed 0:5459cdde6298 85 * - QEI_RESET_POS: Reset Position Counter
eembed 0:5459cdde6298 86 * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
eembed 0:5459cdde6298 87 * - QEI_RESET_VEL: Reset Velocity
eembed 0:5459cdde6298 88 * - QEI_RESET_IDX: Reset Index Counter
eembed 0:5459cdde6298 89 */
eembed 0:5459cdde6298 90 void Reset(uint32_t ulResetType);
eembed 0:5459cdde6298 91
eembed 0:5459cdde6298 92 /** Powers down the QEI block, returns pins to GPIO mode
eembed 0:5459cdde6298 93 *
eembed 0:5459cdde6298 94 */
eembed 0:5459cdde6298 95 void DeInit();
eembed 0:5459cdde6298 96
eembed 0:5459cdde6298 97 /** Report direction (QEISTAT bit DIR)
eembed 0:5459cdde6298 98 *
eembed 0:5459cdde6298 99 * @return State of the DIR bit (SET or RESET)
eembed 0:5459cdde6298 100 */
eembed 0:5459cdde6298 101 FlagStatus Direction();
eembed 0:5459cdde6298 102
eembed 0:5459cdde6298 103 /**
eembed 0:5459cdde6298 104 * @brief Get current position value in QEI peripheral
eembed 0:5459cdde6298 105 *
eembed 0:5459cdde6298 106 * @return Current position value of QEI peripheral
eembed 0:5459cdde6298 107 */
eembed 0:5459cdde6298 108 uint32_t GetPosition();
eembed 0:5459cdde6298 109
eembed 0:5459cdde6298 110 /** Set max position value for QEI peripheral
eembed 0:5459cdde6298 111 *
eembed 0:5459cdde6298 112 * @param[in] ulMaxPos Max position value to set
eembed 0:5459cdde6298 113 * @return None
eembed 0:5459cdde6298 114 */
eembed 0:5459cdde6298 115 void SetMaxPosition(uint32_t ulMaxPos);
eembed 0:5459cdde6298 116
eembed 0:5459cdde6298 117 /** Set position compare value for QEI peripheral
eembed 0:5459cdde6298 118 * @param[in] bPosCompCh Compare Position channel, should be:
eembed 0:5459cdde6298 119 * - QEI_COMPPOS_CH_0: QEI compare position channel 0
eembed 0:5459cdde6298 120 * - QEI_COMPPOS_CH_1: QEI compare position channel 1
eembed 0:5459cdde6298 121 * - QEI_COMPPOS_CH_2: QEI compare position channel 2
eembed 0:5459cdde6298 122 * @param[in] ulPosComp Compare Position value to set
eembed 0:5459cdde6298 123 * @return None
eembed 0:5459cdde6298 124 */
eembed 0:5459cdde6298 125 void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp);
eembed 0:5459cdde6298 126
eembed 0:5459cdde6298 127 /** Get current index counter of QEI peripheral
eembed 0:5459cdde6298 128 *
eembed 0:5459cdde6298 129 * @return Current value of QEI index counter
eembed 0:5459cdde6298 130 */
eembed 0:5459cdde6298 131 uint32_t GetIndex();
eembed 0:5459cdde6298 132
eembed 0:5459cdde6298 133 /** Set value for index compare in QEI peripheral
eembed 0:5459cdde6298 134 * @param[in] ulIndexComp Compare Index Value to set
eembed 0:5459cdde6298 135 * @return None
eembed 0:5459cdde6298 136 */
eembed 0:5459cdde6298 137 void SetIndexComp( uint32_t ulIndexComp);
eembed 0:5459cdde6298 138
eembed 0:5459cdde6298 139 /** Set Velocity timer reload value
eembed 0:5459cdde6298 140 *
eembed 0:5459cdde6298 141 * @param[in] ulReloadValue Velocity timer reload count
eembed 0:5459cdde6298 142 * @return None
eembed 0:5459cdde6298 143 */
eembed 0:5459cdde6298 144 void SetVelocityTimerReload( uint32_t ulReloadValue);
eembed 0:5459cdde6298 145
eembed 0:5459cdde6298 146 /** Set Velocity timer reload value in microseconds
eembed 0:5459cdde6298 147 *
eembed 0:5459cdde6298 148 * @param[in] ulReloadValue Velocity timer reload count
eembed 0:5459cdde6298 149 * @return None
eembed 0:5459cdde6298 150 */
eembed 0:5459cdde6298 151 void SetVelocityTimerReload_us( uint32_t ulReloadValue);
eembed 0:5459cdde6298 152
eembed 0:5459cdde6298 153 /** Get current timer counter in QEI peripheral
eembed 0:5459cdde6298 154 *
eembed 0:5459cdde6298 155 * @return Current timer counter in QEI peripheral
eembed 0:5459cdde6298 156 */
eembed 0:5459cdde6298 157 uint32_t GetTimer();
eembed 0:5459cdde6298 158
eembed 0:5459cdde6298 159 /** Get current velocity pulse counter in current time period
eembed 0:5459cdde6298 160 *
eembed 0:5459cdde6298 161 * @return Current velocity pulse counter value
eembed 0:5459cdde6298 162 */
eembed 0:5459cdde6298 163 uint32_t GetVelocity();
eembed 0:5459cdde6298 164
eembed 0:5459cdde6298 165 /** Get the most recently measured velocity of the QEI. When
eembed 0:5459cdde6298 166 * the Velocity timer in QEI is over-flow, the current velocity
eembed 0:5459cdde6298 167 * value will be loaded into Velocity Capture register.
eembed 0:5459cdde6298 168 *
eembed 0:5459cdde6298 169 * @return The most recently measured velocity value
eembed 0:5459cdde6298 170 */
eembed 0:5459cdde6298 171 uint32_t GetVelocityCap();
eembed 0:5459cdde6298 172
eembed 0:5459cdde6298 173 /** Set Velocity Compare value for QEI peripheral
eembed 0:5459cdde6298 174 *
eembed 0:5459cdde6298 175 * @param[in] ulVelComp Compare Velocity value to set
eembed 0:5459cdde6298 176 * @return None
eembed 0:5459cdde6298 177 */
eembed 0:5459cdde6298 178 void SetVelocityComp( uint32_t ulVelComp);
eembed 0:5459cdde6298 179
eembed 0:5459cdde6298 180 /** Set value of sampling count for the digital filter in
eembed 0:5459cdde6298 181 * QEI peripheral
eembed 0:5459cdde6298 182 *
eembed 0:5459cdde6298 183 * @param[in] ulSamplingPulse Value of sampling count to set
eembed 0:5459cdde6298 184 * @return None
eembed 0:5459cdde6298 185 */
eembed 0:5459cdde6298 186 void SetDigiFilter( uint32_t ulSamplingPulse);
eembed 0:5459cdde6298 187
eembed 0:5459cdde6298 188 /** Check whether if specified interrupt flag status in QEI
eembed 0:5459cdde6298 189 * peripheral is set or not
eembed 0:5459cdde6298 190 *
eembed 0:5459cdde6298 191 * @param[in] ulIntType Interrupt Flag Status type, should be:
eembed 0:5459cdde6298 192 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
eembed 0:5459cdde6298 193 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
eembed 0:5459cdde6298 194 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
eembed 0:5459cdde6298 195 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
eembed 0:5459cdde6298 196 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
eembed 0:5459cdde6298 197 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
eembed 0:5459cdde6298 198 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
eembed 0:5459cdde6298 199 current position interrupt
eembed 0:5459cdde6298 200 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
eembed 0:5459cdde6298 201 current position interrupt
eembed 0:5459cdde6298 202 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
eembed 0:5459cdde6298 203 current position interrupt
eembed 0:5459cdde6298 204 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
eembed 0:5459cdde6298 205 index count interrupt
eembed 0:5459cdde6298 206 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
eembed 0:5459cdde6298 207 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
eembed 0:5459cdde6298 208 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
eembed 0:5459cdde6298 209 * @return New State of specified interrupt flag status (SET or RESET)
eembed 0:5459cdde6298 210 */
eembed 0:5459cdde6298 211 FlagStatus GetIntStatus( uint32_t ulIntType);
eembed 0:5459cdde6298 212
eembed 0:5459cdde6298 213 /** Enable/Disable specified interrupt in QEI peripheral
eembed 0:5459cdde6298 214 *
eembed 0:5459cdde6298 215 * @param[in] ulIntType Interrupt Flag Status type, should be:
eembed 0:5459cdde6298 216 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
eembed 0:5459cdde6298 217 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
eembed 0:5459cdde6298 218 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
eembed 0:5459cdde6298 219 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
eembed 0:5459cdde6298 220 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
eembed 0:5459cdde6298 221 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
eembed 0:5459cdde6298 222 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
eembed 0:5459cdde6298 223 * current position interrupt
eembed 0:5459cdde6298 224 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
eembed 0:5459cdde6298 225 * current position interrupt
eembed 0:5459cdde6298 226 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
eembed 0:5459cdde6298 227 * current position interrupt
eembed 0:5459cdde6298 228 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
eembed 0:5459cdde6298 229 * index count interrupt
eembed 0:5459cdde6298 230 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
eembed 0:5459cdde6298 231 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
eembed 0:5459cdde6298 232 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
eembed 0:5459cdde6298 233 * @param[in] NewState New function state, should be:
eembed 0:5459cdde6298 234 * - DISABLE
eembed 0:5459cdde6298 235 * - ENABLE
eembed 0:5459cdde6298 236 * @return None
eembed 0:5459cdde6298 237 */
eembed 0:5459cdde6298 238 void IntCmd( uint32_t ulIntType, FunctionalState NewState);
eembed 0:5459cdde6298 239
eembed 0:5459cdde6298 240 /** Asserts specified interrupt in QEI peripheral
eembed 0:5459cdde6298 241 *
eembed 0:5459cdde6298 242 * @param[in] ulIntType Interrupt Flag Status type, should be:
eembed 0:5459cdde6298 243 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
eembed 0:5459cdde6298 244 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
eembed 0:5459cdde6298 245 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
eembed 0:5459cdde6298 246 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
eembed 0:5459cdde6298 247 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
eembed 0:5459cdde6298 248 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
eembed 0:5459cdde6298 249 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
eembed 0:5459cdde6298 250 current position interrupt
eembed 0:5459cdde6298 251 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
eembed 0:5459cdde6298 252 current position interrupt
eembed 0:5459cdde6298 253 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
eembed 0:5459cdde6298 254 current position interrupt
eembed 0:5459cdde6298 255 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
eembed 0:5459cdde6298 256 index count interrupt
eembed 0:5459cdde6298 257 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
eembed 0:5459cdde6298 258 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
eembed 0:5459cdde6298 259 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
eembed 0:5459cdde6298 260 * @return None
eembed 0:5459cdde6298 261 */
eembed 0:5459cdde6298 262 void IntSet( uint32_t ulIntType);
eembed 0:5459cdde6298 263
eembed 0:5459cdde6298 264 /** De-asserts specified interrupt (pending) in QEI peripheral
eembed 0:5459cdde6298 265 *
eembed 0:5459cdde6298 266 * @param[in] ulIntType Interrupt Flag Status type, should be:
eembed 0:5459cdde6298 267 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
eembed 0:5459cdde6298 268 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
eembed 0:5459cdde6298 269 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
eembed 0:5459cdde6298 270 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
eembed 0:5459cdde6298 271 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
eembed 0:5459cdde6298 272 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
eembed 0:5459cdde6298 273 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
eembed 0:5459cdde6298 274 current position interrupt
eembed 0:5459cdde6298 275 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
eembed 0:5459cdde6298 276 current position interrupt
eembed 0:5459cdde6298 277 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
eembed 0:5459cdde6298 278 current position interrupt
eembed 0:5459cdde6298 279 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
eembed 0:5459cdde6298 280 index count interrupt
eembed 0:5459cdde6298 281 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
eembed 0:5459cdde6298 282 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
eembed 0:5459cdde6298 283 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
eembed 0:5459cdde6298 284 * @return None
eembed 0:5459cdde6298 285 */
eembed 0:5459cdde6298 286 void IntClear( uint32_t ulIntType);
eembed 0:5459cdde6298 287
eembed 0:5459cdde6298 288 /** Append interrupt handler for specific QEI interrupt source
eembed 0:5459cdde6298 289 *
eembed 0:5459cdde6298 290 * @param[in] ulISRType Interrupt Flag Status type, should be:
eembed 0:5459cdde6298 291 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
eembed 0:5459cdde6298 292 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
eembed 0:5459cdde6298 293 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
eembed 0:5459cdde6298 294 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
eembed 0:5459cdde6298 295 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
eembed 0:5459cdde6298 296 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
eembed 0:5459cdde6298 297 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
eembed 0:5459cdde6298 298 * current position interrupt
eembed 0:5459cdde6298 299 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
eembed 0:5459cdde6298 300 * current position interrupt
eembed 0:5459cdde6298 301 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
eembed 0:5459cdde6298 302 * current position interrupt
eembed 0:5459cdde6298 303 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
eembed 0:5459cdde6298 304 * index count interrupt
eembed 0:5459cdde6298 305 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
eembed 0:5459cdde6298 306 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
eembed 0:5459cdde6298 307 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
eembed 0:5459cdde6298 308 *
eembed 0:5459cdde6298 309 * @return none
eembed 0:5459cdde6298 310 */
eembed 0:5459cdde6298 311 void AppendISR(uint32_t ulISRType, void(*fptr)(void));
eembed 0:5459cdde6298 312
eembed 0:5459cdde6298 313 /** Unappend interrupt handler for specific QEI interrupt source
eembed 0:5459cdde6298 314 *
eembed 0:5459cdde6298 315 * @param[in] ulISRType Interrupt Flag Status type, should be:
eembed 0:5459cdde6298 316 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
eembed 0:5459cdde6298 317 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
eembed 0:5459cdde6298 318 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
eembed 0:5459cdde6298 319 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
eembed 0:5459cdde6298 320 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
eembed 0:5459cdde6298 321 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
eembed 0:5459cdde6298 322 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
eembed 0:5459cdde6298 323 * current position interrupt
eembed 0:5459cdde6298 324 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
eembed 0:5459cdde6298 325 * current position interrupt
eembed 0:5459cdde6298 326 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
eembed 0:5459cdde6298 327 * current position interrupt
eembed 0:5459cdde6298 328 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
eembed 0:5459cdde6298 329 * index count interrupt
eembed 0:5459cdde6298 330 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
eembed 0:5459cdde6298 331 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
eembed 0:5459cdde6298 332 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
eembed 0:5459cdde6298 333 *
eembed 0:5459cdde6298 334 * @return none
eembed 0:5459cdde6298 335 */
eembed 0:5459cdde6298 336 void UnAppendISR(uint32_t ulISRType);
eembed 0:5459cdde6298 337
eembed 0:5459cdde6298 338
eembed 0:5459cdde6298 339 /**
eembed 0:5459cdde6298 340 * @brief Calculates the actual velocity in RPM passed via velocity
eembed 0:5459cdde6298 341 * capture value and Pulse Per Revolution (of the encoder) value
eembed 0:5459cdde6298 342 * parameter input.
eembed 0:5459cdde6298 343 *
eembed 0:5459cdde6298 344 * @param[in] ulVelCapValue Velocity capture input value that can
eembed 0:5459cdde6298 345 * be got from QEI_GetVelocityCap() function
eembed 0:5459cdde6298 346 * @param[in] ulPPR Pulse per round of encoder
eembed 0:5459cdde6298 347 * @return The actual value of velocity in RPM (Revolutions per minute)
eembed 0:5459cdde6298 348 */
eembed 0:5459cdde6298 349 uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR);
eembed 0:5459cdde6298 350
eembed 0:5459cdde6298 351
eembed 0:5459cdde6298 352 /* Public Macros -------------------------------------------------------------- */
eembed 0:5459cdde6298 353 /* QEI Reset types */
eembed 0:5459cdde6298 354 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
eembed 0:5459cdde6298 355 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
eembed 0:5459cdde6298 356 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
eembed 0:5459cdde6298 357 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
eembed 0:5459cdde6298 358
eembed 0:5459cdde6298 359 /* QEI Direction Invert Type Option */
eembed 0:5459cdde6298 360 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
eembed 0:5459cdde6298 361 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
eembed 0:5459cdde6298 362
eembed 0:5459cdde6298 363 /* QEI Signal Mode Option */
eembed 0:5459cdde6298 364 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
eembed 0:5459cdde6298 365 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
eembed 0:5459cdde6298 366
eembed 0:5459cdde6298 367 /* QEI Capture Mode Option */
eembed 0:5459cdde6298 368 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
eembed 0:5459cdde6298 369 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
eembed 0:5459cdde6298 370
eembed 0:5459cdde6298 371 /* QEI Invert Index Signal Option */
eembed 0:5459cdde6298 372 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
eembed 0:5459cdde6298 373 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
eembed 0:5459cdde6298 374
eembed 0:5459cdde6298 375 /* QEI timer reload option */
eembed 0:5459cdde6298 376 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
eembed 0:5459cdde6298 377 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
eembed 0:5459cdde6298 378
eembed 0:5459cdde6298 379 /* QEI Flag Status type */
eembed 0:5459cdde6298 380 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
eembed 0:5459cdde6298 381
eembed 0:5459cdde6298 382 /* QEI Compare Position channel option */
eembed 0:5459cdde6298 383 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
eembed 0:5459cdde6298 384 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
eembed 0:5459cdde6298 385 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
eembed 0:5459cdde6298 386
eembed 0:5459cdde6298 387 /* QEI interrupt flag type */
eembed 0:5459cdde6298 388 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
eembed 0:5459cdde6298 389 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
eembed 0:5459cdde6298 390 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
eembed 0:5459cdde6298 391 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
eembed 0:5459cdde6298 392 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
eembed 0:5459cdde6298 393 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
eembed 0:5459cdde6298 394 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
eembed 0:5459cdde6298 395 current position interrupt */
eembed 0:5459cdde6298 396 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
eembed 0:5459cdde6298 397 current position interrupt */
eembed 0:5459cdde6298 398 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
eembed 0:5459cdde6298 399 current position interrupt */
eembed 0:5459cdde6298 400 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
eembed 0:5459cdde6298 401 index count interrupt */
eembed 0:5459cdde6298 402 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
eembed 0:5459cdde6298 403 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
eembed 0:5459cdde6298 404 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
eembed 0:5459cdde6298 405
eembed 0:5459cdde6298 406 /* QEI Process position reporting options */
eembed 0:5459cdde6298 407 #define QEI_PROCESS_OPERATE 0;
eembed 0:5459cdde6298 408 #define QEI_PROCESS_RESET 1;
eembed 0:5459cdde6298 409 #define QEI_PROCESS_INCREMENTAL 0;
eembed 0:5459cdde6298 410 #define QEI_PROCESS_ACCUMULATE 1;
eembed 0:5459cdde6298 411 #define QEI_PROCESS_LINEAR 0;
eembed 0:5459cdde6298 412 #define QEI_PROCESS_WEIGHTED 1;
eembed 0:5459cdde6298 413
eembed 0:5459cdde6298 414 private:
eembed 0:5459cdde6298 415 static void _Qeiisr(void);
eembed 0:5459cdde6298 416 void Qeiisr(void);
eembed 0:5459cdde6298 417 static QEIHW *instance;
eembed 0:5459cdde6298 418
eembed 0:5459cdde6298 419 void(*_qei_isr[13])();
eembed 0:5459cdde6298 420
eembed 0:5459cdde6298 421
eembed 0:5459cdde6298 422 /* Private Macros ------------------------------------------------------------- */
eembed 0:5459cdde6298 423 /* --------------------- BIT DEFINITIONS -------------------------------------- */
eembed 0:5459cdde6298 424 /* Quadrature Encoder Interface Control Register Definition --------------------- */
eembed 0:5459cdde6298 425 /*********************************************************************//**
eembed 0:5459cdde6298 426 * Macro defines for QEI Control register
eembed 0:5459cdde6298 427 **********************************************************************/
eembed 0:5459cdde6298 428 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
eembed 0:5459cdde6298 429 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
eembed 0:5459cdde6298 430 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
eembed 0:5459cdde6298 431 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
eembed 0:5459cdde6298 432 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
eembed 0:5459cdde6298 433
eembed 0:5459cdde6298 434 /*********************************************************************//**
eembed 0:5459cdde6298 435 * Macro defines for QEI Configuration register
eembed 0:5459cdde6298 436 **********************************************************************/
eembed 0:5459cdde6298 437 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
eembed 0:5459cdde6298 438 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
eembed 0:5459cdde6298 439 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
eembed 0:5459cdde6298 440 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
eembed 0:5459cdde6298 441 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
eembed 0:5459cdde6298 442
eembed 0:5459cdde6298 443 /*********************************************************************//**
eembed 0:5459cdde6298 444 * Macro defines for QEI Status register
eembed 0:5459cdde6298 445 **********************************************************************/
eembed 0:5459cdde6298 446 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
eembed 0:5459cdde6298 447 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
eembed 0:5459cdde6298 448
eembed 0:5459cdde6298 449 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
eembed 0:5459cdde6298 450 /*********************************************************************//**
eembed 0:5459cdde6298 451 * Macro defines for QEI Interrupt Status register
eembed 0:5459cdde6298 452 **********************************************************************/
eembed 0:5459cdde6298 453 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
eembed 0:5459cdde6298 454 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
eembed 0:5459cdde6298 455 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
eembed 0:5459cdde6298 456 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
eembed 0:5459cdde6298 457 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
eembed 0:5459cdde6298 458 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
eembed 0:5459cdde6298 459 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
eembed 0:5459cdde6298 460 current position */
eembed 0:5459cdde6298 461 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
eembed 0:5459cdde6298 462 current position */
eembed 0:5459cdde6298 463 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
eembed 0:5459cdde6298 464 current position */
eembed 0:5459cdde6298 465 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
eembed 0:5459cdde6298 466 index count */
eembed 0:5459cdde6298 467 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
eembed 0:5459cdde6298 468 both the POS0_Int bit is set and the REV_Int is set */
eembed 0:5459cdde6298 469 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
eembed 0:5459cdde6298 470 both the POS1_Int bit is set and the REV_Int is set */
eembed 0:5459cdde6298 471 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
eembed 0:5459cdde6298 472 both the POS2_Int bit is set and the REV_Int is set */
eembed 0:5459cdde6298 473 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
eembed 0:5459cdde6298 474
eembed 0:5459cdde6298 475 /*********************************************************************//**
eembed 0:5459cdde6298 476 * Macro defines for QEI Interrupt Set register
eembed 0:5459cdde6298 477 **********************************************************************/
eembed 0:5459cdde6298 478 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
eembed 0:5459cdde6298 479 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
eembed 0:5459cdde6298 480 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
eembed 0:5459cdde6298 481 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
eembed 0:5459cdde6298 482 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
eembed 0:5459cdde6298 483 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
eembed 0:5459cdde6298 484 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
eembed 0:5459cdde6298 485 current position */
eembed 0:5459cdde6298 486 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
eembed 0:5459cdde6298 487 current position */
eembed 0:5459cdde6298 488 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
eembed 0:5459cdde6298 489 current position */
eembed 0:5459cdde6298 490 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
eembed 0:5459cdde6298 491 index count */
eembed 0:5459cdde6298 492 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
eembed 0:5459cdde6298 493 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
eembed 0:5459cdde6298 494 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
eembed 0:5459cdde6298 495 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
eembed 0:5459cdde6298 496
eembed 0:5459cdde6298 497 /*********************************************************************//**
eembed 0:5459cdde6298 498 * Macro defines for QEI Interrupt Clear register
eembed 0:5459cdde6298 499 **********************************************************************/
eembed 0:5459cdde6298 500 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
eembed 0:5459cdde6298 501 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
eembed 0:5459cdde6298 502 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
eembed 0:5459cdde6298 503 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
eembed 0:5459cdde6298 504 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
eembed 0:5459cdde6298 505 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
eembed 0:5459cdde6298 506 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
eembed 0:5459cdde6298 507 current position */
eembed 0:5459cdde6298 508 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
eembed 0:5459cdde6298 509 current position */
eembed 0:5459cdde6298 510 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
eembed 0:5459cdde6298 511 current position */
eembed 0:5459cdde6298 512 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
eembed 0:5459cdde6298 513 index count */
eembed 0:5459cdde6298 514 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
eembed 0:5459cdde6298 515 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
eembed 0:5459cdde6298 516 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
eembed 0:5459cdde6298 517 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
eembed 0:5459cdde6298 518
eembed 0:5459cdde6298 519 /*********************************************************************//**
eembed 0:5459cdde6298 520 * Macro defines for QEI Interrupt Enable register
eembed 0:5459cdde6298 521 **********************************************************************/
eembed 0:5459cdde6298 522 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
eembed 0:5459cdde6298 523 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
eembed 0:5459cdde6298 524 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
eembed 0:5459cdde6298 525 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
eembed 0:5459cdde6298 526 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
eembed 0:5459cdde6298 527 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
eembed 0:5459cdde6298 528 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
eembed 0:5459cdde6298 529 current position */
eembed 0:5459cdde6298 530 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
eembed 0:5459cdde6298 531 current position */
eembed 0:5459cdde6298 532 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
eembed 0:5459cdde6298 533 current position */
eembed 0:5459cdde6298 534 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
eembed 0:5459cdde6298 535 index count */
eembed 0:5459cdde6298 536 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
eembed 0:5459cdde6298 537 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
eembed 0:5459cdde6298 538 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
eembed 0:5459cdde6298 539 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
eembed 0:5459cdde6298 540
eembed 0:5459cdde6298 541 /*********************************************************************//**
eembed 0:5459cdde6298 542 * Macro defines for QEI Interrupt Enable Set register
eembed 0:5459cdde6298 543 **********************************************************************/
eembed 0:5459cdde6298 544 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
eembed 0:5459cdde6298 545 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
eembed 0:5459cdde6298 546 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
eembed 0:5459cdde6298 547 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
eembed 0:5459cdde6298 548 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
eembed 0:5459cdde6298 549 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
eembed 0:5459cdde6298 550 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
eembed 0:5459cdde6298 551 current position */
eembed 0:5459cdde6298 552 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
eembed 0:5459cdde6298 553 current position */
eembed 0:5459cdde6298 554 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
eembed 0:5459cdde6298 555 current position */
eembed 0:5459cdde6298 556 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
eembed 0:5459cdde6298 557 index count */
eembed 0:5459cdde6298 558 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
eembed 0:5459cdde6298 559 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
eembed 0:5459cdde6298 560 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
eembed 0:5459cdde6298 561 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
eembed 0:5459cdde6298 562
eembed 0:5459cdde6298 563 /*********************************************************************//**
eembed 0:5459cdde6298 564 * Macro defines for QEI Interrupt Enable Clear register
eembed 0:5459cdde6298 565 **********************************************************************/
eembed 0:5459cdde6298 566 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
eembed 0:5459cdde6298 567 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
eembed 0:5459cdde6298 568 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
eembed 0:5459cdde6298 569 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
eembed 0:5459cdde6298 570 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
eembed 0:5459cdde6298 571 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
eembed 0:5459cdde6298 572 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
eembed 0:5459cdde6298 573 current position */
eembed 0:5459cdde6298 574 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
eembed 0:5459cdde6298 575 current position */
eembed 0:5459cdde6298 576 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
eembed 0:5459cdde6298 577 current position */
eembed 0:5459cdde6298 578 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
eembed 0:5459cdde6298 579 index count */
eembed 0:5459cdde6298 580 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
eembed 0:5459cdde6298 581 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
eembed 0:5459cdde6298 582 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
eembed 0:5459cdde6298 583 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
eembed 0:5459cdde6298 584
eembed 0:5459cdde6298 585 /*********************************************************************//**
eembed 0:5459cdde6298 586 * Macro defines for PCONP register QEI-related bits
eembed 0:5459cdde6298 587 **********************************************************************/
eembed 0:5459cdde6298 588 #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
eembed 0:5459cdde6298 589 #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
eembed 0:5459cdde6298 590
eembed 0:5459cdde6298 591 /*********************************************************************//**
eembed 0:5459cdde6298 592 * Macro defines for PCLKSELx register QEI-related bits
eembed 0:5459cdde6298 593 **********************************************************************/
eembed 0:5459cdde6298 594 #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */
eembed 0:5459cdde6298 595 #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */
eembed 0:5459cdde6298 596 #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */
eembed 0:5459cdde6298 597 #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */
eembed 0:5459cdde6298 598 #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */
eembed 0:5459cdde6298 599 /*********************************************************************//**
eembed 0:5459cdde6298 600 * Macro defines for PINSEL3 register QEI-related bits
eembed 0:5459cdde6298 601 **********************************************************************/
eembed 0:5459cdde6298 602 #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */
eembed 0:5459cdde6298 603 #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */
eembed 0:5459cdde6298 604 #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */
eembed 0:5459cdde6298 605 #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */
eembed 0:5459cdde6298 606 #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */
eembed 0:5459cdde6298 607 #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */
eembed 0:5459cdde6298 608
eembed 0:5459cdde6298 609 /*********************************************************************//**
eembed 0:5459cdde6298 610 * Macro defines for PINMODE3 register QEI-related bits
eembed 0:5459cdde6298 611 **********************************************************************/
eembed 0:5459cdde6298 612 #define PIN_PULL_UP 0UL
eembed 0:5459cdde6298 613 #define PIN_REPEATER 1UL
eembed 0:5459cdde6298 614 #define PIN_NORESISTOR 2UL
eembed 0:5459cdde6298 615 #define PIN_PULL_DOWN 3UL
eembed 0:5459cdde6298 616
eembed 0:5459cdde6298 617 #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */
eembed 0:5459cdde6298 618 #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */
eembed 0:5459cdde6298 619 #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */
eembed 0:5459cdde6298 620
eembed 0:5459cdde6298 621 #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */
eembed 0:5459cdde6298 622 #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */
eembed 0:5459cdde6298 623 #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */
eembed 0:5459cdde6298 624
eembed 0:5459cdde6298 625 #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */
eembed 0:5459cdde6298 626 #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */
eembed 0:5459cdde6298 627 #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */
eembed 0:5459cdde6298 628
eembed 0:5459cdde6298 629 };
eembed 0:5459cdde6298 630
eembed 0:5459cdde6298 631
eembed 0:5459cdde6298 632 #endif /* MBED_QEI_H */
eembed 0:5459cdde6298 633 /* --------------------------------- End Of File ------------------------------ */