shubham c / Mbed 2 deprecated try1_transmitter_unlimited

RFM69hcw transmitter

Dependencies:   mbed

main.cpp@0:c4f462779168, 2014-07-16 (annotated)

Committer:
ee12b079
Date:
Wed Jul 16 14:11:45 2014 +0000
Revision:
0:c4f462779168
RFM69 transmitter with >66 bytes to inifite

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ee12b079 0:c4f462779168 1
ee12b079 0:c4f462779168 2 #include "mbed.h"
ee12b079 0:c4f462779168 3 Serial pc(USBTX, USBRX); // tx, rx
ee12b079 0:c4f462779168 4 SPI spi(p5, p6, p7); // mosi, miso, sclk
ee12b079 0:c4f462779168 5 DigitalOut cs(p8); //slave select or chip select
ee12b079 0:c4f462779168 6 #define TIMES 20
ee12b079 0:c4f462779168 7 #define HK_DATA_LEN 150//in bytes
ee12b079 0:c4f462779168 8 #define LAST HK_DATA_LEN/TIMES
ee12b079 0:c4f462779168 9 Timer t;
ee12b079 0:c4f462779168 10
ee12b079 0:c4f462779168 11 //Observations:
ee12b079 0:c4f462779168 12 //time taken to write 66 bytes to fifo with fifoaccessregister address sending with reading fifo_full once= 0.000218s
ee12b079 0:c4f462779168 13 //time taken to write 66 bytes to fifo with reading fifo_full once = 0.000215
ee12b079 0:c4f462779168 14 //time taken to write fifo_full once = 0.000009
ee12b079 0:c4f462779168 15 //time taken to print timer value = 0.000002
ee12b079 0:c4f462779168 16
ee12b079 0:c4f462779168 17 //results from above observations:
ee12b079 0:c4f462779168 18 //time taken to write 66 bytes to fifo with fifoaccessregister address = 0.000218-0.000011 = 0.000207
ee12b079 0:c4f462779168 19 //time taken to write one byte to fifo with fifoaccessregister address = 0.000207/66 = 0.000003s
ee12b079 0:c4f462779168 20
ee12b079 0:c4f462779168 21
ee12b079 0:c4f462779168 22 void writereg(uint8_t reg,uint8_t val)
ee12b079 0:c4f462779168 23 {
ee12b079 0:c4f462779168 24 cs = 0;
ee12b079 0:c4f462779168 25 __disable_irq();
ee12b079 0:c4f462779168 26 spi.write(reg | 0x80);
ee12b079 0:c4f462779168 27 spi.write(val);
ee12b079 0:c4f462779168 28 __enable_irq();
ee12b079 0:c4f462779168 29 cs = 1;
ee12b079 0:c4f462779168 30 }
ee12b079 0:c4f462779168 31 uint8_t readreg(uint8_t reg)
ee12b079 0:c4f462779168 32 {
ee12b079 0:c4f462779168 33 int val;
ee12b079 0:c4f462779168 34 cs = 0;
ee12b079 0:c4f462779168 35 __disable_irq();
ee12b079 0:c4f462779168 36 spi.write(reg & ~0x80);
ee12b079 0:c4f462779168 37 val = spi.write(0);
ee12b079 0:c4f462779168 38 __enable_irq();
ee12b079 0:c4f462779168 39 cs = 1;
ee12b079 0:c4f462779168 40 return val;
ee12b079 0:c4f462779168 41 }
ee12b079 0:c4f462779168 42
ee12b079 0:c4f462779168 43 int main() {
ee12b079 0:c4f462779168 44 wait(0.5);
ee12b079 0:c4f462779168 45 uint8_t fifo_full = 0x00,fifo_thresh;
ee12b079 0:c4f462779168 46 uint8_t hk[HK_DATA_LEN]; //starts from 0,1,2,3,4!!!
ee12b079 0:c4f462779168 47 //filling hk data
ee12b079 0:c4f462779168 48 for(int n=0; n<HK_DATA_LEN;n++)
ee12b079 0:c4f462779168 49 {
ee12b079 0:c4f462779168 50 if(n%10 == 0)
ee12b079 0:c4f462779168 51 hk[n] = 0xFF;
ee12b079 0:c4f462779168 52 else
ee12b079 0:c4f462779168 53 hk[n] = 0xAA;
ee12b079 0:c4f462779168 54 }
ee12b079 0:c4f462779168 55
ee12b079 0:c4f462779168 56 int i = 0; //for loops
ee12b079 0:c4f462779168 57 int u = 0; //universal count for hk array
ee12b079 0:c4f462779168 58 int bar = 0;
ee12b079 0:c4f462779168 59 uint8_t rval=0x00;
ee12b079 0:c4f462779168 60 cs = 1; // Chip must be deselected
ee12b079 0:c4f462779168 61
ee12b079 0:c4f462779168 62 spi.format(8,0);
ee12b079 0:c4f462779168 63 spi.frequency(10000000); //10MHz SCLK frequency(its max for rfm69hcw)
ee12b079 0:c4f462779168 64
ee12b079 0:c4f462779168 65 //initialization
ee12b079 0:c4f462779168 66
ee12b079 0:c4f462779168 67 //Common configuration registers
ee12b079 0:c4f462779168 68 writereg(0x01,0x04); //sequencer off,standby mode
ee12b079 0:c4f462779168 69 writereg(0x02,0x08); //packet, ook, no dc
ee12b079 0:c4f462779168 70 writereg(0x03,0x68); //1200bps
ee12b079 0:c4f462779168 71 writereg(0x04,0x2B); //1200bps
ee12b079 0:c4f462779168 72 writereg(0x07,0x6C);
ee12b079 0:c4f462779168 73 writereg(0x08,0xc0);
ee12b079 0:c4f462779168 74 writereg(0x09,0x00); //try 6C D0 0B for 435 MHZ //try 6C 40 00 for 432.something //try E4 C0 00 for 915
ee12b079 0:c4f462779168 75
ee12b079 0:c4f462779168 76
ee12b079 0:c4f462779168 77 //Transmitter registers
ee12b079 0:c4f462779168 78 // RegPaLevel
ee12b079 0:c4f462779168 79
ee12b079 0:c4f462779168 80 //IRQ and Pin Mapping Registers
ee12b079 0:c4f462779168 81 //no DIO mapped yet
ee12b079 0:c4f462779168 82 //irq1: modeready used
ee12b079 0:c4f462779168 83 //irq2: fifofull, fifothresh,packetsent used
ee12b079 0:c4f462779168 84
ee12b079 0:c4f462779168 85 //Packet Engine Registers
ee12b079 0:c4f462779168 86 writereg(0x2C,0x00); //set preamble
ee12b079 0:c4f462779168 87 writereg(0x2D,0x00); //set preamble
ee12b079 0:c4f462779168 88 writereg(0x2E,0x80);//sync on with 1 byte of stnc
ee12b079 0:c4f462779168 89 writereg(0x2F,0x5E);//sync word 1
ee12b079 0:c4f462779168 90 writereg(0x37,0x08);//Fixed length, on dc-free, no crc,issue packetready even if crc fails, no address filter
ee12b079 0:c4f462779168 91 writereg(0x38,0x00); //payload length = 0 ... unlimited payload mode
ee12b079 0:c4f462779168 92 writereg(0x3C,0x28); //fifothresh = 40
ee12b079 0:c4f462779168 93
ee12b079 0:c4f462779168 94 //Initialization complete
ee12b079 0:c4f462779168 95 //~~
ee12b079 0:c4f462779168 96 pc.printf("press 't' to transmit\n");
ee12b079 0:c4f462779168 97 while(pc.getc() == 't'){
ee12b079 0:c4f462779168 98 pc.printf("in");
ee12b079 0:c4f462779168 99 //Filling Data into FIFO ABOUT 66 BYTES //fread
ee12b079 0:c4f462779168 100 cs = 0;
ee12b079 0:c4f462779168 101 __disable_irq();
ee12b079 0:c4f462779168 102 spi.write(0x80);//fifo write access
ee12b079 0:c4f462779168 103 __enable_irq();
ee12b079 0:c4f462779168 104 for(i=0;i<66;i++)
ee12b079 0:c4f462779168 105 {
ee12b079 0:c4f462779168 106 __disable_irq();
ee12b079 0:c4f462779168 107 spi.write(hk[i]);
ee12b079 0:c4f462779168 108 __enable_irq();
ee12b079 0:c4f462779168 109 }
ee12b079 0:c4f462779168 110 u=i;//check its 66
ee12b079 0:c4f462779168 111 cs = 1;
ee12b079 0:c4f462779168 112
ee12b079 0:c4f462779168 113
ee12b079 0:c4f462779168 114 //check for fifofull
ee12b079 0:c4f462779168 115 while(fifo_full != 0x80){
ee12b079 0:c4f462779168 116 fifo_full = readreg(0x28);
ee12b079 0:c4f462779168 117 fifo_full = fifo_full & 0x80;
ee12b079 0:c4f462779168 118 }
ee12b079 0:c4f462779168 119
ee12b079 0:c4f462779168 120 //Highpower settings
ee12b079 0:c4f462779168 121 writereg(0x11,0x7F); //RegPalevel (20db) //~
ee12b079 0:c4f462779168 122 writereg(0x13,0x0F); //RegOCP
ee12b079 0:c4f462779168 123 writereg(0x5A,0x5D); //RegTestPa1
ee12b079 0:c4f462779168 124 writereg(0x5C,0x7C); //RegTestPa2
ee12b079 0:c4f462779168 125
ee12b079 0:c4f462779168 126 //Set to Tx mode
ee12b079 0:c4f462779168 127 writereg(0x01,0x0C);
ee12b079 0:c4f462779168 128
ee12b079 0:c4f462779168 129 //Check for fifoThresh
ee12b079 0:c4f462779168 130 fifo_thresh = 0x08;
ee12b079 0:c4f462779168 131 while(fifo_thresh != 0x00)
ee12b079 0:c4f462779168 132 {
ee12b079 0:c4f462779168 133 fifo_thresh = readreg(0x28);
ee12b079 0:c4f462779168 134 fifo_thresh = fifo_thresh & 0x20; //5th bit
ee12b079 0:c4f462779168 135 }
ee12b079 0:c4f462779168 136
ee12b079 0:c4f462779168 137 while(u!=HK_DATA_LEN){
ee12b079 0:c4f462779168 138
ee12b079 0:c4f462779168 139 if((HK_DATA_LEN - u) > TIMES) //==????
ee12b079 0:c4f462779168 140 bar = TIMES;
ee12b079 0:c4f462779168 141 else
ee12b079 0:c4f462779168 142 bar = (HK_DATA_LEN - u)%TIMES;
ee12b079 0:c4f462779168 143
ee12b079 0:c4f462779168 144 //writing again
ee12b079 0:c4f462779168 145 cs = 0;
ee12b079 0:c4f462779168 146 __disable_irq();
ee12b079 0:c4f462779168 147 spi.write(0x80);
ee12b079 0:c4f462779168 148 __enable_irq();
ee12b079 0:c4f462779168 149 for(i=0; i<bar;i++)
ee12b079 0:c4f462779168 150 {
ee12b079 0:c4f462779168 151 __disable_irq();
ee12b079 0:c4f462779168 152 spi.write(hk[u + i]);
ee12b079 0:c4f462779168 153 __enable_irq();
ee12b079 0:c4f462779168 154 }
ee12b079 0:c4f462779168 155 u = u + i;
ee12b079 0:c4f462779168 156 cs = 1;
ee12b079 0:c4f462779168 157
ee12b079 0:c4f462779168 158
ee12b079 0:c4f462779168 159 /*******/
ee12b079 0:c4f462779168 160 rval = readreg(0x28);
ee12b079 0:c4f462779168 161 rval = rval & 0x08;
ee12b079 0:c4f462779168 162 if(rval == 0x08)
ee12b079 0:c4f462779168 163 pc.printf("000\n",rval);
ee12b079 0:c4f462779168 164 /******/
ee12b079 0:c4f462779168 165
ee12b079 0:c4f462779168 166
ee12b079 0:c4f462779168 167
ee12b079 0:c4f462779168 168
ee12b079 0:c4f462779168 169
ee12b079 0:c4f462779168 170
ee12b079 0:c4f462779168 171
ee12b079 0:c4f462779168 172 //Check for fifoThresh
ee12b079 0:c4f462779168 173 fifo_thresh = 0x08;
ee12b079 0:c4f462779168 174 while(fifo_thresh != 0x00)
ee12b079 0:c4f462779168 175 {
ee12b079 0:c4f462779168 176 fifo_thresh = readreg(0x28);
ee12b079 0:c4f462779168 177 fifo_thresh = fifo_thresh & 0x20; //5th bit
ee12b079 0:c4f462779168 178 }
ee12b079 0:c4f462779168 179 }
ee12b079 0:c4f462779168 180
ee12b079 0:c4f462779168 181
ee12b079 0:c4f462779168 182 rval = 0;
ee12b079 0:c4f462779168 183 //Check if sent
ee12b079 0:c4f462779168 184 while(rval != 0x08)
ee12b079 0:c4f462779168 185 {
ee12b079 0:c4f462779168 186 rval = readreg(0x28);
ee12b079 0:c4f462779168 187 rval = rval & 0x08;
ee12b079 0:c4f462779168 188 pc.printf("sending... \n");
ee12b079 0:c4f462779168 189 }
ee12b079 0:c4f462779168 190
ee12b079 0:c4f462779168 191 rval = 0;
ee12b079 0:c4f462779168 192 pc.printf("packet sent!!! \n");
ee12b079 0:c4f462779168 193 pc.printf("%d",u);
ee12b079 0:c4f462779168 194 //Switch back to Standby Mode
ee12b079 0:c4f462779168 195 writereg(0x01,0x04);
ee12b079 0:c4f462779168 196 pc.printf("press 't' to transmit");
ee12b079 0:c4f462779168 197 //wait() to be changed while implementation
ee12b079 0:c4f462779168 198 }
ee12b079 0:c4f462779168 199
ee12b079 0:c4f462779168 200 //~~
ee12b079 0:c4f462779168 201 }