shubham c / Mbed 2 deprecated beacon_short

code for satellite (short) beacon

Dependencies:   mbed

main.cpp@0:16164bece7bc, 2014-09-10 (annotated)

Committer:
ee12b079
Date:
Wed Sep 10 17:21:39 2014 +0000
Revision:
0:16164bece7bc
modified code and libraries for m0+ uC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ee12b079 0:16164bece7bc 1 /*Algorithm (Assumption : 15 bytes of hk data with each bit stuffed 16 times, therefore info.rate = 75 bits and signalling rate = 1200bps)
ee12b079 0:16164bece7bc 2
ee12b079 0:16164bece7bc 3 I) Initialization
ee12b079 0:16164bece7bc 4 -A short_beacon array of 15 bytes = 120 bits (callsign + hk data) is initialized.
ee12b079 0:16164bece7bc 5 -A byte-counter variable is used to keep a count of the no. of eff. bytes written to FIFO
ee12b079 0:16164bece7bc 6 -FIFO THRESH VALUE is set to 48 bytes
ee12b079 0:16164bece7bc 7 II) Wrting to FIFO
ee12b079 0:16164bece7bc 8 1)First 64 bytes (32 eff. bits = 4 eff. bytes since each bit is repeated 16 times ) are written to FIFO, in following way :
ee12b079 0:16164bece7bc 9 i) A byte is read from short_beacon.
ee12b079 0:16164bece7bc 10 ii) Each bit from the byte is checked using pow() function.
ee12b079 0:16164bece7bc 11 iii) If the bit is 1(or 0), then 0xFF( or 0x00) is written to FIFO two times, since we want each bit to be repeated 16 times.
ee12b079 0:16164bece7bc 12 iv)process is continued till byte_counter reaches 4 bytes.
ee12b079 0:16164bece7bc 13 2)fifo_level bit is checked to check if the thresh of 48 bytes is crossed
ee12b079 0:16164bece7bc 14 i) 48 bytes are enough to start transmission.
ee12b079 0:16164bece7bc 15 III) Start Tx mode
ee12b079 0:16164bece7bc 16 1) We wait for bytes upto thresh to be transmitted
ee12b079 0:16164bece7bc 17 2) Again data is is filled in fifo with 16 bytes (1 eff. byte since each bit is repeated 16 times )
ee12b079 0:16164bece7bc 18 3) The above process is continued till byte_counter reaches 15 bytes
ee12b079 0:16164bece7bc 19 IV) Standby mode
ee12b079 0:16164bece7bc 20 1) We wait for packetsent interrupt to fire
ee12b079 0:16164bece7bc 21 2) Then the mode is switched back to Standby
ee12b079 0:16164bece7bc 22
ee12b079 0:16164bece7bc 23
ee12b079 0:16164bece7bc 24 Misc points ( included in testing ):
ee12b079 0:16164bece7bc 25 -An interrupt function (interrupt_func) was defined to check the effect of an external interrupt on the beacon and spi communication.
ee12b079 0:16164bece7bc 26 -A Timer was used to check the the time taken for transmission,
ee12b079 0:16164bece7bc 27 time taken for initialising regs = 0.016397s
ee12b079 0:16164bece7bc 28 time taken to transmit = 1.613444s (expected : 1.600000s with 1200 bps and 240 bytes packet length )
ee12b079 0:16164bece7bc 29 time taken to switch back to standby mode = 0.00166s
ee12b079 0:16164bece7bc 30 total = 1.631501s
ee12b079 0:16164bece7bc 31 -peak power consumption = 130 mA * 3.3 V = 429 mW (matches with datasheet)
ee12b079 0:16164bece7bc 32 (varies widely with data transmitted, above power measured when all bits transmitted are 1s)
ee12b079 0:16164bece7bc 33 -size of compiled and build file = 18,136 bytes ~ 17.7 KB
ee12b079 0:16164bece7bc 34 -pc.printf()s added only for testing
ee12b079 0:16164bece7bc 35 -
ee12b079 0:16164bece7bc 36 */
ee12b079 0:16164bece7bc 37 #include "beacon.h"
ee12b079 0:16164bece7bc 38 Serial pc(USBTX, USBRX); // tx, rx
ee12b079 0:16164bece7bc 39 SPI spi(D11, D12, D13); // mosi, miso, sclk
ee12b079 0:16164bece7bc 40 DigitalOut cs(D10); //slave select or chip select
ee12b079 0:16164bece7bc 41 //InterruptIn button(p9);
ee12b079 0:16164bece7bc 42 //Timer t;
ee12b079 0:16164bece7bc 43
ee12b079 0:16164bece7bc 44 /*void interrupt_func()
ee12b079 0:16164bece7bc 45 {
ee12b079 0:16164bece7bc 46 pc.printf("INTERRUPT_FUNC TRIGGERED\n wait for 3 secs\n");
ee12b079 0:16164bece7bc 47 wait(3);
ee12b079 0:16164bece7bc 48
ee12b079 0:16164bece7bc 49 }*/
ee12b079 0:16164bece7bc 50 void writereg(uint8_t reg,uint8_t val)
ee12b079 0:16164bece7bc 51 {
ee12b079 0:16164bece7bc 52 cs_bar = 0;
ee12b079 0:16164bece7bc 53 spi.write(reg | 0x80);
ee12b079 0:16164bece7bc 54 spi.write(val);
ee12b079 0:16164bece7bc 55 cs_bar = 1;
ee12b079 0:16164bece7bc 56 }
ee12b079 0:16164bece7bc 57 uint8_t readreg(uint8_t reg)
ee12b079 0:16164bece7bc 58 {
ee12b079 0:16164bece7bc 59 uint8_t val;
ee12b079 0:16164bece7bc 60 cs_bar = 0;
ee12b079 0:16164bece7bc 61 spi.write(reg & ~0x80);
ee12b079 0:16164bece7bc 62 val = spi.write(0);
ee12b079 0:16164bece7bc 63 cs_bar = 1;
ee12b079 0:16164bece7bc 64 return val;
ee12b079 0:16164bece7bc 65 }
ee12b079 0:16164bece7bc 66
ee12b079 0:16164bece7bc 67 void SHORT_BEACON() {
ee12b079 0:16164bece7bc 68
ee12b079 0:16164bece7bc 69 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9)
ee12b079 0:16164bece7bc 70 wait(0.02); //takes 10 ms for POR event + 10ms for surety
ee12b079 0:16164bece7bc 71 uint8_t byte_counter = 0;
ee12b079 0:16164bece7bc 72
ee12b079 0:16164bece7bc 73 ShortBeacy Shortbeacon;
ee12b079 0:16164bece7bc 74 //filling hk data
ee12b079 0:16164bece7bc 75 uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
ee12b079 0:16164bece7bc 76
ee12b079 0:16164bece7bc 77 //mask......not used to save memory instead pow() function used for masking
ee12b079 0:16164bece7bc 78 //uint8_t mask[] = {0x80, 0x40, 0x20,0x10,0x8,0x4,0x2,0x1};
ee12b079 0:16164bece7bc 79
ee12b079 0:16164bece7bc 80 spi.format(8,0);
ee12b079 0:16164bece7bc 81 spi.frequency(10000000); //10MHz SCLK frequency(its max for rfm69hcw)
ee12b079 0:16164bece7bc 82
ee12b079 0:16164bece7bc 83 cs_bar = 1; // Chip must be deselected
ee12b079 0:16164bece7bc 84
ee12b079 0:16164bece7bc 85 //initialization
ee12b079 0:16164bece7bc 86 //Common configuration registers
ee12b079 0:16164bece7bc 87 writereg(0x01,0x04); //sequencer on,standby mode
ee12b079 0:16164bece7bc 88 writereg(0x02,0x08); //packet-mode used , ook modultion , no dc-shaping
ee12b079 0:16164bece7bc 89 writereg(0x03,0x68); //1200bps datarate
ee12b079 0:16164bece7bc 90 writereg(0x04,0x2B); //1200bps datarate
ee12b079 0:16164bece7bc 91 writereg(0x07,0x6C); //Frequency MSB
ee12b079 0:16164bece7bc 92 writereg(0x08,0xC0); //Frequency MID
ee12b079 0:16164bece7bc 93 writereg(0x09,0x00); //Frequency LSB ....6C C0 00 for 435 MHZ
ee12b079 0:16164bece7bc 94
ee12b079 0:16164bece7bc 95 //Transmitter registers
ee12b079 0:16164bece7bc 96 // RegPaLevel(default +13 dBm)
ee12b079 0:16164bece7bc 97
ee12b079 0:16164bece7bc 98 //IRQ and Pin Mapping Registers
ee12b079 0:16164bece7bc 99 //no DIO mapped yet
ee12b079 0:16164bece7bc 100 //regirq1(0x27): modeready (8th bit) will be checked for interrupts
ee12b079 0:16164bece7bc 101 //regIrq2(0x28): fifothresh (5th bit) ,packetsent(3rd bit) will be checked for interrupts
ee12b079 0:16164bece7bc 102
ee12b079 0:16164bece7bc 103 //Packet Engine Registers
ee12b079 0:16164bece7bc 104 writereg(0x2C,0x00); //preamble length MSB = 0
ee12b079 0:16164bece7bc 105 writereg(0x2D,0x00); //preamble length LSB = 0
ee12b079 0:16164bece7bc 106
ee12b079 0:16164bece7bc 107 //preamble header needed while testing with RFM69HCW receiver
ee12b079 0:16164bece7bc 108 //writereg(0x2D,0x0A); //preamble length LSB = 10 bytes
ee12b079 0:16164bece7bc 109
ee12b079 0:16164bece7bc 110 writereg(0x2E,0x00); //sync off
ee12b079 0:16164bece7bc 111
ee12b079 0:16164bece7bc 112 //sync header needed while testing with RFM69HCW receiver
ee12b079 0:16164bece7bc 113 //writereg(0x2E,0x80); //sync on
ee12b079 0:16164bece7bc 114 //writereg(0x2F,0x5E); //sync word 1
ee12b079 0:16164bece7bc 115
ee12b079 0:16164bece7bc 116 writereg(0x37,0x08); //packetconfig1 : unlimited packet mode, no dc-free encoding, crc calculation disabled
ee12b079 0:16164bece7bc 117 writereg(0x38,0x00); //payload length = 0 // due to unlimited payload mode
ee12b079 0:16164bece7bc 118 writereg(0x3C,0xB0); //fifo_thresh = 48 ...fifo_level interrupt gets cleared once level goes 48 or below 48 and set once it goes above 48
ee12b079 0:16164bece7bc 119
ee12b079 0:16164bece7bc 120 //Initialization complete
ee12b079 0:16164bece7bc 121
ee12b079 0:16164bece7bc 122 //Initially 4 bytes are added
ee12b079 0:16164bece7bc 123 //Filling Data into FIFO 64 BYTES (eff.32 bits = 4 bytes)
ee12b079 0:16164bece7bc 124 cs_bar = 0;
ee12b079 0:16164bece7bc 125 spi.write(0x80);//fifo write access
ee12b079 0:16164bece7bc 126 for(byte_counter=0 ; byte_counter<4; byte_counter++)
ee12b079 0:16164bece7bc 127 {
ee12b079 0:16164bece7bc 128 for(int i = 0 , i < 8 ; i++)
ee12b079 0:16164bece7bc 129 //for(int i=7; i>=0 ; i--)
ee12b079 0:16164bece7bc 130 {
ee12b079 0:16164bece7bc 131 //if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
ee12b079 0:16164bece7bc 132 if((short_beacon[byte_counter] & mask(i)) != 0) //...........masking not used to save memory
ee12b079 0:16164bece7bc 133 {
ee12b079 0:16164bece7bc 134 spi.write(0xFF);
ee12b079 0:16164bece7bc 135 spi.write(0xFF); //writing twice since every bit is to be transmitted 16 times
ee12b079 0:16164bece7bc 136 }
ee12b079 0:16164bece7bc 137 else
ee12b079 0:16164bece7bc 138 {
ee12b079 0:16164bece7bc 139 spi.write(0x00);
ee12b079 0:16164bece7bc 140 spi.write(0x00);
ee12b079 0:16164bece7bc 141 }
ee12b079 0:16164bece7bc 142 }
ee12b079 0:16164bece7bc 143 }
ee12b079 0:16164bece7bc 144 cs_bar = 1;
ee12b079 0:16164bece7bc 145
ee12b079 0:16164bece7bc 146 //Check for fifoThresh ( 5th bit of 0x28 register should be set once fifo-level is above fifothresh)
ee12b079 0:16164bece7bc 147 while((readreg(0x28) & 0x20) != 0x20);
ee12b079 0:16164bece7bc 148
ee12b079 0:16164bece7bc 149 //Highpower settings
ee12b079 0:16164bece7bc 150 writereg(0x11,0x7F); //RegPalevel (20db) //~
ee12b079 0:16164bece7bc 151 writereg(0x13,0x0F); //RegOCP
ee12b079 0:16164bece7bc 152 writereg(0x5A,0x5D); //RegTestPa1
ee12b079 0:16164bece7bc 153 writereg(0x5C,0x7C); //RegTestPa2
ee12b079 0:16164bece7bc 154
ee12b079 0:16164bece7bc 155 //Set to Tx mode
ee12b079 0:16164bece7bc 156 writereg(0x01,0x0C);
ee12b079 0:16164bece7bc 157
ee12b079 0:16164bece7bc 158 //t.start();
ee12b079 0:16164bece7bc 159
ee12b079 0:16164bece7bc 160 //Check for fifoThresh
ee12b079 0:16164bece7bc 161 while((readreg(0x28) & 0x20) != 0x00); //( 5th bit of 0x28 register should be set once fifo-level goes below fifothresh)
ee12b079 0:16164bece7bc 162
ee12b079 0:16164bece7bc 163 for(;byte_counter<15;byte_counter++) //
ee12b079 0:16164bece7bc 164 {
ee12b079 0:16164bece7bc 165
ee12b079 0:16164bece7bc 166 //writing 1 eff. byte = 16 actual bytes( due to sttuffing)
ee12b079 0:16164bece7bc 167 cs_bar = 0;
ee12b079 0:16164bece7bc 168 spi.write(0x80);
ee12b079 0:16164bece7bc 169
ee12b079 0:16164bece7bc 170 for(int i = 0 , i < 8 ; i++)
ee12b079 0:16164bece7bc 171 //for(int i=7; i>=0 ;i--)
ee12b079 0:16164bece7bc 172 {
ee12b079 0:16164bece7bc 173 //if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
ee12b079 0:16164bece7bc 174 if((short_beacon[byte_counter] & mask(i)) != 0)//.........masking not used to save memory
ee12b079 0:16164bece7bc 175 {
ee12b079 0:16164bece7bc 176 spi.write(0xFF);
ee12b079 0:16164bece7bc 177 spi.write(0xFF);
ee12b079 0:16164bece7bc 178 }
ee12b079 0:16164bece7bc 179 else
ee12b079 0:16164bece7bc 180 {
ee12b079 0:16164bece7bc 181 spi.write(0x00);
ee12b079 0:16164bece7bc 182 spi.write(0x00);
ee12b079 0:16164bece7bc 183 }
ee12b079 0:16164bece7bc 184 }
ee12b079 0:16164bece7bc 185 cs_bar = 1;
ee12b079 0:16164bece7bc 186
ee12b079 0:16164bece7bc 187 //Check for fifoThresh
ee12b079 0:16164bece7bc 188 while((readreg(0x28) & 0x20) != 0x00);
ee12b079 0:16164bece7bc 189 }
ee12b079 0:16164bece7bc 190 //wait for packet sent bit to fire
ee12b079 0:16164bece7bc 191 while((readreg(0x28) & 0x08) != 0x08);
ee12b079 0:16164bece7bc 192 //t.stop();
ee12b079 0:16164bece7bc 193 //pc.printf("packet sent!!! \n");
ee12b079 0:16164bece7bc 194
ee12b079 0:16164bece7bc 195 //Switch back to Standby Mode
ee12b079 0:16164bece7bc 196 writereg(0x01,0x04);
ee12b079 0:16164bece7bc 197
ee12b079 0:16164bece7bc 198 //Lowpower settings
ee12b079 0:16164bece7bc 199 writereg(0x11,0x9F); //RegPalevel (13db)
ee12b079 0:16164bece7bc 200 writereg(0x13,0x1A); //RegOCP
ee12b079 0:16164bece7bc 201 writereg(0x5A,0x55); //RegTestPa1(setting PA_BOOST on RFIO)
ee12b079 0:16164bece7bc 202 writereg(0x5C,0x70); //RegTestPa2(setting PA_BOOST on RFIO)
ee12b079 0:16164bece7bc 203
ee12b079 0:16164bece7bc 204 //wait for modeready
ee12b079 0:16164bece7bc 205 while((readreg(0x27)&0x80)!=0x80);
ee12b079 0:16164bece7bc 206
ee12b079 0:16164bece7bc 207 //pc.printf("%f", t.read());
ee12b079 0:16164bece7bc 208 }