shubham c / Mbed 2 deprecated SBC_TEST_CDMS_CODE

CDMS code for testing sbc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

i2c.h@275:a2f1d544ab8b, 2016-07-24 (annotated)

Committer:
ee12b079
Date:
Sun Jul 24 12:15:03 2016 +0000
Revision:
275:a2f1d544ab8b
Parent:
209:63e9c8f8b5d2
Child:
215:6848a51af734
Child:
227:05e929bdd4dc
CDMS code for testing sbc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aniruddhv 52:0bd68655c651 1 #define tm_len 134
aniruddhv 52:0bd68655c651 2 #define tc_len 135
aniruddhv 52:0bd68655c651 3 #define tc_test_len 135
aniruddhv 52:0bd68655c651 4
aniruddhv 52:0bd68655c651 5 const int addr = 0x20; //slave address
ee12b079 161:a63672bf4423 6 bool write_ack = false;
ee12b079 161:a63672bf4423 7 bool read_ack = false;
ee12b079 161:a63672bf4423 8 const int addr_pl = 0x20<<1; //PL address
ee12b079 162:48fda0b8d573 9 const int addr_bae = 0x20; ///bae address
ee12b079 209:63e9c8f8b5d2 10 //uint8_t rcv_isr = 0;
aniruddhv 52:0bd68655c651 11
aniruddhv 52:0bd68655c651 12 int count = 0;
aniruddhv 52:0bd68655c651 13
ee12b079 161:a63672bf4423 14 char PL_I2C_DATA[134];//Payload i2c array
ee12b079 161:a63672bf4423 15 uint8_t PL_TM_SIZE;//size of data to bev read from i2c
ee12b079 209:63e9c8f8b5d2 16 uint32_t pdirr1;
ee12b079 209:63e9c8f8b5d2 17 uint32_t pdirw1;
aniruddhv 52:0bd68655c651 18
ee12b079 209:63e9c8f8b5d2 19 void I2C_busreset()
ee12b079 209:63e9c8f8b5d2 20 {
ee12b079 209:63e9c8f8b5d2 21 PORTE->PCR[1] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 22 PORTE->PCR[0] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 23 I2C0->C1 &= 0x7f; //Disabling I2C module
ee12b079 209:63e9c8f8b5d2 24 SIM->SCGC4 &= 0xffffffbf; //Disabling clock to I2C module
ee12b079 209:63e9c8f8b5d2 25 SIM->SCGC4 |= 0x00000040; //Enabling clock to I2C module
ee12b079 209:63e9c8f8b5d2 26 I2C0->C1 |= 0x80; //Enabling I2C module
ee12b079 209:63e9c8f8b5d2 27 PORTE->PCR[1] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 28 PORTE->PCR[0] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 29 Thread::wait(1); //Wait for all I2C registers to be updates to their their values
ee12b079 209:63e9c8f8b5d2 30 }
ee12b079 209:63e9c8f8b5d2 31 bool FCTN_I2C_READ_PL(char *data,int length) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 32 {
ee12b079 209:63e9c8f8b5d2 33 PL_I2C_GPIO = 1;
ee12b079 184:d75cea6f5d49 34 read_ack = master.read(addr_pl|1,data,length);
ee12b079 209:63e9c8f8b5d2 35 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 36 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 37 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 38 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
ee12b079 209:63e9c8f8b5d2 39 {
ee12b079 209:63e9c8f8b5d2 40 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
ee12b079 209:63e9c8f8b5d2 41 {
ee12b079 209:63e9c8f8b5d2 42 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 43 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 44 i2c_count++;
ee12b079 209:63e9c8f8b5d2 45 }
ee12b079 209:63e9c8f8b5d2 46 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
ee12b079 209:63e9c8f8b5d2 47 {
ee12b079 209:63e9c8f8b5d2 48 gPC.printf("\n\rData received from BAE");
ee12b079 209:63e9c8f8b5d2 49 }
ee12b079 209:63e9c8f8b5d2 50 else
ee12b079 209:63e9c8f8b5d2 51 {
ee12b079 209:63e9c8f8b5d2 52 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 53 read_ack = 1;
ee12b079 209:63e9c8f8b5d2 54 }
ee12b079 209:63e9c8f8b5d2 55 }
ee12b079 209:63e9c8f8b5d2 56 else if (read_ack == 1)
ee12b079 184:d75cea6f5d49 57 {
ee12b079 209:63e9c8f8b5d2 58 I2C_busreset();
ee12b079 184:d75cea6f5d49 59 }
ee12b079 209:63e9c8f8b5d2 60 PL_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 61 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 62 return read_ack;
ee12b079 209:63e9c8f8b5d2 63
ee12b079 184:d75cea6f5d49 64 }
ee12b079 209:63e9c8f8b5d2 65 bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 66 {
ee12b079 209:63e9c8f8b5d2 67 write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload
ee12b079 209:63e9c8f8b5d2 68 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 69 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 70 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 71 if(write_ack == 0)
ee12b079 209:63e9c8f8b5d2 72 {
ee12b079 209:63e9c8f8b5d2 73 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
ee12b079 209:63e9c8f8b5d2 74 {
ee12b079 209:63e9c8f8b5d2 75 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 76 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 77 i2c_count++;
ee12b079 209:63e9c8f8b5d2 78 }
ee12b079 209:63e9c8f8b5d2 79 if(((pdirw1 & 0x03000000)==0x03000000))
ee12b079 209:63e9c8f8b5d2 80 {
ee12b079 209:63e9c8f8b5d2 81 gPC.printf("\n\r Data sent");
ee12b079 209:63e9c8f8b5d2 82 }
ee12b079 209:63e9c8f8b5d2 83 else
ee12b079 209:63e9c8f8b5d2 84 {
ee12b079 209:63e9c8f8b5d2 85 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 86 write_ack = 1;
ee12b079 209:63e9c8f8b5d2 87 }
ee12b079 209:63e9c8f8b5d2 88 }
ee12b079 209:63e9c8f8b5d2 89 if (write_ack == 1)
ee12b079 209:63e9c8f8b5d2 90 {
ee12b079 209:63e9c8f8b5d2 91 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 92 }
ee12b079 209:63e9c8f8b5d2 93 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 94 return write_ack;
ee12b079 209:63e9c8f8b5d2 95 }
ee12b079 209:63e9c8f8b5d2 96 bool FCTN_I2C_READ(char *data,int length) // Returns 0 for success
ee12b079 162:48fda0b8d573 97 {
ee12b079 162:48fda0b8d573 98 CDMS_I2C_GPIO = 1;
ee12b079 162:48fda0b8d573 99 read_ack = master.read(addr_bae|1,data,length);
ee12b079 209:63e9c8f8b5d2 100 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 101 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 102 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 103 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
ee12b079 162:48fda0b8d573 104 {
ee12b079 209:63e9c8f8b5d2 105 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
ee12b079 209:63e9c8f8b5d2 106 {
ee12b079 209:63e9c8f8b5d2 107 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 108 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 109 i2c_count++;
ee12b079 209:63e9c8f8b5d2 110 }
ee12b079 209:63e9c8f8b5d2 111 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
ee12b079 209:63e9c8f8b5d2 112 {
ee12b079 209:63e9c8f8b5d2 113 gPC.printf("\n\rData received from BAE");
ee12b079 209:63e9c8f8b5d2 114 }
ee12b079 209:63e9c8f8b5d2 115 else
ee12b079 209:63e9c8f8b5d2 116 {
ee12b079 209:63e9c8f8b5d2 117 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 118 read_ack = 1;
ee12b079 209:63e9c8f8b5d2 119 }
ee12b079 162:48fda0b8d573 120 }
ee12b079 209:63e9c8f8b5d2 121 else if (read_ack == 1)
ee12b079 209:63e9c8f8b5d2 122 {
ee12b079 209:63e9c8f8b5d2 123 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 124 }
ee12b079 162:48fda0b8d573 125 CDMS_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 126 i2c_count = 0;
ee12b079 198:17200a427e71 127 return read_ack;
ee12b079 162:48fda0b8d573 128 }
ee12b079 162:48fda0b8d573 129
ee12b079 209:63e9c8f8b5d2 130 bool FCTN_I2C_WRITE(char *data,int tc_len2) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 131 {
ee12b079 162:48fda0b8d573 132 CDMS_I2C_GPIO = 1;
ee12b079 209:63e9c8f8b5d2 133 write_ack = master.write(addr_bae|0x00,data,tc_len2);
ee12b079 209:63e9c8f8b5d2 134 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 135 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 136 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 137 if(write_ack == 0)
ee12b079 162:48fda0b8d573 138 {
ee12b079 209:63e9c8f8b5d2 139 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
ee12b079 209:63e9c8f8b5d2 140 {
ee12b079 209:63e9c8f8b5d2 141 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 142 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 143 i2c_count++;
ee12b079 209:63e9c8f8b5d2 144 }
ee12b079 209:63e9c8f8b5d2 145 if(((pdirw1 & 0x03000000)==0x03000000))
ee12b079 209:63e9c8f8b5d2 146 {
ee12b079 209:63e9c8f8b5d2 147 gPC.printf("\n\r Data sent");
ee12b079 209:63e9c8f8b5d2 148 }
ee12b079 209:63e9c8f8b5d2 149 else
ee12b079 209:63e9c8f8b5d2 150 {
ee12b079 209:63e9c8f8b5d2 151 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 152 write_ack = 1;
ee12b079 209:63e9c8f8b5d2 153 }
ee12b079 209:63e9c8f8b5d2 154 }
ee12b079 209:63e9c8f8b5d2 155 if (write_ack == 1)
ee12b079 209:63e9c8f8b5d2 156 {
ee12b079 209:63e9c8f8b5d2 157 I2C_busreset();
ee12b079 162:48fda0b8d573 158 }
ee12b079 162:48fda0b8d573 159 CDMS_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 160 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 161 return write_ack;
aniruddhv 52:0bd68655c651 162 }