shubham c / Mbed 2 deprecated SBC_TEST_CDMS_CODE

CDMS code for testing sbc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

i2c.h@215:6848a51af734, 2016-07-03 (annotated)

Committer:
chaithanyarss
Date:
Sun Jul 03 09:33:33 2016 +0000
Revision:
215:6848a51af734
Parent:
209:63e9c8f8b5d2
Child:
220:2aeab83212e6
Reset CDMS added;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aniruddhv 52:0bd68655c651 1 #define tm_len 134
aniruddhv 52:0bd68655c651 2 #define tc_len 135
aniruddhv 52:0bd68655c651 3 #define tc_test_len 135
aniruddhv 52:0bd68655c651 4
aniruddhv 52:0bd68655c651 5 const int addr = 0x20; //slave address
ee12b079 161:a63672bf4423 6 bool write_ack = false;
ee12b079 161:a63672bf4423 7 bool read_ack = false;
ee12b079 161:a63672bf4423 8 const int addr_pl = 0x20<<1; //PL address
ee12b079 162:48fda0b8d573 9 const int addr_bae = 0x20; ///bae address
ee12b079 209:63e9c8f8b5d2 10 //uint8_t rcv_isr = 0;
aniruddhv 52:0bd68655c651 11
aniruddhv 52:0bd68655c651 12 int count = 0;
aniruddhv 52:0bd68655c651 13
ee12b079 161:a63672bf4423 14 char PL_I2C_DATA[134];//Payload i2c array
ee12b079 161:a63672bf4423 15 uint8_t PL_TM_SIZE;//size of data to bev read from i2c
ee12b079 209:63e9c8f8b5d2 16 uint32_t pdirr1;
ee12b079 209:63e9c8f8b5d2 17 uint32_t pdirw1;
aniruddhv 52:0bd68655c651 18
ee12b079 209:63e9c8f8b5d2 19 void I2C_busreset()
ee12b079 209:63e9c8f8b5d2 20 {
ee12b079 209:63e9c8f8b5d2 21 PORTE->PCR[1] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 22 PORTE->PCR[0] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 23 I2C0->C1 &= 0x7f; //Disabling I2C module
ee12b079 209:63e9c8f8b5d2 24 SIM->SCGC4 &= 0xffffffbf; //Disabling clock to I2C module
ee12b079 209:63e9c8f8b5d2 25 SIM->SCGC4 |= 0x00000040; //Enabling clock to I2C module
ee12b079 209:63e9c8f8b5d2 26 I2C0->C1 |= 0x80; //Enabling I2C module
ee12b079 209:63e9c8f8b5d2 27 PORTE->PCR[1] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 28 PORTE->PCR[0] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
chaithanyarss 215:6848a51af734 29 wait_ms(1); //Wait for all I2C registers to be updates to their their values
ee12b079 209:63e9c8f8b5d2 30 }
ee12b079 209:63e9c8f8b5d2 31 bool FCTN_I2C_READ_PL(char *data,int length) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 32 {
ee12b079 209:63e9c8f8b5d2 33 PL_I2C_GPIO = 1;
ee12b079 184:d75cea6f5d49 34 read_ack = master.read(addr_pl|1,data,length);
chaithanyarss 215:6848a51af734 35 wait_ms(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 36 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 37 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 38 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
ee12b079 209:63e9c8f8b5d2 39 {
ee12b079 209:63e9c8f8b5d2 40 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
ee12b079 209:63e9c8f8b5d2 41 {
chaithanyarss 215:6848a51af734 42 wait_ms(1);
ee12b079 209:63e9c8f8b5d2 43 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 44 i2c_count++;
ee12b079 209:63e9c8f8b5d2 45 }
ee12b079 209:63e9c8f8b5d2 46 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
ee12b079 209:63e9c8f8b5d2 47 {
chaithanyarss 215:6848a51af734 48 TIME_LATEST_I2C_SPEED = FCTN_CDMS_RD_RTC() >> 7;
chaithanyarss 215:6848a51af734 49 gPC.printf("\n\rData received from PL");
ee12b079 209:63e9c8f8b5d2 50 }
ee12b079 209:63e9c8f8b5d2 51 else
chaithanyarss 215:6848a51af734 52 {
chaithanyarss 215:6848a51af734 53 CDMS_I2C_ERR_SPEED_COUNTER++;
ee12b079 209:63e9c8f8b5d2 54 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 55 read_ack = 1;
ee12b079 209:63e9c8f8b5d2 56 }
ee12b079 209:63e9c8f8b5d2 57 }
ee12b079 209:63e9c8f8b5d2 58 else if (read_ack == 1)
ee12b079 184:d75cea6f5d49 59 {
ee12b079 209:63e9c8f8b5d2 60 I2C_busreset();
ee12b079 184:d75cea6f5d49 61 }
ee12b079 209:63e9c8f8b5d2 62 PL_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 63 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 64 return read_ack;
ee12b079 209:63e9c8f8b5d2 65
ee12b079 184:d75cea6f5d49 66 }
ee12b079 209:63e9c8f8b5d2 67 bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 68 {
ee12b079 209:63e9c8f8b5d2 69 write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload
chaithanyarss 215:6848a51af734 70 wait_ms(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 71 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 72 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 73 if(write_ack == 0)
ee12b079 209:63e9c8f8b5d2 74 {
ee12b079 209:63e9c8f8b5d2 75 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
ee12b079 209:63e9c8f8b5d2 76 {
chaithanyarss 215:6848a51af734 77 wait_ms(1);
ee12b079 209:63e9c8f8b5d2 78 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 79 i2c_count++;
ee12b079 209:63e9c8f8b5d2 80 }
ee12b079 209:63e9c8f8b5d2 81 if(((pdirw1 & 0x03000000)==0x03000000))
ee12b079 209:63e9c8f8b5d2 82 {
chaithanyarss 215:6848a51af734 83 TIME_LATEST_I2C_SPEED = FCTN_CDMS_RD_RTC() >> 7;
chaithanyarss 215:6848a51af734 84 gPC.printf("\n\r Data sent to PL");
ee12b079 209:63e9c8f8b5d2 85 }
ee12b079 209:63e9c8f8b5d2 86 else
ee12b079 209:63e9c8f8b5d2 87 {
chaithanyarss 215:6848a51af734 88 CDMS_I2C_ERR_SPEED_COUNTER++;
ee12b079 209:63e9c8f8b5d2 89 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 90 write_ack = 1;
ee12b079 209:63e9c8f8b5d2 91 }
ee12b079 209:63e9c8f8b5d2 92 }
ee12b079 209:63e9c8f8b5d2 93 if (write_ack == 1)
ee12b079 209:63e9c8f8b5d2 94 {
ee12b079 209:63e9c8f8b5d2 95 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 96 }
ee12b079 209:63e9c8f8b5d2 97 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 98 return write_ack;
ee12b079 209:63e9c8f8b5d2 99 }
ee12b079 209:63e9c8f8b5d2 100 bool FCTN_I2C_READ(char *data,int length) // Returns 0 for success
ee12b079 162:48fda0b8d573 101 {
ee12b079 162:48fda0b8d573 102 CDMS_I2C_GPIO = 1;
ee12b079 162:48fda0b8d573 103 read_ack = master.read(addr_bae|1,data,length);
chaithanyarss 215:6848a51af734 104 wait_ms(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 105 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 106 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 107 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
ee12b079 162:48fda0b8d573 108 {
ee12b079 209:63e9c8f8b5d2 109 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
ee12b079 209:63e9c8f8b5d2 110 {
chaithanyarss 215:6848a51af734 111 wait_ms(1);
ee12b079 209:63e9c8f8b5d2 112 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 113 i2c_count++;
ee12b079 209:63e9c8f8b5d2 114 }
ee12b079 209:63e9c8f8b5d2 115 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
ee12b079 209:63e9c8f8b5d2 116 {
chaithanyarss 215:6848a51af734 117 TIME_LATEST_I2C_BAE = FCTN_CDMS_RD_RTC() >> 7;
ee12b079 209:63e9c8f8b5d2 118 gPC.printf("\n\rData received from BAE");
ee12b079 209:63e9c8f8b5d2 119 }
ee12b079 209:63e9c8f8b5d2 120 else
chaithanyarss 215:6848a51af734 121 {
chaithanyarss 215:6848a51af734 122 CDMS_I2C_ERR_BAE_COUNTER++;
ee12b079 209:63e9c8f8b5d2 123 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 124 read_ack = 1;
ee12b079 209:63e9c8f8b5d2 125 }
ee12b079 162:48fda0b8d573 126 }
ee12b079 209:63e9c8f8b5d2 127 else if (read_ack == 1)
ee12b079 209:63e9c8f8b5d2 128 {
ee12b079 209:63e9c8f8b5d2 129 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 130 }
ee12b079 162:48fda0b8d573 131 CDMS_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 132 i2c_count = 0;
ee12b079 198:17200a427e71 133 return read_ack;
ee12b079 162:48fda0b8d573 134 }
ee12b079 162:48fda0b8d573 135
ee12b079 209:63e9c8f8b5d2 136 bool FCTN_I2C_WRITE(char *data,int tc_len2) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 137 {
ee12b079 162:48fda0b8d573 138 CDMS_I2C_GPIO = 1;
ee12b079 209:63e9c8f8b5d2 139 write_ack = master.write(addr_bae|0x00,data,tc_len2);
chaithanyarss 215:6848a51af734 140 wait_ms(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 141 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 142 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 143 if(write_ack == 0)
ee12b079 162:48fda0b8d573 144 {
ee12b079 209:63e9c8f8b5d2 145 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
ee12b079 209:63e9c8f8b5d2 146 {
chaithanyarss 215:6848a51af734 147 wait_ms(1);
ee12b079 209:63e9c8f8b5d2 148 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 149 i2c_count++;
ee12b079 209:63e9c8f8b5d2 150 }
ee12b079 209:63e9c8f8b5d2 151 if(((pdirw1 & 0x03000000)==0x03000000))
ee12b079 209:63e9c8f8b5d2 152 {
chaithanyarss 215:6848a51af734 153 TIME_LATEST_I2C_BAE = FCTN_CDMS_RD_RTC() >> 7;
chaithanyarss 215:6848a51af734 154 gPC.printf("\n\r Data sent BAE");
ee12b079 209:63e9c8f8b5d2 155 }
ee12b079 209:63e9c8f8b5d2 156 else
ee12b079 209:63e9c8f8b5d2 157 {
chaithanyarss 215:6848a51af734 158 CDMS_I2C_ERR_BAE_COUNTER++;
ee12b079 209:63e9c8f8b5d2 159 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 160 write_ack = 1;
ee12b079 209:63e9c8f8b5d2 161 }
ee12b079 209:63e9c8f8b5d2 162 }
ee12b079 209:63e9c8f8b5d2 163 if (write_ack == 1)
ee12b079 209:63e9c8f8b5d2 164 {
ee12b079 209:63e9c8f8b5d2 165 I2C_busreset();
ee12b079 162:48fda0b8d573 166 }
ee12b079 162:48fda0b8d573 167 CDMS_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 168 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 169 return write_ack;
aniruddhv 52:0bd68655c651 170 }