iyhda

Dependencies:   mbed

Files at this revision

API Documentation at this revision

Comitter:
ee12b079
Date:
Fri Feb 06 15:58:37 2015 +0000
Parent:
0:c793eb8100c9
Commit message:
For BAE integration

Changed in this revision

main.cpp Show annotated file Show diff for this revision Revisions of this file
mbed.bld Show annotated file Show diff for this revision Revisions of this file
diff -r c793eb8100c9 -r 2b6cdf97b912 main.cpp
--- a/main.cpp	Tue Jul 15 09:29:35 2014 +0000
+++ b/main.cpp	Fri Feb 06 15:58:37 2015 +0000
@@ -5,7 +5,7 @@
 //sync word ....callsign
 //don't wait for sync_match!!!!!!!!!!!!!!!
 
-/*
+/*f
 regIrq2(0x28) :
 
 regpacketconfig 1(0x37) :
@@ -18,8 +18,8 @@
 #include "mbed.h"
 #define TIMES 20
 Serial pc(USBTX, USBRX);           // tx, rx
-SPI spi(p11, p12, p13);               // mosi, miso, sclk
-DigitalOut cs(p8);                 //slave select or chip select
+SPI spi(D11, D12, D13);               // mosi, miso, sclk
+DigitalOut cs(D10);                 //slave select or chip select
 
 void writereg(uint8_t reg,uint8_t val)
 {
@@ -51,20 +51,27 @@
     int u = 0;
     int hk_data_len = 240;
     uint8_t hk[240];
+    
+       if (readreg(0x15) == 0xB0) pc.printf("spi connection valid\n");
+    else {pc.printf("error in spi connection\n"); wait(10); }
+    
     //initialization
-    
+    //pc.printf("0x%X",readreg(0x01));
     //Common configuration registers
-    writereg(0x01,0x04);       //sequencer off,standby mode
-    writereg(0x02,0x08);// | 0x01);       //packet, ook, no dc
+    writereg(0x01,0x00);       //sequencer off,standby mode
+    writereg(0x02,0x08);// | 0x01);       //packet, ook, no dc           //0x00 for fsk   //default = 0x08 for ook
     writereg(0x03,0x68);       //1200bps
     writereg(0x04,0x2B);       //1200bps
+    /*writereg(0x03,0x03);       //38.4kbps
+    writereg(0x04,0x41);       //38.4kbps*/
+    
     writereg(0x07,0x6C);       
     writereg(0x08,0xC0);
-    writereg(0x09,0x00);       //try 6C D0 0B for 435 MHZ    //try 6C 40 00 for 432.something            //try E4 C0 00 for 915   //6C D6 73 for 435.1Mhz
+    writereg(0x09,0x00);       //try 6C C0 00 for 435 MHZ    //try 6C 40 00 for 432.something            //try E4 C0 00 for 915   //6C D6 73 for 435.1Mhz
                                // 6D1015 for 436 MHZ
     //rx registers
     writereg(0x18,0x08);       //RegLNA using agc
-    writereg(0x19,0x42);       //Regrxbw (data is successfully received  from 5.2 khz onwards for 1200bps)
+    writereg(0x19,0x51);       //Regrxbw (data is successfully received  from 5.2 khz onwards for 1200bps)
                                //keep it as 0x51 for 83.3kHz, 0x42 for 62.5kHz, 0x49 for 100 kHz, 0x40 for 250khz, 57 for 1.3khz, 56 for 2.6khz  
                                //46 for 3.9khz
     
@@ -73,15 +80,18 @@
     //irq1: modeready, rssi, syncaddressmatch used.
     //irq2: fifonnotempty, payloadready used.
     //rssi thresh is default = -117 dbm
-    writereg(0x29,180);       //rssi_thresh = -110 (0x6E)          //0xB4 for -180       //0x96 for -150dBm
+    writereg(0x29,0xB4);       //rssi_thresh = -110 (0x6E)          //0xB4 for -180       //0x96 for -150dBm
                                //0x78 for -120
     
     //Packet Engine Registers
     writereg(0x2C,0x00);
     writereg(0x2D,0x0A);//preamblesize = 10 bytes
+//    writereg(0x2E,0x80);//sync on , FIFO filling condition : if SyncAddress interrupt occurs
     writereg(0x2E,0x80);//sync on , FIFO filling condition : if SyncAddress interrupt occurs
-    writereg(0x2F,0x5E);//sync word 1
-    writereg(0x37,0x08 | 0x40) ;//| 0x10);//Fixed length, on dc-free, no crc,issue packetready even if crc fails, no address filter
+    writereg(0x2F,0x5e);//sync word 1
+//    writereg(0x30,0x23);//sync word 1
+//    writereg(0x31,0x45);//sync word 1
+    writereg(0x37,0x08| 0x10);//| 0x40);//Fixed length, on dc-free(0x40), no crc(0x10),issue packetready even if crc fails, no address filter
     writereg(0x38,0x00);//payload_length= 0 due to unlimited packet mode
     writereg(0x3C,0x27);//fifothresh is 39 because we want it to be set when it reaches 40
     
@@ -97,14 +107,14 @@
     pc.printf("receiver is on, ready to accept.....\n");
     
     //wait for rssi to cross rssi_thresh
-    while((readreg(0x27)& 0x08) != 0x08);//{pc.printf("w:rssi\n");} 
+    while((readreg(0x27)& 0x08) != 0x08)pc.printf("w:rssi\n"); 
 
     //wait for SyncAddressMatch 
-    while((readreg(0x27) & 0x01) != 0x01);//{pc.printf("w:sync\n");}
+    while((readreg(0x27) & 0x01) != 0x01)pc.printf("w:sync\n");
      
     //pc.printf("receiving.....\n");
     //check for fifo_thresh
-    while((readreg(0x28) & 0x20) != 0x20);//{pc.printf("w:fifo_thresh\n");} 
+    while((readreg(0x28) & 0x20) != 0x20)pc.printf("w:fifo_thresh\n"); 
         
     while(bar == TIMES)//fifo_thresh
     {                
@@ -141,8 +151,8 @@
     for (; u < hk_data_len  ; u++)
     hk[u] = spi.write(0);
     cs = 1;
-    pc.printf("shortbeacon[] : \n");
-    
+    pc.printf("Received data:\n");
+    //for(int i=0;i<240;i++) pc.printf("0x%X",hk[i]);
     // converting uint_8 to bool
     bool shortbeacon[120];
     for(int i = 0; i<120; i++)
diff -r c793eb8100c9 -r 2b6cdf97b912 mbed.bld
--- a/mbed.bld	Tue Jul 15 09:29:35 2014 +0000
+++ b/mbed.bld	Fri Feb 06 15:58:37 2015 +0000
@@ -1,1 +1,1 @@
-http://mbed.org/users/mbed_official/code/mbed/builds/04dd9b1680ae
\ No newline at end of file
+http://mbed.org/users/mbed_official/code/mbed/builds/4fc01daae5a5
\ No newline at end of file