shubham c / Mbed 2 deprecated Beacon_final_receiver

iyhda

Dependencies:   mbed

main.cpp@1:2b6cdf97b912, 2015-02-06 (annotated)

Committer:
ee12b079
Date:
Fri Feb 06 15:58:37 2015 +0000
Revision:
1:2b6cdf97b912
Parent:
0:c793eb8100c9 
For BAE integration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ee12b079 0:c793eb8100c9 1 //changed the receiver bandwidth to 83.3 khz
ee12b079 0:c793eb8100c9 2 //experiment on bandwidth stuff
ee12b079 0:c793eb8100c9 3 //shaping in transmitter
ee12b079 0:c793eb8100c9 4 //rssi thresh, etc.
ee12b079 0:c793eb8100c9 5 //sync word ....callsign
ee12b079 0:c793eb8100c9 6 //don't wait for sync_match!!!!!!!!!!!!!!!
ee12b079 0:c793eb8100c9 7
ee12b079 1:2b6cdf97b912 8 /*f
ee12b079 0:c793eb8100c9 9 regIrq2(0x28) :
ee12b079 0:c793eb8100c9 10
ee12b079 0:c793eb8100c9 11 regpacketconfig 1(0x37) :
ee12b079 0:c793eb8100c9 12 set crc detection/calc. on : | 0x10
ee12b079 0:c793eb8100c9 13 crcautoclearoff : | 0x08
ee12b079 0:c793eb8100c9 14
ee12b079 0:c793eb8100c9 15 for data whitening : regpacketconfig 1(0x37) :| 0x40
ee12b079 0:c793eb8100c9 16 */
ee12b079 0:c793eb8100c9 17
ee12b079 0:c793eb8100c9 18 #include "mbed.h"
ee12b079 0:c793eb8100c9 19 #define TIMES 20
ee12b079 0:c793eb8100c9 20 Serial pc(USBTX, USBRX); // tx, rx
ee12b079 1:2b6cdf97b912 21 SPI spi(D11, D12, D13); // mosi, miso, sclk
ee12b079 1:2b6cdf97b912 22 DigitalOut cs(D10); //slave select or chip select
ee12b079 0:c793eb8100c9 23
ee12b079 0:c793eb8100c9 24 void writereg(uint8_t reg,uint8_t val)
ee12b079 0:c793eb8100c9 25 {
ee12b079 0:c793eb8100c9 26 cs = 0;
ee12b079 0:c793eb8100c9 27 __disable_irq();
ee12b079 0:c793eb8100c9 28 spi.write(reg | 0x80);
ee12b079 0:c793eb8100c9 29 spi.write(val);
ee12b079 0:c793eb8100c9 30 __enable_irq();
ee12b079 0:c793eb8100c9 31 cs = 1;
ee12b079 0:c793eb8100c9 32 }
ee12b079 0:c793eb8100c9 33 uint8_t readreg(uint8_t reg)
ee12b079 0:c793eb8100c9 34 {
ee12b079 0:c793eb8100c9 35 int val;
ee12b079 0:c793eb8100c9 36 cs = 0;
ee12b079 0:c793eb8100c9 37 __disable_irq();
ee12b079 0:c793eb8100c9 38 spi.write(reg & ~0x80);
ee12b079 0:c793eb8100c9 39 val = spi.write(0);
ee12b079 0:c793eb8100c9 40 __enable_irq();
ee12b079 0:c793eb8100c9 41 cs = 1;
ee12b079 0:c793eb8100c9 42 return val;
ee12b079 0:c793eb8100c9 43 }
ee12b079 0:c793eb8100c9 44
ee12b079 0:c793eb8100c9 45 int main(){
ee12b079 0:c793eb8100c9 46 wait(0.1); //wait for POR to complete
ee12b079 0:c793eb8100c9 47 cs = 1; // Chip must be deselected
ee12b079 0:c793eb8100c9 48 int bar = TIMES;
ee12b079 0:c793eb8100c9 49 spi.format(8,0);
ee12b079 0:c793eb8100c9 50 spi.frequency(10000000); //10MHz SCLK frequency(its max for rfm69hcw)
ee12b079 0:c793eb8100c9 51 int u = 0;
ee12b079 0:c793eb8100c9 52 int hk_data_len = 240;
ee12b079 0:c793eb8100c9 53 uint8_t hk[240];
ee12b079 1:2b6cdf97b912 54
ee12b079 1:2b6cdf97b912 55 if (readreg(0x15) == 0xB0) pc.printf("spi connection valid\n");
ee12b079 1:2b6cdf97b912 56 else {pc.printf("error in spi connection\n"); wait(10); }
ee12b079 1:2b6cdf97b912 57
ee12b079 0:c793eb8100c9 58 //initialization
ee12b079 1:2b6cdf97b912 59 //pc.printf("0x%X",readreg(0x01));
ee12b079 0:c793eb8100c9 60 //Common configuration registers
ee12b079 1:2b6cdf97b912 61 writereg(0x01,0x00); //sequencer off,standby mode
ee12b079 1:2b6cdf97b912 62 writereg(0x02,0x08);// | 0x01); //packet, ook, no dc //0x00 for fsk //default = 0x08 for ook
ee12b079 0:c793eb8100c9 63 writereg(0x03,0x68); //1200bps
ee12b079 0:c793eb8100c9 64 writereg(0x04,0x2B); //1200bps
ee12b079 1:2b6cdf97b912 65 /*writereg(0x03,0x03); //38.4kbps
ee12b079 1:2b6cdf97b912 66 writereg(0x04,0x41); //38.4kbps*/
ee12b079 1:2b6cdf97b912 67
ee12b079 0:c793eb8100c9 68 writereg(0x07,0x6C);
ee12b079 0:c793eb8100c9 69 writereg(0x08,0xC0);
ee12b079 1:2b6cdf97b912 70 writereg(0x09,0x00); //try 6C C0 00 for 435 MHZ //try 6C 40 00 for 432.something //try E4 C0 00 for 915 //6C D6 73 for 435.1Mhz
ee12b079 0:c793eb8100c9 71 // 6D1015 for 436 MHZ
ee12b079 0:c793eb8100c9 72 //rx registers
ee12b079 0:c793eb8100c9 73 writereg(0x18,0x08); //RegLNA using agc
ee12b079 1:2b6cdf97b912 74 writereg(0x19,0x51); //Regrxbw (data is successfully received from 5.2 khz onwards for 1200bps)
ee12b079 0:c793eb8100c9 75 //keep it as 0x51 for 83.3kHz, 0x42 for 62.5kHz, 0x49 for 100 kHz, 0x40 for 250khz, 57 for 1.3khz, 56 for 2.6khz
ee12b079 0:c793eb8100c9 76 //46 for 3.9khz
ee12b079 0:c793eb8100c9 77
ee12b079 0:c793eb8100c9 78
ee12b079 0:c793eb8100c9 79 //IRQ and pin mapping
ee12b079 0:c793eb8100c9 80 //irq1: modeready, rssi, syncaddressmatch used.
ee12b079 0:c793eb8100c9 81 //irq2: fifonnotempty, payloadready used.
ee12b079 0:c793eb8100c9 82 //rssi thresh is default = -117 dbm
ee12b079 1:2b6cdf97b912 83 writereg(0x29,0xB4); //rssi_thresh = -110 (0x6E) //0xB4 for -180 //0x96 for -150dBm
ee12b079 0:c793eb8100c9 84 //0x78 for -120
ee12b079 0:c793eb8100c9 85
ee12b079 0:c793eb8100c9 86 //Packet Engine Registers
ee12b079 0:c793eb8100c9 87 writereg(0x2C,0x00);
ee12b079 0:c793eb8100c9 88 writereg(0x2D,0x0A);//preamblesize = 10 bytes
ee12b079 1:2b6cdf97b912 89 // writereg(0x2E,0x80);//sync on , FIFO filling condition : if SyncAddress interrupt occurs
ee12b079 0:c793eb8100c9 90 writereg(0x2E,0x80);//sync on , FIFO filling condition : if SyncAddress interrupt occurs
ee12b079 1:2b6cdf97b912 91 writereg(0x2F,0x5e);//sync word 1
ee12b079 1:2b6cdf97b912 92 // writereg(0x30,0x23);//sync word 1
ee12b079 1:2b6cdf97b912 93 // writereg(0x31,0x45);//sync word 1
ee12b079 1:2b6cdf97b912 94 writereg(0x37,0x08| 0x10);//| 0x40);//Fixed length, on dc-free(0x40), no crc(0x10),issue packetready even if crc fails, no address filter
ee12b079 0:c793eb8100c9 95 writereg(0x38,0x00);//payload_length= 0 due to unlimited packet mode
ee12b079 0:c793eb8100c9 96 writereg(0x3C,0x27);//fifothresh is 39 because we want it to be set when it reaches 40
ee12b079 0:c793eb8100c9 97
ee12b079 0:c793eb8100c9 98 pc.printf("press 'r' to start receiver\n");
ee12b079 0:c793eb8100c9 99 while(pc.getc()== 'r'){
ee12b079 0:c793eb8100c9 100 //force rx in WAIT mode
ee12b079 0:c793eb8100c9 101 writereg(0x3D,0x04);//avoid rx deadlocks
ee12b079 0:c793eb8100c9 102 //set to Rx mode
ee12b079 0:c793eb8100c9 103 writereg(0x01,0x10);
ee12b079 0:c793eb8100c9 104
ee12b079 0:c793eb8100c9 105 //wait for modeready
ee12b079 0:c793eb8100c9 106 while((readreg(0x27)&0x80)!=0x80);
ee12b079 0:c793eb8100c9 107 pc.printf("receiver is on, ready to accept.....\n");
ee12b079 0:c793eb8100c9 108
ee12b079 0:c793eb8100c9 109 //wait for rssi to cross rssi_thresh
ee12b079 1:2b6cdf97b912 110 while((readreg(0x27)& 0x08) != 0x08)pc.printf("w:rssi\n");
ee12b079 0:c793eb8100c9 111
ee12b079 0:c793eb8100c9 112 //wait for SyncAddressMatch
ee12b079 1:2b6cdf97b912 113 while((readreg(0x27) & 0x01) != 0x01)pc.printf("w:sync\n");
ee12b079 0:c793eb8100c9 114
ee12b079 0:c793eb8100c9 115 //pc.printf("receiving.....\n");
ee12b079 0:c793eb8100c9 116 //check for fifo_thresh
ee12b079 1:2b6cdf97b912 117 while((readreg(0x28) & 0x20) != 0x20)pc.printf("w:fifo_thresh\n");
ee12b079 0:c793eb8100c9 118
ee12b079 0:c793eb8100c9 119 while(bar == TIMES)//fifo_thresh
ee12b079 0:c793eb8100c9 120 {
ee12b079 0:c793eb8100c9 121 if((hk_data_len - u - 40) >= TIMES)
ee12b079 0:c793eb8100c9 122 bar = TIMES;
ee12b079 0:c793eb8100c9 123 else
ee12b079 0:c793eb8100c9 124 bar = (hk_data_len - u - 40)%TIMES;
ee12b079 0:c793eb8100c9 125 //reading
ee12b079 0:c793eb8100c9 126 cs = 0;
ee12b079 0:c793eb8100c9 127 spi.write(0x00);
ee12b079 0:c793eb8100c9 128 for(int i=0; i<TIMES;i++,u++)
ee12b079 0:c793eb8100c9 129 hk[u] = spi.write(0);
ee12b079 0:c793eb8100c9 130 cs = 1;
ee12b079 0:c793eb8100c9 131 //check for fifo_thresh
ee12b079 0:c793eb8100c9 132 while((readreg(0x28) & 0x20) != 0x20);
ee12b079 0:c793eb8100c9 133 }
ee12b079 0:c793eb8100c9 134 //Check if received
ee12b079 0:c793eb8100c9 135 //while((readreg(0x28) & 0x04) != 0x04);.......donno why not getting fired!!!!!!!
ee12b079 0:c793eb8100c9 136
ee12b079 0:c793eb8100c9 137 //check for fifo_thresh!!!!!
ee12b079 0:c793eb8100c9 138 while((readreg(0x28) & 0x20) != 0x20);
ee12b079 0:c793eb8100c9 139
ee12b079 0:c793eb8100c9 140 pc.printf("\n\npacket received!!! \n\n");
ee12b079 0:c793eb8100c9 141
ee12b079 0:c793eb8100c9 142 wait(1);
ee12b079 0:c793eb8100c9 143 //Switch back to Standby Mode
ee12b079 0:c793eb8100c9 144 writereg(0x01,0x04);
ee12b079 0:c793eb8100c9 145 //wait for modeready
ee12b079 0:c793eb8100c9 146 while((readreg(0x27)&0x80)!=0x80);
ee12b079 0:c793eb8100c9 147
ee12b079 0:c793eb8100c9 148 //reading remaining 40 bytes
ee12b079 0:c793eb8100c9 149 cs = 0;
ee12b079 0:c793eb8100c9 150 spi.write(0x00);
ee12b079 0:c793eb8100c9 151 for (; u < hk_data_len ; u++)
ee12b079 0:c793eb8100c9 152 hk[u] = spi.write(0);
ee12b079 0:c793eb8100c9 153 cs = 1;
ee12b079 1:2b6cdf97b912 154 pc.printf("Received data:\n");
ee12b079 1:2b6cdf97b912 155 //for(int i=0;i<240;i++) pc.printf("0x%X",hk[i]);
ee12b079 0:c793eb8100c9 156 // converting uint_8 to bool
ee12b079 0:c793eb8100c9 157 bool shortbeacon[120];
ee12b079 0:c793eb8100c9 158 for(int i = 0; i<120; i++)
ee12b079 0:c793eb8100c9 159 hk[2*i] == 0xFF ? shortbeacon[i] = 1 :shortbeacon[i] = 0;
ee12b079 0:c793eb8100c9 160 /*for(int i = 0; i<120 ; i++)
ee12b079 0:c793eb8100c9 161 pc.printf(" %d \n",shortbeacon[i]);*/
ee12b079 0:c793eb8100c9 162
ee12b079 0:c793eb8100c9 163 //converting bool to uint_8
ee12b079 0:c793eb8100c9 164 uint8_t s_beacon[15];
ee12b079 0:c793eb8100c9 165 for(int i = 0, m =0 ; i < 15 ; i++ )
ee12b079 0:c793eb8100c9 166 for(int n = 0; n < 8; n++,m++)
ee12b079 0:c793eb8100c9 167 {
ee12b079 0:c793eb8100c9 168 if(shortbeacon[m])
ee12b079 0:c793eb8100c9 169 {
ee12b079 0:c793eb8100c9 170 s_beacon[i]<<=1;
ee12b079 0:c793eb8100c9 171 s_beacon[i] |= 0x01;
ee12b079 0:c793eb8100c9 172 }
ee12b079 0:c793eb8100c9 173 else
ee12b079 0:c793eb8100c9 174 s_beacon[i] <<= 1;
ee12b079 0:c793eb8100c9 175 }
ee12b079 0:c793eb8100c9 176
ee12b079 0:c793eb8100c9 177
ee12b079 0:c793eb8100c9 178 pc.printf("Call Sign : ");
ee12b079 0:c793eb8100c9 179 for(int i = 0; i<7 ; i++)
ee12b079 0:c793eb8100c9 180 pc.printf(" %X ",s_beacon[i]);
ee12b079 0:c793eb8100c9 181
ee12b079 0:c793eb8100c9 182 pc.printf("\n\nVoltage[0] : ");
ee12b079 0:c793eb8100c9 183 pc.printf(" 0x%X \n\n",s_beacon[7]);
ee12b079 0:c793eb8100c9 184
ee12b079 0:c793eb8100c9 185 pc.printf("AngularSpeed[0] : ");
ee12b079 0:c793eb8100c9 186 pc.printf(" 0x%X \n\n",s_beacon[8]);
ee12b079 0:c793eb8100c9 187
ee12b079 0:c793eb8100c9 188 pc.printf("AngularSpeed[1] : ");
ee12b079 0:c793eb8100c9 189 pc.printf(" 0x%X \n\n",s_beacon[9]);
ee12b079 0:c793eb8100c9 190
ee12b079 0:c793eb8100c9 191 pc.printf("SubsystemStatus[0] : ");
ee12b079 0:c793eb8100c9 192 pc.printf(" 0x%X \n\n",s_beacon[10]);
ee12b079 0:c793eb8100c9 193
ee12b079 0:c793eb8100c9 194 pc.printf("Temp[0] : ");
ee12b079 0:c793eb8100c9 195 pc.printf(" 0x%X \n\n",s_beacon[11]);
ee12b079 0:c793eb8100c9 196
ee12b079 0:c793eb8100c9 197 pc.printf("Temp[1] : ");
ee12b079 0:c793eb8100c9 198 pc.printf(" 0x%X \n\n",s_beacon[12]);
ee12b079 0:c793eb8100c9 199
ee12b079 0:c793eb8100c9 200 pc.printf("Temp[2] : ");
ee12b079 0:c793eb8100c9 201 pc.printf(" 0x%X \n\n",s_beacon[13]);
ee12b079 0:c793eb8100c9 202
ee12b079 0:c793eb8100c9 203 pc.printf("ErrorFlag[0] : ");
ee12b079 0:c793eb8100c9 204 pc.printf(" 0x%X \n\n",s_beacon[14]);
ee12b079 0:c793eb8100c9 205
ee12b079 0:c793eb8100c9 206 }
ee12b079 0:c793eb8100c9 207 }