mbed library sources
Dependents: FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more
targets/hal/TARGET_STM/TARGET_STM32F4XX/us_ticker.c@0:6bc4ac881c8e, 2016-07-28 (annotated)
- Committer:
- ebrus
- Date:
- Thu Jul 28 15:56:34 2016 +0000
- Revision:
- 0:6bc4ac881c8e
1;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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ebrus | 0:6bc4ac881c8e | 1 | /* mbed Microcontroller Library |
ebrus | 0:6bc4ac881c8e | 2 | * Copyright (c) 2006-2013 ARM Limited |
ebrus | 0:6bc4ac881c8e | 3 | * |
ebrus | 0:6bc4ac881c8e | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
ebrus | 0:6bc4ac881c8e | 5 | * you may not use this file except in compliance with the License. |
ebrus | 0:6bc4ac881c8e | 6 | * You may obtain a copy of the License at |
ebrus | 0:6bc4ac881c8e | 7 | * |
ebrus | 0:6bc4ac881c8e | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
ebrus | 0:6bc4ac881c8e | 9 | * |
ebrus | 0:6bc4ac881c8e | 10 | * Unless required by applicable law or agreed to in writing, software |
ebrus | 0:6bc4ac881c8e | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
ebrus | 0:6bc4ac881c8e | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
ebrus | 0:6bc4ac881c8e | 13 | * See the License for the specific language governing permissions and |
ebrus | 0:6bc4ac881c8e | 14 | * limitations under the License. |
ebrus | 0:6bc4ac881c8e | 15 | */ |
ebrus | 0:6bc4ac881c8e | 16 | #include <stddef.h> |
ebrus | 0:6bc4ac881c8e | 17 | #include "us_ticker_api.h" |
ebrus | 0:6bc4ac881c8e | 18 | #include "PeripheralNames.h" |
ebrus | 0:6bc4ac881c8e | 19 | |
ebrus | 0:6bc4ac881c8e | 20 | #define US_TICKER_TIMER TIM2 |
ebrus | 0:6bc4ac881c8e | 21 | #define US_TICKER_TIMER_IRQn TIM2_IRQn |
ebrus | 0:6bc4ac881c8e | 22 | |
ebrus | 0:6bc4ac881c8e | 23 | int us_ticker_inited = 0; |
ebrus | 0:6bc4ac881c8e | 24 | |
ebrus | 0:6bc4ac881c8e | 25 | void us_ticker_init(void) { |
ebrus | 0:6bc4ac881c8e | 26 | if (us_ticker_inited) return; |
ebrus | 0:6bc4ac881c8e | 27 | us_ticker_inited = 1; |
ebrus | 0:6bc4ac881c8e | 28 | |
ebrus | 0:6bc4ac881c8e | 29 | RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; |
ebrus | 0:6bc4ac881c8e | 30 | |
ebrus | 0:6bc4ac881c8e | 31 | uint32_t PCLK = SystemCoreClock / 4; |
ebrus | 0:6bc4ac881c8e | 32 | |
ebrus | 0:6bc4ac881c8e | 33 | uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) |
ebrus | 0:6bc4ac881c8e | 34 | US_TICKER_TIMER->PSC = prescale - 1; |
ebrus | 0:6bc4ac881c8e | 35 | US_TICKER_TIMER->CR1 |= TIM_CR1_CEN; |
ebrus | 0:6bc4ac881c8e | 36 | // Trigger an update - this needs to happen after the counter is enabled. |
ebrus | 0:6bc4ac881c8e | 37 | US_TICKER_TIMER->EGR |= TIM_EGR_UG; |
ebrus | 0:6bc4ac881c8e | 38 | |
ebrus | 0:6bc4ac881c8e | 39 | NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); |
ebrus | 0:6bc4ac881c8e | 40 | NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
ebrus | 0:6bc4ac881c8e | 41 | } |
ebrus | 0:6bc4ac881c8e | 42 | |
ebrus | 0:6bc4ac881c8e | 43 | uint32_t us_ticker_read() { |
ebrus | 0:6bc4ac881c8e | 44 | if (!us_ticker_inited) |
ebrus | 0:6bc4ac881c8e | 45 | us_ticker_init(); |
ebrus | 0:6bc4ac881c8e | 46 | |
ebrus | 0:6bc4ac881c8e | 47 | return US_TICKER_TIMER->CNT; |
ebrus | 0:6bc4ac881c8e | 48 | } |
ebrus | 0:6bc4ac881c8e | 49 | |
ebrus | 0:6bc4ac881c8e | 50 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
ebrus | 0:6bc4ac881c8e | 51 | // set match value |
ebrus | 0:6bc4ac881c8e | 52 | US_TICKER_TIMER->CCR1 = (uint32_t)timestamp; |
ebrus | 0:6bc4ac881c8e | 53 | // enable compare interrupt |
ebrus | 0:6bc4ac881c8e | 54 | US_TICKER_TIMER->DIER |= TIM_DIER_CC1IE; |
ebrus | 0:6bc4ac881c8e | 55 | } |
ebrus | 0:6bc4ac881c8e | 56 | |
ebrus | 0:6bc4ac881c8e | 57 | void us_ticker_disable_interrupt(void) { |
ebrus | 0:6bc4ac881c8e | 58 | US_TICKER_TIMER->DIER &= ~TIM_DIER_CC1IE; |
ebrus | 0:6bc4ac881c8e | 59 | } |
ebrus | 0:6bc4ac881c8e | 60 | |
ebrus | 0:6bc4ac881c8e | 61 | void us_ticker_clear_interrupt(void) { |
ebrus | 0:6bc4ac881c8e | 62 | US_TICKER_TIMER->SR &= ~TIM_SR_CC1IF; |
ebrus | 0:6bc4ac881c8e | 63 | } |