mbed library sources
Dependents: FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more
targets/hal/TARGET_STM/TARGET_STM32F407VG/pinmap.c@0:6bc4ac881c8e, 2016-07-28 (annotated)
- Committer:
- ebrus
- Date:
- Thu Jul 28 15:56:34 2016 +0000
- Revision:
- 0:6bc4ac881c8e
1;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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ebrus | 0:6bc4ac881c8e | 1 | /* mbed Microcontroller Library |
ebrus | 0:6bc4ac881c8e | 2 | ******************************************************************************* |
ebrus | 0:6bc4ac881c8e | 3 | * Copyright (c) 2014, STMicroelectronics |
ebrus | 0:6bc4ac881c8e | 4 | * All rights reserved. |
ebrus | 0:6bc4ac881c8e | 5 | * |
ebrus | 0:6bc4ac881c8e | 6 | * Redistribution and use in source and binary forms, with or without |
ebrus | 0:6bc4ac881c8e | 7 | * modification, are permitted provided that the following conditions are met: |
ebrus | 0:6bc4ac881c8e | 8 | * |
ebrus | 0:6bc4ac881c8e | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
ebrus | 0:6bc4ac881c8e | 10 | * this list of conditions and the following disclaimer. |
ebrus | 0:6bc4ac881c8e | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
ebrus | 0:6bc4ac881c8e | 12 | * this list of conditions and the following disclaimer in the documentation |
ebrus | 0:6bc4ac881c8e | 13 | * and/or other materials provided with the distribution. |
ebrus | 0:6bc4ac881c8e | 14 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
ebrus | 0:6bc4ac881c8e | 15 | * may be used to endorse or promote products derived from this software |
ebrus | 0:6bc4ac881c8e | 16 | * without specific prior written permission. |
ebrus | 0:6bc4ac881c8e | 17 | * |
ebrus | 0:6bc4ac881c8e | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
ebrus | 0:6bc4ac881c8e | 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
ebrus | 0:6bc4ac881c8e | 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
ebrus | 0:6bc4ac881c8e | 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
ebrus | 0:6bc4ac881c8e | 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
ebrus | 0:6bc4ac881c8e | 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
ebrus | 0:6bc4ac881c8e | 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
ebrus | 0:6bc4ac881c8e | 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
ebrus | 0:6bc4ac881c8e | 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
ebrus | 0:6bc4ac881c8e | 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
ebrus | 0:6bc4ac881c8e | 28 | ******************************************************************************* |
ebrus | 0:6bc4ac881c8e | 29 | */ |
ebrus | 0:6bc4ac881c8e | 30 | #include "mbed_assert.h" |
ebrus | 0:6bc4ac881c8e | 31 | #include "pinmap.h" |
ebrus | 0:6bc4ac881c8e | 32 | #include "PortNames.h" |
ebrus | 0:6bc4ac881c8e | 33 | #include "mbed_error.h" |
ebrus | 0:6bc4ac881c8e | 34 | |
ebrus | 0:6bc4ac881c8e | 35 | // GPIO mode look-up table |
ebrus | 0:6bc4ac881c8e | 36 | static const uint32_t gpio_mode[13] = { |
ebrus | 0:6bc4ac881c8e | 37 | 0x00000000, // 0 = GPIO_MODE_INPUT |
ebrus | 0:6bc4ac881c8e | 38 | 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP |
ebrus | 0:6bc4ac881c8e | 39 | 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD |
ebrus | 0:6bc4ac881c8e | 40 | 0x00000002, // 3 = GPIO_MODE_AF_PP |
ebrus | 0:6bc4ac881c8e | 41 | 0x00000012, // 4 = GPIO_MODE_AF_OD |
ebrus | 0:6bc4ac881c8e | 42 | 0x00000003, // 5 = GPIO_MODE_ANALOG |
ebrus | 0:6bc4ac881c8e | 43 | 0x10110000, // 6 = GPIO_MODE_IT_RISING |
ebrus | 0:6bc4ac881c8e | 44 | 0x10210000, // 7 = GPIO_MODE_IT_FALLING |
ebrus | 0:6bc4ac881c8e | 45 | 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING |
ebrus | 0:6bc4ac881c8e | 46 | 0x10120000, // 9 = GPIO_MODE_EVT_RISING |
ebrus | 0:6bc4ac881c8e | 47 | 0x10220000, // 10 = GPIO_MODE_EVT_FALLING |
ebrus | 0:6bc4ac881c8e | 48 | 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING |
ebrus | 0:6bc4ac881c8e | 49 | 0x10000000 // 12 = Reset GPIO_MODE_IT_EVT |
ebrus | 0:6bc4ac881c8e | 50 | }; |
ebrus | 0:6bc4ac881c8e | 51 | |
ebrus | 0:6bc4ac881c8e | 52 | // Enable GPIO clock and return GPIO base address |
ebrus | 0:6bc4ac881c8e | 53 | uint32_t Set_GPIO_Clock(uint32_t port_idx) { |
ebrus | 0:6bc4ac881c8e | 54 | uint32_t gpio_add = 0; |
ebrus | 0:6bc4ac881c8e | 55 | switch (port_idx) { |
ebrus | 0:6bc4ac881c8e | 56 | case PortA: |
ebrus | 0:6bc4ac881c8e | 57 | gpio_add = GPIOA_BASE; |
ebrus | 0:6bc4ac881c8e | 58 | __GPIOA_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 59 | break; |
ebrus | 0:6bc4ac881c8e | 60 | case PortB: |
ebrus | 0:6bc4ac881c8e | 61 | gpio_add = GPIOB_BASE; |
ebrus | 0:6bc4ac881c8e | 62 | __GPIOB_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 63 | break; |
ebrus | 0:6bc4ac881c8e | 64 | case PortC: |
ebrus | 0:6bc4ac881c8e | 65 | gpio_add = GPIOC_BASE; |
ebrus | 0:6bc4ac881c8e | 66 | __GPIOC_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 67 | break; |
ebrus | 0:6bc4ac881c8e | 68 | case PortD: |
ebrus | 0:6bc4ac881c8e | 69 | gpio_add = GPIOD_BASE; |
ebrus | 0:6bc4ac881c8e | 70 | __GPIOD_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 71 | break; |
ebrus | 0:6bc4ac881c8e | 72 | case PortE: |
ebrus | 0:6bc4ac881c8e | 73 | gpio_add = GPIOE_BASE; |
ebrus | 0:6bc4ac881c8e | 74 | __GPIOE_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 75 | break; |
ebrus | 0:6bc4ac881c8e | 76 | case PortF: |
ebrus | 0:6bc4ac881c8e | 77 | gpio_add = GPIOF_BASE; |
ebrus | 0:6bc4ac881c8e | 78 | __GPIOF_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 79 | break; |
ebrus | 0:6bc4ac881c8e | 80 | case PortG: |
ebrus | 0:6bc4ac881c8e | 81 | gpio_add = GPIOG_BASE; |
ebrus | 0:6bc4ac881c8e | 82 | __GPIOG_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 83 | break; |
ebrus | 0:6bc4ac881c8e | 84 | case PortH: |
ebrus | 0:6bc4ac881c8e | 85 | gpio_add = GPIOH_BASE; |
ebrus | 0:6bc4ac881c8e | 86 | __GPIOH_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 87 | break; |
ebrus | 0:6bc4ac881c8e | 88 | case PortI: |
ebrus | 0:6bc4ac881c8e | 89 | gpio_add = GPIOI_BASE; |
ebrus | 0:6bc4ac881c8e | 90 | __GPIOI_CLK_ENABLE(); |
ebrus | 0:6bc4ac881c8e | 91 | break; |
ebrus | 0:6bc4ac881c8e | 92 | default: |
ebrus | 0:6bc4ac881c8e | 93 | error("Pinmap error: wrong port number."); |
ebrus | 0:6bc4ac881c8e | 94 | break; |
ebrus | 0:6bc4ac881c8e | 95 | } |
ebrus | 0:6bc4ac881c8e | 96 | return gpio_add; |
ebrus | 0:6bc4ac881c8e | 97 | } |
ebrus | 0:6bc4ac881c8e | 98 | |
ebrus | 0:6bc4ac881c8e | 99 | /** |
ebrus | 0:6bc4ac881c8e | 100 | * Configure pin (mode, speed, output type and pull-up/pull-down) |
ebrus | 0:6bc4ac881c8e | 101 | */ |
ebrus | 0:6bc4ac881c8e | 102 | void pin_function(PinName pin, int data) { |
ebrus | 0:6bc4ac881c8e | 103 | MBED_ASSERT(pin != (PinName)NC); |
ebrus | 0:6bc4ac881c8e | 104 | // Get the pin informations |
ebrus | 0:6bc4ac881c8e | 105 | uint32_t mode = STM_PIN_MODE(data); |
ebrus | 0:6bc4ac881c8e | 106 | uint32_t pupd = STM_PIN_PUPD(data); |
ebrus | 0:6bc4ac881c8e | 107 | uint32_t afnum = STM_PIN_AFNUM(data); |
ebrus | 0:6bc4ac881c8e | 108 | |
ebrus | 0:6bc4ac881c8e | 109 | uint32_t port_index = STM_PORT(pin); |
ebrus | 0:6bc4ac881c8e | 110 | uint32_t pin_index = STM_PIN(pin); |
ebrus | 0:6bc4ac881c8e | 111 | |
ebrus | 0:6bc4ac881c8e | 112 | // Enable GPIO clock |
ebrus | 0:6bc4ac881c8e | 113 | uint32_t gpio_add = Set_GPIO_Clock(port_index); |
ebrus | 0:6bc4ac881c8e | 114 | GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; |
ebrus | 0:6bc4ac881c8e | 115 | |
ebrus | 0:6bc4ac881c8e | 116 | // Configure GPIO |
ebrus | 0:6bc4ac881c8e | 117 | GPIO_InitTypeDef GPIO_InitStructure; |
ebrus | 0:6bc4ac881c8e | 118 | GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); |
ebrus | 0:6bc4ac881c8e | 119 | GPIO_InitStructure.Mode = gpio_mode[mode]; |
ebrus | 0:6bc4ac881c8e | 120 | GPIO_InitStructure.Pull = pupd; |
ebrus | 0:6bc4ac881c8e | 121 | GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; |
ebrus | 0:6bc4ac881c8e | 122 | GPIO_InitStructure.Alternate = afnum; |
ebrus | 0:6bc4ac881c8e | 123 | HAL_GPIO_Init(gpio, &GPIO_InitStructure); |
ebrus | 0:6bc4ac881c8e | 124 | |
ebrus | 0:6bc4ac881c8e | 125 | // [TODO] Disconnect JTAG-DP + SW-DP signals. |
ebrus | 0:6bc4ac881c8e | 126 | // Warning: Need to reconnect under reset |
ebrus | 0:6bc4ac881c8e | 127 | //if ((pin == PA_13) || (pin == PA_14)) { |
ebrus | 0:6bc4ac881c8e | 128 | // |
ebrus | 0:6bc4ac881c8e | 129 | //} |
ebrus | 0:6bc4ac881c8e | 130 | //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) { |
ebrus | 0:6bc4ac881c8e | 131 | // |
ebrus | 0:6bc4ac881c8e | 132 | //} |
ebrus | 0:6bc4ac881c8e | 133 | } |
ebrus | 0:6bc4ac881c8e | 134 | |
ebrus | 0:6bc4ac881c8e | 135 | /** |
ebrus | 0:6bc4ac881c8e | 136 | * Configure pin pull-up/pull-down |
ebrus | 0:6bc4ac881c8e | 137 | */ |
ebrus | 0:6bc4ac881c8e | 138 | void pin_mode(PinName pin, PinMode mode) { |
ebrus | 0:6bc4ac881c8e | 139 | MBED_ASSERT(pin != (PinName)NC); |
ebrus | 0:6bc4ac881c8e | 140 | uint32_t port_index = STM_PORT(pin); |
ebrus | 0:6bc4ac881c8e | 141 | uint32_t pin_index = STM_PIN(pin); |
ebrus | 0:6bc4ac881c8e | 142 | |
ebrus | 0:6bc4ac881c8e | 143 | // Enable GPIO clock |
ebrus | 0:6bc4ac881c8e | 144 | uint32_t gpio_add = Set_GPIO_Clock(port_index); |
ebrus | 0:6bc4ac881c8e | 145 | GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; |
ebrus | 0:6bc4ac881c8e | 146 | |
ebrus | 0:6bc4ac881c8e | 147 | // Configure pull-up/pull-down resistors |
ebrus | 0:6bc4ac881c8e | 148 | uint32_t pupd = (uint32_t)mode; |
ebrus | 0:6bc4ac881c8e | 149 | if (pupd > 2) |
ebrus | 0:6bc4ac881c8e | 150 | pupd = 0; // Open-drain = No pull-up/No pull-down |
ebrus | 0:6bc4ac881c8e | 151 | gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); |
ebrus | 0:6bc4ac881c8e | 152 | gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); |
ebrus | 0:6bc4ac881c8e | 153 | |
ebrus | 0:6bc4ac881c8e | 154 | } |