Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_irq_api.c@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:6bc4ac881c8e 1 /* mbed Microcontroller Library
ebrus 0:6bc4ac881c8e 2 *******************************************************************************
ebrus 0:6bc4ac881c8e 3 * Copyright (c) 2014, STMicroelectronics
ebrus 0:6bc4ac881c8e 4 * All rights reserved.
ebrus 0:6bc4ac881c8e 5 *
ebrus 0:6bc4ac881c8e 6 * Redistribution and use in source and binary forms, with or without
ebrus 0:6bc4ac881c8e 7 * modification, are permitted provided that the following conditions are met:
ebrus 0:6bc4ac881c8e 8 *
ebrus 0:6bc4ac881c8e 9 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:6bc4ac881c8e 10 * this list of conditions and the following disclaimer.
ebrus 0:6bc4ac881c8e 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:6bc4ac881c8e 12 * this list of conditions and the following disclaimer in the documentation
ebrus 0:6bc4ac881c8e 13 * and/or other materials provided with the distribution.
ebrus 0:6bc4ac881c8e 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:6bc4ac881c8e 15 * may be used to endorse or promote products derived from this software
ebrus 0:6bc4ac881c8e 16 * without specific prior written permission.
ebrus 0:6bc4ac881c8e 17 *
ebrus 0:6bc4ac881c8e 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:6bc4ac881c8e 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:6bc4ac881c8e 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:6bc4ac881c8e 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:6bc4ac881c8e 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:6bc4ac881c8e 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:6bc4ac881c8e 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:6bc4ac881c8e 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:6bc4ac881c8e 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:6bc4ac881c8e 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:6bc4ac881c8e 28 *******************************************************************************
ebrus 0:6bc4ac881c8e 29 */
ebrus 0:6bc4ac881c8e 30 #include <stddef.h>
ebrus 0:6bc4ac881c8e 31 #include "cmsis.h"
ebrus 0:6bc4ac881c8e 32
ebrus 0:6bc4ac881c8e 33 #include "gpio_irq_api.h"
ebrus 0:6bc4ac881c8e 34 #include "pinmap.h"
ebrus 0:6bc4ac881c8e 35 #include "mbed_error.h"
ebrus 0:6bc4ac881c8e 36
ebrus 0:6bc4ac881c8e 37 #define EDGE_NONE (0)
ebrus 0:6bc4ac881c8e 38 #define EDGE_RISE (1)
ebrus 0:6bc4ac881c8e 39 #define EDGE_FALL (2)
ebrus 0:6bc4ac881c8e 40 #define EDGE_BOTH (3)
ebrus 0:6bc4ac881c8e 41
ebrus 0:6bc4ac881c8e 42 #define CHANNEL_NUM (7)
ebrus 0:6bc4ac881c8e 43
ebrus 0:6bc4ac881c8e 44 static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
ebrus 0:6bc4ac881c8e 45 static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
ebrus 0:6bc4ac881c8e 46 static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
ebrus 0:6bc4ac881c8e 47
ebrus 0:6bc4ac881c8e 48 static gpio_irq_handler irq_handler;
ebrus 0:6bc4ac881c8e 49
ebrus 0:6bc4ac881c8e 50 static void handle_interrupt_in(uint32_t irq_index) {
ebrus 0:6bc4ac881c8e 51 // Retrieve the gpio and pin that generate the irq
ebrus 0:6bc4ac881c8e 52 GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]);
ebrus 0:6bc4ac881c8e 53 uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
ebrus 0:6bc4ac881c8e 54
ebrus 0:6bc4ac881c8e 55 // Clear interrupt flag
ebrus 0:6bc4ac881c8e 56 if (EXTI_GetITStatus(channel_pin[irq_index]) != RESET) {
ebrus 0:6bc4ac881c8e 57 EXTI_ClearITPendingBit(channel_pin[irq_index]);
ebrus 0:6bc4ac881c8e 58 }
ebrus 0:6bc4ac881c8e 59
ebrus 0:6bc4ac881c8e 60 if (channel_ids[irq_index] == 0) return;
ebrus 0:6bc4ac881c8e 61
ebrus 0:6bc4ac881c8e 62 // Check which edge has generated the irq
ebrus 0:6bc4ac881c8e 63 if ((gpio->IDR & pin) == 0) {
ebrus 0:6bc4ac881c8e 64 irq_handler(channel_ids[irq_index], IRQ_FALL);
ebrus 0:6bc4ac881c8e 65 } else {
ebrus 0:6bc4ac881c8e 66 irq_handler(channel_ids[irq_index], IRQ_RISE);
ebrus 0:6bc4ac881c8e 67 }
ebrus 0:6bc4ac881c8e 68 }
ebrus 0:6bc4ac881c8e 69
ebrus 0:6bc4ac881c8e 70 static void gpio_irq0(void) {
ebrus 0:6bc4ac881c8e 71 handle_interrupt_in(0); // EXTI line 0
ebrus 0:6bc4ac881c8e 72 }
ebrus 0:6bc4ac881c8e 73
ebrus 0:6bc4ac881c8e 74 static void gpio_irq1(void) {
ebrus 0:6bc4ac881c8e 75 handle_interrupt_in(1); // EXTI line 1
ebrus 0:6bc4ac881c8e 76 }
ebrus 0:6bc4ac881c8e 77
ebrus 0:6bc4ac881c8e 78 static void gpio_irq2(void) {
ebrus 0:6bc4ac881c8e 79 handle_interrupt_in(2); // EXTI line 2
ebrus 0:6bc4ac881c8e 80 }
ebrus 0:6bc4ac881c8e 81
ebrus 0:6bc4ac881c8e 82 static void gpio_irq3(void) {
ebrus 0:6bc4ac881c8e 83 handle_interrupt_in(3); // EXTI line 3
ebrus 0:6bc4ac881c8e 84 }
ebrus 0:6bc4ac881c8e 85
ebrus 0:6bc4ac881c8e 86 static void gpio_irq4(void) {
ebrus 0:6bc4ac881c8e 87 handle_interrupt_in(4); // EXTI line 4
ebrus 0:6bc4ac881c8e 88 }
ebrus 0:6bc4ac881c8e 89
ebrus 0:6bc4ac881c8e 90 static void gpio_irq5(void) {
ebrus 0:6bc4ac881c8e 91 handle_interrupt_in(5); // EXTI lines 5 to 9
ebrus 0:6bc4ac881c8e 92 }
ebrus 0:6bc4ac881c8e 93
ebrus 0:6bc4ac881c8e 94 static void gpio_irq6(void) {
ebrus 0:6bc4ac881c8e 95 handle_interrupt_in(6); // EXTI lines 10 to 15
ebrus 0:6bc4ac881c8e 96 }
ebrus 0:6bc4ac881c8e 97
ebrus 0:6bc4ac881c8e 98 extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
ebrus 0:6bc4ac881c8e 99
ebrus 0:6bc4ac881c8e 100 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
ebrus 0:6bc4ac881c8e 101 IRQn_Type irq_n = (IRQn_Type)0;
ebrus 0:6bc4ac881c8e 102 uint32_t vector = 0;
ebrus 0:6bc4ac881c8e 103 uint32_t irq_index;
ebrus 0:6bc4ac881c8e 104
ebrus 0:6bc4ac881c8e 105 if (pin == NC) return -1;
ebrus 0:6bc4ac881c8e 106
ebrus 0:6bc4ac881c8e 107 uint32_t port_index = STM_PORT(pin);
ebrus 0:6bc4ac881c8e 108 uint32_t pin_index = STM_PIN(pin);
ebrus 0:6bc4ac881c8e 109
ebrus 0:6bc4ac881c8e 110 // Select irq number and interrupt routine
ebrus 0:6bc4ac881c8e 111 switch (pin_index) {
ebrus 0:6bc4ac881c8e 112 case 0:
ebrus 0:6bc4ac881c8e 113 irq_n = EXTI0_IRQn;
ebrus 0:6bc4ac881c8e 114 vector = (uint32_t)&gpio_irq0;
ebrus 0:6bc4ac881c8e 115 irq_index = 0;
ebrus 0:6bc4ac881c8e 116 break;
ebrus 0:6bc4ac881c8e 117 case 1:
ebrus 0:6bc4ac881c8e 118 irq_n = EXTI1_IRQn;
ebrus 0:6bc4ac881c8e 119 vector = (uint32_t)&gpio_irq1;
ebrus 0:6bc4ac881c8e 120 irq_index = 1;
ebrus 0:6bc4ac881c8e 121 break;
ebrus 0:6bc4ac881c8e 122 case 2:
ebrus 0:6bc4ac881c8e 123 irq_n = EXTI2_TS_IRQn;
ebrus 0:6bc4ac881c8e 124 vector = (uint32_t)&gpio_irq2;
ebrus 0:6bc4ac881c8e 125 irq_index = 2;
ebrus 0:6bc4ac881c8e 126 break;
ebrus 0:6bc4ac881c8e 127 case 3:
ebrus 0:6bc4ac881c8e 128 irq_n = EXTI3_IRQn;
ebrus 0:6bc4ac881c8e 129 vector = (uint32_t)&gpio_irq3;
ebrus 0:6bc4ac881c8e 130 irq_index = 3;
ebrus 0:6bc4ac881c8e 131 break;
ebrus 0:6bc4ac881c8e 132 case 4:
ebrus 0:6bc4ac881c8e 133 irq_n = EXTI4_IRQn;
ebrus 0:6bc4ac881c8e 134 vector = (uint32_t)&gpio_irq4;
ebrus 0:6bc4ac881c8e 135 irq_index = 4;
ebrus 0:6bc4ac881c8e 136 break;
ebrus 0:6bc4ac881c8e 137 case 5:
ebrus 0:6bc4ac881c8e 138 case 6:
ebrus 0:6bc4ac881c8e 139 case 7:
ebrus 0:6bc4ac881c8e 140 case 8:
ebrus 0:6bc4ac881c8e 141 case 9:
ebrus 0:6bc4ac881c8e 142 irq_n = EXTI9_5_IRQn;
ebrus 0:6bc4ac881c8e 143 vector = (uint32_t)&gpio_irq5;
ebrus 0:6bc4ac881c8e 144 irq_index = 5;
ebrus 0:6bc4ac881c8e 145 break;
ebrus 0:6bc4ac881c8e 146 case 10:
ebrus 0:6bc4ac881c8e 147 case 11:
ebrus 0:6bc4ac881c8e 148 case 12:
ebrus 0:6bc4ac881c8e 149 case 13:
ebrus 0:6bc4ac881c8e 150 case 14:
ebrus 0:6bc4ac881c8e 151 case 15:
ebrus 0:6bc4ac881c8e 152 irq_n = EXTI15_10_IRQn;
ebrus 0:6bc4ac881c8e 153 vector = (uint32_t)&gpio_irq6;
ebrus 0:6bc4ac881c8e 154 irq_index = 6;
ebrus 0:6bc4ac881c8e 155 break;
ebrus 0:6bc4ac881c8e 156 default:
ebrus 0:6bc4ac881c8e 157 error("This pin is not supported with InterruptIn.");
ebrus 0:6bc4ac881c8e 158 return -1;
ebrus 0:6bc4ac881c8e 159 }
ebrus 0:6bc4ac881c8e 160
ebrus 0:6bc4ac881c8e 161 // Enable GPIO clock
ebrus 0:6bc4ac881c8e 162 uint32_t gpio_add = Set_GPIO_Clock(port_index);
ebrus 0:6bc4ac881c8e 163
ebrus 0:6bc4ac881c8e 164 // Enable SYSCFG clock
ebrus 0:6bc4ac881c8e 165 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
ebrus 0:6bc4ac881c8e 166
ebrus 0:6bc4ac881c8e 167 // Connect EXTI line to pin
ebrus 0:6bc4ac881c8e 168 SYSCFG_EXTILineConfig(port_index, pin_index);
ebrus 0:6bc4ac881c8e 169
ebrus 0:6bc4ac881c8e 170 // Configure EXTI line
ebrus 0:6bc4ac881c8e 171 EXTI_InitTypeDef EXTI_InitStructure;
ebrus 0:6bc4ac881c8e 172 EXTI_InitStructure.EXTI_Line = pin_index;
ebrus 0:6bc4ac881c8e 173 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
ebrus 0:6bc4ac881c8e 174 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
ebrus 0:6bc4ac881c8e 175 EXTI_InitStructure.EXTI_LineCmd = ENABLE;
ebrus 0:6bc4ac881c8e 176 EXTI_Init(&EXTI_InitStructure);
ebrus 0:6bc4ac881c8e 177
ebrus 0:6bc4ac881c8e 178 // Enable and set EXTI interrupt to the lowest priority
ebrus 0:6bc4ac881c8e 179 NVIC_InitTypeDef NVIC_InitStructure;
ebrus 0:6bc4ac881c8e 180 NVIC_InitStructure.NVIC_IRQChannel = irq_n;
ebrus 0:6bc4ac881c8e 181 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
ebrus 0:6bc4ac881c8e 182 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
ebrus 0:6bc4ac881c8e 183 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
ebrus 0:6bc4ac881c8e 184 NVIC_Init(&NVIC_InitStructure);
ebrus 0:6bc4ac881c8e 185
ebrus 0:6bc4ac881c8e 186 NVIC_SetVector(irq_n, vector);
ebrus 0:6bc4ac881c8e 187 NVIC_EnableIRQ(irq_n);
ebrus 0:6bc4ac881c8e 188
ebrus 0:6bc4ac881c8e 189 // Save informations for future use
ebrus 0:6bc4ac881c8e 190 obj->irq_n = irq_n;
ebrus 0:6bc4ac881c8e 191 obj->irq_index = irq_index;
ebrus 0:6bc4ac881c8e 192 obj->event = EDGE_NONE;
ebrus 0:6bc4ac881c8e 193 channel_ids[irq_index] = id;
ebrus 0:6bc4ac881c8e 194 channel_gpio[irq_index] = gpio_add;
ebrus 0:6bc4ac881c8e 195 channel_pin[irq_index] = pin_index;
ebrus 0:6bc4ac881c8e 196
ebrus 0:6bc4ac881c8e 197 irq_handler = handler;
ebrus 0:6bc4ac881c8e 198
ebrus 0:6bc4ac881c8e 199 return 0;
ebrus 0:6bc4ac881c8e 200 }
ebrus 0:6bc4ac881c8e 201
ebrus 0:6bc4ac881c8e 202 void gpio_irq_free(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 203 channel_ids[obj->irq_index] = 0;
ebrus 0:6bc4ac881c8e 204 channel_gpio[obj->irq_index] = 0;
ebrus 0:6bc4ac881c8e 205 channel_pin[obj->irq_index] = 0;
ebrus 0:6bc4ac881c8e 206 // Disable EXTI line
ebrus 0:6bc4ac881c8e 207 EXTI_InitTypeDef EXTI_InitStructure;
ebrus 0:6bc4ac881c8e 208 EXTI_StructInit(&EXTI_InitStructure);
ebrus 0:6bc4ac881c8e 209 EXTI_Init(&EXTI_InitStructure);
ebrus 0:6bc4ac881c8e 210 obj->event = EDGE_NONE;
ebrus 0:6bc4ac881c8e 211 }
ebrus 0:6bc4ac881c8e 212
ebrus 0:6bc4ac881c8e 213 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
ebrus 0:6bc4ac881c8e 214 EXTI_InitTypeDef EXTI_InitStructure;
ebrus 0:6bc4ac881c8e 215
ebrus 0:6bc4ac881c8e 216 EXTI_InitStructure.EXTI_Line = channel_pin[obj->irq_index];
ebrus 0:6bc4ac881c8e 217 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
ebrus 0:6bc4ac881c8e 218
ebrus 0:6bc4ac881c8e 219 if (event == IRQ_RISE) {
ebrus 0:6bc4ac881c8e 220 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
ebrus 0:6bc4ac881c8e 221 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
ebrus 0:6bc4ac881c8e 222 obj->event = EDGE_BOTH;
ebrus 0:6bc4ac881c8e 223 } else { // NONE or RISE
ebrus 0:6bc4ac881c8e 224 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
ebrus 0:6bc4ac881c8e 225 obj->event = EDGE_RISE;
ebrus 0:6bc4ac881c8e 226 }
ebrus 0:6bc4ac881c8e 227 }
ebrus 0:6bc4ac881c8e 228
ebrus 0:6bc4ac881c8e 229 if (event == IRQ_FALL) {
ebrus 0:6bc4ac881c8e 230 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
ebrus 0:6bc4ac881c8e 231 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
ebrus 0:6bc4ac881c8e 232 obj->event = EDGE_BOTH;
ebrus 0:6bc4ac881c8e 233 } else { // NONE or FALL
ebrus 0:6bc4ac881c8e 234 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
ebrus 0:6bc4ac881c8e 235 obj->event = EDGE_FALL;
ebrus 0:6bc4ac881c8e 236 }
ebrus 0:6bc4ac881c8e 237 }
ebrus 0:6bc4ac881c8e 238
ebrus 0:6bc4ac881c8e 239 if (enable) {
ebrus 0:6bc4ac881c8e 240 EXTI_InitStructure.EXTI_LineCmd = ENABLE;
ebrus 0:6bc4ac881c8e 241 } else {
ebrus 0:6bc4ac881c8e 242 EXTI_InitStructure.EXTI_LineCmd = DISABLE;
ebrus 0:6bc4ac881c8e 243 }
ebrus 0:6bc4ac881c8e 244
ebrus 0:6bc4ac881c8e 245 EXTI_Init(&EXTI_InitStructure);
ebrus 0:6bc4ac881c8e 246 }
ebrus 0:6bc4ac881c8e 247
ebrus 0:6bc4ac881c8e 248 void gpio_irq_enable(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 249 NVIC_EnableIRQ(obj->irq_n);
ebrus 0:6bc4ac881c8e 250 }
ebrus 0:6bc4ac881c8e 251
ebrus 0:6bc4ac881c8e 252 void gpio_irq_disable(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 253 NVIC_DisableIRQ(obj->irq_n);
ebrus 0:6bc4ac881c8e 254 obj->event = EDGE_NONE;
ebrus 0:6bc4ac881c8e 255 }