mbed library sources
Dependents: FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more
targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c@0:6bc4ac881c8e, 2016-07-28 (annotated)
- Committer:
- ebrus
- Date:
- Thu Jul 28 15:56:34 2016 +0000
- Revision:
- 0:6bc4ac881c8e
1;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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ebrus | 0:6bc4ac881c8e | 1 | /* mbed Microcontroller Library |
ebrus | 0:6bc4ac881c8e | 2 | * Copyright (c) 2006-2013 ARM Limited |
ebrus | 0:6bc4ac881c8e | 3 | * |
ebrus | 0:6bc4ac881c8e | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
ebrus | 0:6bc4ac881c8e | 5 | * you may not use this file except in compliance with the License. |
ebrus | 0:6bc4ac881c8e | 6 | * You may obtain a copy of the License at |
ebrus | 0:6bc4ac881c8e | 7 | * |
ebrus | 0:6bc4ac881c8e | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
ebrus | 0:6bc4ac881c8e | 9 | * |
ebrus | 0:6bc4ac881c8e | 10 | * Unless required by applicable law or agreed to in writing, software |
ebrus | 0:6bc4ac881c8e | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
ebrus | 0:6bc4ac881c8e | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
ebrus | 0:6bc4ac881c8e | 13 | * See the License for the specific language governing permissions and |
ebrus | 0:6bc4ac881c8e | 14 | * limitations under the License. |
ebrus | 0:6bc4ac881c8e | 15 | */ |
ebrus | 0:6bc4ac881c8e | 16 | #include "sleep_api.h" |
ebrus | 0:6bc4ac881c8e | 17 | #include "cmsis.h" |
ebrus | 0:6bc4ac881c8e | 18 | #include "PeripheralPins.h" |
ebrus | 0:6bc4ac881c8e | 19 | |
ebrus | 0:6bc4ac881c8e | 20 | //Normal wait mode |
ebrus | 0:6bc4ac881c8e | 21 | void sleep(void) |
ebrus | 0:6bc4ac881c8e | 22 | { |
ebrus | 0:6bc4ac881c8e | 23 | SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; |
ebrus | 0:6bc4ac881c8e | 24 | |
ebrus | 0:6bc4ac881c8e | 25 | //Normal sleep mode for ARM core: |
ebrus | 0:6bc4ac881c8e | 26 | SCB->SCR = 0; |
ebrus | 0:6bc4ac881c8e | 27 | __WFI(); |
ebrus | 0:6bc4ac881c8e | 28 | } |
ebrus | 0:6bc4ac881c8e | 29 | |
ebrus | 0:6bc4ac881c8e | 30 | //Very low-power stop mode |
ebrus | 0:6bc4ac881c8e | 31 | void deepsleep(void) |
ebrus | 0:6bc4ac881c8e | 32 | { |
ebrus | 0:6bc4ac881c8e | 33 | //Check if PLL/FLL is enabled: |
ebrus | 0:6bc4ac881c8e | 34 | uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); |
ebrus | 0:6bc4ac881c8e | 35 | |
ebrus | 0:6bc4ac881c8e | 36 | SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; |
ebrus | 0:6bc4ac881c8e | 37 | SMC->PMCTRL = SMC_PMCTRL_STOPM(2); |
ebrus | 0:6bc4ac881c8e | 38 | |
ebrus | 0:6bc4ac881c8e | 39 | //Deep sleep for ARM core: |
ebrus | 0:6bc4ac881c8e | 40 | SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos; |
ebrus | 0:6bc4ac881c8e | 41 | |
ebrus | 0:6bc4ac881c8e | 42 | __WFI(); |
ebrus | 0:6bc4ac881c8e | 43 | |
ebrus | 0:6bc4ac881c8e | 44 | //Switch back to PLL as clock source if needed |
ebrus | 0:6bc4ac881c8e | 45 | //The interrupt that woke up the device will run at reduced speed |
ebrus | 0:6bc4ac881c8e | 46 | if (PLL_FLL_en) { |
ebrus | 0:6bc4ac881c8e | 47 | #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available |
ebrus | 0:6bc4ac881c8e | 48 | if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */ |
ebrus | 0:6bc4ac881c8e | 49 | while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ |
ebrus | 0:6bc4ac881c8e | 50 | #endif |
ebrus | 0:6bc4ac881c8e | 51 | MCG->C1 &= ~MCG_C1_CLKS_MASK; |
ebrus | 0:6bc4ac881c8e | 52 | } |
ebrus | 0:6bc4ac881c8e | 53 | |
ebrus | 0:6bc4ac881c8e | 54 | } |