mbed library sources
Dependents: FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more
targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c@0:6bc4ac881c8e, 2016-07-28 (annotated)
- Committer:
- ebrus
- Date:
- Thu Jul 28 15:56:34 2016 +0000
- Revision:
- 0:6bc4ac881c8e
1;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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ebrus | 0:6bc4ac881c8e | 1 | /* mbed Microcontroller Library |
ebrus | 0:6bc4ac881c8e | 2 | * Copyright (c) 2006-2013 ARM Limited |
ebrus | 0:6bc4ac881c8e | 3 | * |
ebrus | 0:6bc4ac881c8e | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
ebrus | 0:6bc4ac881c8e | 5 | * you may not use this file except in compliance with the License. |
ebrus | 0:6bc4ac881c8e | 6 | * You may obtain a copy of the License at |
ebrus | 0:6bc4ac881c8e | 7 | * |
ebrus | 0:6bc4ac881c8e | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
ebrus | 0:6bc4ac881c8e | 9 | * |
ebrus | 0:6bc4ac881c8e | 10 | * Unless required by applicable law or agreed to in writing, software |
ebrus | 0:6bc4ac881c8e | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
ebrus | 0:6bc4ac881c8e | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
ebrus | 0:6bc4ac881c8e | 13 | * See the License for the specific language governing permissions and |
ebrus | 0:6bc4ac881c8e | 14 | * limitations under the License. |
ebrus | 0:6bc4ac881c8e | 15 | */ |
ebrus | 0:6bc4ac881c8e | 16 | #include "rtc_api.h" |
ebrus | 0:6bc4ac881c8e | 17 | #include "PeripheralPins.h" |
ebrus | 0:6bc4ac881c8e | 18 | |
ebrus | 0:6bc4ac881c8e | 19 | static void init(void) { |
ebrus | 0:6bc4ac881c8e | 20 | // enable RTC clock |
ebrus | 0:6bc4ac881c8e | 21 | SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; |
ebrus | 0:6bc4ac881c8e | 22 | |
ebrus | 0:6bc4ac881c8e | 23 | pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC) |
ebrus | 0:6bc4ac881c8e | 24 | |
ebrus | 0:6bc4ac881c8e | 25 | // select RTC clock source |
ebrus | 0:6bc4ac881c8e | 26 | SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; |
ebrus | 0:6bc4ac881c8e | 27 | SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral); |
ebrus | 0:6bc4ac881c8e | 28 | } |
ebrus | 0:6bc4ac881c8e | 29 | |
ebrus | 0:6bc4ac881c8e | 30 | void rtc_init(void) { |
ebrus | 0:6bc4ac881c8e | 31 | init(); |
ebrus | 0:6bc4ac881c8e | 32 | |
ebrus | 0:6bc4ac881c8e | 33 | //Configure the TSR. default value: 1 |
ebrus | 0:6bc4ac881c8e | 34 | RTC->TSR = 1; |
ebrus | 0:6bc4ac881c8e | 35 | |
ebrus | 0:6bc4ac881c8e | 36 | if (PinMap_RTC[0].pin == NC) { //Use OSC32K |
ebrus | 0:6bc4ac881c8e | 37 | RTC->CR |= RTC_CR_OSCE_MASK; |
ebrus | 0:6bc4ac881c8e | 38 | //delay for OSCE stabilization |
ebrus | 0:6bc4ac881c8e | 39 | for(int i=0; i<0x1000; i++) __NOP(); |
ebrus | 0:6bc4ac881c8e | 40 | } |
ebrus | 0:6bc4ac881c8e | 41 | |
ebrus | 0:6bc4ac881c8e | 42 | // enable counter |
ebrus | 0:6bc4ac881c8e | 43 | RTC->SR |= RTC_SR_TCE_MASK; |
ebrus | 0:6bc4ac881c8e | 44 | } |
ebrus | 0:6bc4ac881c8e | 45 | |
ebrus | 0:6bc4ac881c8e | 46 | void rtc_free(void) { |
ebrus | 0:6bc4ac881c8e | 47 | // [TODO] |
ebrus | 0:6bc4ac881c8e | 48 | } |
ebrus | 0:6bc4ac881c8e | 49 | |
ebrus | 0:6bc4ac881c8e | 50 | /* |
ebrus | 0:6bc4ac881c8e | 51 | * Little check routine to see if the RTC has been enabled |
ebrus | 0:6bc4ac881c8e | 52 | * 0 = Disabled, 1 = Enabled |
ebrus | 0:6bc4ac881c8e | 53 | */ |
ebrus | 0:6bc4ac881c8e | 54 | int rtc_isenabled(void) { |
ebrus | 0:6bc4ac881c8e | 55 | // even if the RTC module is enabled, |
ebrus | 0:6bc4ac881c8e | 56 | // as we use RTC_CLKIN and an external clock, |
ebrus | 0:6bc4ac881c8e | 57 | // we need to reconfigure the pins. That is why we |
ebrus | 0:6bc4ac881c8e | 58 | // call init() if the rtc is enabled |
ebrus | 0:6bc4ac881c8e | 59 | |
ebrus | 0:6bc4ac881c8e | 60 | // if RTC not enabled return 0 |
ebrus | 0:6bc4ac881c8e | 61 | SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; |
ebrus | 0:6bc4ac881c8e | 62 | SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; |
ebrus | 0:6bc4ac881c8e | 63 | if ((RTC->SR & RTC_SR_TCE_MASK) == 0) |
ebrus | 0:6bc4ac881c8e | 64 | return 0; |
ebrus | 0:6bc4ac881c8e | 65 | |
ebrus | 0:6bc4ac881c8e | 66 | init(); |
ebrus | 0:6bc4ac881c8e | 67 | return 1; |
ebrus | 0:6bc4ac881c8e | 68 | } |
ebrus | 0:6bc4ac881c8e | 69 | |
ebrus | 0:6bc4ac881c8e | 70 | time_t rtc_read(void) { |
ebrus | 0:6bc4ac881c8e | 71 | return RTC->TSR; |
ebrus | 0:6bc4ac881c8e | 72 | } |
ebrus | 0:6bc4ac881c8e | 73 | |
ebrus | 0:6bc4ac881c8e | 74 | void rtc_write(time_t t) { |
ebrus | 0:6bc4ac881c8e | 75 | // disable counter |
ebrus | 0:6bc4ac881c8e | 76 | RTC->SR &= ~RTC_SR_TCE_MASK; |
ebrus | 0:6bc4ac881c8e | 77 | |
ebrus | 0:6bc4ac881c8e | 78 | // we do not write 0 into TSR |
ebrus | 0:6bc4ac881c8e | 79 | // to avoid invalid time |
ebrus | 0:6bc4ac881c8e | 80 | if (t == 0) |
ebrus | 0:6bc4ac881c8e | 81 | t = 1; |
ebrus | 0:6bc4ac881c8e | 82 | |
ebrus | 0:6bc4ac881c8e | 83 | // write seconds |
ebrus | 0:6bc4ac881c8e | 84 | RTC->TSR = t; |
ebrus | 0:6bc4ac881c8e | 85 | |
ebrus | 0:6bc4ac881c8e | 86 | // re-enable counter |
ebrus | 0:6bc4ac881c8e | 87 | RTC->SR |= RTC_SR_TCE_MASK; |
ebrus | 0:6bc4ac881c8e | 88 | } |