Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

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ebrus 0:6bc4ac881c8e 1 /* mbed Microcontroller Library
ebrus 0:6bc4ac881c8e 2 *******************************************************************************
ebrus 0:6bc4ac881c8e 3 * Copyright (c) 2014, STMicroelectronics
ebrus 0:6bc4ac881c8e 4 * All rights reserved.
ebrus 0:6bc4ac881c8e 5 *
ebrus 0:6bc4ac881c8e 6 * Redistribution and use in source and binary forms, with or without
ebrus 0:6bc4ac881c8e 7 * modification, are permitted provided that the following conditions are met:
ebrus 0:6bc4ac881c8e 8 *
ebrus 0:6bc4ac881c8e 9 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:6bc4ac881c8e 10 * this list of conditions and the following disclaimer.
ebrus 0:6bc4ac881c8e 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:6bc4ac881c8e 12 * this list of conditions and the following disclaimer in the documentation
ebrus 0:6bc4ac881c8e 13 * and/or other materials provided with the distribution.
ebrus 0:6bc4ac881c8e 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:6bc4ac881c8e 15 * may be used to endorse or promote products derived from this software
ebrus 0:6bc4ac881c8e 16 * without specific prior written permission.
ebrus 0:6bc4ac881c8e 17 *
ebrus 0:6bc4ac881c8e 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:6bc4ac881c8e 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:6bc4ac881c8e 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:6bc4ac881c8e 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:6bc4ac881c8e 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:6bc4ac881c8e 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:6bc4ac881c8e 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:6bc4ac881c8e 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:6bc4ac881c8e 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:6bc4ac881c8e 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:6bc4ac881c8e 28 *******************************************************************************
ebrus 0:6bc4ac881c8e 29 */
ebrus 0:6bc4ac881c8e 30 #include "mbed_assert.h"
ebrus 0:6bc4ac881c8e 31 #include "pinmap.h"
ebrus 0:6bc4ac881c8e 32 #include "PortNames.h"
ebrus 0:6bc4ac881c8e 33 #include "mbed_error.h"
ebrus 0:6bc4ac881c8e 34
ebrus 0:6bc4ac881c8e 35 // Alternate-function mapping
ebrus 0:6bc4ac881c8e 36 #define AF_NUM (10)
ebrus 0:6bc4ac881c8e 37 static const uint32_t AF_mapping[AF_NUM] = {
ebrus 0:6bc4ac881c8e 38 0, // 0 = No AF
ebrus 0:6bc4ac881c8e 39 GPIO_Remap_SPI1, // 1
ebrus 0:6bc4ac881c8e 40 GPIO_Remap_I2C1, // 2
ebrus 0:6bc4ac881c8e 41 GPIO_Remap_USART1, // 3
ebrus 0:6bc4ac881c8e 42 GPIO_Remap_USART2, // 4
ebrus 0:6bc4ac881c8e 43 GPIO_PartialRemap_USART3, // 5
ebrus 0:6bc4ac881c8e 44 GPIO_PartialRemap_TIM1, // 6
ebrus 0:6bc4ac881c8e 45 GPIO_PartialRemap_TIM3, // 7
ebrus 0:6bc4ac881c8e 46 GPIO_FullRemap_TIM2, // 8
ebrus 0:6bc4ac881c8e 47 GPIO_FullRemap_TIM3 // 9
ebrus 0:6bc4ac881c8e 48 };
ebrus 0:6bc4ac881c8e 49
ebrus 0:6bc4ac881c8e 50 // Enable GPIO clock and return GPIO base address
ebrus 0:6bc4ac881c8e 51 uint32_t Set_GPIO_Clock(uint32_t port_idx) {
ebrus 0:6bc4ac881c8e 52 uint32_t gpio_add = 0;
ebrus 0:6bc4ac881c8e 53 switch (port_idx) {
ebrus 0:6bc4ac881c8e 54 case PortA:
ebrus 0:6bc4ac881c8e 55 gpio_add = GPIOA_BASE;
ebrus 0:6bc4ac881c8e 56 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
ebrus 0:6bc4ac881c8e 57 break;
ebrus 0:6bc4ac881c8e 58 case PortB:
ebrus 0:6bc4ac881c8e 59 gpio_add = GPIOB_BASE;
ebrus 0:6bc4ac881c8e 60 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
ebrus 0:6bc4ac881c8e 61 break;
ebrus 0:6bc4ac881c8e 62 case PortC:
ebrus 0:6bc4ac881c8e 63 gpio_add = GPIOC_BASE;
ebrus 0:6bc4ac881c8e 64 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
ebrus 0:6bc4ac881c8e 65 break;
ebrus 0:6bc4ac881c8e 66 case PortD:
ebrus 0:6bc4ac881c8e 67 gpio_add = GPIOD_BASE;
ebrus 0:6bc4ac881c8e 68 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
ebrus 0:6bc4ac881c8e 69 break;
ebrus 0:6bc4ac881c8e 70 default:
ebrus 0:6bc4ac881c8e 71 error("Port number is not correct.");
ebrus 0:6bc4ac881c8e 72 break;
ebrus 0:6bc4ac881c8e 73 }
ebrus 0:6bc4ac881c8e 74 return gpio_add;
ebrus 0:6bc4ac881c8e 75 }
ebrus 0:6bc4ac881c8e 76
ebrus 0:6bc4ac881c8e 77 /**
ebrus 0:6bc4ac881c8e 78 * Configure pin (input, output, alternate function or analog) + output speed + AF
ebrus 0:6bc4ac881c8e 79 */
ebrus 0:6bc4ac881c8e 80 void pin_function(PinName pin, int data) {
ebrus 0:6bc4ac881c8e 81 MBED_ASSERT(pin != (PinName)NC);
ebrus 0:6bc4ac881c8e 82 // Get the pin informations
ebrus 0:6bc4ac881c8e 83 uint32_t mode = STM_PIN_MODE(data);
ebrus 0:6bc4ac881c8e 84 uint32_t afnum = STM_PIN_AFNUM(data);
ebrus 0:6bc4ac881c8e 85
ebrus 0:6bc4ac881c8e 86 uint32_t port_index = STM_PORT(pin);
ebrus 0:6bc4ac881c8e 87 uint32_t pin_index = STM_PIN(pin);
ebrus 0:6bc4ac881c8e 88
ebrus 0:6bc4ac881c8e 89 // Enable GPIO clock
ebrus 0:6bc4ac881c8e 90 uint32_t gpio_add = Set_GPIO_Clock(port_index);
ebrus 0:6bc4ac881c8e 91 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
ebrus 0:6bc4ac881c8e 92
ebrus 0:6bc4ac881c8e 93 // Enable AFIO clock
ebrus 0:6bc4ac881c8e 94 RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
ebrus 0:6bc4ac881c8e 95
ebrus 0:6bc4ac881c8e 96 // Configure Alternate Function
ebrus 0:6bc4ac881c8e 97 // Warning: Must be done before the GPIO is initialized
ebrus 0:6bc4ac881c8e 98 if ((afnum > 0) && (afnum < AF_NUM)) {
ebrus 0:6bc4ac881c8e 99 GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE);
ebrus 0:6bc4ac881c8e 100 }
ebrus 0:6bc4ac881c8e 101
ebrus 0:6bc4ac881c8e 102 // Configure GPIO
ebrus 0:6bc4ac881c8e 103 GPIO_InitTypeDef GPIO_InitStructure;
ebrus 0:6bc4ac881c8e 104 GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
ebrus 0:6bc4ac881c8e 105 GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode;
ebrus 0:6bc4ac881c8e 106 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
ebrus 0:6bc4ac881c8e 107 GPIO_Init(gpio, &GPIO_InitStructure);
ebrus 0:6bc4ac881c8e 108
ebrus 0:6bc4ac881c8e 109 // Disconnect JTAG-DP + SW-DP signals.
ebrus 0:6bc4ac881c8e 110 // Warning: Need to reconnect under reset
ebrus 0:6bc4ac881c8e 111 if ((pin == PA_13) || (pin == PA_14)) {
ebrus 0:6bc4ac881c8e 112 GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE);
ebrus 0:6bc4ac881c8e 113 }
ebrus 0:6bc4ac881c8e 114 if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
ebrus 0:6bc4ac881c8e 115 GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
ebrus 0:6bc4ac881c8e 116 }
ebrus 0:6bc4ac881c8e 117 }
ebrus 0:6bc4ac881c8e 118
ebrus 0:6bc4ac881c8e 119 /**
ebrus 0:6bc4ac881c8e 120 * Configure pin pull-up/pull-down
ebrus 0:6bc4ac881c8e 121 */
ebrus 0:6bc4ac881c8e 122 void pin_mode(PinName pin, PinMode mode) {
ebrus 0:6bc4ac881c8e 123 MBED_ASSERT(pin != (PinName)NC);
ebrus 0:6bc4ac881c8e 124 GPIO_InitTypeDef GPIO_InitStructure;
ebrus 0:6bc4ac881c8e 125
ebrus 0:6bc4ac881c8e 126 uint32_t port_index = STM_PORT(pin);
ebrus 0:6bc4ac881c8e 127 uint32_t pin_index = STM_PIN(pin);
ebrus 0:6bc4ac881c8e 128
ebrus 0:6bc4ac881c8e 129 // Enable GPIO clock
ebrus 0:6bc4ac881c8e 130 uint32_t gpio_add = Set_GPIO_Clock(port_index);
ebrus 0:6bc4ac881c8e 131 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
ebrus 0:6bc4ac881c8e 132
ebrus 0:6bc4ac881c8e 133 // Configure open-drain and pull-up/down
ebrus 0:6bc4ac881c8e 134 switch (mode) {
ebrus 0:6bc4ac881c8e 135 case PullNone:
ebrus 0:6bc4ac881c8e 136 return;
ebrus 0:6bc4ac881c8e 137 case PullUp:
ebrus 0:6bc4ac881c8e 138 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
ebrus 0:6bc4ac881c8e 139 break;
ebrus 0:6bc4ac881c8e 140 case PullDown:
ebrus 0:6bc4ac881c8e 141 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
ebrus 0:6bc4ac881c8e 142 break;
ebrus 0:6bc4ac881c8e 143 case OpenDrain:
ebrus 0:6bc4ac881c8e 144 if (pin_index < 8) {
ebrus 0:6bc4ac881c8e 145 if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode
ebrus 0:6bc4ac881c8e 146 gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain
ebrus 0:6bc4ac881c8e 147 }
ebrus 0:6bc4ac881c8e 148 } else {
ebrus 0:6bc4ac881c8e 149 if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) > 0) { // MODE bits = Output mode
ebrus 0:6bc4ac881c8e 150 gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain
ebrus 0:6bc4ac881c8e 151 }
ebrus 0:6bc4ac881c8e 152 }
ebrus 0:6bc4ac881c8e 153 return;
ebrus 0:6bc4ac881c8e 154 default:
ebrus 0:6bc4ac881c8e 155 break;
ebrus 0:6bc4ac881c8e 156 }
ebrus 0:6bc4ac881c8e 157
ebrus 0:6bc4ac881c8e 158 // Configure GPIO
ebrus 0:6bc4ac881c8e 159 GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index);
ebrus 0:6bc4ac881c8e 160 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
ebrus 0:6bc4ac881c8e 161 GPIO_Init(gpio, &GPIO_InitStructure);
ebrus 0:6bc4ac881c8e 162 }