Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_irq_api.c@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:6bc4ac881c8e 1 /* mbed Microcontroller Library
ebrus 0:6bc4ac881c8e 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:6bc4ac881c8e 3 *
ebrus 0:6bc4ac881c8e 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:6bc4ac881c8e 5 * you may not use this file except in compliance with the License.
ebrus 0:6bc4ac881c8e 6 * You may obtain a copy of the License at
ebrus 0:6bc4ac881c8e 7 *
ebrus 0:6bc4ac881c8e 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:6bc4ac881c8e 9 *
ebrus 0:6bc4ac881c8e 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:6bc4ac881c8e 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:6bc4ac881c8e 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:6bc4ac881c8e 13 * See the License for the specific language governing permissions and
ebrus 0:6bc4ac881c8e 14 * limitations under the License.
ebrus 0:6bc4ac881c8e 15 */
ebrus 0:6bc4ac881c8e 16 #include <stddef.h>
ebrus 0:6bc4ac881c8e 17 #include "cmsis.h"
ebrus 0:6bc4ac881c8e 18
ebrus 0:6bc4ac881c8e 19 #include "gpio_irq_api.h"
ebrus 0:6bc4ac881c8e 20
ebrus 0:6bc4ac881c8e 21 #if DEVICE_INTERRUPTIN
ebrus 0:6bc4ac881c8e 22
ebrus 0:6bc4ac881c8e 23 #include "gpio_api.h"
ebrus 0:6bc4ac881c8e 24 #include "fsl_gpio_hal.h"
ebrus 0:6bc4ac881c8e 25 #include "fsl_port_hal.h"
ebrus 0:6bc4ac881c8e 26 #include "mbed_error.h"
ebrus 0:6bc4ac881c8e 27
ebrus 0:6bc4ac881c8e 28 #define CHANNEL_NUM 160
ebrus 0:6bc4ac881c8e 29
ebrus 0:6bc4ac881c8e 30 static uint32_t channel_ids[CHANNEL_NUM] = {0};
ebrus 0:6bc4ac881c8e 31 static gpio_irq_handler irq_handler;
ebrus 0:6bc4ac881c8e 32
ebrus 0:6bc4ac881c8e 33 #define IRQ_DISABLED (0)
ebrus 0:6bc4ac881c8e 34 #define IRQ_RAISING_EDGE (9)
ebrus 0:6bc4ac881c8e 35 #define IRQ_FALLING_EDGE (10)
ebrus 0:6bc4ac881c8e 36 #define IRQ_EITHER_EDGE (11)
ebrus 0:6bc4ac881c8e 37
ebrus 0:6bc4ac881c8e 38 static void handle_interrupt_in(PortName port, int ch_base) {
ebrus 0:6bc4ac881c8e 39 uint32_t i;
ebrus 0:6bc4ac881c8e 40 uint32_t port_addrs[] = PORT_BASE_ADDRS;
ebrus 0:6bc4ac881c8e 41
ebrus 0:6bc4ac881c8e 42 for (i = 0; i < 32; i++) {
ebrus 0:6bc4ac881c8e 43 if (PORT_HAL_IsPinIntPending(port_addrs[port], i)) {
ebrus 0:6bc4ac881c8e 44 uint32_t id = channel_ids[ch_base + i];
ebrus 0:6bc4ac881c8e 45 if (id == 0) {
ebrus 0:6bc4ac881c8e 46 continue;
ebrus 0:6bc4ac881c8e 47 }
ebrus 0:6bc4ac881c8e 48
ebrus 0:6bc4ac881c8e 49 gpio_irq_event event = IRQ_NONE;
ebrus 0:6bc4ac881c8e 50 uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
ebrus 0:6bc4ac881c8e 51 switch (BR_PORT_PCRn_IRQC(port_addrs[port], i)) {
ebrus 0:6bc4ac881c8e 52 case IRQ_RAISING_EDGE:
ebrus 0:6bc4ac881c8e 53 event = IRQ_RISE;
ebrus 0:6bc4ac881c8e 54 break;
ebrus 0:6bc4ac881c8e 55
ebrus 0:6bc4ac881c8e 56 case IRQ_FALLING_EDGE:
ebrus 0:6bc4ac881c8e 57 event = IRQ_FALL;
ebrus 0:6bc4ac881c8e 58 break;
ebrus 0:6bc4ac881c8e 59
ebrus 0:6bc4ac881c8e 60 case IRQ_EITHER_EDGE:
ebrus 0:6bc4ac881c8e 61 event = (GPIO_HAL_ReadPinInput(gpio_addrs[port], i)) ? (IRQ_RISE) : (IRQ_FALL);
ebrus 0:6bc4ac881c8e 62 break;
ebrus 0:6bc4ac881c8e 63 }
ebrus 0:6bc4ac881c8e 64 if (event != IRQ_NONE) {
ebrus 0:6bc4ac881c8e 65 irq_handler(id, event);
ebrus 0:6bc4ac881c8e 66 }
ebrus 0:6bc4ac881c8e 67 }
ebrus 0:6bc4ac881c8e 68 }
ebrus 0:6bc4ac881c8e 69 PORT_HAL_ClearPortIntFlag(port_addrs[port]);
ebrus 0:6bc4ac881c8e 70 }
ebrus 0:6bc4ac881c8e 71
ebrus 0:6bc4ac881c8e 72 void gpio_irqA(void) {handle_interrupt_in(PortA, 0);}
ebrus 0:6bc4ac881c8e 73 void gpio_irqB(void) {handle_interrupt_in(PortB, 32);}
ebrus 0:6bc4ac881c8e 74 void gpio_irqC(void) {handle_interrupt_in(PortC, 64);}
ebrus 0:6bc4ac881c8e 75 void gpio_irqD(void) {handle_interrupt_in(PortD, 96);}
ebrus 0:6bc4ac881c8e 76 void gpio_irqE(void) {handle_interrupt_in(PortE, 128);}
ebrus 0:6bc4ac881c8e 77
ebrus 0:6bc4ac881c8e 78 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
ebrus 0:6bc4ac881c8e 79 if (pin == NC) {
ebrus 0:6bc4ac881c8e 80 return -1;
ebrus 0:6bc4ac881c8e 81 }
ebrus 0:6bc4ac881c8e 82
ebrus 0:6bc4ac881c8e 83 irq_handler = handler;
ebrus 0:6bc4ac881c8e 84 obj->port = pin >> GPIO_PORT_SHIFT;
ebrus 0:6bc4ac881c8e 85 obj->pin = pin & 0x7F;
ebrus 0:6bc4ac881c8e 86
ebrus 0:6bc4ac881c8e 87 uint32_t ch_base = 0;
ebrus 0:6bc4ac881c8e 88 uint32_t vector = (uint32_t)gpio_irqA;
ebrus 0:6bc4ac881c8e 89 IRQn_Type irq_n = PORTA_IRQn;
ebrus 0:6bc4ac881c8e 90 switch (obj->port) {
ebrus 0:6bc4ac881c8e 91 case PortA:
ebrus 0:6bc4ac881c8e 92 ch_base = 0;
ebrus 0:6bc4ac881c8e 93 irq_n = PORTA_IRQn;
ebrus 0:6bc4ac881c8e 94 vector = (uint32_t)gpio_irqA;
ebrus 0:6bc4ac881c8e 95 break;
ebrus 0:6bc4ac881c8e 96 case PortB:
ebrus 0:6bc4ac881c8e 97 ch_base = 32;
ebrus 0:6bc4ac881c8e 98 irq_n = PORTB_IRQn;
ebrus 0:6bc4ac881c8e 99 vector = (uint32_t)gpio_irqB;
ebrus 0:6bc4ac881c8e 100 break;
ebrus 0:6bc4ac881c8e 101 case PortC:
ebrus 0:6bc4ac881c8e 102 ch_base = 64;
ebrus 0:6bc4ac881c8e 103 irq_n = PORTC_IRQn;
ebrus 0:6bc4ac881c8e 104 vector = (uint32_t)gpio_irqC;
ebrus 0:6bc4ac881c8e 105 break;
ebrus 0:6bc4ac881c8e 106 case PortD:
ebrus 0:6bc4ac881c8e 107 ch_base = 96;
ebrus 0:6bc4ac881c8e 108 irq_n = PORTD_IRQn;
ebrus 0:6bc4ac881c8e 109 vector = (uint32_t)gpio_irqD;
ebrus 0:6bc4ac881c8e 110 break;
ebrus 0:6bc4ac881c8e 111 case PortE:
ebrus 0:6bc4ac881c8e 112 ch_base = 128;
ebrus 0:6bc4ac881c8e 113 irq_n = PORTE_IRQn;
ebrus 0:6bc4ac881c8e 114 vector = (uint32_t)gpio_irqE;
ebrus 0:6bc4ac881c8e 115 break;
ebrus 0:6bc4ac881c8e 116
ebrus 0:6bc4ac881c8e 117 default:
ebrus 0:6bc4ac881c8e 118 error("gpio_irq only supported on port A-E.");
ebrus 0:6bc4ac881c8e 119 break;
ebrus 0:6bc4ac881c8e 120 }
ebrus 0:6bc4ac881c8e 121 NVIC_SetVector(irq_n, vector);
ebrus 0:6bc4ac881c8e 122 NVIC_EnableIRQ(irq_n);
ebrus 0:6bc4ac881c8e 123
ebrus 0:6bc4ac881c8e 124 obj->ch = ch_base + obj->pin;
ebrus 0:6bc4ac881c8e 125 channel_ids[obj->ch] = id;
ebrus 0:6bc4ac881c8e 126
ebrus 0:6bc4ac881c8e 127 return 0;
ebrus 0:6bc4ac881c8e 128 }
ebrus 0:6bc4ac881c8e 129
ebrus 0:6bc4ac881c8e 130 void gpio_irq_free(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 131 channel_ids[obj->ch] = 0;
ebrus 0:6bc4ac881c8e 132 }
ebrus 0:6bc4ac881c8e 133
ebrus 0:6bc4ac881c8e 134 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
ebrus 0:6bc4ac881c8e 135 uint32_t port_addrs[] = PORT_BASE_ADDRS;
ebrus 0:6bc4ac881c8e 136 port_interrupt_config_t irq_settings = kPortIntDisabled;
ebrus 0:6bc4ac881c8e 137
ebrus 0:6bc4ac881c8e 138 switch (BR_PORT_PCRn_IRQC(port_addrs[obj->port], obj->pin)) {
ebrus 0:6bc4ac881c8e 139 case IRQ_DISABLED:
ebrus 0:6bc4ac881c8e 140 if (enable)
ebrus 0:6bc4ac881c8e 141 irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntFallingEdge);
ebrus 0:6bc4ac881c8e 142 break;
ebrus 0:6bc4ac881c8e 143
ebrus 0:6bc4ac881c8e 144 case IRQ_RAISING_EDGE:
ebrus 0:6bc4ac881c8e 145 if (enable) {
ebrus 0:6bc4ac881c8e 146 irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntEitherEdge);
ebrus 0:6bc4ac881c8e 147 } else {
ebrus 0:6bc4ac881c8e 148 if (event == IRQ_FALL)
ebrus 0:6bc4ac881c8e 149 irq_settings = kPortIntRisingEdge;
ebrus 0:6bc4ac881c8e 150 }
ebrus 0:6bc4ac881c8e 151 break;
ebrus 0:6bc4ac881c8e 152
ebrus 0:6bc4ac881c8e 153 case IRQ_FALLING_EDGE:
ebrus 0:6bc4ac881c8e 154 if (enable) {
ebrus 0:6bc4ac881c8e 155 irq_settings = (event == IRQ_FALL) ? (kPortIntFallingEdge) : (kPortIntEitherEdge);
ebrus 0:6bc4ac881c8e 156 } else {
ebrus 0:6bc4ac881c8e 157 if (event == IRQ_RISE)
ebrus 0:6bc4ac881c8e 158 irq_settings = kPortIntFallingEdge;
ebrus 0:6bc4ac881c8e 159 }
ebrus 0:6bc4ac881c8e 160 break;
ebrus 0:6bc4ac881c8e 161
ebrus 0:6bc4ac881c8e 162 case IRQ_EITHER_EDGE:
ebrus 0:6bc4ac881c8e 163 if (enable) {
ebrus 0:6bc4ac881c8e 164 irq_settings = kPortIntEitherEdge;
ebrus 0:6bc4ac881c8e 165 } else {
ebrus 0:6bc4ac881c8e 166 irq_settings = (event == IRQ_RISE) ? (kPortIntFallingEdge) : (kPortIntRisingEdge);
ebrus 0:6bc4ac881c8e 167 }
ebrus 0:6bc4ac881c8e 168 break;
ebrus 0:6bc4ac881c8e 169 }
ebrus 0:6bc4ac881c8e 170
ebrus 0:6bc4ac881c8e 171 PORT_HAL_SetPinIntMode(port_addrs[obj->port], obj->pin, irq_settings);
ebrus 0:6bc4ac881c8e 172 PORT_HAL_ClearPinIntFlag(port_addrs[obj->port], obj->pin);
ebrus 0:6bc4ac881c8e 173 }
ebrus 0:6bc4ac881c8e 174
ebrus 0:6bc4ac881c8e 175 void gpio_irq_enable(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 176 switch (obj->port) {
ebrus 0:6bc4ac881c8e 177 case PortA:
ebrus 0:6bc4ac881c8e 178 NVIC_EnableIRQ(PORTA_IRQn);
ebrus 0:6bc4ac881c8e 179 break;
ebrus 0:6bc4ac881c8e 180 case PortB:
ebrus 0:6bc4ac881c8e 181 NVIC_EnableIRQ(PORTB_IRQn);
ebrus 0:6bc4ac881c8e 182 break;
ebrus 0:6bc4ac881c8e 183 case PortC:
ebrus 0:6bc4ac881c8e 184 NVIC_EnableIRQ(PORTC_IRQn);
ebrus 0:6bc4ac881c8e 185 break;
ebrus 0:6bc4ac881c8e 186 case PortD:
ebrus 0:6bc4ac881c8e 187 NVIC_EnableIRQ(PORTD_IRQn);
ebrus 0:6bc4ac881c8e 188 break;
ebrus 0:6bc4ac881c8e 189 case PortE:
ebrus 0:6bc4ac881c8e 190 NVIC_EnableIRQ(PORTE_IRQn);
ebrus 0:6bc4ac881c8e 191 break;
ebrus 0:6bc4ac881c8e 192 }
ebrus 0:6bc4ac881c8e 193 }
ebrus 0:6bc4ac881c8e 194
ebrus 0:6bc4ac881c8e 195 void gpio_irq_disable(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 196 switch (obj->port) {
ebrus 0:6bc4ac881c8e 197 case PortA:
ebrus 0:6bc4ac881c8e 198 NVIC_DisableIRQ(PORTA_IRQn);
ebrus 0:6bc4ac881c8e 199 break;
ebrus 0:6bc4ac881c8e 200 case PortB:
ebrus 0:6bc4ac881c8e 201 NVIC_DisableIRQ(PORTB_IRQn);
ebrus 0:6bc4ac881c8e 202 break;
ebrus 0:6bc4ac881c8e 203 case PortC:
ebrus 0:6bc4ac881c8e 204 NVIC_DisableIRQ(PORTC_IRQn);
ebrus 0:6bc4ac881c8e 205 break;
ebrus 0:6bc4ac881c8e 206 case PortD:
ebrus 0:6bc4ac881c8e 207 NVIC_DisableIRQ(PORTD_IRQn);
ebrus 0:6bc4ac881c8e 208 break;
ebrus 0:6bc4ac881c8e 209 case PortE:
ebrus 0:6bc4ac881c8e 210 NVIC_DisableIRQ(PORTE_IRQn);
ebrus 0:6bc4ac881c8e 211 break;
ebrus 0:6bc4ac881c8e 212 }
ebrus 0:6bc4ac881c8e 213 }
ebrus 0:6bc4ac881c8e 214
ebrus 0:6bc4ac881c8e 215 #endif