mbed library sources
Dependents: FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more
targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c@0:6bc4ac881c8e, 2016-07-28 (annotated)
- Committer:
- ebrus
- Date:
- Thu Jul 28 15:56:34 2016 +0000
- Revision:
- 0:6bc4ac881c8e
1;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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ebrus | 0:6bc4ac881c8e | 1 | /* mbed Microcontroller Library |
ebrus | 0:6bc4ac881c8e | 2 | * Copyright (c) 2006-2013 ARM Limited |
ebrus | 0:6bc4ac881c8e | 3 | * |
ebrus | 0:6bc4ac881c8e | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
ebrus | 0:6bc4ac881c8e | 5 | * you may not use this file except in compliance with the License. |
ebrus | 0:6bc4ac881c8e | 6 | * You may obtain a copy of the License at |
ebrus | 0:6bc4ac881c8e | 7 | * |
ebrus | 0:6bc4ac881c8e | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
ebrus | 0:6bc4ac881c8e | 9 | * |
ebrus | 0:6bc4ac881c8e | 10 | * Unless required by applicable law or agreed to in writing, software |
ebrus | 0:6bc4ac881c8e | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
ebrus | 0:6bc4ac881c8e | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
ebrus | 0:6bc4ac881c8e | 13 | * See the License for the specific language governing permissions and |
ebrus | 0:6bc4ac881c8e | 14 | * limitations under the License. |
ebrus | 0:6bc4ac881c8e | 15 | */ |
ebrus | 0:6bc4ac881c8e | 16 | #include "mbed_assert.h" |
ebrus | 0:6bc4ac881c8e | 17 | #include "analogin_api.h" |
ebrus | 0:6bc4ac881c8e | 18 | |
ebrus | 0:6bc4ac881c8e | 19 | #include "cmsis.h" |
ebrus | 0:6bc4ac881c8e | 20 | #include "pinmap.h" |
ebrus | 0:6bc4ac881c8e | 21 | #include "clk_freqs.h" |
ebrus | 0:6bc4ac881c8e | 22 | #include "PeripheralPins.h" |
ebrus | 0:6bc4ac881c8e | 23 | |
ebrus | 0:6bc4ac881c8e | 24 | #define MAX_FADC 6000000 |
ebrus | 0:6bc4ac881c8e | 25 | #define CHANNELS_A_SHIFT 5 |
ebrus | 0:6bc4ac881c8e | 26 | |
ebrus | 0:6bc4ac881c8e | 27 | |
ebrus | 0:6bc4ac881c8e | 28 | void analogin_init(analogin_t *obj, PinName pin) { |
ebrus | 0:6bc4ac881c8e | 29 | obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); |
ebrus | 0:6bc4ac881c8e | 30 | MBED_ASSERT(obj->adc != (ADCName)NC); |
ebrus | 0:6bc4ac881c8e | 31 | |
ebrus | 0:6bc4ac881c8e | 32 | SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK; |
ebrus | 0:6bc4ac881c8e | 33 | |
ebrus | 0:6bc4ac881c8e | 34 | uint32_t port = (uint32_t)pin >> PORT_SHIFT; |
ebrus | 0:6bc4ac881c8e | 35 | SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); |
ebrus | 0:6bc4ac881c8e | 36 | |
ebrus | 0:6bc4ac881c8e | 37 | uint32_t cfg2_muxsel = ADC_CFG2_MUXSEL_MASK; |
ebrus | 0:6bc4ac881c8e | 38 | if (obj->adc & (1 << CHANNELS_A_SHIFT)) { |
ebrus | 0:6bc4ac881c8e | 39 | cfg2_muxsel = 0; |
ebrus | 0:6bc4ac881c8e | 40 | } |
ebrus | 0:6bc4ac881c8e | 41 | |
ebrus | 0:6bc4ac881c8e | 42 | // bus clk |
ebrus | 0:6bc4ac881c8e | 43 | uint32_t PCLK = bus_frequency(); |
ebrus | 0:6bc4ac881c8e | 44 | uint32_t clkdiv; |
ebrus | 0:6bc4ac881c8e | 45 | for (clkdiv = 0; clkdiv < 4; clkdiv++) { |
ebrus | 0:6bc4ac881c8e | 46 | if ((PCLK >> clkdiv) <= MAX_FADC) |
ebrus | 0:6bc4ac881c8e | 47 | break; |
ebrus | 0:6bc4ac881c8e | 48 | } |
ebrus | 0:6bc4ac881c8e | 49 | if (clkdiv == 4) //Set max div |
ebrus | 0:6bc4ac881c8e | 50 | clkdiv = 0x7; |
ebrus | 0:6bc4ac881c8e | 51 | |
ebrus | 0:6bc4ac881c8e | 52 | ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc & ~(1 << CHANNELS_A_SHIFT)); |
ebrus | 0:6bc4ac881c8e | 53 | |
ebrus | 0:6bc4ac881c8e | 54 | ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration |
ebrus | 0:6bc4ac881c8e | 55 | | ADC_CFG1_ADIV(clkdiv & 0x3) // Clock Divide Select: (Input Clock)/8 |
ebrus | 0:6bc4ac881c8e | 56 | | ADC_CFG1_ADLSMP_MASK // Long Sample Time |
ebrus | 0:6bc4ac881c8e | 57 | | ADC_CFG1_MODE(3) // (16)bits Resolution |
ebrus | 0:6bc4ac881c8e | 58 | | ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock: (Bus Clock)/2 |
ebrus | 0:6bc4ac881c8e | 59 | |
ebrus | 0:6bc4ac881c8e | 60 | ADC0->CFG2 = cfg2_muxsel // ADxxb or ADxxa channels |
ebrus | 0:6bc4ac881c8e | 61 | | ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable |
ebrus | 0:6bc4ac881c8e | 62 | | ADC_CFG2_ADHSC_MASK // High-Speed Configuration |
ebrus | 0:6bc4ac881c8e | 63 | | ADC_CFG2_ADLSTS(0); // Long Sample Time Select |
ebrus | 0:6bc4ac881c8e | 64 | |
ebrus | 0:6bc4ac881c8e | 65 | ADC0->SC2 = ADC_SC2_REFSEL(0); // Default Voltage Reference |
ebrus | 0:6bc4ac881c8e | 66 | |
ebrus | 0:6bc4ac881c8e | 67 | ADC0->SC3 = ADC_SC3_AVGE_MASK // Hardware Average Enable |
ebrus | 0:6bc4ac881c8e | 68 | | ADC_SC3_AVGS(0); // 4 Samples Averaged |
ebrus | 0:6bc4ac881c8e | 69 | |
ebrus | 0:6bc4ac881c8e | 70 | pinmap_pinout(pin, PinMap_ADC); |
ebrus | 0:6bc4ac881c8e | 71 | } |
ebrus | 0:6bc4ac881c8e | 72 | |
ebrus | 0:6bc4ac881c8e | 73 | uint16_t analogin_read_u16(analogin_t *obj) { |
ebrus | 0:6bc4ac881c8e | 74 | // start conversion |
ebrus | 0:6bc4ac881c8e | 75 | ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc & ~(1 << CHANNELS_A_SHIFT)); |
ebrus | 0:6bc4ac881c8e | 76 | |
ebrus | 0:6bc4ac881c8e | 77 | // Wait Conversion Complete |
ebrus | 0:6bc4ac881c8e | 78 | while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK); |
ebrus | 0:6bc4ac881c8e | 79 | |
ebrus | 0:6bc4ac881c8e | 80 | // Return value |
ebrus | 0:6bc4ac881c8e | 81 | return (uint16_t)ADC0->R[0]; |
ebrus | 0:6bc4ac881c8e | 82 | } |
ebrus | 0:6bc4ac881c8e | 83 | |
ebrus | 0:6bc4ac881c8e | 84 | float analogin_read(analogin_t *obj) { |
ebrus | 0:6bc4ac881c8e | 85 | uint16_t value = analogin_read_u16(obj); |
ebrus | 0:6bc4ac881c8e | 86 | return (float)value * (1.0f / (float)0xFFFF); |
ebrus | 0:6bc4ac881c8e | 87 | } |
ebrus | 0:6bc4ac881c8e | 88 |