Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

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ebrus 0:6bc4ac881c8e 1 /* mbed Microcontroller Library
ebrus 0:6bc4ac881c8e 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:6bc4ac881c8e 3 *
ebrus 0:6bc4ac881c8e 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:6bc4ac881c8e 5 * you may not use this file except in compliance with the License.
ebrus 0:6bc4ac881c8e 6 * You may obtain a copy of the License at
ebrus 0:6bc4ac881c8e 7 *
ebrus 0:6bc4ac881c8e 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:6bc4ac881c8e 9 *
ebrus 0:6bc4ac881c8e 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:6bc4ac881c8e 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:6bc4ac881c8e 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:6bc4ac881c8e 13 * See the License for the specific language governing permissions and
ebrus 0:6bc4ac881c8e 14 * limitations under the License.
ebrus 0:6bc4ac881c8e 15 */
ebrus 0:6bc4ac881c8e 16 #include "mbed_assert.h"
ebrus 0:6bc4ac881c8e 17 #include "spi_api.h"
ebrus 0:6bc4ac881c8e 18
ebrus 0:6bc4ac881c8e 19 #include <math.h>
ebrus 0:6bc4ac881c8e 20
ebrus 0:6bc4ac881c8e 21 #include "cmsis.h"
ebrus 0:6bc4ac881c8e 22 #include "pinmap.h"
ebrus 0:6bc4ac881c8e 23
ebrus 0:6bc4ac881c8e 24 static const PinMap PinMap_SPI_SCLK[] = {
ebrus 0:6bc4ac881c8e 25 {PTA15, SPI_0, 2},
ebrus 0:6bc4ac881c8e 26 {PTB9, SPI_1, 2},
ebrus 0:6bc4ac881c8e 27 {PTB11, SPI_1, 2},
ebrus 0:6bc4ac881c8e 28 {PTC5, SPI_0, 2},
ebrus 0:6bc4ac881c8e 29 {PTD1, SPI_0, 2},
ebrus 0:6bc4ac881c8e 30 {PTD5, SPI_1, 2},
ebrus 0:6bc4ac881c8e 31 {PTE2, SPI_1, 2},
ebrus 0:6bc4ac881c8e 32 {PTE17, SPI_0, 2},
ebrus 0:6bc4ac881c8e 33 {NC , NC , 0}
ebrus 0:6bc4ac881c8e 34 };
ebrus 0:6bc4ac881c8e 35
ebrus 0:6bc4ac881c8e 36 static const PinMap PinMap_SPI_MOSI[] = {
ebrus 0:6bc4ac881c8e 37 {PTA16, SPI_0, 2},
ebrus 0:6bc4ac881c8e 38 {PTA17, SPI_0, 5},
ebrus 0:6bc4ac881c8e 39 {PTB16, SPI_1, 2},
ebrus 0:6bc4ac881c8e 40 {PTB17, SPI_1, 5},
ebrus 0:6bc4ac881c8e 41 {PTC6, SPI_0, 2},
ebrus 0:6bc4ac881c8e 42 {PTC7, SPI_0, 5},
ebrus 0:6bc4ac881c8e 43 {PTD2, SPI_0, 2},
ebrus 0:6bc4ac881c8e 44 {PTD3, SPI_0, 5},
ebrus 0:6bc4ac881c8e 45 {PTD6, SPI_1, 2},
ebrus 0:6bc4ac881c8e 46 {PTD7, SPI_1, 5},
ebrus 0:6bc4ac881c8e 47 {PTE1, SPI_1, 2},
ebrus 0:6bc4ac881c8e 48 {PTE3, SPI_1, 5},
ebrus 0:6bc4ac881c8e 49 {PTE18, SPI_0, 2},
ebrus 0:6bc4ac881c8e 50 {PTE19, SPI_0, 5},
ebrus 0:6bc4ac881c8e 51 {NC , NC , 0}
ebrus 0:6bc4ac881c8e 52 };
ebrus 0:6bc4ac881c8e 53
ebrus 0:6bc4ac881c8e 54 static const PinMap PinMap_SPI_MISO[] = {
ebrus 0:6bc4ac881c8e 55 {PTA16, SPI_0, 5},
ebrus 0:6bc4ac881c8e 56 {PTA17, SPI_0, 2},
ebrus 0:6bc4ac881c8e 57 {PTB16, SPI_1, 5},
ebrus 0:6bc4ac881c8e 58 {PTB17, SPI_1, 2},
ebrus 0:6bc4ac881c8e 59 {PTC6, SPI_0, 5},
ebrus 0:6bc4ac881c8e 60 {PTC7, SPI_0, 2},
ebrus 0:6bc4ac881c8e 61 {PTD2, SPI_0, 5},
ebrus 0:6bc4ac881c8e 62 {PTD3, SPI_0, 2},
ebrus 0:6bc4ac881c8e 63 {PTD6, SPI_1, 5},
ebrus 0:6bc4ac881c8e 64 {PTD7, SPI_1, 2},
ebrus 0:6bc4ac881c8e 65 {PTE1, SPI_1, 5},
ebrus 0:6bc4ac881c8e 66 {PTE3, SPI_1, 2},
ebrus 0:6bc4ac881c8e 67 {PTE18, SPI_0, 5},
ebrus 0:6bc4ac881c8e 68 {PTE19, SPI_0, 2},
ebrus 0:6bc4ac881c8e 69 {NC , NC , 0}
ebrus 0:6bc4ac881c8e 70 };
ebrus 0:6bc4ac881c8e 71
ebrus 0:6bc4ac881c8e 72 static const PinMap PinMap_SPI_SSEL[] = {
ebrus 0:6bc4ac881c8e 73 {PTA14, SPI_0, 2},
ebrus 0:6bc4ac881c8e 74 {PTB10, SPI_1, 2},
ebrus 0:6bc4ac881c8e 75 {PTC4, SPI_0, 2},
ebrus 0:6bc4ac881c8e 76 {PTD0, SPI_0, 2},
ebrus 0:6bc4ac881c8e 77 {PTD4, SPI_1, 2},
ebrus 0:6bc4ac881c8e 78 {PTE4, SPI_1, 2},
ebrus 0:6bc4ac881c8e 79 {PTE16, SPI_0, 2},
ebrus 0:6bc4ac881c8e 80 {NC , NC , 0}
ebrus 0:6bc4ac881c8e 81 };
ebrus 0:6bc4ac881c8e 82
ebrus 0:6bc4ac881c8e 83 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
ebrus 0:6bc4ac881c8e 84 // determine the SPI to use
ebrus 0:6bc4ac881c8e 85 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
ebrus 0:6bc4ac881c8e 86 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
ebrus 0:6bc4ac881c8e 87 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
ebrus 0:6bc4ac881c8e 88 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
ebrus 0:6bc4ac881c8e 89 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
ebrus 0:6bc4ac881c8e 90 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
ebrus 0:6bc4ac881c8e 91
ebrus 0:6bc4ac881c8e 92 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
ebrus 0:6bc4ac881c8e 93 MBED_ASSERT((int)obj->spi != NC);
ebrus 0:6bc4ac881c8e 94
ebrus 0:6bc4ac881c8e 95 // enable power and clocking
ebrus 0:6bc4ac881c8e 96 switch ((int)obj->spi) {
ebrus 0:6bc4ac881c8e 97 case SPI_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 22; break;
ebrus 0:6bc4ac881c8e 98 case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
ebrus 0:6bc4ac881c8e 99 }
ebrus 0:6bc4ac881c8e 100
ebrus 0:6bc4ac881c8e 101 // set default format and frequency
ebrus 0:6bc4ac881c8e 102 if (ssel == NC) {
ebrus 0:6bc4ac881c8e 103 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
ebrus 0:6bc4ac881c8e 104 } else {
ebrus 0:6bc4ac881c8e 105 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
ebrus 0:6bc4ac881c8e 106 }
ebrus 0:6bc4ac881c8e 107 spi_frequency(obj, 1000000);
ebrus 0:6bc4ac881c8e 108
ebrus 0:6bc4ac881c8e 109 // enable SPI
ebrus 0:6bc4ac881c8e 110 obj->spi->C1 |= SPI_C1_SPE_MASK;
ebrus 0:6bc4ac881c8e 111 obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit
ebrus 0:6bc4ac881c8e 112
ebrus 0:6bc4ac881c8e 113 // pin out the spi pins
ebrus 0:6bc4ac881c8e 114 pinmap_pinout(mosi, PinMap_SPI_MOSI);
ebrus 0:6bc4ac881c8e 115 pinmap_pinout(miso, PinMap_SPI_MISO);
ebrus 0:6bc4ac881c8e 116 pinmap_pinout(sclk, PinMap_SPI_SCLK);
ebrus 0:6bc4ac881c8e 117 if (ssel != NC) {
ebrus 0:6bc4ac881c8e 118 pinmap_pinout(ssel, PinMap_SPI_SSEL);
ebrus 0:6bc4ac881c8e 119 }
ebrus 0:6bc4ac881c8e 120 }
ebrus 0:6bc4ac881c8e 121
ebrus 0:6bc4ac881c8e 122 void spi_free(spi_t *obj) {
ebrus 0:6bc4ac881c8e 123 // [TODO]
ebrus 0:6bc4ac881c8e 124 }
ebrus 0:6bc4ac881c8e 125 void spi_format(spi_t *obj, int bits, int mode, int slave) {
ebrus 0:6bc4ac881c8e 126 MBED_ASSERT((bits == 8) || (bits == 16));
ebrus 0:6bc4ac881c8e 127 MBED_ASSERT((mode >= 0) && (mode <= 3));
ebrus 0:6bc4ac881c8e 128
ebrus 0:6bc4ac881c8e 129 uint8_t polarity = (mode & 0x2) ? 1 : 0;
ebrus 0:6bc4ac881c8e 130 uint8_t phase = (mode & 0x1) ? 1 : 0;
ebrus 0:6bc4ac881c8e 131 uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
ebrus 0:6bc4ac881c8e 132
ebrus 0:6bc4ac881c8e 133 // clear MSTR, CPOL and CPHA bits
ebrus 0:6bc4ac881c8e 134 obj->spi->C1 &= ~(0x7 << 2);
ebrus 0:6bc4ac881c8e 135
ebrus 0:6bc4ac881c8e 136 // write new value
ebrus 0:6bc4ac881c8e 137 obj->spi->C1 |= c1_data;
ebrus 0:6bc4ac881c8e 138 if (bits == 8) {
ebrus 0:6bc4ac881c8e 139 obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK;
ebrus 0:6bc4ac881c8e 140 } else {
ebrus 0:6bc4ac881c8e 141 obj->spi->C2 |= SPI_C2_SPIMODE_MASK;
ebrus 0:6bc4ac881c8e 142 }
ebrus 0:6bc4ac881c8e 143 }
ebrus 0:6bc4ac881c8e 144
ebrus 0:6bc4ac881c8e 145 void spi_frequency(spi_t *obj, int hz) {
ebrus 0:6bc4ac881c8e 146 uint32_t error = 0;
ebrus 0:6bc4ac881c8e 147 uint32_t p_error = 0xffffffff;
ebrus 0:6bc4ac881c8e 148 uint32_t ref = 0;
ebrus 0:6bc4ac881c8e 149 uint8_t spr = 0;
ebrus 0:6bc4ac881c8e 150 uint8_t ref_spr = 0;
ebrus 0:6bc4ac881c8e 151 uint8_t ref_prescaler = 0;
ebrus 0:6bc4ac881c8e 152
ebrus 0:6bc4ac881c8e 153 // bus clk
ebrus 0:6bc4ac881c8e 154 uint32_t PCLK = SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
ebrus 0:6bc4ac881c8e 155 uint8_t prescaler = 1;
ebrus 0:6bc4ac881c8e 156 uint8_t divisor = 2;
ebrus 0:6bc4ac881c8e 157
ebrus 0:6bc4ac881c8e 158 for (prescaler = 1; prescaler <= 8; prescaler++) {
ebrus 0:6bc4ac881c8e 159 divisor = 2;
ebrus 0:6bc4ac881c8e 160 for (spr = 0; spr <= 8; spr++, divisor *= 2) {
ebrus 0:6bc4ac881c8e 161 ref = PCLK / (prescaler*divisor);
ebrus 0:6bc4ac881c8e 162 if (ref > (uint32_t)hz)
ebrus 0:6bc4ac881c8e 163 continue;
ebrus 0:6bc4ac881c8e 164 error = hz - ref;
ebrus 0:6bc4ac881c8e 165 if (error < p_error) {
ebrus 0:6bc4ac881c8e 166 ref_spr = spr;
ebrus 0:6bc4ac881c8e 167 ref_prescaler = prescaler - 1;
ebrus 0:6bc4ac881c8e 168 p_error = error;
ebrus 0:6bc4ac881c8e 169 }
ebrus 0:6bc4ac881c8e 170 }
ebrus 0:6bc4ac881c8e 171 }
ebrus 0:6bc4ac881c8e 172
ebrus 0:6bc4ac881c8e 173 // set SPPR and SPR
ebrus 0:6bc4ac881c8e 174 obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
ebrus 0:6bc4ac881c8e 175 }
ebrus 0:6bc4ac881c8e 176
ebrus 0:6bc4ac881c8e 177 static inline int spi_writeable(spi_t * obj) {
ebrus 0:6bc4ac881c8e 178 return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
ebrus 0:6bc4ac881c8e 179 }
ebrus 0:6bc4ac881c8e 180
ebrus 0:6bc4ac881c8e 181 static inline int spi_readable(spi_t * obj) {
ebrus 0:6bc4ac881c8e 182 return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
ebrus 0:6bc4ac881c8e 183 }
ebrus 0:6bc4ac881c8e 184
ebrus 0:6bc4ac881c8e 185 int spi_master_write(spi_t *obj, int value) {
ebrus 0:6bc4ac881c8e 186 int ret;
ebrus 0:6bc4ac881c8e 187 if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
ebrus 0:6bc4ac881c8e 188 // 16bit
ebrus 0:6bc4ac881c8e 189 while(!spi_writeable(obj));
ebrus 0:6bc4ac881c8e 190 obj->spi->DL = (value & 0xff);
ebrus 0:6bc4ac881c8e 191 obj->spi->DH = ((value >> 8) & 0xff);
ebrus 0:6bc4ac881c8e 192
ebrus 0:6bc4ac881c8e 193 // wait rx buffer full
ebrus 0:6bc4ac881c8e 194 while (!spi_readable(obj));
ebrus 0:6bc4ac881c8e 195 ret = obj->spi->DH;
ebrus 0:6bc4ac881c8e 196 ret = (ret << 8) | obj->spi->DL;
ebrus 0:6bc4ac881c8e 197 } else {
ebrus 0:6bc4ac881c8e 198 //8bit
ebrus 0:6bc4ac881c8e 199 while(!spi_writeable(obj));
ebrus 0:6bc4ac881c8e 200 obj->spi->DL = (value & 0xff);
ebrus 0:6bc4ac881c8e 201
ebrus 0:6bc4ac881c8e 202 // wait rx buffer full
ebrus 0:6bc4ac881c8e 203 while (!spi_readable(obj));
ebrus 0:6bc4ac881c8e 204 ret = (obj->spi->DL & 0xff);
ebrus 0:6bc4ac881c8e 205 }
ebrus 0:6bc4ac881c8e 206
ebrus 0:6bc4ac881c8e 207 return ret;
ebrus 0:6bc4ac881c8e 208 }
ebrus 0:6bc4ac881c8e 209
ebrus 0:6bc4ac881c8e 210 int spi_slave_receive(spi_t *obj) {
ebrus 0:6bc4ac881c8e 211 return spi_readable(obj);
ebrus 0:6bc4ac881c8e 212 }
ebrus 0:6bc4ac881c8e 213
ebrus 0:6bc4ac881c8e 214 int spi_slave_read(spi_t *obj) {
ebrus 0:6bc4ac881c8e 215 int ret;
ebrus 0:6bc4ac881c8e 216 if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
ebrus 0:6bc4ac881c8e 217 ret = obj->spi->DH;
ebrus 0:6bc4ac881c8e 218 ret = ((ret << 8) | obj->spi->DL);
ebrus 0:6bc4ac881c8e 219 } else {
ebrus 0:6bc4ac881c8e 220 ret = obj->spi->DL;
ebrus 0:6bc4ac881c8e 221 }
ebrus 0:6bc4ac881c8e 222 return ret;
ebrus 0:6bc4ac881c8e 223 }
ebrus 0:6bc4ac881c8e 224
ebrus 0:6bc4ac881c8e 225 void spi_slave_write(spi_t *obj, int value) {
ebrus 0:6bc4ac881c8e 226 while (!spi_writeable(obj));
ebrus 0:6bc4ac881c8e 227 if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
ebrus 0:6bc4ac881c8e 228 obj->spi->DL = (value & 0xff);
ebrus 0:6bc4ac881c8e 229 obj->spi->DH = ((value >> 8) & 0xff);
ebrus 0:6bc4ac881c8e 230 } else {
ebrus 0:6bc4ac881c8e 231 obj->spi->DL = value;
ebrus 0:6bc4ac881c8e 232 }
ebrus 0:6bc4ac881c8e 233
ebrus 0:6bc4ac881c8e 234 }