Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:6bc4ac881c8e 1 /* mbed Microcontroller Library
ebrus 0:6bc4ac881c8e 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:6bc4ac881c8e 3 *
ebrus 0:6bc4ac881c8e 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:6bc4ac881c8e 5 * you may not use this file except in compliance with the License.
ebrus 0:6bc4ac881c8e 6 * You may obtain a copy of the License at
ebrus 0:6bc4ac881c8e 7 *
ebrus 0:6bc4ac881c8e 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:6bc4ac881c8e 9 *
ebrus 0:6bc4ac881c8e 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:6bc4ac881c8e 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:6bc4ac881c8e 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:6bc4ac881c8e 13 * See the License for the specific language governing permissions and
ebrus 0:6bc4ac881c8e 14 * limitations under the License.
ebrus 0:6bc4ac881c8e 15 */
ebrus 0:6bc4ac881c8e 16 #include <stddef.h>
ebrus 0:6bc4ac881c8e 17 #include "cmsis.h"
ebrus 0:6bc4ac881c8e 18
ebrus 0:6bc4ac881c8e 19 #include "gpio_irq_api.h"
ebrus 0:6bc4ac881c8e 20 #include "gpio_api.h"
ebrus 0:6bc4ac881c8e 21 #include "mbed_error.h"
ebrus 0:6bc4ac881c8e 22
ebrus 0:6bc4ac881c8e 23 #define CHANNEL_NUM 96
ebrus 0:6bc4ac881c8e 24
ebrus 0:6bc4ac881c8e 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
ebrus 0:6bc4ac881c8e 26 static gpio_irq_handler irq_handler;
ebrus 0:6bc4ac881c8e 27
ebrus 0:6bc4ac881c8e 28 #define IRQ_DISABLED (0)
ebrus 0:6bc4ac881c8e 29 #define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
ebrus 0:6bc4ac881c8e 30 #define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
ebrus 0:6bc4ac881c8e 31 #define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
ebrus 0:6bc4ac881c8e 32
ebrus 0:6bc4ac881c8e 33 const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001};
ebrus 0:6bc4ac881c8e 34
ebrus 0:6bc4ac881c8e 35 static void handle_interrupt_in(PORT_Type *port, int ch_base) {
ebrus 0:6bc4ac881c8e 36 uint32_t isfr;
ebrus 0:6bc4ac881c8e 37 uint8_t location;
ebrus 0:6bc4ac881c8e 38
ebrus 0:6bc4ac881c8e 39 while((isfr = port->ISFR) != 0) {
ebrus 0:6bc4ac881c8e 40 location = 0;
ebrus 0:6bc4ac881c8e 41 for (int i = 0; i < 5; i++) {
ebrus 0:6bc4ac881c8e 42 if (!(isfr & (search_bits[i] << location)))
ebrus 0:6bc4ac881c8e 43 location += 1 << (4 - i);
ebrus 0:6bc4ac881c8e 44 }
ebrus 0:6bc4ac881c8e 45
ebrus 0:6bc4ac881c8e 46 uint32_t id = channel_ids[ch_base + location];
ebrus 0:6bc4ac881c8e 47 if (id == 0) {
ebrus 0:6bc4ac881c8e 48 continue;
ebrus 0:6bc4ac881c8e 49 }
ebrus 0:6bc4ac881c8e 50
ebrus 0:6bc4ac881c8e 51 FGPIO_Type *gpio;
ebrus 0:6bc4ac881c8e 52 gpio_irq_event event = IRQ_NONE;
ebrus 0:6bc4ac881c8e 53 switch (port->PCR[location] & PORT_PCR_IRQC_MASK) {
ebrus 0:6bc4ac881c8e 54 case IRQ_RAISING_EDGE:
ebrus 0:6bc4ac881c8e 55 event = IRQ_RISE;
ebrus 0:6bc4ac881c8e 56 break;
ebrus 0:6bc4ac881c8e 57
ebrus 0:6bc4ac881c8e 58 case IRQ_FALLING_EDGE:
ebrus 0:6bc4ac881c8e 59 event = IRQ_FALL;
ebrus 0:6bc4ac881c8e 60 break;
ebrus 0:6bc4ac881c8e 61
ebrus 0:6bc4ac881c8e 62 case IRQ_EITHER_EDGE:
ebrus 0:6bc4ac881c8e 63 if (port == PORTA) {
ebrus 0:6bc4ac881c8e 64 gpio = FPTA;
ebrus 0:6bc4ac881c8e 65 } else if (port == PORTC) {
ebrus 0:6bc4ac881c8e 66 gpio = FPTC;
ebrus 0:6bc4ac881c8e 67 } else {
ebrus 0:6bc4ac881c8e 68 gpio = FPTD;
ebrus 0:6bc4ac881c8e 69 }
ebrus 0:6bc4ac881c8e 70 event = (gpio->PDIR & (1<<location)) ? (IRQ_RISE) : (IRQ_FALL);
ebrus 0:6bc4ac881c8e 71 break;
ebrus 0:6bc4ac881c8e 72 }
ebrus 0:6bc4ac881c8e 73 if (event != IRQ_NONE) {
ebrus 0:6bc4ac881c8e 74 irq_handler(id, event);
ebrus 0:6bc4ac881c8e 75 }
ebrus 0:6bc4ac881c8e 76 port->ISFR = 1 << location;
ebrus 0:6bc4ac881c8e 77 }
ebrus 0:6bc4ac881c8e 78 }
ebrus 0:6bc4ac881c8e 79
ebrus 0:6bc4ac881c8e 80 void gpio_irqA(void) {
ebrus 0:6bc4ac881c8e 81 handle_interrupt_in(PORTA, 0);
ebrus 0:6bc4ac881c8e 82 }
ebrus 0:6bc4ac881c8e 83
ebrus 0:6bc4ac881c8e 84 /* PORTC and PORTD share same vector */
ebrus 0:6bc4ac881c8e 85 void gpio_irqCD(void) {
ebrus 0:6bc4ac881c8e 86 if ((SIM->SCGC5 & SIM_SCGC5_PORTC_MASK) && (PORTC->ISFR)) {
ebrus 0:6bc4ac881c8e 87 handle_interrupt_in(PORTC, 32);
ebrus 0:6bc4ac881c8e 88 } else if ((SIM->SCGC5 & SIM_SCGC5_PORTD_MASK) && (PORTD->ISFR)) {
ebrus 0:6bc4ac881c8e 89 handle_interrupt_in(PORTD, 64);
ebrus 0:6bc4ac881c8e 90 }
ebrus 0:6bc4ac881c8e 91 }
ebrus 0:6bc4ac881c8e 92
ebrus 0:6bc4ac881c8e 93 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
ebrus 0:6bc4ac881c8e 94 if (pin == NC)
ebrus 0:6bc4ac881c8e 95 return -1;
ebrus 0:6bc4ac881c8e 96
ebrus 0:6bc4ac881c8e 97 irq_handler = handler;
ebrus 0:6bc4ac881c8e 98
ebrus 0:6bc4ac881c8e 99 obj->port = pin >> PORT_SHIFT;
ebrus 0:6bc4ac881c8e 100 obj->pin = (pin & 0x7F) >> 2;
ebrus 0:6bc4ac881c8e 101
ebrus 0:6bc4ac881c8e 102 uint32_t ch_base, vector;
ebrus 0:6bc4ac881c8e 103 IRQn_Type irq_n;
ebrus 0:6bc4ac881c8e 104 switch (obj->port) {
ebrus 0:6bc4ac881c8e 105 case PortA:
ebrus 0:6bc4ac881c8e 106 ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
ebrus 0:6bc4ac881c8e 107 break;
ebrus 0:6bc4ac881c8e 108
ebrus 0:6bc4ac881c8e 109 case PortC:
ebrus 0:6bc4ac881c8e 110 ch_base = 32; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD;
ebrus 0:6bc4ac881c8e 111 break;
ebrus 0:6bc4ac881c8e 112
ebrus 0:6bc4ac881c8e 113 case PortD:
ebrus 0:6bc4ac881c8e 114 ch_base = 64; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD;
ebrus 0:6bc4ac881c8e 115 break;
ebrus 0:6bc4ac881c8e 116
ebrus 0:6bc4ac881c8e 117 default:
ebrus 0:6bc4ac881c8e 118 error("gpio_irq only supported on port A,C and D");
ebrus 0:6bc4ac881c8e 119 break;
ebrus 0:6bc4ac881c8e 120 }
ebrus 0:6bc4ac881c8e 121 NVIC_SetVector(irq_n, vector);
ebrus 0:6bc4ac881c8e 122 NVIC_EnableIRQ(irq_n);
ebrus 0:6bc4ac881c8e 123
ebrus 0:6bc4ac881c8e 124 obj->ch = ch_base + obj->pin;
ebrus 0:6bc4ac881c8e 125 channel_ids[obj->ch] = id;
ebrus 0:6bc4ac881c8e 126
ebrus 0:6bc4ac881c8e 127 return 0;
ebrus 0:6bc4ac881c8e 128 }
ebrus 0:6bc4ac881c8e 129
ebrus 0:6bc4ac881c8e 130 void gpio_irq_free(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 131 channel_ids[obj->ch] = 0;
ebrus 0:6bc4ac881c8e 132 }
ebrus 0:6bc4ac881c8e 133
ebrus 0:6bc4ac881c8e 134 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
ebrus 0:6bc4ac881c8e 135 PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
ebrus 0:6bc4ac881c8e 136
ebrus 0:6bc4ac881c8e 137 uint32_t irq_settings = IRQ_DISABLED;
ebrus 0:6bc4ac881c8e 138
ebrus 0:6bc4ac881c8e 139 switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
ebrus 0:6bc4ac881c8e 140 case IRQ_DISABLED:
ebrus 0:6bc4ac881c8e 141 if (enable) {
ebrus 0:6bc4ac881c8e 142 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
ebrus 0:6bc4ac881c8e 143 }
ebrus 0:6bc4ac881c8e 144 break;
ebrus 0:6bc4ac881c8e 145
ebrus 0:6bc4ac881c8e 146 case IRQ_RAISING_EDGE:
ebrus 0:6bc4ac881c8e 147 if (enable) {
ebrus 0:6bc4ac881c8e 148 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
ebrus 0:6bc4ac881c8e 149 } else {
ebrus 0:6bc4ac881c8e 150 if (event == IRQ_FALL)
ebrus 0:6bc4ac881c8e 151 irq_settings = IRQ_RAISING_EDGE;
ebrus 0:6bc4ac881c8e 152 }
ebrus 0:6bc4ac881c8e 153 break;
ebrus 0:6bc4ac881c8e 154
ebrus 0:6bc4ac881c8e 155 case IRQ_FALLING_EDGE:
ebrus 0:6bc4ac881c8e 156 if (enable) {
ebrus 0:6bc4ac881c8e 157 irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
ebrus 0:6bc4ac881c8e 158 } else {
ebrus 0:6bc4ac881c8e 159 if (event == IRQ_RISE)
ebrus 0:6bc4ac881c8e 160 irq_settings = IRQ_FALLING_EDGE;
ebrus 0:6bc4ac881c8e 161 }
ebrus 0:6bc4ac881c8e 162 break;
ebrus 0:6bc4ac881c8e 163
ebrus 0:6bc4ac881c8e 164 case IRQ_EITHER_EDGE:
ebrus 0:6bc4ac881c8e 165 if (enable) {
ebrus 0:6bc4ac881c8e 166 irq_settings = IRQ_EITHER_EDGE;
ebrus 0:6bc4ac881c8e 167 } else {
ebrus 0:6bc4ac881c8e 168 irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
ebrus 0:6bc4ac881c8e 169 }
ebrus 0:6bc4ac881c8e 170 break;
ebrus 0:6bc4ac881c8e 171 }
ebrus 0:6bc4ac881c8e 172
ebrus 0:6bc4ac881c8e 173 // Interrupt configuration and clear interrupt
ebrus 0:6bc4ac881c8e 174 port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
ebrus 0:6bc4ac881c8e 175 }
ebrus 0:6bc4ac881c8e 176
ebrus 0:6bc4ac881c8e 177 void gpio_irq_enable(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 178 if (obj->port == PortA) {
ebrus 0:6bc4ac881c8e 179 NVIC_EnableIRQ(PORTA_IRQn);
ebrus 0:6bc4ac881c8e 180 } else {
ebrus 0:6bc4ac881c8e 181 NVIC_EnableIRQ(PORTC_PORTD_IRQn);
ebrus 0:6bc4ac881c8e 182 }
ebrus 0:6bc4ac881c8e 183 }
ebrus 0:6bc4ac881c8e 184
ebrus 0:6bc4ac881c8e 185 void gpio_irq_disable(gpio_irq_t *obj) {
ebrus 0:6bc4ac881c8e 186 if (obj->port == PortA) {
ebrus 0:6bc4ac881c8e 187 NVIC_DisableIRQ(PORTA_IRQn);
ebrus 0:6bc4ac881c8e 188 } else {
ebrus 0:6bc4ac881c8e 189 NVIC_DisableIRQ(PORTC_PORTD_IRQn);
ebrus 0:6bc4ac881c8e 190 }
ebrus 0:6bc4ac881c8e 191 }