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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f407xx.h@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

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ebrus 0:6bc4ac881c8e 1 /**
ebrus 0:6bc4ac881c8e 2 ******************************************************************************
ebrus 0:6bc4ac881c8e 3 * @file stm32f407xx.h
ebrus 0:6bc4ac881c8e 4 * @author MCD Application Team
ebrus 0:6bc4ac881c8e 5 * @version V2.1.0
ebrus 0:6bc4ac881c8e 6 * @date 19-June-2014
ebrus 0:6bc4ac881c8e 7 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
ebrus 0:6bc4ac881c8e 8 *
ebrus 0:6bc4ac881c8e 9 * This file contains:
ebrus 0:6bc4ac881c8e 10 * - Data structures and the address mapping for all peripherals
ebrus 0:6bc4ac881c8e 11 * - Peripheral's registers declarations and bits definition
ebrus 0:6bc4ac881c8e 12 * - Macros to access peripheral’s registers hardware
ebrus 0:6bc4ac881c8e 13 *
ebrus 0:6bc4ac881c8e 14 ******************************************************************************
ebrus 0:6bc4ac881c8e 15 * @attention
ebrus 0:6bc4ac881c8e 16 *
ebrus 0:6bc4ac881c8e 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:6bc4ac881c8e 18 *
ebrus 0:6bc4ac881c8e 19 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:6bc4ac881c8e 20 * are permitted provided that the following conditions are met:
ebrus 0:6bc4ac881c8e 21 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:6bc4ac881c8e 22 * this list of conditions and the following disclaimer.
ebrus 0:6bc4ac881c8e 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:6bc4ac881c8e 24 * this list of conditions and the following disclaimer in the documentation
ebrus 0:6bc4ac881c8e 25 * and/or other materials provided with the distribution.
ebrus 0:6bc4ac881c8e 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:6bc4ac881c8e 27 * may be used to endorse or promote products derived from this software
ebrus 0:6bc4ac881c8e 28 * without specific prior written permission.
ebrus 0:6bc4ac881c8e 29 *
ebrus 0:6bc4ac881c8e 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:6bc4ac881c8e 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:6bc4ac881c8e 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:6bc4ac881c8e 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:6bc4ac881c8e 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:6bc4ac881c8e 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:6bc4ac881c8e 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:6bc4ac881c8e 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:6bc4ac881c8e 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:6bc4ac881c8e 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:6bc4ac881c8e 40 *
ebrus 0:6bc4ac881c8e 41 ******************************************************************************
ebrus 0:6bc4ac881c8e 42 */
ebrus 0:6bc4ac881c8e 43
ebrus 0:6bc4ac881c8e 44 /** @addtogroup CMSIS
ebrus 0:6bc4ac881c8e 45 * @{
ebrus 0:6bc4ac881c8e 46 */
ebrus 0:6bc4ac881c8e 47
ebrus 0:6bc4ac881c8e 48 /** @addtogroup stm32f407xx
ebrus 0:6bc4ac881c8e 49 * @{
ebrus 0:6bc4ac881c8e 50 */
ebrus 0:6bc4ac881c8e 51
ebrus 0:6bc4ac881c8e 52 #ifndef __STM32F407xx_H
ebrus 0:6bc4ac881c8e 53 #define __STM32F407xx_H
ebrus 0:6bc4ac881c8e 54
ebrus 0:6bc4ac881c8e 55 #ifdef __cplusplus
ebrus 0:6bc4ac881c8e 56 extern "C" {
ebrus 0:6bc4ac881c8e 57 #endif /* __cplusplus */
ebrus 0:6bc4ac881c8e 58
ebrus 0:6bc4ac881c8e 59
ebrus 0:6bc4ac881c8e 60 /** @addtogroup Configuration_section_for_CMSIS
ebrus 0:6bc4ac881c8e 61 * @{
ebrus 0:6bc4ac881c8e 62 */
ebrus 0:6bc4ac881c8e 63
ebrus 0:6bc4ac881c8e 64 /**
ebrus 0:6bc4ac881c8e 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
ebrus 0:6bc4ac881c8e 66 */
ebrus 0:6bc4ac881c8e 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
ebrus 0:6bc4ac881c8e 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
ebrus 0:6bc4ac881c8e 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
ebrus 0:6bc4ac881c8e 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:6bc4ac881c8e 71 #define __FPU_PRESENT 1 /*!< FPU present */
ebrus 0:6bc4ac881c8e 72
ebrus 0:6bc4ac881c8e 73 /**
ebrus 0:6bc4ac881c8e 74 * @}
ebrus 0:6bc4ac881c8e 75 */
ebrus 0:6bc4ac881c8e 76
ebrus 0:6bc4ac881c8e 77 /** @addtogroup Peripheral_interrupt_number_definition
ebrus 0:6bc4ac881c8e 78 * @{
ebrus 0:6bc4ac881c8e 79 */
ebrus 0:6bc4ac881c8e 80
ebrus 0:6bc4ac881c8e 81 /**
ebrus 0:6bc4ac881c8e 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
ebrus 0:6bc4ac881c8e 83 * in @ref Library_configuration_section
ebrus 0:6bc4ac881c8e 84 */
ebrus 0:6bc4ac881c8e 85 typedef enum
ebrus 0:6bc4ac881c8e 86 {
ebrus 0:6bc4ac881c8e 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
ebrus 0:6bc4ac881c8e 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
ebrus 0:6bc4ac881c8e 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
ebrus 0:6bc4ac881c8e 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
ebrus 0:6bc4ac881c8e 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
ebrus 0:6bc4ac881c8e 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
ebrus 0:6bc4ac881c8e 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
ebrus 0:6bc4ac881c8e 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
ebrus 0:6bc4ac881c8e 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
ebrus 0:6bc4ac881c8e 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
ebrus 0:6bc4ac881c8e 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
ebrus 0:6bc4ac881c8e 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
ebrus 0:6bc4ac881c8e 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
ebrus 0:6bc4ac881c8e 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
ebrus 0:6bc4ac881c8e 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
ebrus 0:6bc4ac881c8e 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
ebrus 0:6bc4ac881c8e 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
ebrus 0:6bc4ac881c8e 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
ebrus 0:6bc4ac881c8e 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
ebrus 0:6bc4ac881c8e 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
ebrus 0:6bc4ac881c8e 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
ebrus 0:6bc4ac881c8e 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
ebrus 0:6bc4ac881c8e 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
ebrus 0:6bc4ac881c8e 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
ebrus 0:6bc4ac881c8e 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
ebrus 0:6bc4ac881c8e 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
ebrus 0:6bc4ac881c8e 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
ebrus 0:6bc4ac881c8e 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ebrus 0:6bc4ac881c8e 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
ebrus 0:6bc4ac881c8e 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
ebrus 0:6bc4ac881c8e 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
ebrus 0:6bc4ac881c8e 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
ebrus 0:6bc4ac881c8e 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
ebrus 0:6bc4ac881c8e 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
ebrus 0:6bc4ac881c8e 121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
ebrus 0:6bc4ac881c8e 122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
ebrus 0:6bc4ac881c8e 123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
ebrus 0:6bc4ac881c8e 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
ebrus 0:6bc4ac881c8e 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
ebrus 0:6bc4ac881c8e 126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
ebrus 0:6bc4ac881c8e 127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
ebrus 0:6bc4ac881c8e 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
ebrus 0:6bc4ac881c8e 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
ebrus 0:6bc4ac881c8e 130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
ebrus 0:6bc4ac881c8e 131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
ebrus 0:6bc4ac881c8e 132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
ebrus 0:6bc4ac881c8e 133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
ebrus 0:6bc4ac881c8e 134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
ebrus 0:6bc4ac881c8e 135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
ebrus 0:6bc4ac881c8e 136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
ebrus 0:6bc4ac881c8e 137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
ebrus 0:6bc4ac881c8e 138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
ebrus 0:6bc4ac881c8e 139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
ebrus 0:6bc4ac881c8e 140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
ebrus 0:6bc4ac881c8e 141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
ebrus 0:6bc4ac881c8e 142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
ebrus 0:6bc4ac881c8e 143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ebrus 0:6bc4ac881c8e 144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
ebrus 0:6bc4ac881c8e 145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
ebrus 0:6bc4ac881c8e 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
ebrus 0:6bc4ac881c8e 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
ebrus 0:6bc4ac881c8e 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
ebrus 0:6bc4ac881c8e 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
ebrus 0:6bc4ac881c8e 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
ebrus 0:6bc4ac881c8e 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
ebrus 0:6bc4ac881c8e 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
ebrus 0:6bc4ac881c8e 153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
ebrus 0:6bc4ac881c8e 154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
ebrus 0:6bc4ac881c8e 155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
ebrus 0:6bc4ac881c8e 156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
ebrus 0:6bc4ac881c8e 157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ebrus 0:6bc4ac881c8e 158 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ebrus 0:6bc4ac881c8e 159 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
ebrus 0:6bc4ac881c8e 160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
ebrus 0:6bc4ac881c8e 161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
ebrus 0:6bc4ac881c8e 162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
ebrus 0:6bc4ac881c8e 163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
ebrus 0:6bc4ac881c8e 164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
ebrus 0:6bc4ac881c8e 165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
ebrus 0:6bc4ac881c8e 166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
ebrus 0:6bc4ac881c8e 167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
ebrus 0:6bc4ac881c8e 168 USART6_IRQn = 71, /*!< USART6 global interrupt */
ebrus 0:6bc4ac881c8e 169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
ebrus 0:6bc4ac881c8e 170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
ebrus 0:6bc4ac881c8e 171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
ebrus 0:6bc4ac881c8e 172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
ebrus 0:6bc4ac881c8e 173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
ebrus 0:6bc4ac881c8e 174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
ebrus 0:6bc4ac881c8e 175 DCMI_IRQn = 78, /*!< DCMI global interrupt */
ebrus 0:6bc4ac881c8e 176 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
ebrus 0:6bc4ac881c8e 177 FPU_IRQn = 81 /*!< FPU global interrupt */
ebrus 0:6bc4ac881c8e 178 } IRQn_Type;
ebrus 0:6bc4ac881c8e 179
ebrus 0:6bc4ac881c8e 180 /**
ebrus 0:6bc4ac881c8e 181 * @}
ebrus 0:6bc4ac881c8e 182 */
ebrus 0:6bc4ac881c8e 183
ebrus 0:6bc4ac881c8e 184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
ebrus 0:6bc4ac881c8e 185 #include "system_stm32f4xx.h"
ebrus 0:6bc4ac881c8e 186 #include <stdint.h>
ebrus 0:6bc4ac881c8e 187
ebrus 0:6bc4ac881c8e 188 /** @addtogroup Peripheral_registers_structures
ebrus 0:6bc4ac881c8e 189 * @{
ebrus 0:6bc4ac881c8e 190 */
ebrus 0:6bc4ac881c8e 191
ebrus 0:6bc4ac881c8e 192 /**
ebrus 0:6bc4ac881c8e 193 * @brief Analog to Digital Converter
ebrus 0:6bc4ac881c8e 194 */
ebrus 0:6bc4ac881c8e 195
ebrus 0:6bc4ac881c8e 196 typedef struct
ebrus 0:6bc4ac881c8e 197 {
ebrus 0:6bc4ac881c8e 198 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 199 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 200 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 201 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 202 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 203 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 204 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 205 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 206 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 207 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 208 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
ebrus 0:6bc4ac881c8e 209 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
ebrus 0:6bc4ac881c8e 210 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
ebrus 0:6bc4ac881c8e 211 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
ebrus 0:6bc4ac881c8e 212 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
ebrus 0:6bc4ac881c8e 213 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
ebrus 0:6bc4ac881c8e 214 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
ebrus 0:6bc4ac881c8e 215 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
ebrus 0:6bc4ac881c8e 216 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
ebrus 0:6bc4ac881c8e 217 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
ebrus 0:6bc4ac881c8e 218 } ADC_TypeDef;
ebrus 0:6bc4ac881c8e 219
ebrus 0:6bc4ac881c8e 220 typedef struct
ebrus 0:6bc4ac881c8e 221 {
ebrus 0:6bc4ac881c8e 222 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
ebrus 0:6bc4ac881c8e 223 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
ebrus 0:6bc4ac881c8e 224 __IO uint32_t CDR; /*!< ADC common regular data register for dual
ebrus 0:6bc4ac881c8e 225 AND triple modes, Address offset: ADC1 base address + 0x308 */
ebrus 0:6bc4ac881c8e 226 } ADC_Common_TypeDef;
ebrus 0:6bc4ac881c8e 227
ebrus 0:6bc4ac881c8e 228
ebrus 0:6bc4ac881c8e 229 /**
ebrus 0:6bc4ac881c8e 230 * @brief Controller Area Network TxMailBox
ebrus 0:6bc4ac881c8e 231 */
ebrus 0:6bc4ac881c8e 232
ebrus 0:6bc4ac881c8e 233 typedef struct
ebrus 0:6bc4ac881c8e 234 {
ebrus 0:6bc4ac881c8e 235 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
ebrus 0:6bc4ac881c8e 236 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
ebrus 0:6bc4ac881c8e 237 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
ebrus 0:6bc4ac881c8e 238 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
ebrus 0:6bc4ac881c8e 239 } CAN_TxMailBox_TypeDef;
ebrus 0:6bc4ac881c8e 240
ebrus 0:6bc4ac881c8e 241 /**
ebrus 0:6bc4ac881c8e 242 * @brief Controller Area Network FIFOMailBox
ebrus 0:6bc4ac881c8e 243 */
ebrus 0:6bc4ac881c8e 244
ebrus 0:6bc4ac881c8e 245 typedef struct
ebrus 0:6bc4ac881c8e 246 {
ebrus 0:6bc4ac881c8e 247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
ebrus 0:6bc4ac881c8e 248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
ebrus 0:6bc4ac881c8e 249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
ebrus 0:6bc4ac881c8e 250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
ebrus 0:6bc4ac881c8e 251 } CAN_FIFOMailBox_TypeDef;
ebrus 0:6bc4ac881c8e 252
ebrus 0:6bc4ac881c8e 253 /**
ebrus 0:6bc4ac881c8e 254 * @brief Controller Area Network FilterRegister
ebrus 0:6bc4ac881c8e 255 */
ebrus 0:6bc4ac881c8e 256
ebrus 0:6bc4ac881c8e 257 typedef struct
ebrus 0:6bc4ac881c8e 258 {
ebrus 0:6bc4ac881c8e 259 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
ebrus 0:6bc4ac881c8e 260 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
ebrus 0:6bc4ac881c8e 261 } CAN_FilterRegister_TypeDef;
ebrus 0:6bc4ac881c8e 262
ebrus 0:6bc4ac881c8e 263 /**
ebrus 0:6bc4ac881c8e 264 * @brief Controller Area Network
ebrus 0:6bc4ac881c8e 265 */
ebrus 0:6bc4ac881c8e 266
ebrus 0:6bc4ac881c8e 267 typedef struct
ebrus 0:6bc4ac881c8e 268 {
ebrus 0:6bc4ac881c8e 269 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 270 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 271 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 272 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 273 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 274 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 275 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 276 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 277 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
ebrus 0:6bc4ac881c8e 278 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
ebrus 0:6bc4ac881c8e 279 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
ebrus 0:6bc4ac881c8e 280 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
ebrus 0:6bc4ac881c8e 281 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
ebrus 0:6bc4ac881c8e 282 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
ebrus 0:6bc4ac881c8e 283 uint32_t RESERVED2; /*!< Reserved, 0x208 */
ebrus 0:6bc4ac881c8e 284 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
ebrus 0:6bc4ac881c8e 285 uint32_t RESERVED3; /*!< Reserved, 0x210 */
ebrus 0:6bc4ac881c8e 286 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
ebrus 0:6bc4ac881c8e 287 uint32_t RESERVED4; /*!< Reserved, 0x218 */
ebrus 0:6bc4ac881c8e 288 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
ebrus 0:6bc4ac881c8e 289 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
ebrus 0:6bc4ac881c8e 290 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
ebrus 0:6bc4ac881c8e 291 } CAN_TypeDef;
ebrus 0:6bc4ac881c8e 292
ebrus 0:6bc4ac881c8e 293 /**
ebrus 0:6bc4ac881c8e 294 * @brief CRC calculation unit
ebrus 0:6bc4ac881c8e 295 */
ebrus 0:6bc4ac881c8e 296
ebrus 0:6bc4ac881c8e 297 typedef struct
ebrus 0:6bc4ac881c8e 298 {
ebrus 0:6bc4ac881c8e 299 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 300 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 301 uint8_t RESERVED0; /*!< Reserved, 0x05 */
ebrus 0:6bc4ac881c8e 302 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ebrus 0:6bc4ac881c8e 303 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 304 } CRC_TypeDef;
ebrus 0:6bc4ac881c8e 305
ebrus 0:6bc4ac881c8e 306 /**
ebrus 0:6bc4ac881c8e 307 * @brief Digital to Analog Converter
ebrus 0:6bc4ac881c8e 308 */
ebrus 0:6bc4ac881c8e 309
ebrus 0:6bc4ac881c8e 310 typedef struct
ebrus 0:6bc4ac881c8e 311 {
ebrus 0:6bc4ac881c8e 312 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 313 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 314 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 315 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 316 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 317 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 318 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 319 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 320 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 321 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 322 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
ebrus 0:6bc4ac881c8e 323 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
ebrus 0:6bc4ac881c8e 324 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
ebrus 0:6bc4ac881c8e 325 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
ebrus 0:6bc4ac881c8e 326 } DAC_TypeDef;
ebrus 0:6bc4ac881c8e 327
ebrus 0:6bc4ac881c8e 328 /**
ebrus 0:6bc4ac881c8e 329 * @brief Debug MCU
ebrus 0:6bc4ac881c8e 330 */
ebrus 0:6bc4ac881c8e 331
ebrus 0:6bc4ac881c8e 332 typedef struct
ebrus 0:6bc4ac881c8e 333 {
ebrus 0:6bc4ac881c8e 334 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 335 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 336 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 337 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 338 }DBGMCU_TypeDef;
ebrus 0:6bc4ac881c8e 339
ebrus 0:6bc4ac881c8e 340 /**
ebrus 0:6bc4ac881c8e 341 * @brief DCMI
ebrus 0:6bc4ac881c8e 342 */
ebrus 0:6bc4ac881c8e 343
ebrus 0:6bc4ac881c8e 344 typedef struct
ebrus 0:6bc4ac881c8e 345 {
ebrus 0:6bc4ac881c8e 346 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 347 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 348 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 349 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 350 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 351 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 352 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 353 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 354 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 355 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 356 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
ebrus 0:6bc4ac881c8e 357 } DCMI_TypeDef;
ebrus 0:6bc4ac881c8e 358
ebrus 0:6bc4ac881c8e 359 /**
ebrus 0:6bc4ac881c8e 360 * @brief DMA Controller
ebrus 0:6bc4ac881c8e 361 */
ebrus 0:6bc4ac881c8e 362
ebrus 0:6bc4ac881c8e 363 typedef struct
ebrus 0:6bc4ac881c8e 364 {
ebrus 0:6bc4ac881c8e 365 __IO uint32_t CR; /*!< DMA stream x configuration register */
ebrus 0:6bc4ac881c8e 366 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
ebrus 0:6bc4ac881c8e 367 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
ebrus 0:6bc4ac881c8e 368 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
ebrus 0:6bc4ac881c8e 369 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
ebrus 0:6bc4ac881c8e 370 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
ebrus 0:6bc4ac881c8e 371 } DMA_Stream_TypeDef;
ebrus 0:6bc4ac881c8e 372
ebrus 0:6bc4ac881c8e 373 typedef struct
ebrus 0:6bc4ac881c8e 374 {
ebrus 0:6bc4ac881c8e 375 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 376 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 377 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 378 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 379 } DMA_TypeDef;
ebrus 0:6bc4ac881c8e 380
ebrus 0:6bc4ac881c8e 381
ebrus 0:6bc4ac881c8e 382 /**
ebrus 0:6bc4ac881c8e 383 * @brief Ethernet MAC
ebrus 0:6bc4ac881c8e 384 */
ebrus 0:6bc4ac881c8e 385
ebrus 0:6bc4ac881c8e 386 typedef struct
ebrus 0:6bc4ac881c8e 387 {
ebrus 0:6bc4ac881c8e 388 __IO uint32_t MACCR;
ebrus 0:6bc4ac881c8e 389 __IO uint32_t MACFFR;
ebrus 0:6bc4ac881c8e 390 __IO uint32_t MACHTHR;
ebrus 0:6bc4ac881c8e 391 __IO uint32_t MACHTLR;
ebrus 0:6bc4ac881c8e 392 __IO uint32_t MACMIIAR;
ebrus 0:6bc4ac881c8e 393 __IO uint32_t MACMIIDR;
ebrus 0:6bc4ac881c8e 394 __IO uint32_t MACFCR;
ebrus 0:6bc4ac881c8e 395 __IO uint32_t MACVLANTR; /* 8 */
ebrus 0:6bc4ac881c8e 396 uint32_t RESERVED0[2];
ebrus 0:6bc4ac881c8e 397 __IO uint32_t MACRWUFFR; /* 11 */
ebrus 0:6bc4ac881c8e 398 __IO uint32_t MACPMTCSR;
ebrus 0:6bc4ac881c8e 399 uint32_t RESERVED1[2];
ebrus 0:6bc4ac881c8e 400 __IO uint32_t MACSR; /* 15 */
ebrus 0:6bc4ac881c8e 401 __IO uint32_t MACIMR;
ebrus 0:6bc4ac881c8e 402 __IO uint32_t MACA0HR;
ebrus 0:6bc4ac881c8e 403 __IO uint32_t MACA0LR;
ebrus 0:6bc4ac881c8e 404 __IO uint32_t MACA1HR;
ebrus 0:6bc4ac881c8e 405 __IO uint32_t MACA1LR;
ebrus 0:6bc4ac881c8e 406 __IO uint32_t MACA2HR;
ebrus 0:6bc4ac881c8e 407 __IO uint32_t MACA2LR;
ebrus 0:6bc4ac881c8e 408 __IO uint32_t MACA3HR;
ebrus 0:6bc4ac881c8e 409 __IO uint32_t MACA3LR; /* 24 */
ebrus 0:6bc4ac881c8e 410 uint32_t RESERVED2[40];
ebrus 0:6bc4ac881c8e 411 __IO uint32_t MMCCR; /* 65 */
ebrus 0:6bc4ac881c8e 412 __IO uint32_t MMCRIR;
ebrus 0:6bc4ac881c8e 413 __IO uint32_t MMCTIR;
ebrus 0:6bc4ac881c8e 414 __IO uint32_t MMCRIMR;
ebrus 0:6bc4ac881c8e 415 __IO uint32_t MMCTIMR; /* 69 */
ebrus 0:6bc4ac881c8e 416 uint32_t RESERVED3[14];
ebrus 0:6bc4ac881c8e 417 __IO uint32_t MMCTGFSCCR; /* 84 */
ebrus 0:6bc4ac881c8e 418 __IO uint32_t MMCTGFMSCCR;
ebrus 0:6bc4ac881c8e 419 uint32_t RESERVED4[5];
ebrus 0:6bc4ac881c8e 420 __IO uint32_t MMCTGFCR;
ebrus 0:6bc4ac881c8e 421 uint32_t RESERVED5[10];
ebrus 0:6bc4ac881c8e 422 __IO uint32_t MMCRFCECR;
ebrus 0:6bc4ac881c8e 423 __IO uint32_t MMCRFAECR;
ebrus 0:6bc4ac881c8e 424 uint32_t RESERVED6[10];
ebrus 0:6bc4ac881c8e 425 __IO uint32_t MMCRGUFCR;
ebrus 0:6bc4ac881c8e 426 uint32_t RESERVED7[334];
ebrus 0:6bc4ac881c8e 427 __IO uint32_t PTPTSCR;
ebrus 0:6bc4ac881c8e 428 __IO uint32_t PTPSSIR;
ebrus 0:6bc4ac881c8e 429 __IO uint32_t PTPTSHR;
ebrus 0:6bc4ac881c8e 430 __IO uint32_t PTPTSLR;
ebrus 0:6bc4ac881c8e 431 __IO uint32_t PTPTSHUR;
ebrus 0:6bc4ac881c8e 432 __IO uint32_t PTPTSLUR;
ebrus 0:6bc4ac881c8e 433 __IO uint32_t PTPTSAR;
ebrus 0:6bc4ac881c8e 434 __IO uint32_t PTPTTHR;
ebrus 0:6bc4ac881c8e 435 __IO uint32_t PTPTTLR;
ebrus 0:6bc4ac881c8e 436 __IO uint32_t RESERVED8;
ebrus 0:6bc4ac881c8e 437 __IO uint32_t PTPTSSR;
ebrus 0:6bc4ac881c8e 438 uint32_t RESERVED9[565];
ebrus 0:6bc4ac881c8e 439 __IO uint32_t DMABMR;
ebrus 0:6bc4ac881c8e 440 __IO uint32_t DMATPDR;
ebrus 0:6bc4ac881c8e 441 __IO uint32_t DMARPDR;
ebrus 0:6bc4ac881c8e 442 __IO uint32_t DMARDLAR;
ebrus 0:6bc4ac881c8e 443 __IO uint32_t DMATDLAR;
ebrus 0:6bc4ac881c8e 444 __IO uint32_t DMASR;
ebrus 0:6bc4ac881c8e 445 __IO uint32_t DMAOMR;
ebrus 0:6bc4ac881c8e 446 __IO uint32_t DMAIER;
ebrus 0:6bc4ac881c8e 447 __IO uint32_t DMAMFBOCR;
ebrus 0:6bc4ac881c8e 448 __IO uint32_t DMARSWTR;
ebrus 0:6bc4ac881c8e 449 uint32_t RESERVED10[8];
ebrus 0:6bc4ac881c8e 450 __IO uint32_t DMACHTDR;
ebrus 0:6bc4ac881c8e 451 __IO uint32_t DMACHRDR;
ebrus 0:6bc4ac881c8e 452 __IO uint32_t DMACHTBAR;
ebrus 0:6bc4ac881c8e 453 __IO uint32_t DMACHRBAR;
ebrus 0:6bc4ac881c8e 454 } ETH_TypeDef;
ebrus 0:6bc4ac881c8e 455
ebrus 0:6bc4ac881c8e 456 /**
ebrus 0:6bc4ac881c8e 457 * @brief External Interrupt/Event Controller
ebrus 0:6bc4ac881c8e 458 */
ebrus 0:6bc4ac881c8e 459
ebrus 0:6bc4ac881c8e 460 typedef struct
ebrus 0:6bc4ac881c8e 461 {
ebrus 0:6bc4ac881c8e 462 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 463 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 464 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 465 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 466 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 467 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 468 } EXTI_TypeDef;
ebrus 0:6bc4ac881c8e 469
ebrus 0:6bc4ac881c8e 470 /**
ebrus 0:6bc4ac881c8e 471 * @brief FLASH Registers
ebrus 0:6bc4ac881c8e 472 */
ebrus 0:6bc4ac881c8e 473
ebrus 0:6bc4ac881c8e 474 typedef struct
ebrus 0:6bc4ac881c8e 475 {
ebrus 0:6bc4ac881c8e 476 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 477 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 478 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 479 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 480 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 481 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 482 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 483 } FLASH_TypeDef;
ebrus 0:6bc4ac881c8e 484
ebrus 0:6bc4ac881c8e 485
ebrus 0:6bc4ac881c8e 486 /**
ebrus 0:6bc4ac881c8e 487 * @brief Flexible Static Memory Controller
ebrus 0:6bc4ac881c8e 488 */
ebrus 0:6bc4ac881c8e 489
ebrus 0:6bc4ac881c8e 490 typedef struct
ebrus 0:6bc4ac881c8e 491 {
ebrus 0:6bc4ac881c8e 492 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
ebrus 0:6bc4ac881c8e 493 } FSMC_Bank1_TypeDef;
ebrus 0:6bc4ac881c8e 494
ebrus 0:6bc4ac881c8e 495 /**
ebrus 0:6bc4ac881c8e 496 * @brief Flexible Static Memory Controller Bank1E
ebrus 0:6bc4ac881c8e 497 */
ebrus 0:6bc4ac881c8e 498
ebrus 0:6bc4ac881c8e 499 typedef struct
ebrus 0:6bc4ac881c8e 500 {
ebrus 0:6bc4ac881c8e 501 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
ebrus 0:6bc4ac881c8e 502 } FSMC_Bank1E_TypeDef;
ebrus 0:6bc4ac881c8e 503
ebrus 0:6bc4ac881c8e 504 /**
ebrus 0:6bc4ac881c8e 505 * @brief Flexible Static Memory Controller Bank2
ebrus 0:6bc4ac881c8e 506 */
ebrus 0:6bc4ac881c8e 507
ebrus 0:6bc4ac881c8e 508 typedef struct
ebrus 0:6bc4ac881c8e 509 {
ebrus 0:6bc4ac881c8e 510 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
ebrus 0:6bc4ac881c8e 511 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
ebrus 0:6bc4ac881c8e 512 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
ebrus 0:6bc4ac881c8e 513 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
ebrus 0:6bc4ac881c8e 514 uint32_t RESERVED0; /*!< Reserved, 0x70 */
ebrus 0:6bc4ac881c8e 515 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
ebrus 0:6bc4ac881c8e 516 uint32_t RESERVED1; /*!< Reserved, 0x78 */
ebrus 0:6bc4ac881c8e 517 uint32_t RESERVED2; /*!< Reserved, 0x7C */
ebrus 0:6bc4ac881c8e 518 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
ebrus 0:6bc4ac881c8e 519 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
ebrus 0:6bc4ac881c8e 520 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
ebrus 0:6bc4ac881c8e 521 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
ebrus 0:6bc4ac881c8e 522 uint32_t RESERVED3; /*!< Reserved, 0x90 */
ebrus 0:6bc4ac881c8e 523 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
ebrus 0:6bc4ac881c8e 524 } FSMC_Bank2_3_TypeDef;
ebrus 0:6bc4ac881c8e 525
ebrus 0:6bc4ac881c8e 526 /**
ebrus 0:6bc4ac881c8e 527 * @brief Flexible Static Memory Controller Bank4
ebrus 0:6bc4ac881c8e 528 */
ebrus 0:6bc4ac881c8e 529
ebrus 0:6bc4ac881c8e 530 typedef struct
ebrus 0:6bc4ac881c8e 531 {
ebrus 0:6bc4ac881c8e 532 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
ebrus 0:6bc4ac881c8e 533 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
ebrus 0:6bc4ac881c8e 534 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
ebrus 0:6bc4ac881c8e 535 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
ebrus 0:6bc4ac881c8e 536 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
ebrus 0:6bc4ac881c8e 537 } FSMC_Bank4_TypeDef;
ebrus 0:6bc4ac881c8e 538
ebrus 0:6bc4ac881c8e 539
ebrus 0:6bc4ac881c8e 540 /**
ebrus 0:6bc4ac881c8e 541 * @brief General Purpose I/O
ebrus 0:6bc4ac881c8e 542 */
ebrus 0:6bc4ac881c8e 543
ebrus 0:6bc4ac881c8e 544 typedef struct
ebrus 0:6bc4ac881c8e 545 {
ebrus 0:6bc4ac881c8e 546 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 547 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 548 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 549 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 550 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 551 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 552 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 553 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
ebrus 0:6bc4ac881c8e 554 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 555 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
ebrus 0:6bc4ac881c8e 556 } GPIO_TypeDef;
ebrus 0:6bc4ac881c8e 557
ebrus 0:6bc4ac881c8e 558 /**
ebrus 0:6bc4ac881c8e 559 * @brief System configuration controller
ebrus 0:6bc4ac881c8e 560 */
ebrus 0:6bc4ac881c8e 561
ebrus 0:6bc4ac881c8e 562 typedef struct
ebrus 0:6bc4ac881c8e 563 {
ebrus 0:6bc4ac881c8e 564 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 565 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 566 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
ebrus 0:6bc4ac881c8e 567 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
ebrus 0:6bc4ac881c8e 568 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 569 } SYSCFG_TypeDef;
ebrus 0:6bc4ac881c8e 570
ebrus 0:6bc4ac881c8e 571 /**
ebrus 0:6bc4ac881c8e 572 * @brief Inter-integrated Circuit Interface
ebrus 0:6bc4ac881c8e 573 */
ebrus 0:6bc4ac881c8e 574
ebrus 0:6bc4ac881c8e 575 typedef struct
ebrus 0:6bc4ac881c8e 576 {
ebrus 0:6bc4ac881c8e 577 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 578 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 579 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 580 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 581 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 582 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 583 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 584 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 585 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 586 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 587 } I2C_TypeDef;
ebrus 0:6bc4ac881c8e 588
ebrus 0:6bc4ac881c8e 589 /**
ebrus 0:6bc4ac881c8e 590 * @brief Independent WATCHDOG
ebrus 0:6bc4ac881c8e 591 */
ebrus 0:6bc4ac881c8e 592
ebrus 0:6bc4ac881c8e 593 typedef struct
ebrus 0:6bc4ac881c8e 594 {
ebrus 0:6bc4ac881c8e 595 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 596 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 597 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 598 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 599 } IWDG_TypeDef;
ebrus 0:6bc4ac881c8e 600
ebrus 0:6bc4ac881c8e 601 /**
ebrus 0:6bc4ac881c8e 602 * @brief Power Control
ebrus 0:6bc4ac881c8e 603 */
ebrus 0:6bc4ac881c8e 604
ebrus 0:6bc4ac881c8e 605 typedef struct
ebrus 0:6bc4ac881c8e 606 {
ebrus 0:6bc4ac881c8e 607 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 608 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 609 } PWR_TypeDef;
ebrus 0:6bc4ac881c8e 610
ebrus 0:6bc4ac881c8e 611 /**
ebrus 0:6bc4ac881c8e 612 * @brief Reset and Clock Control
ebrus 0:6bc4ac881c8e 613 */
ebrus 0:6bc4ac881c8e 614
ebrus 0:6bc4ac881c8e 615 typedef struct
ebrus 0:6bc4ac881c8e 616 {
ebrus 0:6bc4ac881c8e 617 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 618 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 619 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 620 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 621 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 622 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 623 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 624 uint32_t RESERVED0; /*!< Reserved, 0x1C */
ebrus 0:6bc4ac881c8e 625 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 626 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 627 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
ebrus 0:6bc4ac881c8e 628 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
ebrus 0:6bc4ac881c8e 629 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
ebrus 0:6bc4ac881c8e 630 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
ebrus 0:6bc4ac881c8e 631 uint32_t RESERVED2; /*!< Reserved, 0x3C */
ebrus 0:6bc4ac881c8e 632 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
ebrus 0:6bc4ac881c8e 633 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
ebrus 0:6bc4ac881c8e 634 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
ebrus 0:6bc4ac881c8e 635 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
ebrus 0:6bc4ac881c8e 636 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
ebrus 0:6bc4ac881c8e 637 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
ebrus 0:6bc4ac881c8e 638 uint32_t RESERVED4; /*!< Reserved, 0x5C */
ebrus 0:6bc4ac881c8e 639 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
ebrus 0:6bc4ac881c8e 640 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
ebrus 0:6bc4ac881c8e 641 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
ebrus 0:6bc4ac881c8e 642 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
ebrus 0:6bc4ac881c8e 643 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
ebrus 0:6bc4ac881c8e 644 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
ebrus 0:6bc4ac881c8e 645 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
ebrus 0:6bc4ac881c8e 646 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
ebrus 0:6bc4ac881c8e 647
ebrus 0:6bc4ac881c8e 648 } RCC_TypeDef;
ebrus 0:6bc4ac881c8e 649
ebrus 0:6bc4ac881c8e 650 /**
ebrus 0:6bc4ac881c8e 651 * @brief Real-Time Clock
ebrus 0:6bc4ac881c8e 652 */
ebrus 0:6bc4ac881c8e 653
ebrus 0:6bc4ac881c8e 654 typedef struct
ebrus 0:6bc4ac881c8e 655 {
ebrus 0:6bc4ac881c8e 656 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 657 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 658 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 659 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 660 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 661 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 662 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 663 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 664 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 665 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 666 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
ebrus 0:6bc4ac881c8e 667 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
ebrus 0:6bc4ac881c8e 668 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
ebrus 0:6bc4ac881c8e 669 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
ebrus 0:6bc4ac881c8e 670 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
ebrus 0:6bc4ac881c8e 671 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
ebrus 0:6bc4ac881c8e 672 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
ebrus 0:6bc4ac881c8e 673 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
ebrus 0:6bc4ac881c8e 674 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
ebrus 0:6bc4ac881c8e 675 uint32_t RESERVED7; /*!< Reserved, 0x4C */
ebrus 0:6bc4ac881c8e 676 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
ebrus 0:6bc4ac881c8e 677 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
ebrus 0:6bc4ac881c8e 678 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
ebrus 0:6bc4ac881c8e 679 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
ebrus 0:6bc4ac881c8e 680 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
ebrus 0:6bc4ac881c8e 681 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
ebrus 0:6bc4ac881c8e 682 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
ebrus 0:6bc4ac881c8e 683 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
ebrus 0:6bc4ac881c8e 684 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
ebrus 0:6bc4ac881c8e 685 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
ebrus 0:6bc4ac881c8e 686 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
ebrus 0:6bc4ac881c8e 687 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
ebrus 0:6bc4ac881c8e 688 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
ebrus 0:6bc4ac881c8e 689 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
ebrus 0:6bc4ac881c8e 690 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
ebrus 0:6bc4ac881c8e 691 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
ebrus 0:6bc4ac881c8e 692 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
ebrus 0:6bc4ac881c8e 693 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
ebrus 0:6bc4ac881c8e 694 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
ebrus 0:6bc4ac881c8e 695 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
ebrus 0:6bc4ac881c8e 696 } RTC_TypeDef;
ebrus 0:6bc4ac881c8e 697
ebrus 0:6bc4ac881c8e 698
ebrus 0:6bc4ac881c8e 699 /**
ebrus 0:6bc4ac881c8e 700 * @brief SD host Interface
ebrus 0:6bc4ac881c8e 701 */
ebrus 0:6bc4ac881c8e 702
ebrus 0:6bc4ac881c8e 703 typedef struct
ebrus 0:6bc4ac881c8e 704 {
ebrus 0:6bc4ac881c8e 705 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 706 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 707 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 708 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 709 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 710 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 711 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 712 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 713 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 714 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 715 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
ebrus 0:6bc4ac881c8e 716 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
ebrus 0:6bc4ac881c8e 717 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
ebrus 0:6bc4ac881c8e 718 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
ebrus 0:6bc4ac881c8e 719 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
ebrus 0:6bc4ac881c8e 720 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
ebrus 0:6bc4ac881c8e 721 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
ebrus 0:6bc4ac881c8e 722 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
ebrus 0:6bc4ac881c8e 723 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
ebrus 0:6bc4ac881c8e 724 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
ebrus 0:6bc4ac881c8e 725 } SDIO_TypeDef;
ebrus 0:6bc4ac881c8e 726
ebrus 0:6bc4ac881c8e 727 /**
ebrus 0:6bc4ac881c8e 728 * @brief Serial Peripheral Interface
ebrus 0:6bc4ac881c8e 729 */
ebrus 0:6bc4ac881c8e 730
ebrus 0:6bc4ac881c8e 731 typedef struct
ebrus 0:6bc4ac881c8e 732 {
ebrus 0:6bc4ac881c8e 733 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 734 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 735 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 736 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 737 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 738 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 739 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 740 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 741 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 742 } SPI_TypeDef;
ebrus 0:6bc4ac881c8e 743
ebrus 0:6bc4ac881c8e 744 /**
ebrus 0:6bc4ac881c8e 745 * @brief TIM
ebrus 0:6bc4ac881c8e 746 */
ebrus 0:6bc4ac881c8e 747
ebrus 0:6bc4ac881c8e 748 typedef struct
ebrus 0:6bc4ac881c8e 749 {
ebrus 0:6bc4ac881c8e 750 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 751 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 752 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 753 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 754 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 755 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 756 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 757 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
ebrus 0:6bc4ac881c8e 758 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
ebrus 0:6bc4ac881c8e 759 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
ebrus 0:6bc4ac881c8e 760 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
ebrus 0:6bc4ac881c8e 761 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
ebrus 0:6bc4ac881c8e 762 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
ebrus 0:6bc4ac881c8e 763 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
ebrus 0:6bc4ac881c8e 764 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
ebrus 0:6bc4ac881c8e 765 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
ebrus 0:6bc4ac881c8e 766 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
ebrus 0:6bc4ac881c8e 767 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
ebrus 0:6bc4ac881c8e 768 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
ebrus 0:6bc4ac881c8e 769 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
ebrus 0:6bc4ac881c8e 770 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
ebrus 0:6bc4ac881c8e 771 } TIM_TypeDef;
ebrus 0:6bc4ac881c8e 772
ebrus 0:6bc4ac881c8e 773 /**
ebrus 0:6bc4ac881c8e 774 * @brief Universal Synchronous Asynchronous Receiver Transmitter
ebrus 0:6bc4ac881c8e 775 */
ebrus 0:6bc4ac881c8e 776
ebrus 0:6bc4ac881c8e 777 typedef struct
ebrus 0:6bc4ac881c8e 778 {
ebrus 0:6bc4ac881c8e 779 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 780 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 781 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 782 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
ebrus 0:6bc4ac881c8e 783 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
ebrus 0:6bc4ac881c8e 784 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
ebrus 0:6bc4ac881c8e 785 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
ebrus 0:6bc4ac881c8e 786 } USART_TypeDef;
ebrus 0:6bc4ac881c8e 787
ebrus 0:6bc4ac881c8e 788 /**
ebrus 0:6bc4ac881c8e 789 * @brief Window WATCHDOG
ebrus 0:6bc4ac881c8e 790 */
ebrus 0:6bc4ac881c8e 791
ebrus 0:6bc4ac881c8e 792 typedef struct
ebrus 0:6bc4ac881c8e 793 {
ebrus 0:6bc4ac881c8e 794 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 795 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 796 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 797 } WWDG_TypeDef;
ebrus 0:6bc4ac881c8e 798
ebrus 0:6bc4ac881c8e 799 /**
ebrus 0:6bc4ac881c8e 800 * @brief RNG
ebrus 0:6bc4ac881c8e 801 */
ebrus 0:6bc4ac881c8e 802
ebrus 0:6bc4ac881c8e 803 typedef struct
ebrus 0:6bc4ac881c8e 804 {
ebrus 0:6bc4ac881c8e 805 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
ebrus 0:6bc4ac881c8e 806 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
ebrus 0:6bc4ac881c8e 807 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
ebrus 0:6bc4ac881c8e 808 } RNG_TypeDef;
ebrus 0:6bc4ac881c8e 809
ebrus 0:6bc4ac881c8e 810
ebrus 0:6bc4ac881c8e 811
ebrus 0:6bc4ac881c8e 812 /**
ebrus 0:6bc4ac881c8e 813 * @brief __USB_OTG_Core_register
ebrus 0:6bc4ac881c8e 814 */
ebrus 0:6bc4ac881c8e 815 typedef struct
ebrus 0:6bc4ac881c8e 816 {
ebrus 0:6bc4ac881c8e 817 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
ebrus 0:6bc4ac881c8e 818 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
ebrus 0:6bc4ac881c8e 819 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
ebrus 0:6bc4ac881c8e 820 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
ebrus 0:6bc4ac881c8e 821 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
ebrus 0:6bc4ac881c8e 822 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
ebrus 0:6bc4ac881c8e 823 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
ebrus 0:6bc4ac881c8e 824 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
ebrus 0:6bc4ac881c8e 825 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
ebrus 0:6bc4ac881c8e 826 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
ebrus 0:6bc4ac881c8e 827 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
ebrus 0:6bc4ac881c8e 828 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
ebrus 0:6bc4ac881c8e 829 uint32_t Reserved30[2]; /* Reserved 030h*/
ebrus 0:6bc4ac881c8e 830 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
ebrus 0:6bc4ac881c8e 831 __IO uint32_t CID; /* User ID Register 03Ch*/
ebrus 0:6bc4ac881c8e 832 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
ebrus 0:6bc4ac881c8e 833 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
ebrus 0:6bc4ac881c8e 834 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
ebrus 0:6bc4ac881c8e 835 }
ebrus 0:6bc4ac881c8e 836 USB_OTG_GlobalTypeDef;
ebrus 0:6bc4ac881c8e 837
ebrus 0:6bc4ac881c8e 838
ebrus 0:6bc4ac881c8e 839
ebrus 0:6bc4ac881c8e 840 /**
ebrus 0:6bc4ac881c8e 841 * @brief __device_Registers
ebrus 0:6bc4ac881c8e 842 */
ebrus 0:6bc4ac881c8e 843 typedef struct
ebrus 0:6bc4ac881c8e 844 {
ebrus 0:6bc4ac881c8e 845 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
ebrus 0:6bc4ac881c8e 846 __IO uint32_t DCTL; /* dev Control Register 804h*/
ebrus 0:6bc4ac881c8e 847 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
ebrus 0:6bc4ac881c8e 848 uint32_t Reserved0C; /* Reserved 80Ch*/
ebrus 0:6bc4ac881c8e 849 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
ebrus 0:6bc4ac881c8e 850 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
ebrus 0:6bc4ac881c8e 851 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
ebrus 0:6bc4ac881c8e 852 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
ebrus 0:6bc4ac881c8e 853 uint32_t Reserved20; /* Reserved 820h*/
ebrus 0:6bc4ac881c8e 854 uint32_t Reserved9; /* Reserved 824h*/
ebrus 0:6bc4ac881c8e 855 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
ebrus 0:6bc4ac881c8e 856 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
ebrus 0:6bc4ac881c8e 857 __IO uint32_t DTHRCTL; /* dev thr 830h*/
ebrus 0:6bc4ac881c8e 858 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
ebrus 0:6bc4ac881c8e 859 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
ebrus 0:6bc4ac881c8e 860 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
ebrus 0:6bc4ac881c8e 861 uint32_t Reserved40; /* dedicated EP mask 840h*/
ebrus 0:6bc4ac881c8e 862 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
ebrus 0:6bc4ac881c8e 863 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
ebrus 0:6bc4ac881c8e 864 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
ebrus 0:6bc4ac881c8e 865 }
ebrus 0:6bc4ac881c8e 866 USB_OTG_DeviceTypeDef;
ebrus 0:6bc4ac881c8e 867
ebrus 0:6bc4ac881c8e 868
ebrus 0:6bc4ac881c8e 869 /**
ebrus 0:6bc4ac881c8e 870 * @brief __IN_Endpoint-Specific_Register
ebrus 0:6bc4ac881c8e 871 */
ebrus 0:6bc4ac881c8e 872 typedef struct
ebrus 0:6bc4ac881c8e 873 {
ebrus 0:6bc4ac881c8e 874 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
ebrus 0:6bc4ac881c8e 875 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
ebrus 0:6bc4ac881c8e 876 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
ebrus 0:6bc4ac881c8e 877 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
ebrus 0:6bc4ac881c8e 878 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
ebrus 0:6bc4ac881c8e 879 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
ebrus 0:6bc4ac881c8e 880 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
ebrus 0:6bc4ac881c8e 881 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
ebrus 0:6bc4ac881c8e 882 }
ebrus 0:6bc4ac881c8e 883 USB_OTG_INEndpointTypeDef;
ebrus 0:6bc4ac881c8e 884
ebrus 0:6bc4ac881c8e 885
ebrus 0:6bc4ac881c8e 886 /**
ebrus 0:6bc4ac881c8e 887 * @brief __OUT_Endpoint-Specific_Registers
ebrus 0:6bc4ac881c8e 888 */
ebrus 0:6bc4ac881c8e 889 typedef struct
ebrus 0:6bc4ac881c8e 890 {
ebrus 0:6bc4ac881c8e 891 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
ebrus 0:6bc4ac881c8e 892 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
ebrus 0:6bc4ac881c8e 893 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
ebrus 0:6bc4ac881c8e 894 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
ebrus 0:6bc4ac881c8e 895 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
ebrus 0:6bc4ac881c8e 896 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
ebrus 0:6bc4ac881c8e 897 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
ebrus 0:6bc4ac881c8e 898 }
ebrus 0:6bc4ac881c8e 899 USB_OTG_OUTEndpointTypeDef;
ebrus 0:6bc4ac881c8e 900
ebrus 0:6bc4ac881c8e 901
ebrus 0:6bc4ac881c8e 902 /**
ebrus 0:6bc4ac881c8e 903 * @brief __Host_Mode_Register_Structures
ebrus 0:6bc4ac881c8e 904 */
ebrus 0:6bc4ac881c8e 905 typedef struct
ebrus 0:6bc4ac881c8e 906 {
ebrus 0:6bc4ac881c8e 907 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
ebrus 0:6bc4ac881c8e 908 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
ebrus 0:6bc4ac881c8e 909 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
ebrus 0:6bc4ac881c8e 910 uint32_t Reserved40C; /* Reserved 40Ch*/
ebrus 0:6bc4ac881c8e 911 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
ebrus 0:6bc4ac881c8e 912 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
ebrus 0:6bc4ac881c8e 913 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
ebrus 0:6bc4ac881c8e 914 }
ebrus 0:6bc4ac881c8e 915 USB_OTG_HostTypeDef;
ebrus 0:6bc4ac881c8e 916
ebrus 0:6bc4ac881c8e 917
ebrus 0:6bc4ac881c8e 918 /**
ebrus 0:6bc4ac881c8e 919 * @brief __Host_Channel_Specific_Registers
ebrus 0:6bc4ac881c8e 920 */
ebrus 0:6bc4ac881c8e 921 typedef struct
ebrus 0:6bc4ac881c8e 922 {
ebrus 0:6bc4ac881c8e 923 __IO uint32_t HCCHAR;
ebrus 0:6bc4ac881c8e 924 __IO uint32_t HCSPLT;
ebrus 0:6bc4ac881c8e 925 __IO uint32_t HCINT;
ebrus 0:6bc4ac881c8e 926 __IO uint32_t HCINTMSK;
ebrus 0:6bc4ac881c8e 927 __IO uint32_t HCTSIZ;
ebrus 0:6bc4ac881c8e 928 __IO uint32_t HCDMA;
ebrus 0:6bc4ac881c8e 929 uint32_t Reserved[2];
ebrus 0:6bc4ac881c8e 930 }
ebrus 0:6bc4ac881c8e 931 USB_OTG_HostChannelTypeDef;
ebrus 0:6bc4ac881c8e 932
ebrus 0:6bc4ac881c8e 933
ebrus 0:6bc4ac881c8e 934 /**
ebrus 0:6bc4ac881c8e 935 * @brief Peripheral_memory_map
ebrus 0:6bc4ac881c8e 936 */
ebrus 0:6bc4ac881c8e 937 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
ebrus 0:6bc4ac881c8e 938 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
ebrus 0:6bc4ac881c8e 939 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
ebrus 0:6bc4ac881c8e 940 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
ebrus 0:6bc4ac881c8e 941 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
ebrus 0:6bc4ac881c8e 942 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
ebrus 0:6bc4ac881c8e 943 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
ebrus 0:6bc4ac881c8e 944 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
ebrus 0:6bc4ac881c8e 945 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
ebrus 0:6bc4ac881c8e 946 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
ebrus 0:6bc4ac881c8e 947 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
ebrus 0:6bc4ac881c8e 948 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
ebrus 0:6bc4ac881c8e 949 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
ebrus 0:6bc4ac881c8e 950 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
ebrus 0:6bc4ac881c8e 951 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
ebrus 0:6bc4ac881c8e 952 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
ebrus 0:6bc4ac881c8e 953
ebrus 0:6bc4ac881c8e 954 /* Legacy defines */
ebrus 0:6bc4ac881c8e 955 #define SRAM_BASE SRAM1_BASE
ebrus 0:6bc4ac881c8e 956 #define SRAM_BB_BASE SRAM1_BB_BASE
ebrus 0:6bc4ac881c8e 957
ebrus 0:6bc4ac881c8e 958
ebrus 0:6bc4ac881c8e 959 /*!< Peripheral memory map */
ebrus 0:6bc4ac881c8e 960 #define APB1PERIPH_BASE PERIPH_BASE
ebrus 0:6bc4ac881c8e 961 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
ebrus 0:6bc4ac881c8e 962 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
ebrus 0:6bc4ac881c8e 963 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
ebrus 0:6bc4ac881c8e 964
ebrus 0:6bc4ac881c8e 965 /*!< APB1 peripherals */
ebrus 0:6bc4ac881c8e 966 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
ebrus 0:6bc4ac881c8e 967 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
ebrus 0:6bc4ac881c8e 968 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
ebrus 0:6bc4ac881c8e 969 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
ebrus 0:6bc4ac881c8e 970 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
ebrus 0:6bc4ac881c8e 971 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
ebrus 0:6bc4ac881c8e 972 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
ebrus 0:6bc4ac881c8e 973 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
ebrus 0:6bc4ac881c8e 974 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
ebrus 0:6bc4ac881c8e 975 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
ebrus 0:6bc4ac881c8e 976 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
ebrus 0:6bc4ac881c8e 977 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
ebrus 0:6bc4ac881c8e 978 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
ebrus 0:6bc4ac881c8e 979 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
ebrus 0:6bc4ac881c8e 980 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
ebrus 0:6bc4ac881c8e 981 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
ebrus 0:6bc4ac881c8e 982 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
ebrus 0:6bc4ac881c8e 983 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
ebrus 0:6bc4ac881c8e 984 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
ebrus 0:6bc4ac881c8e 985 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
ebrus 0:6bc4ac881c8e 986 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
ebrus 0:6bc4ac881c8e 987 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
ebrus 0:6bc4ac881c8e 988 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
ebrus 0:6bc4ac881c8e 989 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
ebrus 0:6bc4ac881c8e 990 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
ebrus 0:6bc4ac881c8e 991 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
ebrus 0:6bc4ac881c8e 992 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
ebrus 0:6bc4ac881c8e 993
ebrus 0:6bc4ac881c8e 994 /*!< APB2 peripherals */
ebrus 0:6bc4ac881c8e 995 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
ebrus 0:6bc4ac881c8e 996 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
ebrus 0:6bc4ac881c8e 997 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
ebrus 0:6bc4ac881c8e 998 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
ebrus 0:6bc4ac881c8e 999 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
ebrus 0:6bc4ac881c8e 1000 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
ebrus 0:6bc4ac881c8e 1001 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
ebrus 0:6bc4ac881c8e 1002 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
ebrus 0:6bc4ac881c8e 1003 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
ebrus 0:6bc4ac881c8e 1004 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
ebrus 0:6bc4ac881c8e 1005 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
ebrus 0:6bc4ac881c8e 1006 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
ebrus 0:6bc4ac881c8e 1007 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
ebrus 0:6bc4ac881c8e 1008 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
ebrus 0:6bc4ac881c8e 1009 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
ebrus 0:6bc4ac881c8e 1010
ebrus 0:6bc4ac881c8e 1011 /*!< AHB1 peripherals */
ebrus 0:6bc4ac881c8e 1012 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
ebrus 0:6bc4ac881c8e 1013 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
ebrus 0:6bc4ac881c8e 1014 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
ebrus 0:6bc4ac881c8e 1015 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
ebrus 0:6bc4ac881c8e 1016 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
ebrus 0:6bc4ac881c8e 1017 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
ebrus 0:6bc4ac881c8e 1018 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
ebrus 0:6bc4ac881c8e 1019 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
ebrus 0:6bc4ac881c8e 1020 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
ebrus 0:6bc4ac881c8e 1021 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
ebrus 0:6bc4ac881c8e 1022 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
ebrus 0:6bc4ac881c8e 1023 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
ebrus 0:6bc4ac881c8e 1024 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
ebrus 0:6bc4ac881c8e 1025 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
ebrus 0:6bc4ac881c8e 1026 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
ebrus 0:6bc4ac881c8e 1027 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
ebrus 0:6bc4ac881c8e 1028 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
ebrus 0:6bc4ac881c8e 1029 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
ebrus 0:6bc4ac881c8e 1030 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
ebrus 0:6bc4ac881c8e 1031 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
ebrus 0:6bc4ac881c8e 1032 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
ebrus 0:6bc4ac881c8e 1033 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
ebrus 0:6bc4ac881c8e 1034 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
ebrus 0:6bc4ac881c8e 1035 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
ebrus 0:6bc4ac881c8e 1036 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
ebrus 0:6bc4ac881c8e 1037 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
ebrus 0:6bc4ac881c8e 1038 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
ebrus 0:6bc4ac881c8e 1039 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
ebrus 0:6bc4ac881c8e 1040 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
ebrus 0:6bc4ac881c8e 1041 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
ebrus 0:6bc4ac881c8e 1042 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
ebrus 0:6bc4ac881c8e 1043 #define ETH_MAC_BASE (ETH_BASE)
ebrus 0:6bc4ac881c8e 1044 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
ebrus 0:6bc4ac881c8e 1045 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
ebrus 0:6bc4ac881c8e 1046 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
ebrus 0:6bc4ac881c8e 1047
ebrus 0:6bc4ac881c8e 1048 /*!< AHB2 peripherals */
ebrus 0:6bc4ac881c8e 1049 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
ebrus 0:6bc4ac881c8e 1050 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
ebrus 0:6bc4ac881c8e 1051
ebrus 0:6bc4ac881c8e 1052 /*!< FSMC Bankx registers base address */
ebrus 0:6bc4ac881c8e 1053 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
ebrus 0:6bc4ac881c8e 1054 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
ebrus 0:6bc4ac881c8e 1055 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
ebrus 0:6bc4ac881c8e 1056 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
ebrus 0:6bc4ac881c8e 1057
ebrus 0:6bc4ac881c8e 1058 /* Debug MCU registers base address */
ebrus 0:6bc4ac881c8e 1059 #define DBGMCU_BASE ((uint32_t )0xE0042000)
ebrus 0:6bc4ac881c8e 1060
ebrus 0:6bc4ac881c8e 1061 /*!< USB registers base address */
ebrus 0:6bc4ac881c8e 1062 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
ebrus 0:6bc4ac881c8e 1063 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
ebrus 0:6bc4ac881c8e 1064
ebrus 0:6bc4ac881c8e 1065 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
ebrus 0:6bc4ac881c8e 1066 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
ebrus 0:6bc4ac881c8e 1067 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
ebrus 0:6bc4ac881c8e 1068 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
ebrus 0:6bc4ac881c8e 1069 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
ebrus 0:6bc4ac881c8e 1070 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
ebrus 0:6bc4ac881c8e 1071 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
ebrus 0:6bc4ac881c8e 1072 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
ebrus 0:6bc4ac881c8e 1073 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
ebrus 0:6bc4ac881c8e 1074 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
ebrus 0:6bc4ac881c8e 1075 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
ebrus 0:6bc4ac881c8e 1076 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
ebrus 0:6bc4ac881c8e 1077
ebrus 0:6bc4ac881c8e 1078 /**
ebrus 0:6bc4ac881c8e 1079 * @}
ebrus 0:6bc4ac881c8e 1080 */
ebrus 0:6bc4ac881c8e 1081
ebrus 0:6bc4ac881c8e 1082 /** @addtogroup Peripheral_declaration
ebrus 0:6bc4ac881c8e 1083 * @{
ebrus 0:6bc4ac881c8e 1084 */
ebrus 0:6bc4ac881c8e 1085 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
ebrus 0:6bc4ac881c8e 1086 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
ebrus 0:6bc4ac881c8e 1087 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
ebrus 0:6bc4ac881c8e 1088 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
ebrus 0:6bc4ac881c8e 1089 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
ebrus 0:6bc4ac881c8e 1090 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
ebrus 0:6bc4ac881c8e 1091 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
ebrus 0:6bc4ac881c8e 1092 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
ebrus 0:6bc4ac881c8e 1093 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
ebrus 0:6bc4ac881c8e 1094 #define RTC ((RTC_TypeDef *) RTC_BASE)
ebrus 0:6bc4ac881c8e 1095 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
ebrus 0:6bc4ac881c8e 1096 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
ebrus 0:6bc4ac881c8e 1097 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
ebrus 0:6bc4ac881c8e 1098 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
ebrus 0:6bc4ac881c8e 1099 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
ebrus 0:6bc4ac881c8e 1100 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
ebrus 0:6bc4ac881c8e 1101 #define USART2 ((USART_TypeDef *) USART2_BASE)
ebrus 0:6bc4ac881c8e 1102 #define USART3 ((USART_TypeDef *) USART3_BASE)
ebrus 0:6bc4ac881c8e 1103 #define UART4 ((USART_TypeDef *) UART4_BASE)
ebrus 0:6bc4ac881c8e 1104 #define UART5 ((USART_TypeDef *) UART5_BASE)
ebrus 0:6bc4ac881c8e 1105 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
ebrus 0:6bc4ac881c8e 1106 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
ebrus 0:6bc4ac881c8e 1107 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
ebrus 0:6bc4ac881c8e 1108 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
ebrus 0:6bc4ac881c8e 1109 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
ebrus 0:6bc4ac881c8e 1110 #define PWR ((PWR_TypeDef *) PWR_BASE)
ebrus 0:6bc4ac881c8e 1111 #define DAC ((DAC_TypeDef *) DAC_BASE)
ebrus 0:6bc4ac881c8e 1112 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
ebrus 0:6bc4ac881c8e 1113 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
ebrus 0:6bc4ac881c8e 1114 #define USART1 ((USART_TypeDef *) USART1_BASE)
ebrus 0:6bc4ac881c8e 1115 #define USART6 ((USART_TypeDef *) USART6_BASE)
ebrus 0:6bc4ac881c8e 1116 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
ebrus 0:6bc4ac881c8e 1117 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
ebrus 0:6bc4ac881c8e 1118 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
ebrus 0:6bc4ac881c8e 1119 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
ebrus 0:6bc4ac881c8e 1120 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
ebrus 0:6bc4ac881c8e 1121 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
ebrus 0:6bc4ac881c8e 1122 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
ebrus 0:6bc4ac881c8e 1123 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
ebrus 0:6bc4ac881c8e 1124 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
ebrus 0:6bc4ac881c8e 1125 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
ebrus 0:6bc4ac881c8e 1126 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
ebrus 0:6bc4ac881c8e 1127 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
ebrus 0:6bc4ac881c8e 1128 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
ebrus 0:6bc4ac881c8e 1129 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
ebrus 0:6bc4ac881c8e 1130 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
ebrus 0:6bc4ac881c8e 1131 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
ebrus 0:6bc4ac881c8e 1132 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
ebrus 0:6bc4ac881c8e 1133 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
ebrus 0:6bc4ac881c8e 1134 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
ebrus 0:6bc4ac881c8e 1135 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
ebrus 0:6bc4ac881c8e 1136 #define CRC ((CRC_TypeDef *) CRC_BASE)
ebrus 0:6bc4ac881c8e 1137 #define RCC ((RCC_TypeDef *) RCC_BASE)
ebrus 0:6bc4ac881c8e 1138 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
ebrus 0:6bc4ac881c8e 1139 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
ebrus 0:6bc4ac881c8e 1140 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
ebrus 0:6bc4ac881c8e 1141 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
ebrus 0:6bc4ac881c8e 1142 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
ebrus 0:6bc4ac881c8e 1143 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
ebrus 0:6bc4ac881c8e 1144 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
ebrus 0:6bc4ac881c8e 1145 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
ebrus 0:6bc4ac881c8e 1146 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
ebrus 0:6bc4ac881c8e 1147 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
ebrus 0:6bc4ac881c8e 1148 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
ebrus 0:6bc4ac881c8e 1149 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
ebrus 0:6bc4ac881c8e 1150 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
ebrus 0:6bc4ac881c8e 1151 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
ebrus 0:6bc4ac881c8e 1152 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
ebrus 0:6bc4ac881c8e 1153 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
ebrus 0:6bc4ac881c8e 1154 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
ebrus 0:6bc4ac881c8e 1155 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
ebrus 0:6bc4ac881c8e 1156 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
ebrus 0:6bc4ac881c8e 1157 #define ETH ((ETH_TypeDef *) ETH_BASE)
ebrus 0:6bc4ac881c8e 1158 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
ebrus 0:6bc4ac881c8e 1159 #define RNG ((RNG_TypeDef *) RNG_BASE)
ebrus 0:6bc4ac881c8e 1160 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
ebrus 0:6bc4ac881c8e 1161 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
ebrus 0:6bc4ac881c8e 1162 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
ebrus 0:6bc4ac881c8e 1163 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
ebrus 0:6bc4ac881c8e 1164
ebrus 0:6bc4ac881c8e 1165 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
ebrus 0:6bc4ac881c8e 1166
ebrus 0:6bc4ac881c8e 1167 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
ebrus 0:6bc4ac881c8e 1168 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
ebrus 0:6bc4ac881c8e 1169
ebrus 0:6bc4ac881c8e 1170 /**
ebrus 0:6bc4ac881c8e 1171 * @}
ebrus 0:6bc4ac881c8e 1172 */
ebrus 0:6bc4ac881c8e 1173
ebrus 0:6bc4ac881c8e 1174 /** @addtogroup Exported_constants
ebrus 0:6bc4ac881c8e 1175 * @{
ebrus 0:6bc4ac881c8e 1176 */
ebrus 0:6bc4ac881c8e 1177
ebrus 0:6bc4ac881c8e 1178 /** @addtogroup Peripheral_Registers_Bits_Definition
ebrus 0:6bc4ac881c8e 1179 * @{
ebrus 0:6bc4ac881c8e 1180 */
ebrus 0:6bc4ac881c8e 1181
ebrus 0:6bc4ac881c8e 1182 /******************************************************************************/
ebrus 0:6bc4ac881c8e 1183 /* Peripheral Registers_Bits_Definition */
ebrus 0:6bc4ac881c8e 1184 /******************************************************************************/
ebrus 0:6bc4ac881c8e 1185
ebrus 0:6bc4ac881c8e 1186 /******************************************************************************/
ebrus 0:6bc4ac881c8e 1187 /* */
ebrus 0:6bc4ac881c8e 1188 /* Analog to Digital Converter */
ebrus 0:6bc4ac881c8e 1189 /* */
ebrus 0:6bc4ac881c8e 1190 /******************************************************************************/
ebrus 0:6bc4ac881c8e 1191 /******************** Bit definition for ADC_SR register ********************/
ebrus 0:6bc4ac881c8e 1192 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
ebrus 0:6bc4ac881c8e 1193 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
ebrus 0:6bc4ac881c8e 1194 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
ebrus 0:6bc4ac881c8e 1195 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
ebrus 0:6bc4ac881c8e 1196 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
ebrus 0:6bc4ac881c8e 1197 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
ebrus 0:6bc4ac881c8e 1198
ebrus 0:6bc4ac881c8e 1199 /******************* Bit definition for ADC_CR1 register ********************/
ebrus 0:6bc4ac881c8e 1200 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
ebrus 0:6bc4ac881c8e 1201 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1202 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1203 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1204 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1205 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1206 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
ebrus 0:6bc4ac881c8e 1207 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
ebrus 0:6bc4ac881c8e 1208 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
ebrus 0:6bc4ac881c8e 1209 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
ebrus 0:6bc4ac881c8e 1210 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
ebrus 0:6bc4ac881c8e 1211 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
ebrus 0:6bc4ac881c8e 1212 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
ebrus 0:6bc4ac881c8e 1213 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
ebrus 0:6bc4ac881c8e 1214 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
ebrus 0:6bc4ac881c8e 1215 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1216 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1217 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1218 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
ebrus 0:6bc4ac881c8e 1219 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
ebrus 0:6bc4ac881c8e 1220 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
ebrus 0:6bc4ac881c8e 1221 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1222 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1223 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
ebrus 0:6bc4ac881c8e 1224
ebrus 0:6bc4ac881c8e 1225 /******************* Bit definition for ADC_CR2 register ********************/
ebrus 0:6bc4ac881c8e 1226 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
ebrus 0:6bc4ac881c8e 1227 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
ebrus 0:6bc4ac881c8e 1228 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
ebrus 0:6bc4ac881c8e 1229 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
ebrus 0:6bc4ac881c8e 1230 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
ebrus 0:6bc4ac881c8e 1231 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
ebrus 0:6bc4ac881c8e 1232 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
ebrus 0:6bc4ac881c8e 1233 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1234 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1235 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1236 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1237 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
ebrus 0:6bc4ac881c8e 1238 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1239 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1240 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
ebrus 0:6bc4ac881c8e 1241 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
ebrus 0:6bc4ac881c8e 1242 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1243 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1244 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1245 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1246 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
ebrus 0:6bc4ac881c8e 1247 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1248 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1249 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
ebrus 0:6bc4ac881c8e 1250
ebrus 0:6bc4ac881c8e 1251 /****************** Bit definition for ADC_SMPR1 register *******************/
ebrus 0:6bc4ac881c8e 1252 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
ebrus 0:6bc4ac881c8e 1253 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1254 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1255 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1256 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
ebrus 0:6bc4ac881c8e 1257 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1258 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1259 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1260 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
ebrus 0:6bc4ac881c8e 1261 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1262 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1263 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1264 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
ebrus 0:6bc4ac881c8e 1265 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1266 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1267 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1268 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
ebrus 0:6bc4ac881c8e 1269 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1270 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1271 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1272 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
ebrus 0:6bc4ac881c8e 1273 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1274 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1275 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1276 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
ebrus 0:6bc4ac881c8e 1277 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1278 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1279 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1280 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
ebrus 0:6bc4ac881c8e 1281 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1282 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1283 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1284 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
ebrus 0:6bc4ac881c8e 1285 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1286 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1287 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1288
ebrus 0:6bc4ac881c8e 1289 /****************** Bit definition for ADC_SMPR2 register *******************/
ebrus 0:6bc4ac881c8e 1290 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
ebrus 0:6bc4ac881c8e 1291 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1292 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1293 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1294 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
ebrus 0:6bc4ac881c8e 1295 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1296 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1297 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1298 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
ebrus 0:6bc4ac881c8e 1299 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1300 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1301 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1302 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
ebrus 0:6bc4ac881c8e 1303 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1304 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1305 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1306 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
ebrus 0:6bc4ac881c8e 1307 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1308 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1309 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1310 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
ebrus 0:6bc4ac881c8e 1311 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1312 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1313 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1314 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
ebrus 0:6bc4ac881c8e 1315 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1316 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1317 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1318 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
ebrus 0:6bc4ac881c8e 1319 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1320 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1321 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1322 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
ebrus 0:6bc4ac881c8e 1323 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1324 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1325 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1326 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
ebrus 0:6bc4ac881c8e 1327 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1328 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1329 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1330
ebrus 0:6bc4ac881c8e 1331 /****************** Bit definition for ADC_JOFR1 register *******************/
ebrus 0:6bc4ac881c8e 1332 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
ebrus 0:6bc4ac881c8e 1333
ebrus 0:6bc4ac881c8e 1334 /****************** Bit definition for ADC_JOFR2 register *******************/
ebrus 0:6bc4ac881c8e 1335 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
ebrus 0:6bc4ac881c8e 1336
ebrus 0:6bc4ac881c8e 1337 /****************** Bit definition for ADC_JOFR3 register *******************/
ebrus 0:6bc4ac881c8e 1338 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
ebrus 0:6bc4ac881c8e 1339
ebrus 0:6bc4ac881c8e 1340 /****************** Bit definition for ADC_JOFR4 register *******************/
ebrus 0:6bc4ac881c8e 1341 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
ebrus 0:6bc4ac881c8e 1342
ebrus 0:6bc4ac881c8e 1343 /******************* Bit definition for ADC_HTR register ********************/
ebrus 0:6bc4ac881c8e 1344 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
ebrus 0:6bc4ac881c8e 1345
ebrus 0:6bc4ac881c8e 1346 /******************* Bit definition for ADC_LTR register ********************/
ebrus 0:6bc4ac881c8e 1347 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
ebrus 0:6bc4ac881c8e 1348
ebrus 0:6bc4ac881c8e 1349 /******************* Bit definition for ADC_SQR1 register *******************/
ebrus 0:6bc4ac881c8e 1350 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1351 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1352 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1353 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1354 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1355 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1356 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1357 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1358 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1359 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1360 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1361 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1362 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1363 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1364 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1365 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1366 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1367 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1368 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1369 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1370 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1371 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1372 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1373 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1374 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
ebrus 0:6bc4ac881c8e 1375 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1376 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1377 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1378 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1379
ebrus 0:6bc4ac881c8e 1380 /******************* Bit definition for ADC_SQR2 register *******************/
ebrus 0:6bc4ac881c8e 1381 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1382 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1383 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1384 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1385 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1386 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1387 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1388 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1389 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1390 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1391 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1392 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1393 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1394 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1395 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1396 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1397 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1398 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1399 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1400 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1401 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1402 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1403 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1404 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1405 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1406 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1407 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1408 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1409 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1410 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1411 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1412 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1413 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1414 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1415 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1416 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1417
ebrus 0:6bc4ac881c8e 1418 /******************* Bit definition for ADC_SQR3 register *******************/
ebrus 0:6bc4ac881c8e 1419 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1420 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1421 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1422 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1423 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1424 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1425 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1426 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1427 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1428 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1429 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1430 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1431 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1432 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1433 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1434 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1435 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1436 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1437 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1438 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1439 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1440 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1441 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1442 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1443 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1444 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1445 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1446 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1447 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1448 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1449 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
ebrus 0:6bc4ac881c8e 1450 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1451 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1452 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1453 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1454 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1455
ebrus 0:6bc4ac881c8e 1456 /******************* Bit definition for ADC_JSQR register *******************/
ebrus 0:6bc4ac881c8e 1457 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
ebrus 0:6bc4ac881c8e 1458 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1459 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1460 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1461 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1462 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1463 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
ebrus 0:6bc4ac881c8e 1464 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1465 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1466 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1467 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1468 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1469 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
ebrus 0:6bc4ac881c8e 1470 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1471 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1472 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1473 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1474 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1475 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
ebrus 0:6bc4ac881c8e 1476 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1477 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1478 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1479 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1480 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1481 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
ebrus 0:6bc4ac881c8e 1482 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1483 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1484
ebrus 0:6bc4ac881c8e 1485 /******************* Bit definition for ADC_JDR1 register *******************/
ebrus 0:6bc4ac881c8e 1486 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
ebrus 0:6bc4ac881c8e 1487
ebrus 0:6bc4ac881c8e 1488 /******************* Bit definition for ADC_JDR2 register *******************/
ebrus 0:6bc4ac881c8e 1489 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
ebrus 0:6bc4ac881c8e 1490
ebrus 0:6bc4ac881c8e 1491 /******************* Bit definition for ADC_JDR3 register *******************/
ebrus 0:6bc4ac881c8e 1492 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
ebrus 0:6bc4ac881c8e 1493
ebrus 0:6bc4ac881c8e 1494 /******************* Bit definition for ADC_JDR4 register *******************/
ebrus 0:6bc4ac881c8e 1495 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
ebrus 0:6bc4ac881c8e 1496
ebrus 0:6bc4ac881c8e 1497 /******************** Bit definition for ADC_DR register ********************/
ebrus 0:6bc4ac881c8e 1498 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
ebrus 0:6bc4ac881c8e 1499 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
ebrus 0:6bc4ac881c8e 1500
ebrus 0:6bc4ac881c8e 1501 /******************* Bit definition for ADC_CSR register ********************/
ebrus 0:6bc4ac881c8e 1502 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
ebrus 0:6bc4ac881c8e 1503 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
ebrus 0:6bc4ac881c8e 1504 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
ebrus 0:6bc4ac881c8e 1505 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
ebrus 0:6bc4ac881c8e 1506 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
ebrus 0:6bc4ac881c8e 1507 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
ebrus 0:6bc4ac881c8e 1508 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
ebrus 0:6bc4ac881c8e 1509 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
ebrus 0:6bc4ac881c8e 1510 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
ebrus 0:6bc4ac881c8e 1511 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
ebrus 0:6bc4ac881c8e 1512 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
ebrus 0:6bc4ac881c8e 1513 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
ebrus 0:6bc4ac881c8e 1514 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
ebrus 0:6bc4ac881c8e 1515 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
ebrus 0:6bc4ac881c8e 1516 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
ebrus 0:6bc4ac881c8e 1517 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
ebrus 0:6bc4ac881c8e 1518 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
ebrus 0:6bc4ac881c8e 1519 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
ebrus 0:6bc4ac881c8e 1520
ebrus 0:6bc4ac881c8e 1521 /******************* Bit definition for ADC_CCR register ********************/
ebrus 0:6bc4ac881c8e 1522 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
ebrus 0:6bc4ac881c8e 1523 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1524 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1525 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1526 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1527 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 1528 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
ebrus 0:6bc4ac881c8e 1529 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1530 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1531 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1532 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1533 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
ebrus 0:6bc4ac881c8e 1534 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
ebrus 0:6bc4ac881c8e 1535 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1536 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1537 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
ebrus 0:6bc4ac881c8e 1538 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1539 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1540 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
ebrus 0:6bc4ac881c8e 1541 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
ebrus 0:6bc4ac881c8e 1542
ebrus 0:6bc4ac881c8e 1543 /******************* Bit definition for ADC_CDR register ********************/
ebrus 0:6bc4ac881c8e 1544 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
ebrus 0:6bc4ac881c8e 1545 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
ebrus 0:6bc4ac881c8e 1546
ebrus 0:6bc4ac881c8e 1547 /******************************************************************************/
ebrus 0:6bc4ac881c8e 1548 /* */
ebrus 0:6bc4ac881c8e 1549 /* Controller Area Network */
ebrus 0:6bc4ac881c8e 1550 /* */
ebrus 0:6bc4ac881c8e 1551 /******************************************************************************/
ebrus 0:6bc4ac881c8e 1552 /*!<CAN control and status registers */
ebrus 0:6bc4ac881c8e 1553 /******************* Bit definition for CAN_MCR register ********************/
ebrus 0:6bc4ac881c8e 1554 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
ebrus 0:6bc4ac881c8e 1555 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
ebrus 0:6bc4ac881c8e 1556 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
ebrus 0:6bc4ac881c8e 1557 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
ebrus 0:6bc4ac881c8e 1558 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
ebrus 0:6bc4ac881c8e 1559 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
ebrus 0:6bc4ac881c8e 1560 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
ebrus 0:6bc4ac881c8e 1561 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
ebrus 0:6bc4ac881c8e 1562 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
ebrus 0:6bc4ac881c8e 1563 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
ebrus 0:6bc4ac881c8e 1564 /******************* Bit definition for CAN_MSR register ********************/
ebrus 0:6bc4ac881c8e 1565 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
ebrus 0:6bc4ac881c8e 1566 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
ebrus 0:6bc4ac881c8e 1567 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
ebrus 0:6bc4ac881c8e 1568 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
ebrus 0:6bc4ac881c8e 1569 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
ebrus 0:6bc4ac881c8e 1570 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
ebrus 0:6bc4ac881c8e 1571 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
ebrus 0:6bc4ac881c8e 1572 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
ebrus 0:6bc4ac881c8e 1573 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
ebrus 0:6bc4ac881c8e 1574
ebrus 0:6bc4ac881c8e 1575 /******************* Bit definition for CAN_TSR register ********************/
ebrus 0:6bc4ac881c8e 1576 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
ebrus 0:6bc4ac881c8e 1577 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
ebrus 0:6bc4ac881c8e 1578 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
ebrus 0:6bc4ac881c8e 1579 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
ebrus 0:6bc4ac881c8e 1580 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
ebrus 0:6bc4ac881c8e 1581 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
ebrus 0:6bc4ac881c8e 1582 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
ebrus 0:6bc4ac881c8e 1583 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
ebrus 0:6bc4ac881c8e 1584 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
ebrus 0:6bc4ac881c8e 1585 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
ebrus 0:6bc4ac881c8e 1586 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
ebrus 0:6bc4ac881c8e 1587 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
ebrus 0:6bc4ac881c8e 1588 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
ebrus 0:6bc4ac881c8e 1589 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
ebrus 0:6bc4ac881c8e 1590 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
ebrus 0:6bc4ac881c8e 1591 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
ebrus 0:6bc4ac881c8e 1592
ebrus 0:6bc4ac881c8e 1593 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
ebrus 0:6bc4ac881c8e 1594 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
ebrus 0:6bc4ac881c8e 1595 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
ebrus 0:6bc4ac881c8e 1596 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
ebrus 0:6bc4ac881c8e 1597
ebrus 0:6bc4ac881c8e 1598 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
ebrus 0:6bc4ac881c8e 1599 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
ebrus 0:6bc4ac881c8e 1600 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
ebrus 0:6bc4ac881c8e 1601 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
ebrus 0:6bc4ac881c8e 1602
ebrus 0:6bc4ac881c8e 1603 /******************* Bit definition for CAN_RF0R register *******************/
ebrus 0:6bc4ac881c8e 1604 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
ebrus 0:6bc4ac881c8e 1605 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
ebrus 0:6bc4ac881c8e 1606 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
ebrus 0:6bc4ac881c8e 1607 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
ebrus 0:6bc4ac881c8e 1608
ebrus 0:6bc4ac881c8e 1609 /******************* Bit definition for CAN_RF1R register *******************/
ebrus 0:6bc4ac881c8e 1610 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
ebrus 0:6bc4ac881c8e 1611 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
ebrus 0:6bc4ac881c8e 1612 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
ebrus 0:6bc4ac881c8e 1613 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
ebrus 0:6bc4ac881c8e 1614
ebrus 0:6bc4ac881c8e 1615 /******************** Bit definition for CAN_IER register *******************/
ebrus 0:6bc4ac881c8e 1616 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
ebrus 0:6bc4ac881c8e 1617 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
ebrus 0:6bc4ac881c8e 1618 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
ebrus 0:6bc4ac881c8e 1619 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
ebrus 0:6bc4ac881c8e 1620 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
ebrus 0:6bc4ac881c8e 1621 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
ebrus 0:6bc4ac881c8e 1622 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
ebrus 0:6bc4ac881c8e 1623 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
ebrus 0:6bc4ac881c8e 1624 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
ebrus 0:6bc4ac881c8e 1625 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
ebrus 0:6bc4ac881c8e 1626 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
ebrus 0:6bc4ac881c8e 1627 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 1628 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
ebrus 0:6bc4ac881c8e 1629 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
ebrus 0:6bc4ac881c8e 1630 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
ebrus 0:6bc4ac881c8e 1631 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
ebrus 0:6bc4ac881c8e 1632 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
ebrus 0:6bc4ac881c8e 1633 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
ebrus 0:6bc4ac881c8e 1634 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
ebrus 0:6bc4ac881c8e 1635
ebrus 0:6bc4ac881c8e 1636
ebrus 0:6bc4ac881c8e 1637 /******************** Bit definition for CAN_ESR register *******************/
ebrus 0:6bc4ac881c8e 1638 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
ebrus 0:6bc4ac881c8e 1639 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
ebrus 0:6bc4ac881c8e 1640 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
ebrus 0:6bc4ac881c8e 1641
ebrus 0:6bc4ac881c8e 1642 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
ebrus 0:6bc4ac881c8e 1643 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1644 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1645 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1646
ebrus 0:6bc4ac881c8e 1647 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
ebrus 0:6bc4ac881c8e 1648 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
ebrus 0:6bc4ac881c8e 1649
ebrus 0:6bc4ac881c8e 1650 /******************* Bit definition for CAN_BTR register ********************/
ebrus 0:6bc4ac881c8e 1651 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
ebrus 0:6bc4ac881c8e 1652 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
ebrus 0:6bc4ac881c8e 1653 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1654 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1655 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1656 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 1657 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
ebrus 0:6bc4ac881c8e 1658 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1659 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1660 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 1661 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
ebrus 0:6bc4ac881c8e 1662 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 1663 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 1664 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
ebrus 0:6bc4ac881c8e 1665 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
ebrus 0:6bc4ac881c8e 1666
ebrus 0:6bc4ac881c8e 1667
ebrus 0:6bc4ac881c8e 1668 /*!<Mailbox registers */
ebrus 0:6bc4ac881c8e 1669 /****************** Bit definition for CAN_TI0R register ********************/
ebrus 0:6bc4ac881c8e 1670 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
ebrus 0:6bc4ac881c8e 1671 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:6bc4ac881c8e 1672 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:6bc4ac881c8e 1673 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
ebrus 0:6bc4ac881c8e 1674 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:6bc4ac881c8e 1675
ebrus 0:6bc4ac881c8e 1676 /****************** Bit definition for CAN_TDT0R register *******************/
ebrus 0:6bc4ac881c8e 1677 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:6bc4ac881c8e 1678 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
ebrus 0:6bc4ac881c8e 1679 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:6bc4ac881c8e 1680
ebrus 0:6bc4ac881c8e 1681 /****************** Bit definition for CAN_TDL0R register *******************/
ebrus 0:6bc4ac881c8e 1682 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:6bc4ac881c8e 1683 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:6bc4ac881c8e 1684 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:6bc4ac881c8e 1685 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:6bc4ac881c8e 1686
ebrus 0:6bc4ac881c8e 1687 /****************** Bit definition for CAN_TDH0R register *******************/
ebrus 0:6bc4ac881c8e 1688 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:6bc4ac881c8e 1689 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:6bc4ac881c8e 1690 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:6bc4ac881c8e 1691 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:6bc4ac881c8e 1692
ebrus 0:6bc4ac881c8e 1693 /******************* Bit definition for CAN_TI1R register *******************/
ebrus 0:6bc4ac881c8e 1694 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
ebrus 0:6bc4ac881c8e 1695 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:6bc4ac881c8e 1696 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:6bc4ac881c8e 1697 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
ebrus 0:6bc4ac881c8e 1698 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:6bc4ac881c8e 1699
ebrus 0:6bc4ac881c8e 1700 /******************* Bit definition for CAN_TDT1R register ******************/
ebrus 0:6bc4ac881c8e 1701 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:6bc4ac881c8e 1702 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
ebrus 0:6bc4ac881c8e 1703 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:6bc4ac881c8e 1704
ebrus 0:6bc4ac881c8e 1705 /******************* Bit definition for CAN_TDL1R register ******************/
ebrus 0:6bc4ac881c8e 1706 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:6bc4ac881c8e 1707 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:6bc4ac881c8e 1708 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:6bc4ac881c8e 1709 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:6bc4ac881c8e 1710
ebrus 0:6bc4ac881c8e 1711 /******************* Bit definition for CAN_TDH1R register ******************/
ebrus 0:6bc4ac881c8e 1712 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:6bc4ac881c8e 1713 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:6bc4ac881c8e 1714 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:6bc4ac881c8e 1715 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:6bc4ac881c8e 1716
ebrus 0:6bc4ac881c8e 1717 /******************* Bit definition for CAN_TI2R register *******************/
ebrus 0:6bc4ac881c8e 1718 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
ebrus 0:6bc4ac881c8e 1719 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:6bc4ac881c8e 1720 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:6bc4ac881c8e 1721 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
ebrus 0:6bc4ac881c8e 1722 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:6bc4ac881c8e 1723
ebrus 0:6bc4ac881c8e 1724 /******************* Bit definition for CAN_TDT2R register ******************/
ebrus 0:6bc4ac881c8e 1725 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:6bc4ac881c8e 1726 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
ebrus 0:6bc4ac881c8e 1727 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:6bc4ac881c8e 1728
ebrus 0:6bc4ac881c8e 1729 /******************* Bit definition for CAN_TDL2R register ******************/
ebrus 0:6bc4ac881c8e 1730 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:6bc4ac881c8e 1731 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:6bc4ac881c8e 1732 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:6bc4ac881c8e 1733 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:6bc4ac881c8e 1734
ebrus 0:6bc4ac881c8e 1735 /******************* Bit definition for CAN_TDH2R register ******************/
ebrus 0:6bc4ac881c8e 1736 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:6bc4ac881c8e 1737 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:6bc4ac881c8e 1738 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:6bc4ac881c8e 1739 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:6bc4ac881c8e 1740
ebrus 0:6bc4ac881c8e 1741 /******************* Bit definition for CAN_RI0R register *******************/
ebrus 0:6bc4ac881c8e 1742 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:6bc4ac881c8e 1743 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:6bc4ac881c8e 1744 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
ebrus 0:6bc4ac881c8e 1745 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:6bc4ac881c8e 1746
ebrus 0:6bc4ac881c8e 1747 /******************* Bit definition for CAN_RDT0R register ******************/
ebrus 0:6bc4ac881c8e 1748 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:6bc4ac881c8e 1749 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
ebrus 0:6bc4ac881c8e 1750 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:6bc4ac881c8e 1751
ebrus 0:6bc4ac881c8e 1752 /******************* Bit definition for CAN_RDL0R register ******************/
ebrus 0:6bc4ac881c8e 1753 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:6bc4ac881c8e 1754 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:6bc4ac881c8e 1755 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:6bc4ac881c8e 1756 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:6bc4ac881c8e 1757
ebrus 0:6bc4ac881c8e 1758 /******************* Bit definition for CAN_RDH0R register ******************/
ebrus 0:6bc4ac881c8e 1759 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:6bc4ac881c8e 1760 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:6bc4ac881c8e 1761 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:6bc4ac881c8e 1762 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:6bc4ac881c8e 1763
ebrus 0:6bc4ac881c8e 1764 /******************* Bit definition for CAN_RI1R register *******************/
ebrus 0:6bc4ac881c8e 1765 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
ebrus 0:6bc4ac881c8e 1766 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
ebrus 0:6bc4ac881c8e 1767 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
ebrus 0:6bc4ac881c8e 1768 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
ebrus 0:6bc4ac881c8e 1769
ebrus 0:6bc4ac881c8e 1770 /******************* Bit definition for CAN_RDT1R register ******************/
ebrus 0:6bc4ac881c8e 1771 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
ebrus 0:6bc4ac881c8e 1772 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
ebrus 0:6bc4ac881c8e 1773 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
ebrus 0:6bc4ac881c8e 1774
ebrus 0:6bc4ac881c8e 1775 /******************* Bit definition for CAN_RDL1R register ******************/
ebrus 0:6bc4ac881c8e 1776 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
ebrus 0:6bc4ac881c8e 1777 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
ebrus 0:6bc4ac881c8e 1778 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
ebrus 0:6bc4ac881c8e 1779 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
ebrus 0:6bc4ac881c8e 1780
ebrus 0:6bc4ac881c8e 1781 /******************* Bit definition for CAN_RDH1R register ******************/
ebrus 0:6bc4ac881c8e 1782 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
ebrus 0:6bc4ac881c8e 1783 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
ebrus 0:6bc4ac881c8e 1784 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
ebrus 0:6bc4ac881c8e 1785 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
ebrus 0:6bc4ac881c8e 1786
ebrus 0:6bc4ac881c8e 1787 /*!<CAN filter registers */
ebrus 0:6bc4ac881c8e 1788 /******************* Bit definition for CAN_FMR register ********************/
ebrus 0:6bc4ac881c8e 1789 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
ebrus 0:6bc4ac881c8e 1790 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
ebrus 0:6bc4ac881c8e 1791
ebrus 0:6bc4ac881c8e 1792 /******************* Bit definition for CAN_FM1R register *******************/
ebrus 0:6bc4ac881c8e 1793 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
ebrus 0:6bc4ac881c8e 1794 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
ebrus 0:6bc4ac881c8e 1795 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
ebrus 0:6bc4ac881c8e 1796 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
ebrus 0:6bc4ac881c8e 1797 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
ebrus 0:6bc4ac881c8e 1798 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
ebrus 0:6bc4ac881c8e 1799 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
ebrus 0:6bc4ac881c8e 1800 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
ebrus 0:6bc4ac881c8e 1801 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
ebrus 0:6bc4ac881c8e 1802 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
ebrus 0:6bc4ac881c8e 1803 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
ebrus 0:6bc4ac881c8e 1804 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
ebrus 0:6bc4ac881c8e 1805 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
ebrus 0:6bc4ac881c8e 1806 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
ebrus 0:6bc4ac881c8e 1807 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
ebrus 0:6bc4ac881c8e 1808
ebrus 0:6bc4ac881c8e 1809 /******************* Bit definition for CAN_FS1R register *******************/
ebrus 0:6bc4ac881c8e 1810 #define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
ebrus 0:6bc4ac881c8e 1811 #define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
ebrus 0:6bc4ac881c8e 1812 #define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
ebrus 0:6bc4ac881c8e 1813 #define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
ebrus 0:6bc4ac881c8e 1814 #define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
ebrus 0:6bc4ac881c8e 1815 #define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
ebrus 0:6bc4ac881c8e 1816 #define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
ebrus 0:6bc4ac881c8e 1817 #define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
ebrus 0:6bc4ac881c8e 1818 #define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
ebrus 0:6bc4ac881c8e 1819 #define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
ebrus 0:6bc4ac881c8e 1820 #define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
ebrus 0:6bc4ac881c8e 1821 #define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
ebrus 0:6bc4ac881c8e 1822 #define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
ebrus 0:6bc4ac881c8e 1823 #define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
ebrus 0:6bc4ac881c8e 1824 #define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
ebrus 0:6bc4ac881c8e 1825
ebrus 0:6bc4ac881c8e 1826 /****************** Bit definition for CAN_FFA1R register *******************/
ebrus 0:6bc4ac881c8e 1827 #define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
ebrus 0:6bc4ac881c8e 1828 #define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
ebrus 0:6bc4ac881c8e 1829 #define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
ebrus 0:6bc4ac881c8e 1830 #define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
ebrus 0:6bc4ac881c8e 1831 #define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
ebrus 0:6bc4ac881c8e 1832 #define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
ebrus 0:6bc4ac881c8e 1833 #define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
ebrus 0:6bc4ac881c8e 1834 #define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
ebrus 0:6bc4ac881c8e 1835 #define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
ebrus 0:6bc4ac881c8e 1836 #define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
ebrus 0:6bc4ac881c8e 1837 #define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
ebrus 0:6bc4ac881c8e 1838 #define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
ebrus 0:6bc4ac881c8e 1839 #define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
ebrus 0:6bc4ac881c8e 1840 #define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
ebrus 0:6bc4ac881c8e 1841 #define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
ebrus 0:6bc4ac881c8e 1842
ebrus 0:6bc4ac881c8e 1843 /******************* Bit definition for CAN_FA1R register *******************/
ebrus 0:6bc4ac881c8e 1844 #define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
ebrus 0:6bc4ac881c8e 1845 #define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
ebrus 0:6bc4ac881c8e 1846 #define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
ebrus 0:6bc4ac881c8e 1847 #define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
ebrus 0:6bc4ac881c8e 1848 #define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
ebrus 0:6bc4ac881c8e 1849 #define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
ebrus 0:6bc4ac881c8e 1850 #define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
ebrus 0:6bc4ac881c8e 1851 #define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
ebrus 0:6bc4ac881c8e 1852 #define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
ebrus 0:6bc4ac881c8e 1853 #define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
ebrus 0:6bc4ac881c8e 1854 #define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
ebrus 0:6bc4ac881c8e 1855 #define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
ebrus 0:6bc4ac881c8e 1856 #define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
ebrus 0:6bc4ac881c8e 1857 #define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
ebrus 0:6bc4ac881c8e 1858 #define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
ebrus 0:6bc4ac881c8e 1859
ebrus 0:6bc4ac881c8e 1860 /******************* Bit definition for CAN_F0R1 register *******************/
ebrus 0:6bc4ac881c8e 1861 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 1862 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 1863 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 1864 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 1865 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 1866 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 1867 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 1868 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 1869 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 1870 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 1871 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 1872 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 1873 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 1874 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 1875 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 1876 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 1877 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 1878 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 1879 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 1880 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 1881 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 1882 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 1883 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 1884 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 1885 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 1886 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 1887 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 1888 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 1889 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 1890 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 1891 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 1892 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 1893
ebrus 0:6bc4ac881c8e 1894 /******************* Bit definition for CAN_F1R1 register *******************/
ebrus 0:6bc4ac881c8e 1895 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 1896 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 1897 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 1898 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 1899 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 1900 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 1901 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 1902 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 1903 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 1904 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 1905 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 1906 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 1907 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 1908 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 1909 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 1910 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 1911 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 1912 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 1913 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 1914 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 1915 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 1916 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 1917 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 1918 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 1919 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 1920 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 1921 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 1922 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 1923 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 1924 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 1925 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 1926 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 1927
ebrus 0:6bc4ac881c8e 1928 /******************* Bit definition for CAN_F2R1 register *******************/
ebrus 0:6bc4ac881c8e 1929 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 1930 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 1931 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 1932 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 1933 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 1934 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 1935 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 1936 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 1937 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 1938 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 1939 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 1940 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 1941 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 1942 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 1943 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 1944 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 1945 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 1946 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 1947 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 1948 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 1949 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 1950 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 1951 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 1952 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 1953 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 1954 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 1955 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 1956 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 1957 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 1958 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 1959 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 1960 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 1961
ebrus 0:6bc4ac881c8e 1962 /******************* Bit definition for CAN_F3R1 register *******************/
ebrus 0:6bc4ac881c8e 1963 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 1964 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 1965 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 1966 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 1967 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 1968 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 1969 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 1970 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 1971 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 1972 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 1973 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 1974 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 1975 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 1976 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 1977 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 1978 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 1979 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 1980 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 1981 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 1982 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 1983 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 1984 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 1985 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 1986 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 1987 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 1988 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 1989 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 1990 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 1991 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 1992 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 1993 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 1994 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 1995
ebrus 0:6bc4ac881c8e 1996 /******************* Bit definition for CAN_F4R1 register *******************/
ebrus 0:6bc4ac881c8e 1997 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 1998 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 1999 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2000 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2001 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2002 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2003 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2004 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2005 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2006 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2007 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2008 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2009 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2010 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2011 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2012 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2013 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2014 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2015 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2016 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2017 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2018 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2019 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2020 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2021 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2022 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2023 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2024 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2025 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2026 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2027 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2028 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2029
ebrus 0:6bc4ac881c8e 2030 /******************* Bit definition for CAN_F5R1 register *******************/
ebrus 0:6bc4ac881c8e 2031 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2032 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2033 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2034 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2035 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2036 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2037 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2038 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2039 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2040 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2041 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2042 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2043 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2044 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2045 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2046 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2047 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2048 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2049 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2050 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2051 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2052 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2053 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2054 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2055 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2056 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2057 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2058 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2059 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2060 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2061 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2062 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2063
ebrus 0:6bc4ac881c8e 2064 /******************* Bit definition for CAN_F6R1 register *******************/
ebrus 0:6bc4ac881c8e 2065 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2066 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2067 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2068 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2069 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2070 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2071 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2072 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2073 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2074 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2075 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2076 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2077 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2078 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2079 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2080 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2081 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2082 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2083 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2084 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2085 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2086 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2087 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2088 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2089 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2090 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2091 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2092 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2093 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2094 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2095 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2096 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2097
ebrus 0:6bc4ac881c8e 2098 /******************* Bit definition for CAN_F7R1 register *******************/
ebrus 0:6bc4ac881c8e 2099 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2100 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2101 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2102 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2103 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2104 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2105 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2106 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2107 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2108 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2109 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2110 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2111 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2112 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2113 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2114 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2115 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2116 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2117 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2118 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2119 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2120 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2121 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2122 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2123 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2124 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2125 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2126 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2127 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2128 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2129 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2130 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2131
ebrus 0:6bc4ac881c8e 2132 /******************* Bit definition for CAN_F8R1 register *******************/
ebrus 0:6bc4ac881c8e 2133 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2134 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2135 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2136 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2137 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2138 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2139 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2140 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2141 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2142 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2143 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2144 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2145 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2146 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2147 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2148 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2149 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2150 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2151 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2152 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2153 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2154 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2155 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2156 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2157 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2158 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2159 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2160 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2161 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2162 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2163 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2164 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2165
ebrus 0:6bc4ac881c8e 2166 /******************* Bit definition for CAN_F9R1 register *******************/
ebrus 0:6bc4ac881c8e 2167 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2168 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2169 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2170 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2171 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2172 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2173 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2174 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2175 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2176 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2177 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2178 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2179 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2180 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2181 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2182 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2183 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2184 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2185 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2186 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2187 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2188 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2189 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2190 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2191 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2192 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2193 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2194 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2195 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2196 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2197 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2198 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2199
ebrus 0:6bc4ac881c8e 2200 /******************* Bit definition for CAN_F10R1 register ******************/
ebrus 0:6bc4ac881c8e 2201 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2202 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2203 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2204 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2205 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2206 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2207 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2208 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2209 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2210 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2211 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2212 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2213 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2214 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2215 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2216 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2217 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2218 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2219 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2220 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2221 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2222 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2223 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2224 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2225 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2226 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2227 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2228 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2229 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2230 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2231 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2232 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2233
ebrus 0:6bc4ac881c8e 2234 /******************* Bit definition for CAN_F11R1 register ******************/
ebrus 0:6bc4ac881c8e 2235 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2236 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2237 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2238 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2239 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2240 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2241 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2242 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2243 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2244 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2245 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2246 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2247 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2248 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2249 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2250 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2251 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2252 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2253 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2254 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2255 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2256 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2257 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2258 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2259 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2260 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2261 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2262 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2263 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2264 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2265 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2266 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2267
ebrus 0:6bc4ac881c8e 2268 /******************* Bit definition for CAN_F12R1 register ******************/
ebrus 0:6bc4ac881c8e 2269 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2270 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2271 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2272 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2273 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2274 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2275 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2276 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2277 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2278 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2279 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2280 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2281 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2282 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2283 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2284 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2285 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2286 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2287 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2288 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2289 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2290 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2291 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2292 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2293 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2294 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2295 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2296 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2297 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2298 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2299 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2300 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2301
ebrus 0:6bc4ac881c8e 2302 /******************* Bit definition for CAN_F13R1 register ******************/
ebrus 0:6bc4ac881c8e 2303 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2304 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2305 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2306 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2307 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2308 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2309 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2310 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2311 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2312 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2313 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2314 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2315 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2316 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2317 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2318 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2319 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2320 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2321 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2322 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2323 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2324 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2325 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2326 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2327 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2328 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2329 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2330 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2331 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2332 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2333 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2334 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2335
ebrus 0:6bc4ac881c8e 2336 /******************* Bit definition for CAN_F0R2 register *******************/
ebrus 0:6bc4ac881c8e 2337 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2338 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2339 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2340 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2341 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2342 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2343 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2344 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2345 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2346 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2347 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2348 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2349 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2350 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2351 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2352 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2353 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2354 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2355 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2356 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2357 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2358 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2359 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2360 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2361 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2362 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2363 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2364 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2365 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2366 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2367 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2368 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2369
ebrus 0:6bc4ac881c8e 2370 /******************* Bit definition for CAN_F1R2 register *******************/
ebrus 0:6bc4ac881c8e 2371 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2372 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2373 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2374 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2375 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2376 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2377 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2378 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2379 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2380 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2381 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2382 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2383 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2384 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2385 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2386 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2387 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2388 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2389 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2390 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2391 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2392 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2393 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2394 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2395 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2396 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2397 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2398 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2399 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2400 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2401 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2402 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2403
ebrus 0:6bc4ac881c8e 2404 /******************* Bit definition for CAN_F2R2 register *******************/
ebrus 0:6bc4ac881c8e 2405 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2406 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2407 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2408 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2409 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2410 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2411 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2412 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2413 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2414 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2415 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2416 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2417 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2418 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2419 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2420 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2421 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2422 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2423 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2424 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2425 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2426 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2427 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2428 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2429 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2430 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2431 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2432 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2433 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2434 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2435 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2436 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2437
ebrus 0:6bc4ac881c8e 2438 /******************* Bit definition for CAN_F3R2 register *******************/
ebrus 0:6bc4ac881c8e 2439 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2440 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2441 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2442 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2443 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2444 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2445 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2446 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2447 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2448 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2449 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2450 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2451 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2452 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2453 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2454 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2455 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2456 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2457 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2458 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2459 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2460 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2461 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2462 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2463 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2464 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2465 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2466 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2467 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2468 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2469 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2470 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2471
ebrus 0:6bc4ac881c8e 2472 /******************* Bit definition for CAN_F4R2 register *******************/
ebrus 0:6bc4ac881c8e 2473 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2474 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2475 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2476 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2477 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2478 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2479 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2480 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2481 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2482 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2483 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2484 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2485 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2486 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2487 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2488 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2489 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2490 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2491 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2492 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2493 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2494 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2495 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2496 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2497 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2498 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2499 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2500 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2501 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2502 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2503 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2504 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2505
ebrus 0:6bc4ac881c8e 2506 /******************* Bit definition for CAN_F5R2 register *******************/
ebrus 0:6bc4ac881c8e 2507 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2508 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2509 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2510 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2511 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2512 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2513 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2514 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2515 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2516 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2517 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2518 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2519 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2520 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2521 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2522 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2523 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2524 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2525 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2526 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2527 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2528 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2529 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2530 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2531 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2532 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2533 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2534 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2535 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2536 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2537 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2538 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2539
ebrus 0:6bc4ac881c8e 2540 /******************* Bit definition for CAN_F6R2 register *******************/
ebrus 0:6bc4ac881c8e 2541 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2542 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2543 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2544 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2545 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2546 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2547 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2548 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2549 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2550 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2551 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2552 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2553 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2554 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2555 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2556 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2557 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2558 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2559 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2560 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2561 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2562 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2563 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2564 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2565 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2566 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2567 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2568 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2569 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2570 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2571 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2572 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2573
ebrus 0:6bc4ac881c8e 2574 /******************* Bit definition for CAN_F7R2 register *******************/
ebrus 0:6bc4ac881c8e 2575 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2576 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2577 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2578 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2579 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2580 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2581 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2582 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2583 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2584 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2585 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2586 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2587 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2588 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2589 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2590 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2591 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2592 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2593 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2594 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2595 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2596 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2597 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2598 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2599 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2600 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2601 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2602 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2603 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2604 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2605 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2606 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2607
ebrus 0:6bc4ac881c8e 2608 /******************* Bit definition for CAN_F8R2 register *******************/
ebrus 0:6bc4ac881c8e 2609 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2610 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2611 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2612 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2613 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2614 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2615 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2616 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2617 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2618 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2619 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2620 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2621 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2622 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2623 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2624 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2625 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2626 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2627 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2628 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2629 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2630 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2631 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2632 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2633 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2634 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2635 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2636 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2637 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2638 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2639 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2640 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2641
ebrus 0:6bc4ac881c8e 2642 /******************* Bit definition for CAN_F9R2 register *******************/
ebrus 0:6bc4ac881c8e 2643 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2644 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2645 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2646 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2647 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2648 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2649 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2650 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2651 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2652 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2653 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2654 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2655 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2656 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2657 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2658 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2659 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2660 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2661 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2662 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2663 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2664 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2665 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2666 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2667 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2668 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2669 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2670 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2671 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2672 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2673 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2674 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2675
ebrus 0:6bc4ac881c8e 2676 /******************* Bit definition for CAN_F10R2 register ******************/
ebrus 0:6bc4ac881c8e 2677 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2678 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2679 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2680 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2681 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2682 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2683 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2684 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2685 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2686 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2687 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2688 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2689 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2690 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2691 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2692 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2693 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2694 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2695 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2696 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2697 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2698 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2699 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2700 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2701 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2702 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2703 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2704 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2705 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2706 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2707 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2708 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2709
ebrus 0:6bc4ac881c8e 2710 /******************* Bit definition for CAN_F11R2 register ******************/
ebrus 0:6bc4ac881c8e 2711 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2712 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2713 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2714 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2715 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2716 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2717 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2718 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2719 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2720 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2721 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2722 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2723 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2724 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2725 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2726 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2727 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2728 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2729 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2730 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2731 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2732 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2733 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2734 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2735 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2736 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2737 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2738 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2739 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2740 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2741 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2742 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2743
ebrus 0:6bc4ac881c8e 2744 /******************* Bit definition for CAN_F12R2 register ******************/
ebrus 0:6bc4ac881c8e 2745 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2746 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2747 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2748 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2749 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2750 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2751 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2752 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2753 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2754 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2755 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2756 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2757 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2758 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2759 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2760 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2761 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2762 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2763 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2764 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2765 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2766 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2767 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2768 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2769 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2770 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2771 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2772 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2773 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2774 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2775 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2776 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2777
ebrus 0:6bc4ac881c8e 2778 /******************* Bit definition for CAN_F13R2 register ******************/
ebrus 0:6bc4ac881c8e 2779 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
ebrus 0:6bc4ac881c8e 2780 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
ebrus 0:6bc4ac881c8e 2781 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
ebrus 0:6bc4ac881c8e 2782 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
ebrus 0:6bc4ac881c8e 2783 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
ebrus 0:6bc4ac881c8e 2784 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
ebrus 0:6bc4ac881c8e 2785 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
ebrus 0:6bc4ac881c8e 2786 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
ebrus 0:6bc4ac881c8e 2787 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
ebrus 0:6bc4ac881c8e 2788 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
ebrus 0:6bc4ac881c8e 2789 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
ebrus 0:6bc4ac881c8e 2790 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
ebrus 0:6bc4ac881c8e 2791 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
ebrus 0:6bc4ac881c8e 2792 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
ebrus 0:6bc4ac881c8e 2793 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
ebrus 0:6bc4ac881c8e 2794 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
ebrus 0:6bc4ac881c8e 2795 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
ebrus 0:6bc4ac881c8e 2796 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
ebrus 0:6bc4ac881c8e 2797 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
ebrus 0:6bc4ac881c8e 2798 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
ebrus 0:6bc4ac881c8e 2799 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
ebrus 0:6bc4ac881c8e 2800 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
ebrus 0:6bc4ac881c8e 2801 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
ebrus 0:6bc4ac881c8e 2802 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
ebrus 0:6bc4ac881c8e 2803 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
ebrus 0:6bc4ac881c8e 2804 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
ebrus 0:6bc4ac881c8e 2805 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
ebrus 0:6bc4ac881c8e 2806 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
ebrus 0:6bc4ac881c8e 2807 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
ebrus 0:6bc4ac881c8e 2808 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
ebrus 0:6bc4ac881c8e 2809 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
ebrus 0:6bc4ac881c8e 2810 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
ebrus 0:6bc4ac881c8e 2811
ebrus 0:6bc4ac881c8e 2812 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2813 /* */
ebrus 0:6bc4ac881c8e 2814 /* CRC calculation unit */
ebrus 0:6bc4ac881c8e 2815 /* */
ebrus 0:6bc4ac881c8e 2816 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2817 /******************* Bit definition for CRC_DR register *********************/
ebrus 0:6bc4ac881c8e 2818 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
ebrus 0:6bc4ac881c8e 2819
ebrus 0:6bc4ac881c8e 2820
ebrus 0:6bc4ac881c8e 2821 /******************* Bit definition for CRC_IDR register ********************/
ebrus 0:6bc4ac881c8e 2822 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
ebrus 0:6bc4ac881c8e 2823
ebrus 0:6bc4ac881c8e 2824
ebrus 0:6bc4ac881c8e 2825 /******************** Bit definition for CRC_CR register ********************/
ebrus 0:6bc4ac881c8e 2826 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
ebrus 0:6bc4ac881c8e 2827
ebrus 0:6bc4ac881c8e 2828
ebrus 0:6bc4ac881c8e 2829 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2830 /* */
ebrus 0:6bc4ac881c8e 2831 /* Digital to Analog Converter */
ebrus 0:6bc4ac881c8e 2832 /* */
ebrus 0:6bc4ac881c8e 2833 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2834 /******************** Bit definition for DAC_CR register ********************/
ebrus 0:6bc4ac881c8e 2835 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
ebrus 0:6bc4ac881c8e 2836 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
ebrus 0:6bc4ac881c8e 2837 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
ebrus 0:6bc4ac881c8e 2838
ebrus 0:6bc4ac881c8e 2839 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
ebrus 0:6bc4ac881c8e 2840 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 2841 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 2842 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 2843
ebrus 0:6bc4ac881c8e 2844 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
ebrus 0:6bc4ac881c8e 2845 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 2846 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 2847
ebrus 0:6bc4ac881c8e 2848 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
ebrus 0:6bc4ac881c8e 2849 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 2850 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 2851 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 2852 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 2853
ebrus 0:6bc4ac881c8e 2854 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
ebrus 0:6bc4ac881c8e 2855 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
ebrus 0:6bc4ac881c8e 2856 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
ebrus 0:6bc4ac881c8e 2857 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
ebrus 0:6bc4ac881c8e 2858
ebrus 0:6bc4ac881c8e 2859 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
ebrus 0:6bc4ac881c8e 2860 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 2861 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 2862 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 2863
ebrus 0:6bc4ac881c8e 2864 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
ebrus 0:6bc4ac881c8e 2865 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 2866 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 2867
ebrus 0:6bc4ac881c8e 2868 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
ebrus 0:6bc4ac881c8e 2869 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 2870 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 2871 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 2872 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 2873
ebrus 0:6bc4ac881c8e 2874 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
ebrus 0:6bc4ac881c8e 2875
ebrus 0:6bc4ac881c8e 2876 /***************** Bit definition for DAC_SWTRIGR register ******************/
ebrus 0:6bc4ac881c8e 2877 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
ebrus 0:6bc4ac881c8e 2878 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
ebrus 0:6bc4ac881c8e 2879
ebrus 0:6bc4ac881c8e 2880 /***************** Bit definition for DAC_DHR12R1 register ******************/
ebrus 0:6bc4ac881c8e 2881 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2882
ebrus 0:6bc4ac881c8e 2883 /***************** Bit definition for DAC_DHR12L1 register ******************/
ebrus 0:6bc4ac881c8e 2884 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
ebrus 0:6bc4ac881c8e 2885
ebrus 0:6bc4ac881c8e 2886 /****************** Bit definition for DAC_DHR8R1 register ******************/
ebrus 0:6bc4ac881c8e 2887 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2888
ebrus 0:6bc4ac881c8e 2889 /***************** Bit definition for DAC_DHR12R2 register ******************/
ebrus 0:6bc4ac881c8e 2890 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2891
ebrus 0:6bc4ac881c8e 2892 /***************** Bit definition for DAC_DHR12L2 register ******************/
ebrus 0:6bc4ac881c8e 2893 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
ebrus 0:6bc4ac881c8e 2894
ebrus 0:6bc4ac881c8e 2895 /****************** Bit definition for DAC_DHR8R2 register ******************/
ebrus 0:6bc4ac881c8e 2896 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2897
ebrus 0:6bc4ac881c8e 2898 /***************** Bit definition for DAC_DHR12RD register ******************/
ebrus 0:6bc4ac881c8e 2899 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2900 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2901
ebrus 0:6bc4ac881c8e 2902 /***************** Bit definition for DAC_DHR12LD register ******************/
ebrus 0:6bc4ac881c8e 2903 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
ebrus 0:6bc4ac881c8e 2904 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
ebrus 0:6bc4ac881c8e 2905
ebrus 0:6bc4ac881c8e 2906 /****************** Bit definition for DAC_DHR8RD register ******************/
ebrus 0:6bc4ac881c8e 2907 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2908 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
ebrus 0:6bc4ac881c8e 2909
ebrus 0:6bc4ac881c8e 2910 /******************* Bit definition for DAC_DOR1 register *******************/
ebrus 0:6bc4ac881c8e 2911 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
ebrus 0:6bc4ac881c8e 2912
ebrus 0:6bc4ac881c8e 2913 /******************* Bit definition for DAC_DOR2 register *******************/
ebrus 0:6bc4ac881c8e 2914 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
ebrus 0:6bc4ac881c8e 2915
ebrus 0:6bc4ac881c8e 2916 /******************** Bit definition for DAC_SR register ********************/
ebrus 0:6bc4ac881c8e 2917 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
ebrus 0:6bc4ac881c8e 2918 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
ebrus 0:6bc4ac881c8e 2919
ebrus 0:6bc4ac881c8e 2920 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2921 /* */
ebrus 0:6bc4ac881c8e 2922 /* Debug MCU */
ebrus 0:6bc4ac881c8e 2923 /* */
ebrus 0:6bc4ac881c8e 2924 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2925
ebrus 0:6bc4ac881c8e 2926 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2927 /* */
ebrus 0:6bc4ac881c8e 2928 /* DCMI */
ebrus 0:6bc4ac881c8e 2929 /* */
ebrus 0:6bc4ac881c8e 2930 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2931 /******************** Bits definition for DCMI_CR register ******************/
ebrus 0:6bc4ac881c8e 2932 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 2933 #define DCMI_CR_CM ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 2934 #define DCMI_CR_CROP ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 2935 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 2936 #define DCMI_CR_ESS ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 2937 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 2938 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 2939 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 2940 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 2941 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 2942 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 2943 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 2944 #define DCMI_CR_CRE ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 2945 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 2946
ebrus 0:6bc4ac881c8e 2947 /******************** Bits definition for DCMI_SR register ******************/
ebrus 0:6bc4ac881c8e 2948 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 2949 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 2950 #define DCMI_SR_FNE ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 2951
ebrus 0:6bc4ac881c8e 2952 /******************** Bits definition for DCMI_RISR register ****************/
ebrus 0:6bc4ac881c8e 2953 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 2954 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 2955 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 2956 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 2957 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 2958
ebrus 0:6bc4ac881c8e 2959 /******************** Bits definition for DCMI_IER register *****************/
ebrus 0:6bc4ac881c8e 2960 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 2961 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 2962 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 2963 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 2964 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 2965
ebrus 0:6bc4ac881c8e 2966 /******************** Bits definition for DCMI_MISR register ****************/
ebrus 0:6bc4ac881c8e 2967 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 2968 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 2969 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 2970 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 2971 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 2972
ebrus 0:6bc4ac881c8e 2973 /******************** Bits definition for DCMI_ICR register *****************/
ebrus 0:6bc4ac881c8e 2974 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 2975 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 2976 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 2977 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 2978 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 2979
ebrus 0:6bc4ac881c8e 2980 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2981 /* */
ebrus 0:6bc4ac881c8e 2982 /* DMA Controller */
ebrus 0:6bc4ac881c8e 2983 /* */
ebrus 0:6bc4ac881c8e 2984 /******************************************************************************/
ebrus 0:6bc4ac881c8e 2985 /******************** Bits definition for DMA_SxCR register *****************/
ebrus 0:6bc4ac881c8e 2986 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
ebrus 0:6bc4ac881c8e 2987 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 2988 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 2989 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 2990 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
ebrus 0:6bc4ac881c8e 2991 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 2992 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 2993 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
ebrus 0:6bc4ac881c8e 2994 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 2995 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 2996 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 2997 #define DMA_SxCR_CT ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 2998 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 2999 #define DMA_SxCR_PL ((uint32_t)0x00030000)
ebrus 0:6bc4ac881c8e 3000 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3001 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 3002 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 3003 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
ebrus 0:6bc4ac881c8e 3004 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 3005 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 3006 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
ebrus 0:6bc4ac881c8e 3007 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3008 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 3009 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3010 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3011 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3012 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
ebrus 0:6bc4ac881c8e 3013 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3014 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 3015 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3016 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3017 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3018 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3019 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3020 #define DMA_SxCR_EN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3021
ebrus 0:6bc4ac881c8e 3022 /******************** Bits definition for DMA_SxCNDTR register **************/
ebrus 0:6bc4ac881c8e 3023 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
ebrus 0:6bc4ac881c8e 3024 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3025 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3026 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3027 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3028 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3029 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3030 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3031 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 3032 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3033 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3034 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3035 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3036 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 3037 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 3038 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 3039 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 3040
ebrus 0:6bc4ac881c8e 3041 /******************** Bits definition for DMA_SxFCR register ****************/
ebrus 0:6bc4ac881c8e 3042 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 3043 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
ebrus 0:6bc4ac881c8e 3044 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3045 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3046 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3047 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3048 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
ebrus 0:6bc4ac881c8e 3049 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3050 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3051
ebrus 0:6bc4ac881c8e 3052 /******************** Bits definition for DMA_LISR register *****************/
ebrus 0:6bc4ac881c8e 3053 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 3054 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 3055 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 3056 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3057 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 3058 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 3059 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 3060 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 3061 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 3062 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3063 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3064 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3065 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3066 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3067 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3068 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3069 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3070 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3071 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3072 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3073
ebrus 0:6bc4ac881c8e 3074 /******************** Bits definition for DMA_HISR register *****************/
ebrus 0:6bc4ac881c8e 3075 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 3076 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 3077 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 3078 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3079 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 3080 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 3081 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 3082 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 3083 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 3084 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3085 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3086 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3087 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3088 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3089 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3090 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3091 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3092 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3093 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3094 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3095
ebrus 0:6bc4ac881c8e 3096 /******************** Bits definition for DMA_LIFCR register ****************/
ebrus 0:6bc4ac881c8e 3097 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 3098 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 3099 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 3100 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3101 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 3102 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 3103 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 3104 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 3105 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 3106 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3107 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3108 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3109 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3110 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3111 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3112 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3113 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3114 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3115 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3116 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3117
ebrus 0:6bc4ac881c8e 3118 /******************** Bits definition for DMA_HIFCR register ****************/
ebrus 0:6bc4ac881c8e 3119 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 3120 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 3121 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 3122 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3123 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 3124 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 3125 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 3126 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 3127 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 3128 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3129 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3130 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3131 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3132 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3133 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3134 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3135 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3136 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3137 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3138 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3139
ebrus 0:6bc4ac881c8e 3140
ebrus 0:6bc4ac881c8e 3141 /******************************************************************************/
ebrus 0:6bc4ac881c8e 3142 /* */
ebrus 0:6bc4ac881c8e 3143 /* External Interrupt/Event Controller */
ebrus 0:6bc4ac881c8e 3144 /* */
ebrus 0:6bc4ac881c8e 3145 /******************************************************************************/
ebrus 0:6bc4ac881c8e 3146 /******************* Bit definition for EXTI_IMR register *******************/
ebrus 0:6bc4ac881c8e 3147 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
ebrus 0:6bc4ac881c8e 3148 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
ebrus 0:6bc4ac881c8e 3149 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
ebrus 0:6bc4ac881c8e 3150 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
ebrus 0:6bc4ac881c8e 3151 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
ebrus 0:6bc4ac881c8e 3152 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
ebrus 0:6bc4ac881c8e 3153 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
ebrus 0:6bc4ac881c8e 3154 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
ebrus 0:6bc4ac881c8e 3155 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
ebrus 0:6bc4ac881c8e 3156 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
ebrus 0:6bc4ac881c8e 3157 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
ebrus 0:6bc4ac881c8e 3158 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
ebrus 0:6bc4ac881c8e 3159 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
ebrus 0:6bc4ac881c8e 3160 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
ebrus 0:6bc4ac881c8e 3161 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
ebrus 0:6bc4ac881c8e 3162 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
ebrus 0:6bc4ac881c8e 3163 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
ebrus 0:6bc4ac881c8e 3164 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
ebrus 0:6bc4ac881c8e 3165 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
ebrus 0:6bc4ac881c8e 3166 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
ebrus 0:6bc4ac881c8e 3167
ebrus 0:6bc4ac881c8e 3168 /******************* Bit definition for EXTI_EMR register *******************/
ebrus 0:6bc4ac881c8e 3169 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
ebrus 0:6bc4ac881c8e 3170 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
ebrus 0:6bc4ac881c8e 3171 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
ebrus 0:6bc4ac881c8e 3172 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
ebrus 0:6bc4ac881c8e 3173 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
ebrus 0:6bc4ac881c8e 3174 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
ebrus 0:6bc4ac881c8e 3175 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
ebrus 0:6bc4ac881c8e 3176 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
ebrus 0:6bc4ac881c8e 3177 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
ebrus 0:6bc4ac881c8e 3178 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
ebrus 0:6bc4ac881c8e 3179 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
ebrus 0:6bc4ac881c8e 3180 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
ebrus 0:6bc4ac881c8e 3181 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
ebrus 0:6bc4ac881c8e 3182 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
ebrus 0:6bc4ac881c8e 3183 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
ebrus 0:6bc4ac881c8e 3184 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
ebrus 0:6bc4ac881c8e 3185 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
ebrus 0:6bc4ac881c8e 3186 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
ebrus 0:6bc4ac881c8e 3187 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
ebrus 0:6bc4ac881c8e 3188 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
ebrus 0:6bc4ac881c8e 3189
ebrus 0:6bc4ac881c8e 3190 /****************** Bit definition for EXTI_RTSR register *******************/
ebrus 0:6bc4ac881c8e 3191 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
ebrus 0:6bc4ac881c8e 3192 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
ebrus 0:6bc4ac881c8e 3193 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
ebrus 0:6bc4ac881c8e 3194 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
ebrus 0:6bc4ac881c8e 3195 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
ebrus 0:6bc4ac881c8e 3196 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
ebrus 0:6bc4ac881c8e 3197 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
ebrus 0:6bc4ac881c8e 3198 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
ebrus 0:6bc4ac881c8e 3199 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
ebrus 0:6bc4ac881c8e 3200 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
ebrus 0:6bc4ac881c8e 3201 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
ebrus 0:6bc4ac881c8e 3202 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
ebrus 0:6bc4ac881c8e 3203 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
ebrus 0:6bc4ac881c8e 3204 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
ebrus 0:6bc4ac881c8e 3205 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
ebrus 0:6bc4ac881c8e 3206 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
ebrus 0:6bc4ac881c8e 3207 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
ebrus 0:6bc4ac881c8e 3208 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
ebrus 0:6bc4ac881c8e 3209 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
ebrus 0:6bc4ac881c8e 3210 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
ebrus 0:6bc4ac881c8e 3211
ebrus 0:6bc4ac881c8e 3212 /****************** Bit definition for EXTI_FTSR register *******************/
ebrus 0:6bc4ac881c8e 3213 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
ebrus 0:6bc4ac881c8e 3214 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
ebrus 0:6bc4ac881c8e 3215 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
ebrus 0:6bc4ac881c8e 3216 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
ebrus 0:6bc4ac881c8e 3217 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
ebrus 0:6bc4ac881c8e 3218 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
ebrus 0:6bc4ac881c8e 3219 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
ebrus 0:6bc4ac881c8e 3220 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
ebrus 0:6bc4ac881c8e 3221 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
ebrus 0:6bc4ac881c8e 3222 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
ebrus 0:6bc4ac881c8e 3223 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
ebrus 0:6bc4ac881c8e 3224 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
ebrus 0:6bc4ac881c8e 3225 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
ebrus 0:6bc4ac881c8e 3226 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
ebrus 0:6bc4ac881c8e 3227 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
ebrus 0:6bc4ac881c8e 3228 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
ebrus 0:6bc4ac881c8e 3229 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
ebrus 0:6bc4ac881c8e 3230 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
ebrus 0:6bc4ac881c8e 3231 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
ebrus 0:6bc4ac881c8e 3232 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
ebrus 0:6bc4ac881c8e 3233
ebrus 0:6bc4ac881c8e 3234 /****************** Bit definition for EXTI_SWIER register ******************/
ebrus 0:6bc4ac881c8e 3235 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
ebrus 0:6bc4ac881c8e 3236 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
ebrus 0:6bc4ac881c8e 3237 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
ebrus 0:6bc4ac881c8e 3238 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
ebrus 0:6bc4ac881c8e 3239 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
ebrus 0:6bc4ac881c8e 3240 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
ebrus 0:6bc4ac881c8e 3241 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
ebrus 0:6bc4ac881c8e 3242 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
ebrus 0:6bc4ac881c8e 3243 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
ebrus 0:6bc4ac881c8e 3244 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
ebrus 0:6bc4ac881c8e 3245 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
ebrus 0:6bc4ac881c8e 3246 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
ebrus 0:6bc4ac881c8e 3247 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
ebrus 0:6bc4ac881c8e 3248 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
ebrus 0:6bc4ac881c8e 3249 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
ebrus 0:6bc4ac881c8e 3250 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
ebrus 0:6bc4ac881c8e 3251 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
ebrus 0:6bc4ac881c8e 3252 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
ebrus 0:6bc4ac881c8e 3253 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
ebrus 0:6bc4ac881c8e 3254 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
ebrus 0:6bc4ac881c8e 3255
ebrus 0:6bc4ac881c8e 3256 /******************* Bit definition for EXTI_PR register ********************/
ebrus 0:6bc4ac881c8e 3257 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
ebrus 0:6bc4ac881c8e 3258 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
ebrus 0:6bc4ac881c8e 3259 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
ebrus 0:6bc4ac881c8e 3260 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
ebrus 0:6bc4ac881c8e 3261 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
ebrus 0:6bc4ac881c8e 3262 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
ebrus 0:6bc4ac881c8e 3263 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
ebrus 0:6bc4ac881c8e 3264 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
ebrus 0:6bc4ac881c8e 3265 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
ebrus 0:6bc4ac881c8e 3266 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
ebrus 0:6bc4ac881c8e 3267 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
ebrus 0:6bc4ac881c8e 3268 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
ebrus 0:6bc4ac881c8e 3269 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
ebrus 0:6bc4ac881c8e 3270 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
ebrus 0:6bc4ac881c8e 3271 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
ebrus 0:6bc4ac881c8e 3272 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
ebrus 0:6bc4ac881c8e 3273 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
ebrus 0:6bc4ac881c8e 3274 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
ebrus 0:6bc4ac881c8e 3275 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
ebrus 0:6bc4ac881c8e 3276 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
ebrus 0:6bc4ac881c8e 3277
ebrus 0:6bc4ac881c8e 3278 /******************************************************************************/
ebrus 0:6bc4ac881c8e 3279 /* */
ebrus 0:6bc4ac881c8e 3280 /* FLASH */
ebrus 0:6bc4ac881c8e 3281 /* */
ebrus 0:6bc4ac881c8e 3282 /******************************************************************************/
ebrus 0:6bc4ac881c8e 3283 /******************* Bits definition for FLASH_ACR register *****************/
ebrus 0:6bc4ac881c8e 3284 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 3285 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
ebrus 0:6bc4ac881c8e 3286 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3287 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3288 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
ebrus 0:6bc4ac881c8e 3289 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3290 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
ebrus 0:6bc4ac881c8e 3291 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
ebrus 0:6bc4ac881c8e 3292 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
ebrus 0:6bc4ac881c8e 3293
ebrus 0:6bc4ac881c8e 3294 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3295 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3296 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3297 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3298 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 3299 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
ebrus 0:6bc4ac881c8e 3300 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
ebrus 0:6bc4ac881c8e 3301
ebrus 0:6bc4ac881c8e 3302 /******************* Bits definition for FLASH_SR register ******************/
ebrus 0:6bc4ac881c8e 3303 #define FLASH_SR_EOP ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3304 #define FLASH_SR_SOP ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3305 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3306 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3307 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3308 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 3309 #define FLASH_SR_BSY ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3310
ebrus 0:6bc4ac881c8e 3311 /******************* Bits definition for FLASH_CR register ******************/
ebrus 0:6bc4ac881c8e 3312 #define FLASH_CR_PG ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3313 #define FLASH_CR_SER ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3314 #define FLASH_CR_MER ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3315 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
ebrus 0:6bc4ac881c8e 3316 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3317 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 3318 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3319 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3320 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 3321 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
ebrus 0:6bc4ac881c8e 3322 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3323 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3324 #define FLASH_CR_STRT ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3325 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3326 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 3327
ebrus 0:6bc4ac881c8e 3328 /******************* Bits definition for FLASH_OPTCR register ***************/
ebrus 0:6bc4ac881c8e 3329 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 3330 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 3331 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 3332 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 3333 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
ebrus 0:6bc4ac881c8e 3334
ebrus 0:6bc4ac881c8e 3335 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 3336 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 3337 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 3338 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
ebrus 0:6bc4ac881c8e 3339 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 3340 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 3341 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 3342 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 3343 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 3344 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 3345 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 3346 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 3347 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
ebrus 0:6bc4ac881c8e 3348 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3349 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 3350 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 3351 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 3352 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 3353 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 3354 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 3355 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 3356 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3357 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 3358 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 3359 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 3360
ebrus 0:6bc4ac881c8e 3361 /****************** Bits definition for FLASH_OPTCR1 register ***************/
ebrus 0:6bc4ac881c8e 3362 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
ebrus 0:6bc4ac881c8e 3363 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 3364 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 3365 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 3366 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 3367 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 3368 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 3369 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 3370 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 3371 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 3372 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 3373 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 3374 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 3375
ebrus 0:6bc4ac881c8e 3376 /******************************************************************************/
ebrus 0:6bc4ac881c8e 3377 /* */
ebrus 0:6bc4ac881c8e 3378 /* Flexible Static Memory Controller */
ebrus 0:6bc4ac881c8e 3379 /* */
ebrus 0:6bc4ac881c8e 3380 /******************************************************************************/
ebrus 0:6bc4ac881c8e 3381 /****************** Bit definition for FSMC_BCR1 register *******************/
ebrus 0:6bc4ac881c8e 3382 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:6bc4ac881c8e 3383 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:6bc4ac881c8e 3384
ebrus 0:6bc4ac881c8e 3385 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:6bc4ac881c8e 3386 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3387 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3388
ebrus 0:6bc4ac881c8e 3389 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:6bc4ac881c8e 3390 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3391 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3392
ebrus 0:6bc4ac881c8e 3393 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:6bc4ac881c8e 3394 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:6bc4ac881c8e 3395 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:6bc4ac881c8e 3396 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:6bc4ac881c8e 3397 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:6bc4ac881c8e 3398 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:6bc4ac881c8e 3399 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:6bc4ac881c8e 3400 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:6bc4ac881c8e 3401 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:6bc4ac881c8e 3402 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:6bc4ac881c8e 3403
ebrus 0:6bc4ac881c8e 3404 /****************** Bit definition for FSMC_BCR2 register *******************/
ebrus 0:6bc4ac881c8e 3405 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:6bc4ac881c8e 3406 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:6bc4ac881c8e 3407
ebrus 0:6bc4ac881c8e 3408 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:6bc4ac881c8e 3409 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3410 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3411
ebrus 0:6bc4ac881c8e 3412 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:6bc4ac881c8e 3413 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3414 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3415
ebrus 0:6bc4ac881c8e 3416 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:6bc4ac881c8e 3417 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:6bc4ac881c8e 3418 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:6bc4ac881c8e 3419 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:6bc4ac881c8e 3420 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:6bc4ac881c8e 3421 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:6bc4ac881c8e 3422 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:6bc4ac881c8e 3423 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:6bc4ac881c8e 3424 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:6bc4ac881c8e 3425 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:6bc4ac881c8e 3426
ebrus 0:6bc4ac881c8e 3427 /****************** Bit definition for FSMC_BCR3 register *******************/
ebrus 0:6bc4ac881c8e 3428 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:6bc4ac881c8e 3429 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:6bc4ac881c8e 3430
ebrus 0:6bc4ac881c8e 3431 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:6bc4ac881c8e 3432 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3433 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3434
ebrus 0:6bc4ac881c8e 3435 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:6bc4ac881c8e 3436 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3437 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3438
ebrus 0:6bc4ac881c8e 3439 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:6bc4ac881c8e 3440 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:6bc4ac881c8e 3441 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:6bc4ac881c8e 3442 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:6bc4ac881c8e 3443 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:6bc4ac881c8e 3444 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:6bc4ac881c8e 3445 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:6bc4ac881c8e 3446 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:6bc4ac881c8e 3447 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:6bc4ac881c8e 3448 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:6bc4ac881c8e 3449
ebrus 0:6bc4ac881c8e 3450 /****************** Bit definition for FSMC_BCR4 register *******************/
ebrus 0:6bc4ac881c8e 3451 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
ebrus 0:6bc4ac881c8e 3452 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
ebrus 0:6bc4ac881c8e 3453
ebrus 0:6bc4ac881c8e 3454 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
ebrus 0:6bc4ac881c8e 3455 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3456 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3457
ebrus 0:6bc4ac881c8e 3458 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
ebrus 0:6bc4ac881c8e 3459 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3460 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3461
ebrus 0:6bc4ac881c8e 3462 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
ebrus 0:6bc4ac881c8e 3463 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
ebrus 0:6bc4ac881c8e 3464 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
ebrus 0:6bc4ac881c8e 3465 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
ebrus 0:6bc4ac881c8e 3466 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
ebrus 0:6bc4ac881c8e 3467 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
ebrus 0:6bc4ac881c8e 3468 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
ebrus 0:6bc4ac881c8e 3469 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
ebrus 0:6bc4ac881c8e 3470 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
ebrus 0:6bc4ac881c8e 3471 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
ebrus 0:6bc4ac881c8e 3472
ebrus 0:6bc4ac881c8e 3473 /****************** Bit definition for FSMC_BTR1 register ******************/
ebrus 0:6bc4ac881c8e 3474 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3475 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3476 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3477 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3478 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3479
ebrus 0:6bc4ac881c8e 3480 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3481 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3482 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3483 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3484 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3485
ebrus 0:6bc4ac881c8e 3486 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3487 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3488 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3489 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3490 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3491
ebrus 0:6bc4ac881c8e 3492 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:6bc4ac881c8e 3493 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3494 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3495 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3496 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3497
ebrus 0:6bc4ac881c8e 3498 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3499 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3500 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3501 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3502 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3503
ebrus 0:6bc4ac881c8e 3504 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3505 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3506 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3507 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3508 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3509
ebrus 0:6bc4ac881c8e 3510 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3511 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3512 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3513
ebrus 0:6bc4ac881c8e 3514 /****************** Bit definition for FSMC_BTR2 register *******************/
ebrus 0:6bc4ac881c8e 3515 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3516 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3517 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3518 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3519 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3520
ebrus 0:6bc4ac881c8e 3521 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3522 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3523 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3524 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3525 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3526
ebrus 0:6bc4ac881c8e 3527 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3528 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3529 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3530 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3531 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3532
ebrus 0:6bc4ac881c8e 3533 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:6bc4ac881c8e 3534 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3535 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3536 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3537 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3538
ebrus 0:6bc4ac881c8e 3539 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3540 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3541 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3542 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3543 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3544
ebrus 0:6bc4ac881c8e 3545 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3546 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3547 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3548 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3549 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3550
ebrus 0:6bc4ac881c8e 3551 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3552 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3553 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3554
ebrus 0:6bc4ac881c8e 3555 /******************* Bit definition for FSMC_BTR3 register *******************/
ebrus 0:6bc4ac881c8e 3556 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3557 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3558 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3559 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3560 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3561
ebrus 0:6bc4ac881c8e 3562 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3563 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3564 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3565 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3566 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3567
ebrus 0:6bc4ac881c8e 3568 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3569 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3570 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3571 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3572 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3573
ebrus 0:6bc4ac881c8e 3574 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:6bc4ac881c8e 3575 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3576 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3577 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3578 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3579
ebrus 0:6bc4ac881c8e 3580 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3581 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3582 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3583 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3584 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3585
ebrus 0:6bc4ac881c8e 3586 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3587 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3588 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3589 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3590 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3591
ebrus 0:6bc4ac881c8e 3592 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3593 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3594 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3595
ebrus 0:6bc4ac881c8e 3596 /****************** Bit definition for FSMC_BTR4 register *******************/
ebrus 0:6bc4ac881c8e 3597 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3598 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3599 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3600 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3601 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3602
ebrus 0:6bc4ac881c8e 3603 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3604 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3605 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3606 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3607 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3608
ebrus 0:6bc4ac881c8e 3609 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3610 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3611 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3612 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3613 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3614
ebrus 0:6bc4ac881c8e 3615 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
ebrus 0:6bc4ac881c8e 3616 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3617 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3618 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3619 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3620
ebrus 0:6bc4ac881c8e 3621 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3622 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3623 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3624 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3625 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3626
ebrus 0:6bc4ac881c8e 3627 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3628 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3629 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3630 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3631 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3632
ebrus 0:6bc4ac881c8e 3633 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3634 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3635 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3636
ebrus 0:6bc4ac881c8e 3637 /****************** Bit definition for FSMC_BWTR1 register ******************/
ebrus 0:6bc4ac881c8e 3638 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3639 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3640 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3641 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3642 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3643
ebrus 0:6bc4ac881c8e 3644 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3645 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3646 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3647 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3648 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3649
ebrus 0:6bc4ac881c8e 3650 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3651 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3652 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3653 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3654 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3655
ebrus 0:6bc4ac881c8e 3656 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3657 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3658 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3659 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3660 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3661
ebrus 0:6bc4ac881c8e 3662 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3663 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3664 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3665 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3666 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3667
ebrus 0:6bc4ac881c8e 3668 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3669 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3670 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3671
ebrus 0:6bc4ac881c8e 3672 /****************** Bit definition for FSMC_BWTR2 register ******************/
ebrus 0:6bc4ac881c8e 3673 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3674 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3675 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3676 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3677 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3678
ebrus 0:6bc4ac881c8e 3679 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3680 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3681 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3682 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3683 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3684
ebrus 0:6bc4ac881c8e 3685 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3686 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3687 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3688 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3689 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3690
ebrus 0:6bc4ac881c8e 3691 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3692 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3693 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
ebrus 0:6bc4ac881c8e 3694 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3695 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3696
ebrus 0:6bc4ac881c8e 3697 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3698 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3699 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3700 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3701 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3702
ebrus 0:6bc4ac881c8e 3703 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3704 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3705 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3706
ebrus 0:6bc4ac881c8e 3707 /****************** Bit definition for FSMC_BWTR3 register ******************/
ebrus 0:6bc4ac881c8e 3708 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3709 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3710 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3711 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3712 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3713
ebrus 0:6bc4ac881c8e 3714 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3715 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3716 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3717 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3718 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3719
ebrus 0:6bc4ac881c8e 3720 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3721 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3722 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3723 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3724 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3725
ebrus 0:6bc4ac881c8e 3726 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3727 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3728 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3729 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3730 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3731
ebrus 0:6bc4ac881c8e 3732 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3733 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3734 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3735 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3736 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3737
ebrus 0:6bc4ac881c8e 3738 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3739 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3740 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3741
ebrus 0:6bc4ac881c8e 3742 /****************** Bit definition for FSMC_BWTR4 register ******************/
ebrus 0:6bc4ac881c8e 3743 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
ebrus 0:6bc4ac881c8e 3744 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3745 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3746 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3747 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3748
ebrus 0:6bc4ac881c8e 3749 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
ebrus 0:6bc4ac881c8e 3750 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3751 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3752 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3753 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3754
ebrus 0:6bc4ac881c8e 3755 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
ebrus 0:6bc4ac881c8e 3756 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3757 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3758 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3759 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3760
ebrus 0:6bc4ac881c8e 3761 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
ebrus 0:6bc4ac881c8e 3762 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3763 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3764 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3765 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3766
ebrus 0:6bc4ac881c8e 3767 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
ebrus 0:6bc4ac881c8e 3768 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3769 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3770 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3771 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3772
ebrus 0:6bc4ac881c8e 3773 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
ebrus 0:6bc4ac881c8e 3774 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3775 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3776
ebrus 0:6bc4ac881c8e 3777 /****************** Bit definition for FSMC_PCR2 register *******************/
ebrus 0:6bc4ac881c8e 3778 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
ebrus 0:6bc4ac881c8e 3779 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
ebrus 0:6bc4ac881c8e 3780 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
ebrus 0:6bc4ac881c8e 3781
ebrus 0:6bc4ac881c8e 3782 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
ebrus 0:6bc4ac881c8e 3783 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3784 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3785
ebrus 0:6bc4ac881c8e 3786 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
ebrus 0:6bc4ac881c8e 3787
ebrus 0:6bc4ac881c8e 3788 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
ebrus 0:6bc4ac881c8e 3789 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3790 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3791 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3792 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3793
ebrus 0:6bc4ac881c8e 3794 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
ebrus 0:6bc4ac881c8e 3795 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3796 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3797 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3798 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3799
ebrus 0:6bc4ac881c8e 3800 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
ebrus 0:6bc4ac881c8e 3801 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3802 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3803 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3804
ebrus 0:6bc4ac881c8e 3805 /****************** Bit definition for FSMC_PCR3 register *******************/
ebrus 0:6bc4ac881c8e 3806 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
ebrus 0:6bc4ac881c8e 3807 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
ebrus 0:6bc4ac881c8e 3808 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
ebrus 0:6bc4ac881c8e 3809
ebrus 0:6bc4ac881c8e 3810 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
ebrus 0:6bc4ac881c8e 3811 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3812 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3813
ebrus 0:6bc4ac881c8e 3814 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
ebrus 0:6bc4ac881c8e 3815
ebrus 0:6bc4ac881c8e 3816 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
ebrus 0:6bc4ac881c8e 3817 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3818 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3819 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3820 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3821
ebrus 0:6bc4ac881c8e 3822 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
ebrus 0:6bc4ac881c8e 3823 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3824 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3825 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3826 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3827
ebrus 0:6bc4ac881c8e 3828 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
ebrus 0:6bc4ac881c8e 3829 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3830 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3831 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3832
ebrus 0:6bc4ac881c8e 3833 /****************** Bit definition for FSMC_PCR4 register *******************/
ebrus 0:6bc4ac881c8e 3834 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
ebrus 0:6bc4ac881c8e 3835 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
ebrus 0:6bc4ac881c8e 3836 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
ebrus 0:6bc4ac881c8e 3837
ebrus 0:6bc4ac881c8e 3838 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
ebrus 0:6bc4ac881c8e 3839 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3840 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3841
ebrus 0:6bc4ac881c8e 3842 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
ebrus 0:6bc4ac881c8e 3843
ebrus 0:6bc4ac881c8e 3844 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
ebrus 0:6bc4ac881c8e 3845 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3846 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3847 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3848 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3849
ebrus 0:6bc4ac881c8e 3850 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
ebrus 0:6bc4ac881c8e 3851 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3852 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3853 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3854 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3855
ebrus 0:6bc4ac881c8e 3856 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
ebrus 0:6bc4ac881c8e 3857 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3858 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3859 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3860
ebrus 0:6bc4ac881c8e 3861 /******************* Bit definition for FSMC_SR2 register *******************/
ebrus 0:6bc4ac881c8e 3862 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
ebrus 0:6bc4ac881c8e 3863 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
ebrus 0:6bc4ac881c8e 3864 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
ebrus 0:6bc4ac881c8e 3865 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
ebrus 0:6bc4ac881c8e 3866 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
ebrus 0:6bc4ac881c8e 3867 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
ebrus 0:6bc4ac881c8e 3868 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
ebrus 0:6bc4ac881c8e 3869
ebrus 0:6bc4ac881c8e 3870 /******************* Bit definition for FSMC_SR3 register *******************/
ebrus 0:6bc4ac881c8e 3871 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
ebrus 0:6bc4ac881c8e 3872 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
ebrus 0:6bc4ac881c8e 3873 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
ebrus 0:6bc4ac881c8e 3874 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
ebrus 0:6bc4ac881c8e 3875 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
ebrus 0:6bc4ac881c8e 3876 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
ebrus 0:6bc4ac881c8e 3877 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
ebrus 0:6bc4ac881c8e 3878
ebrus 0:6bc4ac881c8e 3879 /******************* Bit definition for FSMC_SR4 register *******************/
ebrus 0:6bc4ac881c8e 3880 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
ebrus 0:6bc4ac881c8e 3881 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
ebrus 0:6bc4ac881c8e 3882 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
ebrus 0:6bc4ac881c8e 3883 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
ebrus 0:6bc4ac881c8e 3884 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
ebrus 0:6bc4ac881c8e 3885 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
ebrus 0:6bc4ac881c8e 3886 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
ebrus 0:6bc4ac881c8e 3887
ebrus 0:6bc4ac881c8e 3888 /****************** Bit definition for FSMC_PMEM2 register ******************/
ebrus 0:6bc4ac881c8e 3889 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
ebrus 0:6bc4ac881c8e 3890 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3891 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3892 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3893 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3894 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3895 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3896 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3897 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3898
ebrus 0:6bc4ac881c8e 3899 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
ebrus 0:6bc4ac881c8e 3900 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3901 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3902 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3903 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3904 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3905 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3906 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3907 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3908
ebrus 0:6bc4ac881c8e 3909 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
ebrus 0:6bc4ac881c8e 3910 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3911 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3912 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3913 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3914 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3915 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3916 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3917 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3918
ebrus 0:6bc4ac881c8e 3919 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
ebrus 0:6bc4ac881c8e 3920 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3921 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3922 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3923 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3924 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3925 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3926 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3927 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3928
ebrus 0:6bc4ac881c8e 3929 /****************** Bit definition for FSMC_PMEM3 register ******************/
ebrus 0:6bc4ac881c8e 3930 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
ebrus 0:6bc4ac881c8e 3931 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3932 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3933 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3934 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3935 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3936 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3937 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3938 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3939
ebrus 0:6bc4ac881c8e 3940 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
ebrus 0:6bc4ac881c8e 3941 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3942 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3943 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3944 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3945 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3946 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3947 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3948 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3949
ebrus 0:6bc4ac881c8e 3950 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
ebrus 0:6bc4ac881c8e 3951 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3952 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3953 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3954 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3955 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3956 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3957 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3958 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3959
ebrus 0:6bc4ac881c8e 3960 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
ebrus 0:6bc4ac881c8e 3961 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3962 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3963 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3964 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3965 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3966 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3967 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3968 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3969
ebrus 0:6bc4ac881c8e 3970 /****************** Bit definition for FSMC_PMEM4 register ******************/
ebrus 0:6bc4ac881c8e 3971 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
ebrus 0:6bc4ac881c8e 3972 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3973 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3974 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3975 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3976 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3977 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3978 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3979 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3980
ebrus 0:6bc4ac881c8e 3981 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
ebrus 0:6bc4ac881c8e 3982 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3983 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3984 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3985 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3986 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3987 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3988 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3989 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 3990
ebrus 0:6bc4ac881c8e 3991 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
ebrus 0:6bc4ac881c8e 3992 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 3993 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 3994 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 3995 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 3996 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 3997 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 3998 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 3999 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4000
ebrus 0:6bc4ac881c8e 4001 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
ebrus 0:6bc4ac881c8e 4002 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4003 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4004 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4005 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4006 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4007 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4008 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4009 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4010
ebrus 0:6bc4ac881c8e 4011 /****************** Bit definition for FSMC_PATT2 register ******************/
ebrus 0:6bc4ac881c8e 4012 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
ebrus 0:6bc4ac881c8e 4013 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4014 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4015 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4016 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4017 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4018 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4019 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4020 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4021
ebrus 0:6bc4ac881c8e 4022 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
ebrus 0:6bc4ac881c8e 4023 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4024 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4025 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4026 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4027 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4028 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4029 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4030 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4031
ebrus 0:6bc4ac881c8e 4032 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
ebrus 0:6bc4ac881c8e 4033 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4034 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4035 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4036 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4037 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4038 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4039 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4040 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4041
ebrus 0:6bc4ac881c8e 4042 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
ebrus 0:6bc4ac881c8e 4043 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4044 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4045 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4046 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4047 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4048 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4049 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4050 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4051
ebrus 0:6bc4ac881c8e 4052 /****************** Bit definition for FSMC_PATT3 register ******************/
ebrus 0:6bc4ac881c8e 4053 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
ebrus 0:6bc4ac881c8e 4054 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4055 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4056 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4057 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4058 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4059 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4060 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4061 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4062
ebrus 0:6bc4ac881c8e 4063 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
ebrus 0:6bc4ac881c8e 4064 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4065 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4066 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4067 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4068 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4069 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4070 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4071 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4072
ebrus 0:6bc4ac881c8e 4073 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
ebrus 0:6bc4ac881c8e 4074 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4075 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4076 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4077 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4078 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4079 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4080 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4081 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4082
ebrus 0:6bc4ac881c8e 4083 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
ebrus 0:6bc4ac881c8e 4084 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4085 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4086 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4087 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4088 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4089 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4090 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4091 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4092
ebrus 0:6bc4ac881c8e 4093 /****************** Bit definition for FSMC_PATT4 register ******************/
ebrus 0:6bc4ac881c8e 4094 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
ebrus 0:6bc4ac881c8e 4095 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4096 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4097 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4098 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4099 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4100 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4101 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4102 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4103
ebrus 0:6bc4ac881c8e 4104 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
ebrus 0:6bc4ac881c8e 4105 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4106 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4107 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4108 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4109 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4110 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4111 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4112 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4113
ebrus 0:6bc4ac881c8e 4114 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
ebrus 0:6bc4ac881c8e 4115 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4116 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4117 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4118 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4119 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4120 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4121 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4122 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4123
ebrus 0:6bc4ac881c8e 4124 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
ebrus 0:6bc4ac881c8e 4125 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4126 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4127 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4128 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4129 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4130 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4131 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4132 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4133
ebrus 0:6bc4ac881c8e 4134 /****************** Bit definition for FSMC_PIO4 register *******************/
ebrus 0:6bc4ac881c8e 4135 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
ebrus 0:6bc4ac881c8e 4136 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4137 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4138 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4139 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4140 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4141 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4142 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4143 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4144
ebrus 0:6bc4ac881c8e 4145 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
ebrus 0:6bc4ac881c8e 4146 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4147 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4148 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4149 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4150 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4151 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4152 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4153 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4154
ebrus 0:6bc4ac881c8e 4155 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
ebrus 0:6bc4ac881c8e 4156 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4157 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4158 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4159 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4160 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4161 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4162 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4163 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4164
ebrus 0:6bc4ac881c8e 4165 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
ebrus 0:6bc4ac881c8e 4166 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4167 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4168 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4169 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4170 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4171 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4172 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4173 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4174
ebrus 0:6bc4ac881c8e 4175 /****************** Bit definition for FSMC_ECCR2 register ******************/
ebrus 0:6bc4ac881c8e 4176 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
ebrus 0:6bc4ac881c8e 4177
ebrus 0:6bc4ac881c8e 4178 /****************** Bit definition for FSMC_ECCR3 register ******************/
ebrus 0:6bc4ac881c8e 4179 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
ebrus 0:6bc4ac881c8e 4180
ebrus 0:6bc4ac881c8e 4181 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4182 /* */
ebrus 0:6bc4ac881c8e 4183 /* General Purpose I/O */
ebrus 0:6bc4ac881c8e 4184 /* */
ebrus 0:6bc4ac881c8e 4185 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4186 /****************** Bits definition for GPIO_MODER register *****************/
ebrus 0:6bc4ac881c8e 4187 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
ebrus 0:6bc4ac881c8e 4188 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4189 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4190
ebrus 0:6bc4ac881c8e 4191 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
ebrus 0:6bc4ac881c8e 4192 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4193 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4194
ebrus 0:6bc4ac881c8e 4195 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
ebrus 0:6bc4ac881c8e 4196 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4197 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4198
ebrus 0:6bc4ac881c8e 4199 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
ebrus 0:6bc4ac881c8e 4200 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4201 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4202
ebrus 0:6bc4ac881c8e 4203 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
ebrus 0:6bc4ac881c8e 4204 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4205 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4206
ebrus 0:6bc4ac881c8e 4207 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
ebrus 0:6bc4ac881c8e 4208 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4209 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4210
ebrus 0:6bc4ac881c8e 4211 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
ebrus 0:6bc4ac881c8e 4212 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4213 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4214
ebrus 0:6bc4ac881c8e 4215 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
ebrus 0:6bc4ac881c8e 4216 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4217 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4218
ebrus 0:6bc4ac881c8e 4219 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
ebrus 0:6bc4ac881c8e 4220 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4221 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4222
ebrus 0:6bc4ac881c8e 4223 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
ebrus 0:6bc4ac881c8e 4224 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4225 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4226
ebrus 0:6bc4ac881c8e 4227 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 4228 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4229 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4230
ebrus 0:6bc4ac881c8e 4231 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
ebrus 0:6bc4ac881c8e 4232 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4233 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4234
ebrus 0:6bc4ac881c8e 4235 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
ebrus 0:6bc4ac881c8e 4236 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4237 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4238
ebrus 0:6bc4ac881c8e 4239 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
ebrus 0:6bc4ac881c8e 4240 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4241 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4242
ebrus 0:6bc4ac881c8e 4243 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
ebrus 0:6bc4ac881c8e 4244 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4245 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4246
ebrus 0:6bc4ac881c8e 4247 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
ebrus 0:6bc4ac881c8e 4248 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 4249 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 4250
ebrus 0:6bc4ac881c8e 4251 /****************** Bits definition for GPIO_OTYPER register ****************/
ebrus 0:6bc4ac881c8e 4252 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4253 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4254 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4255 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4256 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4257 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4258 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4259 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4260 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4261 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4262 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4263 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4264 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4265 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4266 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4267 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4268
ebrus 0:6bc4ac881c8e 4269 /****************** Bits definition for GPIO_OSPEEDR register ***************/
ebrus 0:6bc4ac881c8e 4270 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
ebrus 0:6bc4ac881c8e 4271 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4272 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4273
ebrus 0:6bc4ac881c8e 4274 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
ebrus 0:6bc4ac881c8e 4275 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4276 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4277
ebrus 0:6bc4ac881c8e 4278 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
ebrus 0:6bc4ac881c8e 4279 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4280 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4281
ebrus 0:6bc4ac881c8e 4282 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
ebrus 0:6bc4ac881c8e 4283 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4284 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4285
ebrus 0:6bc4ac881c8e 4286 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
ebrus 0:6bc4ac881c8e 4287 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4288 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4289
ebrus 0:6bc4ac881c8e 4290 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
ebrus 0:6bc4ac881c8e 4291 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4292 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4293
ebrus 0:6bc4ac881c8e 4294 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
ebrus 0:6bc4ac881c8e 4295 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4296 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4297
ebrus 0:6bc4ac881c8e 4298 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
ebrus 0:6bc4ac881c8e 4299 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4300 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4301
ebrus 0:6bc4ac881c8e 4302 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
ebrus 0:6bc4ac881c8e 4303 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4304 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4305
ebrus 0:6bc4ac881c8e 4306 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
ebrus 0:6bc4ac881c8e 4307 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4308 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4309
ebrus 0:6bc4ac881c8e 4310 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 4311 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4312 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4313
ebrus 0:6bc4ac881c8e 4314 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
ebrus 0:6bc4ac881c8e 4315 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4316 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4317
ebrus 0:6bc4ac881c8e 4318 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
ebrus 0:6bc4ac881c8e 4319 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4320 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4321
ebrus 0:6bc4ac881c8e 4322 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
ebrus 0:6bc4ac881c8e 4323 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4324 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4325
ebrus 0:6bc4ac881c8e 4326 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
ebrus 0:6bc4ac881c8e 4327 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4328 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4329
ebrus 0:6bc4ac881c8e 4330 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
ebrus 0:6bc4ac881c8e 4331 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 4332 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 4333
ebrus 0:6bc4ac881c8e 4334 /****************** Bits definition for GPIO_PUPDR register *****************/
ebrus 0:6bc4ac881c8e 4335 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
ebrus 0:6bc4ac881c8e 4336 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4337 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4338
ebrus 0:6bc4ac881c8e 4339 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
ebrus 0:6bc4ac881c8e 4340 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4341 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4342
ebrus 0:6bc4ac881c8e 4343 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
ebrus 0:6bc4ac881c8e 4344 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4345 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4346
ebrus 0:6bc4ac881c8e 4347 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
ebrus 0:6bc4ac881c8e 4348 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4349 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4350
ebrus 0:6bc4ac881c8e 4351 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
ebrus 0:6bc4ac881c8e 4352 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4353 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4354
ebrus 0:6bc4ac881c8e 4355 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
ebrus 0:6bc4ac881c8e 4356 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4357 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4358
ebrus 0:6bc4ac881c8e 4359 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
ebrus 0:6bc4ac881c8e 4360 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4361 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4362
ebrus 0:6bc4ac881c8e 4363 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
ebrus 0:6bc4ac881c8e 4364 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4365 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4366
ebrus 0:6bc4ac881c8e 4367 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
ebrus 0:6bc4ac881c8e 4368 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4369 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4370
ebrus 0:6bc4ac881c8e 4371 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
ebrus 0:6bc4ac881c8e 4372 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4373 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4374
ebrus 0:6bc4ac881c8e 4375 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 4376 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4377 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4378
ebrus 0:6bc4ac881c8e 4379 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
ebrus 0:6bc4ac881c8e 4380 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4381 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4382
ebrus 0:6bc4ac881c8e 4383 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
ebrus 0:6bc4ac881c8e 4384 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4385 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4386
ebrus 0:6bc4ac881c8e 4387 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
ebrus 0:6bc4ac881c8e 4388 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4389 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4390
ebrus 0:6bc4ac881c8e 4391 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
ebrus 0:6bc4ac881c8e 4392 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4393 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4394
ebrus 0:6bc4ac881c8e 4395 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
ebrus 0:6bc4ac881c8e 4396 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 4397 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 4398
ebrus 0:6bc4ac881c8e 4399 /****************** Bits definition for GPIO_IDR register *******************/
ebrus 0:6bc4ac881c8e 4400 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4401 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4402 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4403 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4404 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4405 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4406 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4407 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4408 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4409 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4410 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4411 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4412 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4413 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4414 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4415 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4416 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
ebrus 0:6bc4ac881c8e 4417 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
ebrus 0:6bc4ac881c8e 4418 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
ebrus 0:6bc4ac881c8e 4419 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
ebrus 0:6bc4ac881c8e 4420 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
ebrus 0:6bc4ac881c8e 4421 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
ebrus 0:6bc4ac881c8e 4422 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
ebrus 0:6bc4ac881c8e 4423 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
ebrus 0:6bc4ac881c8e 4424 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
ebrus 0:6bc4ac881c8e 4425 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
ebrus 0:6bc4ac881c8e 4426 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
ebrus 0:6bc4ac881c8e 4427 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
ebrus 0:6bc4ac881c8e 4428 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
ebrus 0:6bc4ac881c8e 4429 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
ebrus 0:6bc4ac881c8e 4430 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
ebrus 0:6bc4ac881c8e 4431 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
ebrus 0:6bc4ac881c8e 4432 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
ebrus 0:6bc4ac881c8e 4433
ebrus 0:6bc4ac881c8e 4434 /****************** Bits definition for GPIO_ODR register *******************/
ebrus 0:6bc4ac881c8e 4435 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4436 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4437 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4438 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4439 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4440 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4441 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4442 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4443 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4444 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4445 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4446 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4447 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4448 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4449 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4450 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4451 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
ebrus 0:6bc4ac881c8e 4452 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
ebrus 0:6bc4ac881c8e 4453 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
ebrus 0:6bc4ac881c8e 4454 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
ebrus 0:6bc4ac881c8e 4455 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
ebrus 0:6bc4ac881c8e 4456 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
ebrus 0:6bc4ac881c8e 4457 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
ebrus 0:6bc4ac881c8e 4458 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
ebrus 0:6bc4ac881c8e 4459 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
ebrus 0:6bc4ac881c8e 4460 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
ebrus 0:6bc4ac881c8e 4461 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
ebrus 0:6bc4ac881c8e 4462 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
ebrus 0:6bc4ac881c8e 4463 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
ebrus 0:6bc4ac881c8e 4464 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
ebrus 0:6bc4ac881c8e 4465 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
ebrus 0:6bc4ac881c8e 4466 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
ebrus 0:6bc4ac881c8e 4467 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
ebrus 0:6bc4ac881c8e 4468
ebrus 0:6bc4ac881c8e 4469 /****************** Bits definition for GPIO_BSRR register ******************/
ebrus 0:6bc4ac881c8e 4470 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4471 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4472 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4473 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4474 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4475 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4476 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4477 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4478 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4479 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4480 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4481 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4482 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4483 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4484 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4485 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4486 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4487 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4488 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4489 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4490 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4491 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4492 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4493 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4494 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4495 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4496 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4497 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4498 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4499 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4500 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 4501 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 4502
ebrus 0:6bc4ac881c8e 4503 /****************** Bit definition for GPIO_LCKR register *********************/
ebrus 0:6bc4ac881c8e 4504 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4505 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4506 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4507 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4508 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4509 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4510 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4511 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4512 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4513 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4514 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4515 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4516 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4517 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4518 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4519 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4520 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4521
ebrus 0:6bc4ac881c8e 4522 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4523 /* */
ebrus 0:6bc4ac881c8e 4524 /* Inter-integrated Circuit Interface */
ebrus 0:6bc4ac881c8e 4525 /* */
ebrus 0:6bc4ac881c8e 4526 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4527 /******************* Bit definition for I2C_CR1 register ********************/
ebrus 0:6bc4ac881c8e 4528 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
ebrus 0:6bc4ac881c8e 4529 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
ebrus 0:6bc4ac881c8e 4530 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
ebrus 0:6bc4ac881c8e 4531 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
ebrus 0:6bc4ac881c8e 4532 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
ebrus 0:6bc4ac881c8e 4533 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
ebrus 0:6bc4ac881c8e 4534 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
ebrus 0:6bc4ac881c8e 4535 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
ebrus 0:6bc4ac881c8e 4536 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
ebrus 0:6bc4ac881c8e 4537 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
ebrus 0:6bc4ac881c8e 4538 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
ebrus 0:6bc4ac881c8e 4539 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
ebrus 0:6bc4ac881c8e 4540 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
ebrus 0:6bc4ac881c8e 4541 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
ebrus 0:6bc4ac881c8e 4542
ebrus 0:6bc4ac881c8e 4543 /******************* Bit definition for I2C_CR2 register ********************/
ebrus 0:6bc4ac881c8e 4544 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
ebrus 0:6bc4ac881c8e 4545 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4546 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4547 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4548 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4549 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4550 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4551
ebrus 0:6bc4ac881c8e 4552 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 4553 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
ebrus 0:6bc4ac881c8e 4554 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
ebrus 0:6bc4ac881c8e 4555 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
ebrus 0:6bc4ac881c8e 4556 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
ebrus 0:6bc4ac881c8e 4557
ebrus 0:6bc4ac881c8e 4558 /******************* Bit definition for I2C_OAR1 register *******************/
ebrus 0:6bc4ac881c8e 4559 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
ebrus 0:6bc4ac881c8e 4560 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
ebrus 0:6bc4ac881c8e 4561
ebrus 0:6bc4ac881c8e 4562 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4563 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4564 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4565 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4566 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4567 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4568 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4569 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4570 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
ebrus 0:6bc4ac881c8e 4571 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
ebrus 0:6bc4ac881c8e 4572
ebrus 0:6bc4ac881c8e 4573 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
ebrus 0:6bc4ac881c8e 4574
ebrus 0:6bc4ac881c8e 4575 /******************* Bit definition for I2C_OAR2 register *******************/
ebrus 0:6bc4ac881c8e 4576 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
ebrus 0:6bc4ac881c8e 4577 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
ebrus 0:6bc4ac881c8e 4578
ebrus 0:6bc4ac881c8e 4579 /******************** Bit definition for I2C_DR register ********************/
ebrus 0:6bc4ac881c8e 4580 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
ebrus 0:6bc4ac881c8e 4581
ebrus 0:6bc4ac881c8e 4582 /******************* Bit definition for I2C_SR1 register ********************/
ebrus 0:6bc4ac881c8e 4583 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
ebrus 0:6bc4ac881c8e 4584 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
ebrus 0:6bc4ac881c8e 4585 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
ebrus 0:6bc4ac881c8e 4586 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
ebrus 0:6bc4ac881c8e 4587 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
ebrus 0:6bc4ac881c8e 4588 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
ebrus 0:6bc4ac881c8e 4589 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
ebrus 0:6bc4ac881c8e 4590 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
ebrus 0:6bc4ac881c8e 4591 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
ebrus 0:6bc4ac881c8e 4592 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
ebrus 0:6bc4ac881c8e 4593 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
ebrus 0:6bc4ac881c8e 4594 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
ebrus 0:6bc4ac881c8e 4595 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
ebrus 0:6bc4ac881c8e 4596 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
ebrus 0:6bc4ac881c8e 4597
ebrus 0:6bc4ac881c8e 4598 /******************* Bit definition for I2C_SR2 register ********************/
ebrus 0:6bc4ac881c8e 4599 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
ebrus 0:6bc4ac881c8e 4600 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
ebrus 0:6bc4ac881c8e 4601 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
ebrus 0:6bc4ac881c8e 4602 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
ebrus 0:6bc4ac881c8e 4603 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
ebrus 0:6bc4ac881c8e 4604 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
ebrus 0:6bc4ac881c8e 4605 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
ebrus 0:6bc4ac881c8e 4606 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
ebrus 0:6bc4ac881c8e 4607
ebrus 0:6bc4ac881c8e 4608 /******************* Bit definition for I2C_CCR register ********************/
ebrus 0:6bc4ac881c8e 4609 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
ebrus 0:6bc4ac881c8e 4610 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
ebrus 0:6bc4ac881c8e 4611 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
ebrus 0:6bc4ac881c8e 4612
ebrus 0:6bc4ac881c8e 4613 /****************** Bit definition for I2C_TRISE register *******************/
ebrus 0:6bc4ac881c8e 4614 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
ebrus 0:6bc4ac881c8e 4615
ebrus 0:6bc4ac881c8e 4616 /****************** Bit definition for I2C_FLTR register *******************/
ebrus 0:6bc4ac881c8e 4617 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
ebrus 0:6bc4ac881c8e 4618 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
ebrus 0:6bc4ac881c8e 4619
ebrus 0:6bc4ac881c8e 4620 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4621 /* */
ebrus 0:6bc4ac881c8e 4622 /* Independent WATCHDOG */
ebrus 0:6bc4ac881c8e 4623 /* */
ebrus 0:6bc4ac881c8e 4624 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4625 /******************* Bit definition for IWDG_KR register ********************/
ebrus 0:6bc4ac881c8e 4626 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
ebrus 0:6bc4ac881c8e 4627
ebrus 0:6bc4ac881c8e 4628 /******************* Bit definition for IWDG_PR register ********************/
ebrus 0:6bc4ac881c8e 4629 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
ebrus 0:6bc4ac881c8e 4630 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4631 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4632 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4633
ebrus 0:6bc4ac881c8e 4634 /******************* Bit definition for IWDG_RLR register *******************/
ebrus 0:6bc4ac881c8e 4635 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
ebrus 0:6bc4ac881c8e 4636
ebrus 0:6bc4ac881c8e 4637 /******************* Bit definition for IWDG_SR register ********************/
ebrus 0:6bc4ac881c8e 4638 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
ebrus 0:6bc4ac881c8e 4639 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
ebrus 0:6bc4ac881c8e 4640
ebrus 0:6bc4ac881c8e 4641
ebrus 0:6bc4ac881c8e 4642 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4643 /* */
ebrus 0:6bc4ac881c8e 4644 /* Power Control */
ebrus 0:6bc4ac881c8e 4645 /* */
ebrus 0:6bc4ac881c8e 4646 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4647 /******************** Bit definition for PWR_CR register ********************/
ebrus 0:6bc4ac881c8e 4648 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
ebrus 0:6bc4ac881c8e 4649 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
ebrus 0:6bc4ac881c8e 4650 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
ebrus 0:6bc4ac881c8e 4651 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
ebrus 0:6bc4ac881c8e 4652 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
ebrus 0:6bc4ac881c8e 4653
ebrus 0:6bc4ac881c8e 4654 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
ebrus 0:6bc4ac881c8e 4655 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4656 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4657 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
ebrus 0:6bc4ac881c8e 4658
ebrus 0:6bc4ac881c8e 4659 /*!< PVD level configuration */
ebrus 0:6bc4ac881c8e 4660 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
ebrus 0:6bc4ac881c8e 4661 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
ebrus 0:6bc4ac881c8e 4662 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
ebrus 0:6bc4ac881c8e 4663 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
ebrus 0:6bc4ac881c8e 4664 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
ebrus 0:6bc4ac881c8e 4665 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
ebrus 0:6bc4ac881c8e 4666 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
ebrus 0:6bc4ac881c8e 4667 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
ebrus 0:6bc4ac881c8e 4668
ebrus 0:6bc4ac881c8e 4669 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
ebrus 0:6bc4ac881c8e 4670 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
ebrus 0:6bc4ac881c8e 4671 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
ebrus 0:6bc4ac881c8e 4672 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4673 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4674
ebrus 0:6bc4ac881c8e 4675 /* Legacy define */
ebrus 0:6bc4ac881c8e 4676 #define PWR_CR_PMODE PWR_CR_VOS
ebrus 0:6bc4ac881c8e 4677
ebrus 0:6bc4ac881c8e 4678 /******************* Bit definition for PWR_CSR register ********************/
ebrus 0:6bc4ac881c8e 4679 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
ebrus 0:6bc4ac881c8e 4680 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
ebrus 0:6bc4ac881c8e 4681 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
ebrus 0:6bc4ac881c8e 4682 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
ebrus 0:6bc4ac881c8e 4683 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
ebrus 0:6bc4ac881c8e 4684 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
ebrus 0:6bc4ac881c8e 4685 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
ebrus 0:6bc4ac881c8e 4686
ebrus 0:6bc4ac881c8e 4687 /* Legacy define */
ebrus 0:6bc4ac881c8e 4688 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
ebrus 0:6bc4ac881c8e 4689
ebrus 0:6bc4ac881c8e 4690 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4691 /* */
ebrus 0:6bc4ac881c8e 4692 /* Reset and Clock Control */
ebrus 0:6bc4ac881c8e 4693 /* */
ebrus 0:6bc4ac881c8e 4694 /******************************************************************************/
ebrus 0:6bc4ac881c8e 4695 /******************** Bit definition for RCC_CR register ********************/
ebrus 0:6bc4ac881c8e 4696 #define RCC_CR_HSION ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4697 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4698
ebrus 0:6bc4ac881c8e 4699 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
ebrus 0:6bc4ac881c8e 4700 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4701 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4702 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4703 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4704 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4705
ebrus 0:6bc4ac881c8e 4706 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
ebrus 0:6bc4ac881c8e 4707 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
ebrus 0:6bc4ac881c8e 4708 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
ebrus 0:6bc4ac881c8e 4709 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
ebrus 0:6bc4ac881c8e 4710 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
ebrus 0:6bc4ac881c8e 4711 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
ebrus 0:6bc4ac881c8e 4712 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
ebrus 0:6bc4ac881c8e 4713 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
ebrus 0:6bc4ac881c8e 4714 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
ebrus 0:6bc4ac881c8e 4715
ebrus 0:6bc4ac881c8e 4716 #define RCC_CR_HSEON ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4717 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4718 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4719 #define RCC_CR_CSSON ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4720 #define RCC_CR_PLLON ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4721 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4722 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4723 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4724
ebrus 0:6bc4ac881c8e 4725 /******************** Bit definition for RCC_PLLCFGR register ***************/
ebrus 0:6bc4ac881c8e 4726 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
ebrus 0:6bc4ac881c8e 4727 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4728 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4729 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4730 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4731 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4732 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4733
ebrus 0:6bc4ac881c8e 4734 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
ebrus 0:6bc4ac881c8e 4735 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4736 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4737 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4738 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4739 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4740 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4741 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4742 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4743 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4744
ebrus 0:6bc4ac881c8e 4745 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
ebrus 0:6bc4ac881c8e 4746 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4747 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4748
ebrus 0:6bc4ac881c8e 4749 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4750 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4751 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
ebrus 0:6bc4ac881c8e 4752
ebrus 0:6bc4ac881c8e 4753 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
ebrus 0:6bc4ac881c8e 4754 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4755 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4756 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4757 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4758
ebrus 0:6bc4ac881c8e 4759 /******************** Bit definition for RCC_CFGR register ******************/
ebrus 0:6bc4ac881c8e 4760 /*!< SW configuration */
ebrus 0:6bc4ac881c8e 4761 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
ebrus 0:6bc4ac881c8e 4762 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4763 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4764
ebrus 0:6bc4ac881c8e 4765 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
ebrus 0:6bc4ac881c8e 4766 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
ebrus 0:6bc4ac881c8e 4767 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
ebrus 0:6bc4ac881c8e 4768
ebrus 0:6bc4ac881c8e 4769 /*!< SWS configuration */
ebrus 0:6bc4ac881c8e 4770 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
ebrus 0:6bc4ac881c8e 4771 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4772 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4773
ebrus 0:6bc4ac881c8e 4774 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
ebrus 0:6bc4ac881c8e 4775 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
ebrus 0:6bc4ac881c8e 4776 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
ebrus 0:6bc4ac881c8e 4777
ebrus 0:6bc4ac881c8e 4778 /*!< HPRE configuration */
ebrus 0:6bc4ac881c8e 4779 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
ebrus 0:6bc4ac881c8e 4780 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4781 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4782 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
ebrus 0:6bc4ac881c8e 4783 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
ebrus 0:6bc4ac881c8e 4784
ebrus 0:6bc4ac881c8e 4785 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
ebrus 0:6bc4ac881c8e 4786 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
ebrus 0:6bc4ac881c8e 4787 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
ebrus 0:6bc4ac881c8e 4788 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
ebrus 0:6bc4ac881c8e 4789 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
ebrus 0:6bc4ac881c8e 4790 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
ebrus 0:6bc4ac881c8e 4791 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
ebrus 0:6bc4ac881c8e 4792 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
ebrus 0:6bc4ac881c8e 4793 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
ebrus 0:6bc4ac881c8e 4794
ebrus 0:6bc4ac881c8e 4795 /*!< PPRE1 configuration */
ebrus 0:6bc4ac881c8e 4796 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
ebrus 0:6bc4ac881c8e 4797 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4798 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4799 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
ebrus 0:6bc4ac881c8e 4800
ebrus 0:6bc4ac881c8e 4801 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
ebrus 0:6bc4ac881c8e 4802 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
ebrus 0:6bc4ac881c8e 4803 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
ebrus 0:6bc4ac881c8e 4804 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
ebrus 0:6bc4ac881c8e 4805 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
ebrus 0:6bc4ac881c8e 4806
ebrus 0:6bc4ac881c8e 4807 /*!< PPRE2 configuration */
ebrus 0:6bc4ac881c8e 4808 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
ebrus 0:6bc4ac881c8e 4809 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 4810 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 4811 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
ebrus 0:6bc4ac881c8e 4812
ebrus 0:6bc4ac881c8e 4813 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
ebrus 0:6bc4ac881c8e 4814 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
ebrus 0:6bc4ac881c8e 4815 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
ebrus 0:6bc4ac881c8e 4816 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
ebrus 0:6bc4ac881c8e 4817 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
ebrus 0:6bc4ac881c8e 4818
ebrus 0:6bc4ac881c8e 4819 /*!< RTCPRE configuration */
ebrus 0:6bc4ac881c8e 4820 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
ebrus 0:6bc4ac881c8e 4821 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4822 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4823 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4824 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4825 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4826
ebrus 0:6bc4ac881c8e 4827 /*!< MCO1 configuration */
ebrus 0:6bc4ac881c8e 4828 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
ebrus 0:6bc4ac881c8e 4829 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4830 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4831
ebrus 0:6bc4ac881c8e 4832 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4833
ebrus 0:6bc4ac881c8e 4834 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
ebrus 0:6bc4ac881c8e 4835 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 4836 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4837 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4838
ebrus 0:6bc4ac881c8e 4839 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
ebrus 0:6bc4ac881c8e 4840 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4841 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4842 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4843
ebrus 0:6bc4ac881c8e 4844 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
ebrus 0:6bc4ac881c8e 4845 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 4846 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 4847
ebrus 0:6bc4ac881c8e 4848 /******************** Bit definition for RCC_CIR register *******************/
ebrus 0:6bc4ac881c8e 4849 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4850 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4851 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4852 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4853 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4854 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4855
ebrus 0:6bc4ac881c8e 4856 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4857 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4858 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 4859 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 4860 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4861 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4862 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 4863
ebrus 0:6bc4ac881c8e 4864 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4865 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4866 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4867 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4868 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4869 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4870
ebrus 0:6bc4ac881c8e 4871 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4872
ebrus 0:6bc4ac881c8e 4873 /******************** Bit definition for RCC_AHB1RSTR register **************/
ebrus 0:6bc4ac881c8e 4874 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4875 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4876 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4877 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4878 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4879 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4880 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4881 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4882 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4883 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4884 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4885 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4886 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4887 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4888
ebrus 0:6bc4ac881c8e 4889 /******************** Bit definition for RCC_AHB2RSTR register **************/
ebrus 0:6bc4ac881c8e 4890 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4891 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4892 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4893
ebrus 0:6bc4ac881c8e 4894 /******************** Bit definition for RCC_AHB3RSTR register **************/
ebrus 0:6bc4ac881c8e 4895
ebrus 0:6bc4ac881c8e 4896 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4897
ebrus 0:6bc4ac881c8e 4898 /******************** Bit definition for RCC_APB1RSTR register **************/
ebrus 0:6bc4ac881c8e 4899 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4900 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4901 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4902 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4903 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4904 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4905 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4906 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4907 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4908 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4909 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4910 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4911 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4912 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4913 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4914 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4915 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4916 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4917 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4918 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4919 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4920 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4921 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4922
ebrus 0:6bc4ac881c8e 4923 /******************** Bit definition for RCC_APB2RSTR register **************/
ebrus 0:6bc4ac881c8e 4924 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4925 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4926 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4927 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4928 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4929 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4930 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4931 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4932 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 4933 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4934 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4935
ebrus 0:6bc4ac881c8e 4936 /* Old SPI1RST bit definition, maintained for legacy purpose */
ebrus 0:6bc4ac881c8e 4937 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
ebrus 0:6bc4ac881c8e 4938
ebrus 0:6bc4ac881c8e 4939 /******************** Bit definition for RCC_AHB1ENR register ***************/
ebrus 0:6bc4ac881c8e 4940 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4941 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4942 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4943 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4944 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4945 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4946 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4947 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4948 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4949 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 4950 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4951 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4952 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4953 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4954
ebrus 0:6bc4ac881c8e 4955 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4956 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4957 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 4958 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4959 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4960 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 4961
ebrus 0:6bc4ac881c8e 4962 /******************** Bit definition for RCC_AHB2ENR register ***************/
ebrus 0:6bc4ac881c8e 4963 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4964 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4965 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4966
ebrus 0:6bc4ac881c8e 4967 /******************** Bit definition for RCC_AHB3ENR register ***************/
ebrus 0:6bc4ac881c8e 4968
ebrus 0:6bc4ac881c8e 4969 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4970
ebrus 0:6bc4ac881c8e 4971 /******************** Bit definition for RCC_APB1ENR register ***************/
ebrus 0:6bc4ac881c8e 4972 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4973 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4974 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 4975 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 4976 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 4977 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 4978 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 4979 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 4980 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 4981 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 4982 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 4983 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 4984 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 4985 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 4986 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 4987 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 4988 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 4989 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 4990 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 4991 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 4992 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 4993 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 4994 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 4995
ebrus 0:6bc4ac881c8e 4996 /******************** Bit definition for RCC_APB2ENR register ***************/
ebrus 0:6bc4ac881c8e 4997 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 4998 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 4999 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5000 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5001 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5002 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5003 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5004 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5005 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5006 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5007 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5008 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5009 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5010 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5011 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5012
ebrus 0:6bc4ac881c8e 5013 /******************** Bit definition for RCC_AHB1LPENR register *************/
ebrus 0:6bc4ac881c8e 5014 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5015 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5016 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5017 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5018 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5019 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5020 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5021 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5022 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5023 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5024 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5025 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5026 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5027 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5028 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5029 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5030 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5031 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5032 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5033 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 5034 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 5035 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 5036 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 5037
ebrus 0:6bc4ac881c8e 5038 /******************** Bit definition for RCC_AHB2LPENR register *************/
ebrus 0:6bc4ac881c8e 5039 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5040 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5041 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5042
ebrus 0:6bc4ac881c8e 5043 /******************** Bit definition for RCC_AHB3LPENR register *************/
ebrus 0:6bc4ac881c8e 5044
ebrus 0:6bc4ac881c8e 5045 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5046
ebrus 0:6bc4ac881c8e 5047 /******************** Bit definition for RCC_APB1LPENR register *************/
ebrus 0:6bc4ac881c8e 5048 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5049 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5050 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5051 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5052 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5053 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5054 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5055 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5056 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5057 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5058 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5059 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5060 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5061 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5062 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5063 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5064 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5065 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5066 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 5067 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5068 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5069 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 5070 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 5071
ebrus 0:6bc4ac881c8e 5072 /******************** Bit definition for RCC_APB2LPENR register *************/
ebrus 0:6bc4ac881c8e 5073 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5074 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5075 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5076 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5077 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5078 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5079 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5080 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5081 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5082 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5083 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5084 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5085 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5086
ebrus 0:6bc4ac881c8e 5087 /******************** Bit definition for RCC_BDCR register ******************/
ebrus 0:6bc4ac881c8e 5088 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5089 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5090 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5091
ebrus 0:6bc4ac881c8e 5092 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
ebrus 0:6bc4ac881c8e 5093 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5094 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5095
ebrus 0:6bc4ac881c8e 5096 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5097 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5098
ebrus 0:6bc4ac881c8e 5099 /******************** Bit definition for RCC_CSR register *******************/
ebrus 0:6bc4ac881c8e 5100 #define RCC_CSR_LSION ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5101 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5102 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 5103 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5104 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5105 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 5106 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 5107 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 5108 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 5109 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 5110
ebrus 0:6bc4ac881c8e 5111 /******************** Bit definition for RCC_SSCGR register *****************/
ebrus 0:6bc4ac881c8e 5112 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
ebrus 0:6bc4ac881c8e 5113 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
ebrus 0:6bc4ac881c8e 5114 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 5115 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 5116
ebrus 0:6bc4ac881c8e 5117 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
ebrus 0:6bc4ac881c8e 5118 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
ebrus 0:6bc4ac881c8e 5119 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5120 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5121 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5122 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5123 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5124 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5125 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5126 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5127 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5128
ebrus 0:6bc4ac881c8e 5129 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
ebrus 0:6bc4ac881c8e 5130 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 5131 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 5132 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 5133
ebrus 0:6bc4ac881c8e 5134 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5135 /* */
ebrus 0:6bc4ac881c8e 5136 /* RNG */
ebrus 0:6bc4ac881c8e 5137 /* */
ebrus 0:6bc4ac881c8e 5138 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5139 /******************** Bits definition for RNG_CR register *******************/
ebrus 0:6bc4ac881c8e 5140 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5141 #define RNG_CR_IE ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5142
ebrus 0:6bc4ac881c8e 5143 /******************** Bits definition for RNG_SR register *******************/
ebrus 0:6bc4ac881c8e 5144 #define RNG_SR_DRDY ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5145 #define RNG_SR_CECS ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5146 #define RNG_SR_SECS ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5147 #define RNG_SR_CEIS ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5148 #define RNG_SR_SEIS ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5149
ebrus 0:6bc4ac881c8e 5150 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5151 /* */
ebrus 0:6bc4ac881c8e 5152 /* Real-Time Clock (RTC) */
ebrus 0:6bc4ac881c8e 5153 /* */
ebrus 0:6bc4ac881c8e 5154 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5155 /******************** Bits definition for RTC_TR register *******************/
ebrus 0:6bc4ac881c8e 5156 #define RTC_TR_PM ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5157 #define RTC_TR_HT ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 5158 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5159 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5160 #define RTC_TR_HU ((uint32_t)0x000F0000)
ebrus 0:6bc4ac881c8e 5161 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5162 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5163 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5164 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5165 #define RTC_TR_MNT ((uint32_t)0x00007000)
ebrus 0:6bc4ac881c8e 5166 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5167 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5168 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5169 #define RTC_TR_MNU ((uint32_t)0x00000F00)
ebrus 0:6bc4ac881c8e 5170 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5171 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5172 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5173 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5174 #define RTC_TR_ST ((uint32_t)0x00000070)
ebrus 0:6bc4ac881c8e 5175 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5176 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5177 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5178 #define RTC_TR_SU ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 5179 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5180 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5181 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5182 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5183
ebrus 0:6bc4ac881c8e 5184 /******************** Bits definition for RTC_DR register *******************/
ebrus 0:6bc4ac881c8e 5185 #define RTC_DR_YT ((uint32_t)0x00F00000)
ebrus 0:6bc4ac881c8e 5186 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5187 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5188 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5189 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 5190 #define RTC_DR_YU ((uint32_t)0x000F0000)
ebrus 0:6bc4ac881c8e 5191 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5192 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5193 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5194 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5195 #define RTC_DR_WDU ((uint32_t)0x0000E000)
ebrus 0:6bc4ac881c8e 5196 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5197 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5198 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5199 #define RTC_DR_MT ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5200 #define RTC_DR_MU ((uint32_t)0x00000F00)
ebrus 0:6bc4ac881c8e 5201 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5202 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5203 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5204 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5205 #define RTC_DR_DT ((uint32_t)0x00000030)
ebrus 0:6bc4ac881c8e 5206 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5207 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5208 #define RTC_DR_DU ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 5209 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5210 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5211 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5212 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5213
ebrus 0:6bc4ac881c8e 5214 /******************** Bits definition for RTC_CR register *******************/
ebrus 0:6bc4ac881c8e 5215 #define RTC_CR_COE ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 5216 #define RTC_CR_OSEL ((uint32_t)0x00600000)
ebrus 0:6bc4ac881c8e 5217 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5218 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5219 #define RTC_CR_POL ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5220 #define RTC_CR_COSEL ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5221 #define RTC_CR_BCK ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5222 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5223 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5224 #define RTC_CR_TSIE ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5225 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5226 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5227 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5228 #define RTC_CR_TSE ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5229 #define RTC_CR_WUTE ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5230 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5231 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5232 #define RTC_CR_DCE ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5233 #define RTC_CR_FMT ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5234 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5235 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5236 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5237 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
ebrus 0:6bc4ac881c8e 5238 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5239 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5240 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5241
ebrus 0:6bc4ac881c8e 5242 /******************** Bits definition for RTC_ISR register ******************/
ebrus 0:6bc4ac881c8e 5243 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5244 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5245 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5246 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5247 #define RTC_ISR_TSF ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5248 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5249 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5250 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5251 #define RTC_ISR_INIT ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5252 #define RTC_ISR_INITF ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5253 #define RTC_ISR_RSF ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5254 #define RTC_ISR_INITS ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5255 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5256 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5257 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5258 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5259
ebrus 0:6bc4ac881c8e 5260 /******************** Bits definition for RTC_PRER register *****************/
ebrus 0:6bc4ac881c8e 5261 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
ebrus 0:6bc4ac881c8e 5262 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
ebrus 0:6bc4ac881c8e 5263
ebrus 0:6bc4ac881c8e 5264 /******************** Bits definition for RTC_WUTR register *****************/
ebrus 0:6bc4ac881c8e 5265 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
ebrus 0:6bc4ac881c8e 5266
ebrus 0:6bc4ac881c8e 5267 /******************** Bits definition for RTC_CALIBR register ***************/
ebrus 0:6bc4ac881c8e 5268 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5269 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
ebrus 0:6bc4ac881c8e 5270
ebrus 0:6bc4ac881c8e 5271 /******************** Bits definition for RTC_ALRMAR register ***************/
ebrus 0:6bc4ac881c8e 5272 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 5273 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 5274 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
ebrus 0:6bc4ac881c8e 5275 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 5276 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 5277 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
ebrus 0:6bc4ac881c8e 5278 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 5279 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5280 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5281 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 5282 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 5283 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5284 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 5285 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5286 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5287 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
ebrus 0:6bc4ac881c8e 5288 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5289 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5290 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5291 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5292 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5293 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
ebrus 0:6bc4ac881c8e 5294 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5295 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5296 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5297 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
ebrus 0:6bc4ac881c8e 5298 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5299 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5300 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5301 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5302 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5303 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
ebrus 0:6bc4ac881c8e 5304 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5305 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5306 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5307 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 5308 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5309 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5310 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5311 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5312
ebrus 0:6bc4ac881c8e 5313 /******************** Bits definition for RTC_ALRMBR register ***************/
ebrus 0:6bc4ac881c8e 5314 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 5315 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
ebrus 0:6bc4ac881c8e 5316 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
ebrus 0:6bc4ac881c8e 5317 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
ebrus 0:6bc4ac881c8e 5318 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
ebrus 0:6bc4ac881c8e 5319 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
ebrus 0:6bc4ac881c8e 5320 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 5321 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5322 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5323 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 5324 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 5325 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5326 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 5327 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5328 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5329 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
ebrus 0:6bc4ac881c8e 5330 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5331 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5332 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5333 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5334 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5335 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
ebrus 0:6bc4ac881c8e 5336 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5337 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5338 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5339 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
ebrus 0:6bc4ac881c8e 5340 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5341 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5342 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5343 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5344 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5345 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
ebrus 0:6bc4ac881c8e 5346 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5347 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5348 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5349 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 5350 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5351 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5352 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5353 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5354
ebrus 0:6bc4ac881c8e 5355 /******************** Bits definition for RTC_WPR register ******************/
ebrus 0:6bc4ac881c8e 5356 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
ebrus 0:6bc4ac881c8e 5357
ebrus 0:6bc4ac881c8e 5358 /******************** Bits definition for RTC_SSR register ******************/
ebrus 0:6bc4ac881c8e 5359 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
ebrus 0:6bc4ac881c8e 5360
ebrus 0:6bc4ac881c8e 5361 /******************** Bits definition for RTC_SHIFTR register ***************/
ebrus 0:6bc4ac881c8e 5362 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
ebrus 0:6bc4ac881c8e 5363 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
ebrus 0:6bc4ac881c8e 5364
ebrus 0:6bc4ac881c8e 5365 /******************** Bits definition for RTC_TSTR register *****************/
ebrus 0:6bc4ac881c8e 5366 #define RTC_TSTR_PM ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 5367 #define RTC_TSTR_HT ((uint32_t)0x00300000)
ebrus 0:6bc4ac881c8e 5368 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
ebrus 0:6bc4ac881c8e 5369 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 5370 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
ebrus 0:6bc4ac881c8e 5371 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5372 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5373 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5374 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
ebrus 0:6bc4ac881c8e 5375 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
ebrus 0:6bc4ac881c8e 5376 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5377 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5378 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5379 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
ebrus 0:6bc4ac881c8e 5380 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5381 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5382 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5383 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5384 #define RTC_TSTR_ST ((uint32_t)0x00000070)
ebrus 0:6bc4ac881c8e 5385 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5386 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5387 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5388 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 5389 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5390 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5391 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5392 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5393
ebrus 0:6bc4ac881c8e 5394 /******************** Bits definition for RTC_TSDR register *****************/
ebrus 0:6bc4ac881c8e 5395 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
ebrus 0:6bc4ac881c8e 5396 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5397 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5398 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5399 #define RTC_TSDR_MT ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5400 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
ebrus 0:6bc4ac881c8e 5401 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5402 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5403 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5404 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5405 #define RTC_TSDR_DT ((uint32_t)0x00000030)
ebrus 0:6bc4ac881c8e 5406 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5407 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5408 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
ebrus 0:6bc4ac881c8e 5409 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5410 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5411 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5412 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5413
ebrus 0:6bc4ac881c8e 5414 /******************** Bits definition for RTC_TSSSR register ****************/
ebrus 0:6bc4ac881c8e 5415 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
ebrus 0:6bc4ac881c8e 5416
ebrus 0:6bc4ac881c8e 5417 /******************** Bits definition for RTC_CAL register *****************/
ebrus 0:6bc4ac881c8e 5418 #define RTC_CALR_CALP ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5419 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5420 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5421 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
ebrus 0:6bc4ac881c8e 5422 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5423 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5424 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5425 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5426 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5427 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 5428 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 5429 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5430 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5431
ebrus 0:6bc4ac881c8e 5432 /******************** Bits definition for RTC_TAFCR register ****************/
ebrus 0:6bc4ac881c8e 5433 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 5434 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 5435 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 5436 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
ebrus 0:6bc4ac881c8e 5437 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
ebrus 0:6bc4ac881c8e 5438 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
ebrus 0:6bc4ac881c8e 5439 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
ebrus 0:6bc4ac881c8e 5440 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
ebrus 0:6bc4ac881c8e 5441 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 5442 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 5443 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
ebrus 0:6bc4ac881c8e 5444 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 5445 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
ebrus 0:6bc4ac881c8e 5446 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 5447 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 5448 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 5449 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 5450 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5451 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5452 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5453
ebrus 0:6bc4ac881c8e 5454 /******************** Bits definition for RTC_ALRMASSR register *************/
ebrus 0:6bc4ac881c8e 5455 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
ebrus 0:6bc4ac881c8e 5456 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 5457 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5458 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5459 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 5460 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
ebrus 0:6bc4ac881c8e 5461
ebrus 0:6bc4ac881c8e 5462 /******************** Bits definition for RTC_ALRMBSSR register *************/
ebrus 0:6bc4ac881c8e 5463 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
ebrus 0:6bc4ac881c8e 5464 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
ebrus 0:6bc4ac881c8e 5465 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 5466 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 5467 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
ebrus 0:6bc4ac881c8e 5468 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
ebrus 0:6bc4ac881c8e 5469
ebrus 0:6bc4ac881c8e 5470 /******************** Bits definition for RTC_BKP0R register ****************/
ebrus 0:6bc4ac881c8e 5471 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5472
ebrus 0:6bc4ac881c8e 5473 /******************** Bits definition for RTC_BKP1R register ****************/
ebrus 0:6bc4ac881c8e 5474 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5475
ebrus 0:6bc4ac881c8e 5476 /******************** Bits definition for RTC_BKP2R register ****************/
ebrus 0:6bc4ac881c8e 5477 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5478
ebrus 0:6bc4ac881c8e 5479 /******************** Bits definition for RTC_BKP3R register ****************/
ebrus 0:6bc4ac881c8e 5480 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5481
ebrus 0:6bc4ac881c8e 5482 /******************** Bits definition for RTC_BKP4R register ****************/
ebrus 0:6bc4ac881c8e 5483 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5484
ebrus 0:6bc4ac881c8e 5485 /******************** Bits definition for RTC_BKP5R register ****************/
ebrus 0:6bc4ac881c8e 5486 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5487
ebrus 0:6bc4ac881c8e 5488 /******************** Bits definition for RTC_BKP6R register ****************/
ebrus 0:6bc4ac881c8e 5489 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5490
ebrus 0:6bc4ac881c8e 5491 /******************** Bits definition for RTC_BKP7R register ****************/
ebrus 0:6bc4ac881c8e 5492 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5493
ebrus 0:6bc4ac881c8e 5494 /******************** Bits definition for RTC_BKP8R register ****************/
ebrus 0:6bc4ac881c8e 5495 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5496
ebrus 0:6bc4ac881c8e 5497 /******************** Bits definition for RTC_BKP9R register ****************/
ebrus 0:6bc4ac881c8e 5498 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5499
ebrus 0:6bc4ac881c8e 5500 /******************** Bits definition for RTC_BKP10R register ***************/
ebrus 0:6bc4ac881c8e 5501 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5502
ebrus 0:6bc4ac881c8e 5503 /******************** Bits definition for RTC_BKP11R register ***************/
ebrus 0:6bc4ac881c8e 5504 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5505
ebrus 0:6bc4ac881c8e 5506 /******************** Bits definition for RTC_BKP12R register ***************/
ebrus 0:6bc4ac881c8e 5507 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5508
ebrus 0:6bc4ac881c8e 5509 /******************** Bits definition for RTC_BKP13R register ***************/
ebrus 0:6bc4ac881c8e 5510 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5511
ebrus 0:6bc4ac881c8e 5512 /******************** Bits definition for RTC_BKP14R register ***************/
ebrus 0:6bc4ac881c8e 5513 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5514
ebrus 0:6bc4ac881c8e 5515 /******************** Bits definition for RTC_BKP15R register ***************/
ebrus 0:6bc4ac881c8e 5516 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5517
ebrus 0:6bc4ac881c8e 5518 /******************** Bits definition for RTC_BKP16R register ***************/
ebrus 0:6bc4ac881c8e 5519 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5520
ebrus 0:6bc4ac881c8e 5521 /******************** Bits definition for RTC_BKP17R register ***************/
ebrus 0:6bc4ac881c8e 5522 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5523
ebrus 0:6bc4ac881c8e 5524 /******************** Bits definition for RTC_BKP18R register ***************/
ebrus 0:6bc4ac881c8e 5525 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5526
ebrus 0:6bc4ac881c8e 5527 /******************** Bits definition for RTC_BKP19R register ***************/
ebrus 0:6bc4ac881c8e 5528 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
ebrus 0:6bc4ac881c8e 5529
ebrus 0:6bc4ac881c8e 5530
ebrus 0:6bc4ac881c8e 5531
ebrus 0:6bc4ac881c8e 5532 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5533 /* */
ebrus 0:6bc4ac881c8e 5534 /* SD host Interface */
ebrus 0:6bc4ac881c8e 5535 /* */
ebrus 0:6bc4ac881c8e 5536 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5537 /****************** Bit definition for SDIO_POWER register ******************/
ebrus 0:6bc4ac881c8e 5538 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
ebrus 0:6bc4ac881c8e 5539 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5540 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5541
ebrus 0:6bc4ac881c8e 5542 /****************** Bit definition for SDIO_CLKCR register ******************/
ebrus 0:6bc4ac881c8e 5543 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
ebrus 0:6bc4ac881c8e 5544 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
ebrus 0:6bc4ac881c8e 5545 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
ebrus 0:6bc4ac881c8e 5546 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
ebrus 0:6bc4ac881c8e 5547
ebrus 0:6bc4ac881c8e 5548 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
ebrus 0:6bc4ac881c8e 5549 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5550 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5551
ebrus 0:6bc4ac881c8e 5552 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
ebrus 0:6bc4ac881c8e 5553 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
ebrus 0:6bc4ac881c8e 5554
ebrus 0:6bc4ac881c8e 5555 /******************* Bit definition for SDIO_ARG register *******************/
ebrus 0:6bc4ac881c8e 5556 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
ebrus 0:6bc4ac881c8e 5557
ebrus 0:6bc4ac881c8e 5558 /******************* Bit definition for SDIO_CMD register *******************/
ebrus 0:6bc4ac881c8e 5559 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
ebrus 0:6bc4ac881c8e 5560
ebrus 0:6bc4ac881c8e 5561 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
ebrus 0:6bc4ac881c8e 5562 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
ebrus 0:6bc4ac881c8e 5563 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
ebrus 0:6bc4ac881c8e 5564
ebrus 0:6bc4ac881c8e 5565 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
ebrus 0:6bc4ac881c8e 5566 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
ebrus 0:6bc4ac881c8e 5567 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
ebrus 0:6bc4ac881c8e 5568 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
ebrus 0:6bc4ac881c8e 5569 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
ebrus 0:6bc4ac881c8e 5570 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
ebrus 0:6bc4ac881c8e 5571 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
ebrus 0:6bc4ac881c8e 5572
ebrus 0:6bc4ac881c8e 5573 /***************** Bit definition for SDIO_RESPCMD register *****************/
ebrus 0:6bc4ac881c8e 5574 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
ebrus 0:6bc4ac881c8e 5575
ebrus 0:6bc4ac881c8e 5576 /****************** Bit definition for SDIO_RESP0 register ******************/
ebrus 0:6bc4ac881c8e 5577 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:6bc4ac881c8e 5578
ebrus 0:6bc4ac881c8e 5579 /****************** Bit definition for SDIO_RESP1 register ******************/
ebrus 0:6bc4ac881c8e 5580 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:6bc4ac881c8e 5581
ebrus 0:6bc4ac881c8e 5582 /****************** Bit definition for SDIO_RESP2 register ******************/
ebrus 0:6bc4ac881c8e 5583 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:6bc4ac881c8e 5584
ebrus 0:6bc4ac881c8e 5585 /****************** Bit definition for SDIO_RESP3 register ******************/
ebrus 0:6bc4ac881c8e 5586 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:6bc4ac881c8e 5587
ebrus 0:6bc4ac881c8e 5588 /****************** Bit definition for SDIO_RESP4 register ******************/
ebrus 0:6bc4ac881c8e 5589 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
ebrus 0:6bc4ac881c8e 5590
ebrus 0:6bc4ac881c8e 5591 /****************** Bit definition for SDIO_DTIMER register *****************/
ebrus 0:6bc4ac881c8e 5592 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
ebrus 0:6bc4ac881c8e 5593
ebrus 0:6bc4ac881c8e 5594 /****************** Bit definition for SDIO_DLEN register *******************/
ebrus 0:6bc4ac881c8e 5595 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
ebrus 0:6bc4ac881c8e 5596
ebrus 0:6bc4ac881c8e 5597 /****************** Bit definition for SDIO_DCTRL register ******************/
ebrus 0:6bc4ac881c8e 5598 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
ebrus 0:6bc4ac881c8e 5599 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
ebrus 0:6bc4ac881c8e 5600 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
ebrus 0:6bc4ac881c8e 5601 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
ebrus 0:6bc4ac881c8e 5602
ebrus 0:6bc4ac881c8e 5603 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
ebrus 0:6bc4ac881c8e 5604 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5605 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5606 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 5607 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 5608
ebrus 0:6bc4ac881c8e 5609 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
ebrus 0:6bc4ac881c8e 5610 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
ebrus 0:6bc4ac881c8e 5611 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
ebrus 0:6bc4ac881c8e 5612 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
ebrus 0:6bc4ac881c8e 5613
ebrus 0:6bc4ac881c8e 5614 /****************** Bit definition for SDIO_DCOUNT register *****************/
ebrus 0:6bc4ac881c8e 5615 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
ebrus 0:6bc4ac881c8e 5616
ebrus 0:6bc4ac881c8e 5617 /****************** Bit definition for SDIO_STA register ********************/
ebrus 0:6bc4ac881c8e 5618 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
ebrus 0:6bc4ac881c8e 5619 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
ebrus 0:6bc4ac881c8e 5620 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
ebrus 0:6bc4ac881c8e 5621 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
ebrus 0:6bc4ac881c8e 5622 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
ebrus 0:6bc4ac881c8e 5623 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
ebrus 0:6bc4ac881c8e 5624 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
ebrus 0:6bc4ac881c8e 5625 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
ebrus 0:6bc4ac881c8e 5626 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
ebrus 0:6bc4ac881c8e 5627 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
ebrus 0:6bc4ac881c8e 5628 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
ebrus 0:6bc4ac881c8e 5629 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
ebrus 0:6bc4ac881c8e 5630 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
ebrus 0:6bc4ac881c8e 5631 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
ebrus 0:6bc4ac881c8e 5632 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
ebrus 0:6bc4ac881c8e 5633 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
ebrus 0:6bc4ac881c8e 5634 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
ebrus 0:6bc4ac881c8e 5635 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
ebrus 0:6bc4ac881c8e 5636 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
ebrus 0:6bc4ac881c8e 5637 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
ebrus 0:6bc4ac881c8e 5638 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
ebrus 0:6bc4ac881c8e 5639 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
ebrus 0:6bc4ac881c8e 5640 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
ebrus 0:6bc4ac881c8e 5641 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
ebrus 0:6bc4ac881c8e 5642
ebrus 0:6bc4ac881c8e 5643 /******************* Bit definition for SDIO_ICR register *******************/
ebrus 0:6bc4ac881c8e 5644 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
ebrus 0:6bc4ac881c8e 5645 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
ebrus 0:6bc4ac881c8e 5646 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
ebrus 0:6bc4ac881c8e 5647 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
ebrus 0:6bc4ac881c8e 5648 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
ebrus 0:6bc4ac881c8e 5649 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
ebrus 0:6bc4ac881c8e 5650 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
ebrus 0:6bc4ac881c8e 5651 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
ebrus 0:6bc4ac881c8e 5652 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
ebrus 0:6bc4ac881c8e 5653 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
ebrus 0:6bc4ac881c8e 5654 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
ebrus 0:6bc4ac881c8e 5655 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
ebrus 0:6bc4ac881c8e 5656 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
ebrus 0:6bc4ac881c8e 5657
ebrus 0:6bc4ac881c8e 5658 /****************** Bit definition for SDIO_MASK register *******************/
ebrus 0:6bc4ac881c8e 5659 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
ebrus 0:6bc4ac881c8e 5660 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
ebrus 0:6bc4ac881c8e 5661 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
ebrus 0:6bc4ac881c8e 5662 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
ebrus 0:6bc4ac881c8e 5663 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 5664 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 5665 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
ebrus 0:6bc4ac881c8e 5666 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
ebrus 0:6bc4ac881c8e 5667 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
ebrus 0:6bc4ac881c8e 5668 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 5669 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
ebrus 0:6bc4ac881c8e 5670 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
ebrus 0:6bc4ac881c8e 5671 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
ebrus 0:6bc4ac881c8e 5672 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
ebrus 0:6bc4ac881c8e 5673 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
ebrus 0:6bc4ac881c8e 5674 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
ebrus 0:6bc4ac881c8e 5675 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
ebrus 0:6bc4ac881c8e 5676 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
ebrus 0:6bc4ac881c8e 5677 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
ebrus 0:6bc4ac881c8e 5678 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
ebrus 0:6bc4ac881c8e 5679 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
ebrus 0:6bc4ac881c8e 5680 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
ebrus 0:6bc4ac881c8e 5681 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
ebrus 0:6bc4ac881c8e 5682 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
ebrus 0:6bc4ac881c8e 5683
ebrus 0:6bc4ac881c8e 5684 /***************** Bit definition for SDIO_FIFOCNT register *****************/
ebrus 0:6bc4ac881c8e 5685 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
ebrus 0:6bc4ac881c8e 5686
ebrus 0:6bc4ac881c8e 5687 /****************** Bit definition for SDIO_FIFO register *******************/
ebrus 0:6bc4ac881c8e 5688 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
ebrus 0:6bc4ac881c8e 5689
ebrus 0:6bc4ac881c8e 5690 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5691 /* */
ebrus 0:6bc4ac881c8e 5692 /* Serial Peripheral Interface */
ebrus 0:6bc4ac881c8e 5693 /* */
ebrus 0:6bc4ac881c8e 5694 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5695 /******************* Bit definition for SPI_CR1 register ********************/
ebrus 0:6bc4ac881c8e 5696 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
ebrus 0:6bc4ac881c8e 5697 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
ebrus 0:6bc4ac881c8e 5698 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
ebrus 0:6bc4ac881c8e 5699
ebrus 0:6bc4ac881c8e 5700 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
ebrus 0:6bc4ac881c8e 5701 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5702 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5703 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 5704
ebrus 0:6bc4ac881c8e 5705 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
ebrus 0:6bc4ac881c8e 5706 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
ebrus 0:6bc4ac881c8e 5707 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
ebrus 0:6bc4ac881c8e 5708 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
ebrus 0:6bc4ac881c8e 5709 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
ebrus 0:6bc4ac881c8e 5710 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
ebrus 0:6bc4ac881c8e 5711 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
ebrus 0:6bc4ac881c8e 5712 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
ebrus 0:6bc4ac881c8e 5713 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
ebrus 0:6bc4ac881c8e 5714 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
ebrus 0:6bc4ac881c8e 5715
ebrus 0:6bc4ac881c8e 5716 /******************* Bit definition for SPI_CR2 register ********************/
ebrus 0:6bc4ac881c8e 5717 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
ebrus 0:6bc4ac881c8e 5718 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
ebrus 0:6bc4ac881c8e 5719 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
ebrus 0:6bc4ac881c8e 5720 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
ebrus 0:6bc4ac881c8e 5721 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 5722 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
ebrus 0:6bc4ac881c8e 5723 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
ebrus 0:6bc4ac881c8e 5724
ebrus 0:6bc4ac881c8e 5725 /******************** Bit definition for SPI_SR register ********************/
ebrus 0:6bc4ac881c8e 5726 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
ebrus 0:6bc4ac881c8e 5727 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
ebrus 0:6bc4ac881c8e 5728 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
ebrus 0:6bc4ac881c8e 5729 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
ebrus 0:6bc4ac881c8e 5730 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
ebrus 0:6bc4ac881c8e 5731 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
ebrus 0:6bc4ac881c8e 5732 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
ebrus 0:6bc4ac881c8e 5733 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
ebrus 0:6bc4ac881c8e 5734 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
ebrus 0:6bc4ac881c8e 5735
ebrus 0:6bc4ac881c8e 5736 /******************** Bit definition for SPI_DR register ********************/
ebrus 0:6bc4ac881c8e 5737 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
ebrus 0:6bc4ac881c8e 5738
ebrus 0:6bc4ac881c8e 5739 /******************* Bit definition for SPI_CRCPR register ******************/
ebrus 0:6bc4ac881c8e 5740 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
ebrus 0:6bc4ac881c8e 5741
ebrus 0:6bc4ac881c8e 5742 /****************** Bit definition for SPI_RXCRCR register ******************/
ebrus 0:6bc4ac881c8e 5743 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
ebrus 0:6bc4ac881c8e 5744
ebrus 0:6bc4ac881c8e 5745 /****************** Bit definition for SPI_TXCRCR register ******************/
ebrus 0:6bc4ac881c8e 5746 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
ebrus 0:6bc4ac881c8e 5747
ebrus 0:6bc4ac881c8e 5748 /****************** Bit definition for SPI_I2SCFGR register *****************/
ebrus 0:6bc4ac881c8e 5749 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
ebrus 0:6bc4ac881c8e 5750
ebrus 0:6bc4ac881c8e 5751 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
ebrus 0:6bc4ac881c8e 5752 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5753 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5754
ebrus 0:6bc4ac881c8e 5755 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
ebrus 0:6bc4ac881c8e 5756
ebrus 0:6bc4ac881c8e 5757 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
ebrus 0:6bc4ac881c8e 5758 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5759 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5760
ebrus 0:6bc4ac881c8e 5761 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
ebrus 0:6bc4ac881c8e 5762
ebrus 0:6bc4ac881c8e 5763 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
ebrus 0:6bc4ac881c8e 5764 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 5765 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 5766
ebrus 0:6bc4ac881c8e 5767 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
ebrus 0:6bc4ac881c8e 5768 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
ebrus 0:6bc4ac881c8e 5769
ebrus 0:6bc4ac881c8e 5770 /****************** Bit definition for SPI_I2SPR register *******************/
ebrus 0:6bc4ac881c8e 5771 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
ebrus 0:6bc4ac881c8e 5772 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
ebrus 0:6bc4ac881c8e 5773 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
ebrus 0:6bc4ac881c8e 5774
ebrus 0:6bc4ac881c8e 5775 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5776 /* */
ebrus 0:6bc4ac881c8e 5777 /* SYSCFG */
ebrus 0:6bc4ac881c8e 5778 /* */
ebrus 0:6bc4ac881c8e 5779 /******************************************************************************/
ebrus 0:6bc4ac881c8e 5780 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
ebrus 0:6bc4ac881c8e 5781 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
ebrus 0:6bc4ac881c8e 5782 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 5783 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 5784 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 5785
ebrus 0:6bc4ac881c8e 5786 /****************** Bit definition for SYSCFG_PMC register ******************/
ebrus 0:6bc4ac881c8e 5787 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
ebrus 0:6bc4ac881c8e 5788 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
ebrus 0:6bc4ac881c8e 5789 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
ebrus 0:6bc4ac881c8e 5790
ebrus 0:6bc4ac881c8e 5791 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
ebrus 0:6bc4ac881c8e 5792 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
ebrus 0:6bc4ac881c8e 5793 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
ebrus 0:6bc4ac881c8e 5794 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
ebrus 0:6bc4ac881c8e 5795 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
ebrus 0:6bc4ac881c8e 5796 /**
ebrus 0:6bc4ac881c8e 5797 * @brief EXTI0 configuration
ebrus 0:6bc4ac881c8e 5798 */
ebrus 0:6bc4ac881c8e 5799 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
ebrus 0:6bc4ac881c8e 5800 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
ebrus 0:6bc4ac881c8e 5801 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
ebrus 0:6bc4ac881c8e 5802 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
ebrus 0:6bc4ac881c8e 5803 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
ebrus 0:6bc4ac881c8e 5804 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
ebrus 0:6bc4ac881c8e 5805 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
ebrus 0:6bc4ac881c8e 5806 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
ebrus 0:6bc4ac881c8e 5807 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
ebrus 0:6bc4ac881c8e 5808
ebrus 0:6bc4ac881c8e 5809 /**
ebrus 0:6bc4ac881c8e 5810 * @brief EXTI1 configuration
ebrus 0:6bc4ac881c8e 5811 */
ebrus 0:6bc4ac881c8e 5812 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
ebrus 0:6bc4ac881c8e 5813 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
ebrus 0:6bc4ac881c8e 5814 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
ebrus 0:6bc4ac881c8e 5815 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
ebrus 0:6bc4ac881c8e 5816 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
ebrus 0:6bc4ac881c8e 5817 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
ebrus 0:6bc4ac881c8e 5818 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
ebrus 0:6bc4ac881c8e 5819 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
ebrus 0:6bc4ac881c8e 5820 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
ebrus 0:6bc4ac881c8e 5821
ebrus 0:6bc4ac881c8e 5822 /**
ebrus 0:6bc4ac881c8e 5823 * @brief EXTI2 configuration
ebrus 0:6bc4ac881c8e 5824 */
ebrus 0:6bc4ac881c8e 5825 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
ebrus 0:6bc4ac881c8e 5826 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
ebrus 0:6bc4ac881c8e 5827 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
ebrus 0:6bc4ac881c8e 5828 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
ebrus 0:6bc4ac881c8e 5829 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
ebrus 0:6bc4ac881c8e 5830 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
ebrus 0:6bc4ac881c8e 5831 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
ebrus 0:6bc4ac881c8e 5832 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
ebrus 0:6bc4ac881c8e 5833 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
ebrus 0:6bc4ac881c8e 5834
ebrus 0:6bc4ac881c8e 5835 /**
ebrus 0:6bc4ac881c8e 5836 * @brief EXTI3 configuration
ebrus 0:6bc4ac881c8e 5837 */
ebrus 0:6bc4ac881c8e 5838 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
ebrus 0:6bc4ac881c8e 5839 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
ebrus 0:6bc4ac881c8e 5840 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
ebrus 0:6bc4ac881c8e 5841 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
ebrus 0:6bc4ac881c8e 5842 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
ebrus 0:6bc4ac881c8e 5843 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
ebrus 0:6bc4ac881c8e 5844 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
ebrus 0:6bc4ac881c8e 5845 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
ebrus 0:6bc4ac881c8e 5846 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
ebrus 0:6bc4ac881c8e 5847
ebrus 0:6bc4ac881c8e 5848 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
ebrus 0:6bc4ac881c8e 5849 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
ebrus 0:6bc4ac881c8e 5850 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
ebrus 0:6bc4ac881c8e 5851 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
ebrus 0:6bc4ac881c8e 5852 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
ebrus 0:6bc4ac881c8e 5853 /**
ebrus 0:6bc4ac881c8e 5854 * @brief EXTI4 configuration
ebrus 0:6bc4ac881c8e 5855 */
ebrus 0:6bc4ac881c8e 5856 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
ebrus 0:6bc4ac881c8e 5857 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
ebrus 0:6bc4ac881c8e 5858 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
ebrus 0:6bc4ac881c8e 5859 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
ebrus 0:6bc4ac881c8e 5860 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
ebrus 0:6bc4ac881c8e 5861 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
ebrus 0:6bc4ac881c8e 5862 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
ebrus 0:6bc4ac881c8e 5863 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
ebrus 0:6bc4ac881c8e 5864 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
ebrus 0:6bc4ac881c8e 5865
ebrus 0:6bc4ac881c8e 5866 /**
ebrus 0:6bc4ac881c8e 5867 * @brief EXTI5 configuration
ebrus 0:6bc4ac881c8e 5868 */
ebrus 0:6bc4ac881c8e 5869 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
ebrus 0:6bc4ac881c8e 5870 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
ebrus 0:6bc4ac881c8e 5871 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
ebrus 0:6bc4ac881c8e 5872 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
ebrus 0:6bc4ac881c8e 5873 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
ebrus 0:6bc4ac881c8e 5874 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
ebrus 0:6bc4ac881c8e 5875 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
ebrus 0:6bc4ac881c8e 5876 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
ebrus 0:6bc4ac881c8e 5877 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
ebrus 0:6bc4ac881c8e 5878
ebrus 0:6bc4ac881c8e 5879 /**
ebrus 0:6bc4ac881c8e 5880 * @brief EXTI6 configuration
ebrus 0:6bc4ac881c8e 5881 */
ebrus 0:6bc4ac881c8e 5882 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
ebrus 0:6bc4ac881c8e 5883 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
ebrus 0:6bc4ac881c8e 5884 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
ebrus 0:6bc4ac881c8e 5885 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
ebrus 0:6bc4ac881c8e 5886 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
ebrus 0:6bc4ac881c8e 5887 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
ebrus 0:6bc4ac881c8e 5888 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
ebrus 0:6bc4ac881c8e 5889 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
ebrus 0:6bc4ac881c8e 5890 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
ebrus 0:6bc4ac881c8e 5891
ebrus 0:6bc4ac881c8e 5892 /**
ebrus 0:6bc4ac881c8e 5893 * @brief EXTI7 configuration
ebrus 0:6bc4ac881c8e 5894 */
ebrus 0:6bc4ac881c8e 5895 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
ebrus 0:6bc4ac881c8e 5896 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
ebrus 0:6bc4ac881c8e 5897 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
ebrus 0:6bc4ac881c8e 5898 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
ebrus 0:6bc4ac881c8e 5899 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
ebrus 0:6bc4ac881c8e 5900 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
ebrus 0:6bc4ac881c8e 5901 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
ebrus 0:6bc4ac881c8e 5902 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
ebrus 0:6bc4ac881c8e 5903 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
ebrus 0:6bc4ac881c8e 5904
ebrus 0:6bc4ac881c8e 5905
ebrus 0:6bc4ac881c8e 5906 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
ebrus 0:6bc4ac881c8e 5907 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
ebrus 0:6bc4ac881c8e 5908 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
ebrus 0:6bc4ac881c8e 5909 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
ebrus 0:6bc4ac881c8e 5910 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
ebrus 0:6bc4ac881c8e 5911
ebrus 0:6bc4ac881c8e 5912 /**
ebrus 0:6bc4ac881c8e 5913 * @brief EXTI8 configuration
ebrus 0:6bc4ac881c8e 5914 */
ebrus 0:6bc4ac881c8e 5915 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
ebrus 0:6bc4ac881c8e 5916 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
ebrus 0:6bc4ac881c8e 5917 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
ebrus 0:6bc4ac881c8e 5918 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
ebrus 0:6bc4ac881c8e 5919 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
ebrus 0:6bc4ac881c8e 5920 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
ebrus 0:6bc4ac881c8e 5921 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
ebrus 0:6bc4ac881c8e 5922 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
ebrus 0:6bc4ac881c8e 5923 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
ebrus 0:6bc4ac881c8e 5924
ebrus 0:6bc4ac881c8e 5925 /**
ebrus 0:6bc4ac881c8e 5926 * @brief EXTI9 configuration
ebrus 0:6bc4ac881c8e 5927 */
ebrus 0:6bc4ac881c8e 5928 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
ebrus 0:6bc4ac881c8e 5929 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
ebrus 0:6bc4ac881c8e 5930 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
ebrus 0:6bc4ac881c8e 5931 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
ebrus 0:6bc4ac881c8e 5932 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
ebrus 0:6bc4ac881c8e 5933 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
ebrus 0:6bc4ac881c8e 5934 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
ebrus 0:6bc4ac881c8e 5935 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
ebrus 0:6bc4ac881c8e 5936 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
ebrus 0:6bc4ac881c8e 5937
ebrus 0:6bc4ac881c8e 5938 /**
ebrus 0:6bc4ac881c8e 5939 * @brief EXTI10 configuration
ebrus 0:6bc4ac881c8e 5940 */
ebrus 0:6bc4ac881c8e 5941 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
ebrus 0:6bc4ac881c8e 5942 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
ebrus 0:6bc4ac881c8e 5943 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
ebrus 0:6bc4ac881c8e 5944 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
ebrus 0:6bc4ac881c8e 5945 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
ebrus 0:6bc4ac881c8e 5946 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
ebrus 0:6bc4ac881c8e 5947 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
ebrus 0:6bc4ac881c8e 5948 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
ebrus 0:6bc4ac881c8e 5949 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
ebrus 0:6bc4ac881c8e 5950
ebrus 0:6bc4ac881c8e 5951 /**
ebrus 0:6bc4ac881c8e 5952 * @brief EXTI11 configuration
ebrus 0:6bc4ac881c8e 5953 */
ebrus 0:6bc4ac881c8e 5954 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
ebrus 0:6bc4ac881c8e 5955 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
ebrus 0:6bc4ac881c8e 5956 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
ebrus 0:6bc4ac881c8e 5957 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
ebrus 0:6bc4ac881c8e 5958 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
ebrus 0:6bc4ac881c8e 5959 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
ebrus 0:6bc4ac881c8e 5960 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
ebrus 0:6bc4ac881c8e 5961 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
ebrus 0:6bc4ac881c8e 5962 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
ebrus 0:6bc4ac881c8e 5963
ebrus 0:6bc4ac881c8e 5964 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
ebrus 0:6bc4ac881c8e 5965 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
ebrus 0:6bc4ac881c8e 5966 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
ebrus 0:6bc4ac881c8e 5967 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
ebrus 0:6bc4ac881c8e 5968 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
ebrus 0:6bc4ac881c8e 5969 /**
ebrus 0:6bc4ac881c8e 5970 * @brief EXTI12 configuration
ebrus 0:6bc4ac881c8e 5971 */
ebrus 0:6bc4ac881c8e 5972 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
ebrus 0:6bc4ac881c8e 5973 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
ebrus 0:6bc4ac881c8e 5974 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
ebrus 0:6bc4ac881c8e 5975 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
ebrus 0:6bc4ac881c8e 5976 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
ebrus 0:6bc4ac881c8e 5977 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
ebrus 0:6bc4ac881c8e 5978 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
ebrus 0:6bc4ac881c8e 5979 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
ebrus 0:6bc4ac881c8e 5980
ebrus 0:6bc4ac881c8e 5981 /**
ebrus 0:6bc4ac881c8e 5982 * @brief EXTI13 configuration
ebrus 0:6bc4ac881c8e 5983 */
ebrus 0:6bc4ac881c8e 5984 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
ebrus 0:6bc4ac881c8e 5985 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
ebrus 0:6bc4ac881c8e 5986 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
ebrus 0:6bc4ac881c8e 5987 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
ebrus 0:6bc4ac881c8e 5988 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
ebrus 0:6bc4ac881c8e 5989 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
ebrus 0:6bc4ac881c8e 5990 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
ebrus 0:6bc4ac881c8e 5991 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
ebrus 0:6bc4ac881c8e 5992
ebrus 0:6bc4ac881c8e 5993 /**
ebrus 0:6bc4ac881c8e 5994 * @brief EXTI14 configuration
ebrus 0:6bc4ac881c8e 5995 */
ebrus 0:6bc4ac881c8e 5996 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
ebrus 0:6bc4ac881c8e 5997 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
ebrus 0:6bc4ac881c8e 5998 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
ebrus 0:6bc4ac881c8e 5999 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
ebrus 0:6bc4ac881c8e 6000 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
ebrus 0:6bc4ac881c8e 6001 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
ebrus 0:6bc4ac881c8e 6002 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
ebrus 0:6bc4ac881c8e 6003 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
ebrus 0:6bc4ac881c8e 6004
ebrus 0:6bc4ac881c8e 6005 /**
ebrus 0:6bc4ac881c8e 6006 * @brief EXTI15 configuration
ebrus 0:6bc4ac881c8e 6007 */
ebrus 0:6bc4ac881c8e 6008 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
ebrus 0:6bc4ac881c8e 6009 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
ebrus 0:6bc4ac881c8e 6010 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
ebrus 0:6bc4ac881c8e 6011 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
ebrus 0:6bc4ac881c8e 6012 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
ebrus 0:6bc4ac881c8e 6013 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
ebrus 0:6bc4ac881c8e 6014 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
ebrus 0:6bc4ac881c8e 6015 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
ebrus 0:6bc4ac881c8e 6016
ebrus 0:6bc4ac881c8e 6017 /****************** Bit definition for SYSCFG_CMPCR register ****************/
ebrus 0:6bc4ac881c8e 6018 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
ebrus 0:6bc4ac881c8e 6019 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
ebrus 0:6bc4ac881c8e 6020
ebrus 0:6bc4ac881c8e 6021 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6022 /* */
ebrus 0:6bc4ac881c8e 6023 /* TIM */
ebrus 0:6bc4ac881c8e 6024 /* */
ebrus 0:6bc4ac881c8e 6025 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6026 /******************* Bit definition for TIM_CR1 register ********************/
ebrus 0:6bc4ac881c8e 6027 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
ebrus 0:6bc4ac881c8e 6028 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
ebrus 0:6bc4ac881c8e 6029 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
ebrus 0:6bc4ac881c8e 6030 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
ebrus 0:6bc4ac881c8e 6031 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
ebrus 0:6bc4ac881c8e 6032
ebrus 0:6bc4ac881c8e 6033 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
ebrus 0:6bc4ac881c8e 6034 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6035 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6036
ebrus 0:6bc4ac881c8e 6037 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
ebrus 0:6bc4ac881c8e 6038
ebrus 0:6bc4ac881c8e 6039 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
ebrus 0:6bc4ac881c8e 6040 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6041 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6042
ebrus 0:6bc4ac881c8e 6043 /******************* Bit definition for TIM_CR2 register ********************/
ebrus 0:6bc4ac881c8e 6044 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
ebrus 0:6bc4ac881c8e 6045 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
ebrus 0:6bc4ac881c8e 6046 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
ebrus 0:6bc4ac881c8e 6047
ebrus 0:6bc4ac881c8e 6048 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
ebrus 0:6bc4ac881c8e 6049 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6050 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6051 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6052
ebrus 0:6bc4ac881c8e 6053 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
ebrus 0:6bc4ac881c8e 6054 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
ebrus 0:6bc4ac881c8e 6055 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
ebrus 0:6bc4ac881c8e 6056 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
ebrus 0:6bc4ac881c8e 6057 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
ebrus 0:6bc4ac881c8e 6058 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
ebrus 0:6bc4ac881c8e 6059 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
ebrus 0:6bc4ac881c8e 6060 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
ebrus 0:6bc4ac881c8e 6061
ebrus 0:6bc4ac881c8e 6062 /******************* Bit definition for TIM_SMCR register *******************/
ebrus 0:6bc4ac881c8e 6063 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
ebrus 0:6bc4ac881c8e 6064 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6065 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6066 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6067
ebrus 0:6bc4ac881c8e 6068 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
ebrus 0:6bc4ac881c8e 6069 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6070 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6071 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6072
ebrus 0:6bc4ac881c8e 6073 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
ebrus 0:6bc4ac881c8e 6074
ebrus 0:6bc4ac881c8e 6075 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
ebrus 0:6bc4ac881c8e 6076 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6077 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6078 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6079 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6080
ebrus 0:6bc4ac881c8e 6081 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
ebrus 0:6bc4ac881c8e 6082 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6083 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6084
ebrus 0:6bc4ac881c8e 6085 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
ebrus 0:6bc4ac881c8e 6086 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
ebrus 0:6bc4ac881c8e 6087
ebrus 0:6bc4ac881c8e 6088 /******************* Bit definition for TIM_DIER register *******************/
ebrus 0:6bc4ac881c8e 6089 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
ebrus 0:6bc4ac881c8e 6090 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
ebrus 0:6bc4ac881c8e 6091 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
ebrus 0:6bc4ac881c8e 6092 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
ebrus 0:6bc4ac881c8e 6093 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
ebrus 0:6bc4ac881c8e 6094 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
ebrus 0:6bc4ac881c8e 6095 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
ebrus 0:6bc4ac881c8e 6096 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
ebrus 0:6bc4ac881c8e 6097 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
ebrus 0:6bc4ac881c8e 6098 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
ebrus 0:6bc4ac881c8e 6099 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
ebrus 0:6bc4ac881c8e 6100 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
ebrus 0:6bc4ac881c8e 6101 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
ebrus 0:6bc4ac881c8e 6102 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
ebrus 0:6bc4ac881c8e 6103 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
ebrus 0:6bc4ac881c8e 6104
ebrus 0:6bc4ac881c8e 6105 /******************** Bit definition for TIM_SR register ********************/
ebrus 0:6bc4ac881c8e 6106 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
ebrus 0:6bc4ac881c8e 6107 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
ebrus 0:6bc4ac881c8e 6108 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
ebrus 0:6bc4ac881c8e 6109 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
ebrus 0:6bc4ac881c8e 6110 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
ebrus 0:6bc4ac881c8e 6111 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
ebrus 0:6bc4ac881c8e 6112 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
ebrus 0:6bc4ac881c8e 6113 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
ebrus 0:6bc4ac881c8e 6114 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
ebrus 0:6bc4ac881c8e 6115 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
ebrus 0:6bc4ac881c8e 6116 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
ebrus 0:6bc4ac881c8e 6117 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
ebrus 0:6bc4ac881c8e 6118
ebrus 0:6bc4ac881c8e 6119 /******************* Bit definition for TIM_EGR register ********************/
ebrus 0:6bc4ac881c8e 6120 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
ebrus 0:6bc4ac881c8e 6121 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
ebrus 0:6bc4ac881c8e 6122 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
ebrus 0:6bc4ac881c8e 6123 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
ebrus 0:6bc4ac881c8e 6124 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
ebrus 0:6bc4ac881c8e 6125 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
ebrus 0:6bc4ac881c8e 6126 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
ebrus 0:6bc4ac881c8e 6127 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
ebrus 0:6bc4ac881c8e 6128
ebrus 0:6bc4ac881c8e 6129 /****************** Bit definition for TIM_CCMR1 register *******************/
ebrus 0:6bc4ac881c8e 6130 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
ebrus 0:6bc4ac881c8e 6131 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6132 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6133
ebrus 0:6bc4ac881c8e 6134 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
ebrus 0:6bc4ac881c8e 6135 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
ebrus 0:6bc4ac881c8e 6136
ebrus 0:6bc4ac881c8e 6137 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
ebrus 0:6bc4ac881c8e 6138 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6139 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6140 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6141
ebrus 0:6bc4ac881c8e 6142 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
ebrus 0:6bc4ac881c8e 6143
ebrus 0:6bc4ac881c8e 6144 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
ebrus 0:6bc4ac881c8e 6145 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6146 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6147
ebrus 0:6bc4ac881c8e 6148 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
ebrus 0:6bc4ac881c8e 6149 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
ebrus 0:6bc4ac881c8e 6150
ebrus 0:6bc4ac881c8e 6151 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
ebrus 0:6bc4ac881c8e 6152 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6153 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6154 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6155
ebrus 0:6bc4ac881c8e 6156 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
ebrus 0:6bc4ac881c8e 6157
ebrus 0:6bc4ac881c8e 6158 /*----------------------------------------------------------------------------*/
ebrus 0:6bc4ac881c8e 6159
ebrus 0:6bc4ac881c8e 6160 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
ebrus 0:6bc4ac881c8e 6161 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6162 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6163
ebrus 0:6bc4ac881c8e 6164 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
ebrus 0:6bc4ac881c8e 6165 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6166 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6167 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6168 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6169
ebrus 0:6bc4ac881c8e 6170 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
ebrus 0:6bc4ac881c8e 6171 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6172 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6173
ebrus 0:6bc4ac881c8e 6174 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
ebrus 0:6bc4ac881c8e 6175 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6176 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6177 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6178 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6179
ebrus 0:6bc4ac881c8e 6180 /****************** Bit definition for TIM_CCMR2 register *******************/
ebrus 0:6bc4ac881c8e 6181 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
ebrus 0:6bc4ac881c8e 6182 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6183 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6184
ebrus 0:6bc4ac881c8e 6185 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
ebrus 0:6bc4ac881c8e 6186 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
ebrus 0:6bc4ac881c8e 6187
ebrus 0:6bc4ac881c8e 6188 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
ebrus 0:6bc4ac881c8e 6189 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6190 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6191 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6192
ebrus 0:6bc4ac881c8e 6193 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
ebrus 0:6bc4ac881c8e 6194
ebrus 0:6bc4ac881c8e 6195 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
ebrus 0:6bc4ac881c8e 6196 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6197 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6198
ebrus 0:6bc4ac881c8e 6199 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
ebrus 0:6bc4ac881c8e 6200 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
ebrus 0:6bc4ac881c8e 6201
ebrus 0:6bc4ac881c8e 6202 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
ebrus 0:6bc4ac881c8e 6203 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6204 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6205 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6206
ebrus 0:6bc4ac881c8e 6207 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
ebrus 0:6bc4ac881c8e 6208
ebrus 0:6bc4ac881c8e 6209 /*----------------------------------------------------------------------------*/
ebrus 0:6bc4ac881c8e 6210
ebrus 0:6bc4ac881c8e 6211 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
ebrus 0:6bc4ac881c8e 6212 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6213 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6214
ebrus 0:6bc4ac881c8e 6215 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
ebrus 0:6bc4ac881c8e 6216 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6217 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6218 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6219 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6220
ebrus 0:6bc4ac881c8e 6221 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
ebrus 0:6bc4ac881c8e 6222 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6223 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6224
ebrus 0:6bc4ac881c8e 6225 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
ebrus 0:6bc4ac881c8e 6226 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6227 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6228 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6229 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6230
ebrus 0:6bc4ac881c8e 6231 /******************* Bit definition for TIM_CCER register *******************/
ebrus 0:6bc4ac881c8e 6232 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
ebrus 0:6bc4ac881c8e 6233 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
ebrus 0:6bc4ac881c8e 6234 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
ebrus 0:6bc4ac881c8e 6235 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
ebrus 0:6bc4ac881c8e 6236 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
ebrus 0:6bc4ac881c8e 6237 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
ebrus 0:6bc4ac881c8e 6238 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
ebrus 0:6bc4ac881c8e 6239 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
ebrus 0:6bc4ac881c8e 6240 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
ebrus 0:6bc4ac881c8e 6241 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
ebrus 0:6bc4ac881c8e 6242 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
ebrus 0:6bc4ac881c8e 6243 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
ebrus 0:6bc4ac881c8e 6244 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
ebrus 0:6bc4ac881c8e 6245 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
ebrus 0:6bc4ac881c8e 6246 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
ebrus 0:6bc4ac881c8e 6247
ebrus 0:6bc4ac881c8e 6248 /******************* Bit definition for TIM_CNT register ********************/
ebrus 0:6bc4ac881c8e 6249 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
ebrus 0:6bc4ac881c8e 6250
ebrus 0:6bc4ac881c8e 6251 /******************* Bit definition for TIM_PSC register ********************/
ebrus 0:6bc4ac881c8e 6252 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
ebrus 0:6bc4ac881c8e 6253
ebrus 0:6bc4ac881c8e 6254 /******************* Bit definition for TIM_ARR register ********************/
ebrus 0:6bc4ac881c8e 6255 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
ebrus 0:6bc4ac881c8e 6256
ebrus 0:6bc4ac881c8e 6257 /******************* Bit definition for TIM_RCR register ********************/
ebrus 0:6bc4ac881c8e 6258 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
ebrus 0:6bc4ac881c8e 6259
ebrus 0:6bc4ac881c8e 6260 /******************* Bit definition for TIM_CCR1 register *******************/
ebrus 0:6bc4ac881c8e 6261 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
ebrus 0:6bc4ac881c8e 6262
ebrus 0:6bc4ac881c8e 6263 /******************* Bit definition for TIM_CCR2 register *******************/
ebrus 0:6bc4ac881c8e 6264 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
ebrus 0:6bc4ac881c8e 6265
ebrus 0:6bc4ac881c8e 6266 /******************* Bit definition for TIM_CCR3 register *******************/
ebrus 0:6bc4ac881c8e 6267 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
ebrus 0:6bc4ac881c8e 6268
ebrus 0:6bc4ac881c8e 6269 /******************* Bit definition for TIM_CCR4 register *******************/
ebrus 0:6bc4ac881c8e 6270 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
ebrus 0:6bc4ac881c8e 6271
ebrus 0:6bc4ac881c8e 6272 /******************* Bit definition for TIM_BDTR register *******************/
ebrus 0:6bc4ac881c8e 6273 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
ebrus 0:6bc4ac881c8e 6274 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6275 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6276 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6277 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6278 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6279 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 6280 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 6281 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 6282
ebrus 0:6bc4ac881c8e 6283 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
ebrus 0:6bc4ac881c8e 6284 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6285 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6286
ebrus 0:6bc4ac881c8e 6287 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
ebrus 0:6bc4ac881c8e 6288 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
ebrus 0:6bc4ac881c8e 6289 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
ebrus 0:6bc4ac881c8e 6290 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
ebrus 0:6bc4ac881c8e 6291 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
ebrus 0:6bc4ac881c8e 6292 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
ebrus 0:6bc4ac881c8e 6293
ebrus 0:6bc4ac881c8e 6294 /******************* Bit definition for TIM_DCR register ********************/
ebrus 0:6bc4ac881c8e 6295 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
ebrus 0:6bc4ac881c8e 6296 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6297 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6298 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6299 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6300 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6301
ebrus 0:6bc4ac881c8e 6302 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
ebrus 0:6bc4ac881c8e 6303 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6304 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6305 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6306 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6307 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6308
ebrus 0:6bc4ac881c8e 6309 /******************* Bit definition for TIM_DMAR register *******************/
ebrus 0:6bc4ac881c8e 6310 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
ebrus 0:6bc4ac881c8e 6311
ebrus 0:6bc4ac881c8e 6312 /******************* Bit definition for TIM_OR register *********************/
ebrus 0:6bc4ac881c8e 6313 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
ebrus 0:6bc4ac881c8e 6314 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6315 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6316 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
ebrus 0:6bc4ac881c8e 6317 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6318 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6319
ebrus 0:6bc4ac881c8e 6320
ebrus 0:6bc4ac881c8e 6321 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6322 /* */
ebrus 0:6bc4ac881c8e 6323 /* Universal Synchronous Asynchronous Receiver Transmitter */
ebrus 0:6bc4ac881c8e 6324 /* */
ebrus 0:6bc4ac881c8e 6325 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6326 /******************* Bit definition for USART_SR register *******************/
ebrus 0:6bc4ac881c8e 6327 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
ebrus 0:6bc4ac881c8e 6328 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
ebrus 0:6bc4ac881c8e 6329 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
ebrus 0:6bc4ac881c8e 6330 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
ebrus 0:6bc4ac881c8e 6331 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
ebrus 0:6bc4ac881c8e 6332 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
ebrus 0:6bc4ac881c8e 6333 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
ebrus 0:6bc4ac881c8e 6334 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
ebrus 0:6bc4ac881c8e 6335 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
ebrus 0:6bc4ac881c8e 6336 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
ebrus 0:6bc4ac881c8e 6337
ebrus 0:6bc4ac881c8e 6338 /******************* Bit definition for USART_DR register *******************/
ebrus 0:6bc4ac881c8e 6339 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
ebrus 0:6bc4ac881c8e 6340
ebrus 0:6bc4ac881c8e 6341 /****************** Bit definition for USART_BRR register *******************/
ebrus 0:6bc4ac881c8e 6342 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
ebrus 0:6bc4ac881c8e 6343 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
ebrus 0:6bc4ac881c8e 6344
ebrus 0:6bc4ac881c8e 6345 /****************** Bit definition for USART_CR1 register *******************/
ebrus 0:6bc4ac881c8e 6346 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
ebrus 0:6bc4ac881c8e 6347 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
ebrus 0:6bc4ac881c8e 6348 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
ebrus 0:6bc4ac881c8e 6349 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
ebrus 0:6bc4ac881c8e 6350 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
ebrus 0:6bc4ac881c8e 6351 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
ebrus 0:6bc4ac881c8e 6352 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
ebrus 0:6bc4ac881c8e 6353 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
ebrus 0:6bc4ac881c8e 6354 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
ebrus 0:6bc4ac881c8e 6355 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
ebrus 0:6bc4ac881c8e 6356 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
ebrus 0:6bc4ac881c8e 6357 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
ebrus 0:6bc4ac881c8e 6358 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
ebrus 0:6bc4ac881c8e 6359 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
ebrus 0:6bc4ac881c8e 6360 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
ebrus 0:6bc4ac881c8e 6361
ebrus 0:6bc4ac881c8e 6362 /****************** Bit definition for USART_CR2 register *******************/
ebrus 0:6bc4ac881c8e 6363 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
ebrus 0:6bc4ac881c8e 6364 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
ebrus 0:6bc4ac881c8e 6365 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
ebrus 0:6bc4ac881c8e 6366 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
ebrus 0:6bc4ac881c8e 6367 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
ebrus 0:6bc4ac881c8e 6368 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
ebrus 0:6bc4ac881c8e 6369 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
ebrus 0:6bc4ac881c8e 6370
ebrus 0:6bc4ac881c8e 6371 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
ebrus 0:6bc4ac881c8e 6372 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6373 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6374
ebrus 0:6bc4ac881c8e 6375 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
ebrus 0:6bc4ac881c8e 6376
ebrus 0:6bc4ac881c8e 6377 /****************** Bit definition for USART_CR3 register *******************/
ebrus 0:6bc4ac881c8e 6378 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
ebrus 0:6bc4ac881c8e 6379 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
ebrus 0:6bc4ac881c8e 6380 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
ebrus 0:6bc4ac881c8e 6381 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
ebrus 0:6bc4ac881c8e 6382 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
ebrus 0:6bc4ac881c8e 6383 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
ebrus 0:6bc4ac881c8e 6384 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
ebrus 0:6bc4ac881c8e 6385 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
ebrus 0:6bc4ac881c8e 6386 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
ebrus 0:6bc4ac881c8e 6387 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
ebrus 0:6bc4ac881c8e 6388 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
ebrus 0:6bc4ac881c8e 6389 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
ebrus 0:6bc4ac881c8e 6390
ebrus 0:6bc4ac881c8e 6391 /****************** Bit definition for USART_GTPR register ******************/
ebrus 0:6bc4ac881c8e 6392 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
ebrus 0:6bc4ac881c8e 6393 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6394 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6395 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6396 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6397 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6398 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 6399 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 6400 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 6401
ebrus 0:6bc4ac881c8e 6402 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
ebrus 0:6bc4ac881c8e 6403
ebrus 0:6bc4ac881c8e 6404 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6405 /* */
ebrus 0:6bc4ac881c8e 6406 /* Window WATCHDOG */
ebrus 0:6bc4ac881c8e 6407 /* */
ebrus 0:6bc4ac881c8e 6408 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6409 /******************* Bit definition for WWDG_CR register ********************/
ebrus 0:6bc4ac881c8e 6410 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
ebrus 0:6bc4ac881c8e 6411 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6412 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6413 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6414 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6415 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6416 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 6417 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 6418
ebrus 0:6bc4ac881c8e 6419 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
ebrus 0:6bc4ac881c8e 6420
ebrus 0:6bc4ac881c8e 6421 /******************* Bit definition for WWDG_CFR register *******************/
ebrus 0:6bc4ac881c8e 6422 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
ebrus 0:6bc4ac881c8e 6423 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6424 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6425 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6426 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6427 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6428 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 6429 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 6430
ebrus 0:6bc4ac881c8e 6431 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
ebrus 0:6bc4ac881c8e 6432 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6433 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6434
ebrus 0:6bc4ac881c8e 6435 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
ebrus 0:6bc4ac881c8e 6436
ebrus 0:6bc4ac881c8e 6437 /******************* Bit definition for WWDG_SR register ********************/
ebrus 0:6bc4ac881c8e 6438 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
ebrus 0:6bc4ac881c8e 6439
ebrus 0:6bc4ac881c8e 6440
ebrus 0:6bc4ac881c8e 6441 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6442 /* */
ebrus 0:6bc4ac881c8e 6443 /* DBG */
ebrus 0:6bc4ac881c8e 6444 /* */
ebrus 0:6bc4ac881c8e 6445 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6446 /******************** Bit definition for DBGMCU_IDCODE register *************/
ebrus 0:6bc4ac881c8e 6447 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
ebrus 0:6bc4ac881c8e 6448 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
ebrus 0:6bc4ac881c8e 6449
ebrus 0:6bc4ac881c8e 6450 /******************** Bit definition for DBGMCU_CR register *****************/
ebrus 0:6bc4ac881c8e 6451 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 6452 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 6453 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 6454 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 6455
ebrus 0:6bc4ac881c8e 6456 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
ebrus 0:6bc4ac881c8e 6457 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6458 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6459
ebrus 0:6bc4ac881c8e 6460 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
ebrus 0:6bc4ac881c8e 6461 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 6462 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 6463 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
ebrus 0:6bc4ac881c8e 6464 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
ebrus 0:6bc4ac881c8e 6465 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
ebrus 0:6bc4ac881c8e 6466 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
ebrus 0:6bc4ac881c8e 6467 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
ebrus 0:6bc4ac881c8e 6468 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
ebrus 0:6bc4ac881c8e 6469 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
ebrus 0:6bc4ac881c8e 6470 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
ebrus 0:6bc4ac881c8e 6471 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
ebrus 0:6bc4ac881c8e 6472 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
ebrus 0:6bc4ac881c8e 6473 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
ebrus 0:6bc4ac881c8e 6474 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
ebrus 0:6bc4ac881c8e 6475 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
ebrus 0:6bc4ac881c8e 6476 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
ebrus 0:6bc4ac881c8e 6477 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
ebrus 0:6bc4ac881c8e 6478 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
ebrus 0:6bc4ac881c8e 6479 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
ebrus 0:6bc4ac881c8e 6480
ebrus 0:6bc4ac881c8e 6481 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
ebrus 0:6bc4ac881c8e 6482 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
ebrus 0:6bc4ac881c8e 6483 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
ebrus 0:6bc4ac881c8e 6484 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
ebrus 0:6bc4ac881c8e 6485 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
ebrus 0:6bc4ac881c8e 6486 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
ebrus 0:6bc4ac881c8e 6487
ebrus 0:6bc4ac881c8e 6488 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6489 /* */
ebrus 0:6bc4ac881c8e 6490 /* Ethernet MAC Registers bits definitions */
ebrus 0:6bc4ac881c8e 6491 /* */
ebrus 0:6bc4ac881c8e 6492 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6493 /* Bit definition for Ethernet MAC Control Register register */
ebrus 0:6bc4ac881c8e 6494 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
ebrus 0:6bc4ac881c8e 6495 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
ebrus 0:6bc4ac881c8e 6496 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
ebrus 0:6bc4ac881c8e 6497 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
ebrus 0:6bc4ac881c8e 6498 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
ebrus 0:6bc4ac881c8e 6499 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
ebrus 0:6bc4ac881c8e 6500 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
ebrus 0:6bc4ac881c8e 6501 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
ebrus 0:6bc4ac881c8e 6502 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
ebrus 0:6bc4ac881c8e 6503 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
ebrus 0:6bc4ac881c8e 6504 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
ebrus 0:6bc4ac881c8e 6505 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
ebrus 0:6bc4ac881c8e 6506 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
ebrus 0:6bc4ac881c8e 6507 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
ebrus 0:6bc4ac881c8e 6508 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
ebrus 0:6bc4ac881c8e 6509 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
ebrus 0:6bc4ac881c8e 6510 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
ebrus 0:6bc4ac881c8e 6511 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
ebrus 0:6bc4ac881c8e 6512 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
ebrus 0:6bc4ac881c8e 6513 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
ebrus 0:6bc4ac881c8e 6514 a transmission attempt during retries after a collision: 0 =< r <2^k */
ebrus 0:6bc4ac881c8e 6515 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
ebrus 0:6bc4ac881c8e 6516 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
ebrus 0:6bc4ac881c8e 6517 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
ebrus 0:6bc4ac881c8e 6518 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
ebrus 0:6bc4ac881c8e 6519 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
ebrus 0:6bc4ac881c8e 6520 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
ebrus 0:6bc4ac881c8e 6521 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
ebrus 0:6bc4ac881c8e 6522
ebrus 0:6bc4ac881c8e 6523 /* Bit definition for Ethernet MAC Frame Filter Register */
ebrus 0:6bc4ac881c8e 6524 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
ebrus 0:6bc4ac881c8e 6525 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
ebrus 0:6bc4ac881c8e 6526 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
ebrus 0:6bc4ac881c8e 6527 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
ebrus 0:6bc4ac881c8e 6528 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
ebrus 0:6bc4ac881c8e 6529 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
ebrus 0:6bc4ac881c8e 6530 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
ebrus 0:6bc4ac881c8e 6531 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
ebrus 0:6bc4ac881c8e 6532 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
ebrus 0:6bc4ac881c8e 6533 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
ebrus 0:6bc4ac881c8e 6534 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
ebrus 0:6bc4ac881c8e 6535 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
ebrus 0:6bc4ac881c8e 6536 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
ebrus 0:6bc4ac881c8e 6537 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
ebrus 0:6bc4ac881c8e 6538
ebrus 0:6bc4ac881c8e 6539 /* Bit definition for Ethernet MAC Hash Table High Register */
ebrus 0:6bc4ac881c8e 6540 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
ebrus 0:6bc4ac881c8e 6541
ebrus 0:6bc4ac881c8e 6542 /* Bit definition for Ethernet MAC Hash Table Low Register */
ebrus 0:6bc4ac881c8e 6543 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
ebrus 0:6bc4ac881c8e 6544
ebrus 0:6bc4ac881c8e 6545 /* Bit definition for Ethernet MAC MII Address Register */
ebrus 0:6bc4ac881c8e 6546 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
ebrus 0:6bc4ac881c8e 6547 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
ebrus 0:6bc4ac881c8e 6548 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
ebrus 0:6bc4ac881c8e 6549 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
ebrus 0:6bc4ac881c8e 6550 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
ebrus 0:6bc4ac881c8e 6551 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
ebrus 0:6bc4ac881c8e 6552 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
ebrus 0:6bc4ac881c8e 6553 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
ebrus 0:6bc4ac881c8e 6554 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
ebrus 0:6bc4ac881c8e 6555 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
ebrus 0:6bc4ac881c8e 6556
ebrus 0:6bc4ac881c8e 6557 /* Bit definition for Ethernet MAC MII Data Register */
ebrus 0:6bc4ac881c8e 6558 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
ebrus 0:6bc4ac881c8e 6559
ebrus 0:6bc4ac881c8e 6560 /* Bit definition for Ethernet MAC Flow Control Register */
ebrus 0:6bc4ac881c8e 6561 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
ebrus 0:6bc4ac881c8e 6562 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
ebrus 0:6bc4ac881c8e 6563 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
ebrus 0:6bc4ac881c8e 6564 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
ebrus 0:6bc4ac881c8e 6565 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
ebrus 0:6bc4ac881c8e 6566 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
ebrus 0:6bc4ac881c8e 6567 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
ebrus 0:6bc4ac881c8e 6568 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
ebrus 0:6bc4ac881c8e 6569 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
ebrus 0:6bc4ac881c8e 6570 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
ebrus 0:6bc4ac881c8e 6571 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
ebrus 0:6bc4ac881c8e 6572
ebrus 0:6bc4ac881c8e 6573 /* Bit definition for Ethernet MAC VLAN Tag Register */
ebrus 0:6bc4ac881c8e 6574 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
ebrus 0:6bc4ac881c8e 6575 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
ebrus 0:6bc4ac881c8e 6576
ebrus 0:6bc4ac881c8e 6577 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
ebrus 0:6bc4ac881c8e 6578 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
ebrus 0:6bc4ac881c8e 6579 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
ebrus 0:6bc4ac881c8e 6580 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
ebrus 0:6bc4ac881c8e 6581 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
ebrus 0:6bc4ac881c8e 6582 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
ebrus 0:6bc4ac881c8e 6583 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
ebrus 0:6bc4ac881c8e 6584 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
ebrus 0:6bc4ac881c8e 6585 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
ebrus 0:6bc4ac881c8e 6586 RSVD - Filter1 Command - RSVD - Filter0 Command
ebrus 0:6bc4ac881c8e 6587 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
ebrus 0:6bc4ac881c8e 6588 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
ebrus 0:6bc4ac881c8e 6589 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
ebrus 0:6bc4ac881c8e 6590
ebrus 0:6bc4ac881c8e 6591 /* Bit definition for Ethernet MAC PMT Control and Status Register */
ebrus 0:6bc4ac881c8e 6592 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
ebrus 0:6bc4ac881c8e 6593 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
ebrus 0:6bc4ac881c8e 6594 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
ebrus 0:6bc4ac881c8e 6595 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
ebrus 0:6bc4ac881c8e 6596 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
ebrus 0:6bc4ac881c8e 6597 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
ebrus 0:6bc4ac881c8e 6598 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
ebrus 0:6bc4ac881c8e 6599
ebrus 0:6bc4ac881c8e 6600 /* Bit definition for Ethernet MAC Status Register */
ebrus 0:6bc4ac881c8e 6601 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
ebrus 0:6bc4ac881c8e 6602 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
ebrus 0:6bc4ac881c8e 6603 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
ebrus 0:6bc4ac881c8e 6604 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
ebrus 0:6bc4ac881c8e 6605 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
ebrus 0:6bc4ac881c8e 6606
ebrus 0:6bc4ac881c8e 6607 /* Bit definition for Ethernet MAC Interrupt Mask Register */
ebrus 0:6bc4ac881c8e 6608 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
ebrus 0:6bc4ac881c8e 6609 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
ebrus 0:6bc4ac881c8e 6610
ebrus 0:6bc4ac881c8e 6611 /* Bit definition for Ethernet MAC Address0 High Register */
ebrus 0:6bc4ac881c8e 6612 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
ebrus 0:6bc4ac881c8e 6613
ebrus 0:6bc4ac881c8e 6614 /* Bit definition for Ethernet MAC Address0 Low Register */
ebrus 0:6bc4ac881c8e 6615 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
ebrus 0:6bc4ac881c8e 6616
ebrus 0:6bc4ac881c8e 6617 /* Bit definition for Ethernet MAC Address1 High Register */
ebrus 0:6bc4ac881c8e 6618 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
ebrus 0:6bc4ac881c8e 6619 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
ebrus 0:6bc4ac881c8e 6620 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
ebrus 0:6bc4ac881c8e 6621 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
ebrus 0:6bc4ac881c8e 6622 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
ebrus 0:6bc4ac881c8e 6623 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
ebrus 0:6bc4ac881c8e 6624 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
ebrus 0:6bc4ac881c8e 6625 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
ebrus 0:6bc4ac881c8e 6626 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
ebrus 0:6bc4ac881c8e 6627 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
ebrus 0:6bc4ac881c8e 6628
ebrus 0:6bc4ac881c8e 6629 /* Bit definition for Ethernet MAC Address1 Low Register */
ebrus 0:6bc4ac881c8e 6630 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
ebrus 0:6bc4ac881c8e 6631
ebrus 0:6bc4ac881c8e 6632 /* Bit definition for Ethernet MAC Address2 High Register */
ebrus 0:6bc4ac881c8e 6633 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
ebrus 0:6bc4ac881c8e 6634 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
ebrus 0:6bc4ac881c8e 6635 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
ebrus 0:6bc4ac881c8e 6636 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
ebrus 0:6bc4ac881c8e 6637 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
ebrus 0:6bc4ac881c8e 6638 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
ebrus 0:6bc4ac881c8e 6639 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
ebrus 0:6bc4ac881c8e 6640 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
ebrus 0:6bc4ac881c8e 6641 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
ebrus 0:6bc4ac881c8e 6642 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
ebrus 0:6bc4ac881c8e 6643
ebrus 0:6bc4ac881c8e 6644 /* Bit definition for Ethernet MAC Address2 Low Register */
ebrus 0:6bc4ac881c8e 6645 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
ebrus 0:6bc4ac881c8e 6646
ebrus 0:6bc4ac881c8e 6647 /* Bit definition for Ethernet MAC Address3 High Register */
ebrus 0:6bc4ac881c8e 6648 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
ebrus 0:6bc4ac881c8e 6649 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
ebrus 0:6bc4ac881c8e 6650 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
ebrus 0:6bc4ac881c8e 6651 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
ebrus 0:6bc4ac881c8e 6652 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
ebrus 0:6bc4ac881c8e 6653 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
ebrus 0:6bc4ac881c8e 6654 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
ebrus 0:6bc4ac881c8e 6655 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
ebrus 0:6bc4ac881c8e 6656 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
ebrus 0:6bc4ac881c8e 6657 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
ebrus 0:6bc4ac881c8e 6658
ebrus 0:6bc4ac881c8e 6659 /* Bit definition for Ethernet MAC Address3 Low Register */
ebrus 0:6bc4ac881c8e 6660 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
ebrus 0:6bc4ac881c8e 6661
ebrus 0:6bc4ac881c8e 6662 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6663 /* Ethernet MMC Registers bits definition */
ebrus 0:6bc4ac881c8e 6664 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6665
ebrus 0:6bc4ac881c8e 6666 /* Bit definition for Ethernet MMC Contol Register */
ebrus 0:6bc4ac881c8e 6667 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
ebrus 0:6bc4ac881c8e 6668 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
ebrus 0:6bc4ac881c8e 6669 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
ebrus 0:6bc4ac881c8e 6670 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
ebrus 0:6bc4ac881c8e 6671 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
ebrus 0:6bc4ac881c8e 6672 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
ebrus 0:6bc4ac881c8e 6673
ebrus 0:6bc4ac881c8e 6674 /* Bit definition for Ethernet MMC Receive Interrupt Register */
ebrus 0:6bc4ac881c8e 6675 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6676 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6677 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6678
ebrus 0:6bc4ac881c8e 6679 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
ebrus 0:6bc4ac881c8e 6680 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6681 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6682 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6683
ebrus 0:6bc4ac881c8e 6684 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
ebrus 0:6bc4ac881c8e 6685 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6686 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6687 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6688
ebrus 0:6bc4ac881c8e 6689 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
ebrus 0:6bc4ac881c8e 6690 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6691 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6692 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
ebrus 0:6bc4ac881c8e 6693
ebrus 0:6bc4ac881c8e 6694 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
ebrus 0:6bc4ac881c8e 6695 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
ebrus 0:6bc4ac881c8e 6696
ebrus 0:6bc4ac881c8e 6697 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
ebrus 0:6bc4ac881c8e 6698 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
ebrus 0:6bc4ac881c8e 6699
ebrus 0:6bc4ac881c8e 6700 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
ebrus 0:6bc4ac881c8e 6701 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
ebrus 0:6bc4ac881c8e 6702
ebrus 0:6bc4ac881c8e 6703 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
ebrus 0:6bc4ac881c8e 6704 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
ebrus 0:6bc4ac881c8e 6705
ebrus 0:6bc4ac881c8e 6706 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
ebrus 0:6bc4ac881c8e 6707 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
ebrus 0:6bc4ac881c8e 6708
ebrus 0:6bc4ac881c8e 6709 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
ebrus 0:6bc4ac881c8e 6710 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
ebrus 0:6bc4ac881c8e 6711
ebrus 0:6bc4ac881c8e 6712 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6713 /* Ethernet PTP Registers bits definition */
ebrus 0:6bc4ac881c8e 6714 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6715
ebrus 0:6bc4ac881c8e 6716 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
ebrus 0:6bc4ac881c8e 6717 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
ebrus 0:6bc4ac881c8e 6718 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
ebrus 0:6bc4ac881c8e 6719 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
ebrus 0:6bc4ac881c8e 6720 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
ebrus 0:6bc4ac881c8e 6721 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
ebrus 0:6bc4ac881c8e 6722 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
ebrus 0:6bc4ac881c8e 6723 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
ebrus 0:6bc4ac881c8e 6724 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
ebrus 0:6bc4ac881c8e 6725 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
ebrus 0:6bc4ac881c8e 6726
ebrus 0:6bc4ac881c8e 6727 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
ebrus 0:6bc4ac881c8e 6728 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
ebrus 0:6bc4ac881c8e 6729 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
ebrus 0:6bc4ac881c8e 6730 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
ebrus 0:6bc4ac881c8e 6731 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
ebrus 0:6bc4ac881c8e 6732 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
ebrus 0:6bc4ac881c8e 6733
ebrus 0:6bc4ac881c8e 6734 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
ebrus 0:6bc4ac881c8e 6735 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
ebrus 0:6bc4ac881c8e 6736
ebrus 0:6bc4ac881c8e 6737 /* Bit definition for Ethernet PTP Time Stamp High Register */
ebrus 0:6bc4ac881c8e 6738 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
ebrus 0:6bc4ac881c8e 6739
ebrus 0:6bc4ac881c8e 6740 /* Bit definition for Ethernet PTP Time Stamp Low Register */
ebrus 0:6bc4ac881c8e 6741 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
ebrus 0:6bc4ac881c8e 6742 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
ebrus 0:6bc4ac881c8e 6743
ebrus 0:6bc4ac881c8e 6744 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
ebrus 0:6bc4ac881c8e 6745 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
ebrus 0:6bc4ac881c8e 6746
ebrus 0:6bc4ac881c8e 6747 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
ebrus 0:6bc4ac881c8e 6748 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
ebrus 0:6bc4ac881c8e 6749 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
ebrus 0:6bc4ac881c8e 6750
ebrus 0:6bc4ac881c8e 6751 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
ebrus 0:6bc4ac881c8e 6752 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
ebrus 0:6bc4ac881c8e 6753
ebrus 0:6bc4ac881c8e 6754 /* Bit definition for Ethernet PTP Target Time High Register */
ebrus 0:6bc4ac881c8e 6755 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
ebrus 0:6bc4ac881c8e 6756
ebrus 0:6bc4ac881c8e 6757 /* Bit definition for Ethernet PTP Target Time Low Register */
ebrus 0:6bc4ac881c8e 6758 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
ebrus 0:6bc4ac881c8e 6759
ebrus 0:6bc4ac881c8e 6760 /* Bit definition for Ethernet PTP Time Stamp Status Register */
ebrus 0:6bc4ac881c8e 6761 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
ebrus 0:6bc4ac881c8e 6762 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
ebrus 0:6bc4ac881c8e 6763
ebrus 0:6bc4ac881c8e 6764 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6765 /* Ethernet DMA Registers bits definition */
ebrus 0:6bc4ac881c8e 6766 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6767
ebrus 0:6bc4ac881c8e 6768 /* Bit definition for Ethernet DMA Bus Mode Register */
ebrus 0:6bc4ac881c8e 6769 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
ebrus 0:6bc4ac881c8e 6770 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
ebrus 0:6bc4ac881c8e 6771 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
ebrus 0:6bc4ac881c8e 6772 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
ebrus 0:6bc4ac881c8e 6773 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
ebrus 0:6bc4ac881c8e 6774 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
ebrus 0:6bc4ac881c8e 6775 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
ebrus 0:6bc4ac881c8e 6776 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
ebrus 0:6bc4ac881c8e 6777 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
ebrus 0:6bc4ac881c8e 6778 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
ebrus 0:6bc4ac881c8e 6779 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
ebrus 0:6bc4ac881c8e 6780 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
ebrus 0:6bc4ac881c8e 6781 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
ebrus 0:6bc4ac881c8e 6782 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
ebrus 0:6bc4ac881c8e 6783 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
ebrus 0:6bc4ac881c8e 6784 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
ebrus 0:6bc4ac881c8e 6785 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
ebrus 0:6bc4ac881c8e 6786 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
ebrus 0:6bc4ac881c8e 6787 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
ebrus 0:6bc4ac881c8e 6788 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
ebrus 0:6bc4ac881c8e 6789 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
ebrus 0:6bc4ac881c8e 6790 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
ebrus 0:6bc4ac881c8e 6791 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
ebrus 0:6bc4ac881c8e 6792 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
ebrus 0:6bc4ac881c8e 6793 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
ebrus 0:6bc4ac881c8e 6794 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
ebrus 0:6bc4ac881c8e 6795 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
ebrus 0:6bc4ac881c8e 6796 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
ebrus 0:6bc4ac881c8e 6797 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
ebrus 0:6bc4ac881c8e 6798 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
ebrus 0:6bc4ac881c8e 6799 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
ebrus 0:6bc4ac881c8e 6800 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
ebrus 0:6bc4ac881c8e 6801 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
ebrus 0:6bc4ac881c8e 6802 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
ebrus 0:6bc4ac881c8e 6803 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
ebrus 0:6bc4ac881c8e 6804 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
ebrus 0:6bc4ac881c8e 6805 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
ebrus 0:6bc4ac881c8e 6806 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
ebrus 0:6bc4ac881c8e 6807 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
ebrus 0:6bc4ac881c8e 6808
ebrus 0:6bc4ac881c8e 6809 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
ebrus 0:6bc4ac881c8e 6810 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
ebrus 0:6bc4ac881c8e 6811
ebrus 0:6bc4ac881c8e 6812 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
ebrus 0:6bc4ac881c8e 6813 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
ebrus 0:6bc4ac881c8e 6814
ebrus 0:6bc4ac881c8e 6815 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
ebrus 0:6bc4ac881c8e 6816 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
ebrus 0:6bc4ac881c8e 6817
ebrus 0:6bc4ac881c8e 6818 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
ebrus 0:6bc4ac881c8e 6819 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
ebrus 0:6bc4ac881c8e 6820
ebrus 0:6bc4ac881c8e 6821 /* Bit definition for Ethernet DMA Status Register */
ebrus 0:6bc4ac881c8e 6822 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
ebrus 0:6bc4ac881c8e 6823 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
ebrus 0:6bc4ac881c8e 6824 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
ebrus 0:6bc4ac881c8e 6825 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
ebrus 0:6bc4ac881c8e 6826 /* combination with EBS[2:0] for GetFlagStatus function */
ebrus 0:6bc4ac881c8e 6827 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
ebrus 0:6bc4ac881c8e 6828 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
ebrus 0:6bc4ac881c8e 6829 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
ebrus 0:6bc4ac881c8e 6830 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
ebrus 0:6bc4ac881c8e 6831 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
ebrus 0:6bc4ac881c8e 6832 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
ebrus 0:6bc4ac881c8e 6833 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
ebrus 0:6bc4ac881c8e 6834 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
ebrus 0:6bc4ac881c8e 6835 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
ebrus 0:6bc4ac881c8e 6836 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
ebrus 0:6bc4ac881c8e 6837 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
ebrus 0:6bc4ac881c8e 6838 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
ebrus 0:6bc4ac881c8e 6839 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
ebrus 0:6bc4ac881c8e 6840 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
ebrus 0:6bc4ac881c8e 6841 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
ebrus 0:6bc4ac881c8e 6842 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
ebrus 0:6bc4ac881c8e 6843 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
ebrus 0:6bc4ac881c8e 6844 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
ebrus 0:6bc4ac881c8e 6845 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
ebrus 0:6bc4ac881c8e 6846 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
ebrus 0:6bc4ac881c8e 6847 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
ebrus 0:6bc4ac881c8e 6848 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
ebrus 0:6bc4ac881c8e 6849 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
ebrus 0:6bc4ac881c8e 6850 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
ebrus 0:6bc4ac881c8e 6851 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
ebrus 0:6bc4ac881c8e 6852 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
ebrus 0:6bc4ac881c8e 6853 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
ebrus 0:6bc4ac881c8e 6854 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
ebrus 0:6bc4ac881c8e 6855 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
ebrus 0:6bc4ac881c8e 6856 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
ebrus 0:6bc4ac881c8e 6857 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
ebrus 0:6bc4ac881c8e 6858 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
ebrus 0:6bc4ac881c8e 6859
ebrus 0:6bc4ac881c8e 6860 /* Bit definition for Ethernet DMA Operation Mode Register */
ebrus 0:6bc4ac881c8e 6861 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
ebrus 0:6bc4ac881c8e 6862 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
ebrus 0:6bc4ac881c8e 6863 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
ebrus 0:6bc4ac881c8e 6864 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
ebrus 0:6bc4ac881c8e 6865 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
ebrus 0:6bc4ac881c8e 6866 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
ebrus 0:6bc4ac881c8e 6867 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
ebrus 0:6bc4ac881c8e 6868 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
ebrus 0:6bc4ac881c8e 6869 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
ebrus 0:6bc4ac881c8e 6870 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
ebrus 0:6bc4ac881c8e 6871 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
ebrus 0:6bc4ac881c8e 6872 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
ebrus 0:6bc4ac881c8e 6873 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
ebrus 0:6bc4ac881c8e 6874 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
ebrus 0:6bc4ac881c8e 6875 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
ebrus 0:6bc4ac881c8e 6876 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
ebrus 0:6bc4ac881c8e 6877 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
ebrus 0:6bc4ac881c8e 6878 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
ebrus 0:6bc4ac881c8e 6879 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
ebrus 0:6bc4ac881c8e 6880 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
ebrus 0:6bc4ac881c8e 6881 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
ebrus 0:6bc4ac881c8e 6882 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
ebrus 0:6bc4ac881c8e 6883 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
ebrus 0:6bc4ac881c8e 6884 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
ebrus 0:6bc4ac881c8e 6885
ebrus 0:6bc4ac881c8e 6886 /* Bit definition for Ethernet DMA Interrupt Enable Register */
ebrus 0:6bc4ac881c8e 6887 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
ebrus 0:6bc4ac881c8e 6888 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
ebrus 0:6bc4ac881c8e 6889 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
ebrus 0:6bc4ac881c8e 6890 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
ebrus 0:6bc4ac881c8e 6891 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
ebrus 0:6bc4ac881c8e 6892 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
ebrus 0:6bc4ac881c8e 6893 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
ebrus 0:6bc4ac881c8e 6894 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
ebrus 0:6bc4ac881c8e 6895 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
ebrus 0:6bc4ac881c8e 6896 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
ebrus 0:6bc4ac881c8e 6897 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
ebrus 0:6bc4ac881c8e 6898 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
ebrus 0:6bc4ac881c8e 6899 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
ebrus 0:6bc4ac881c8e 6900 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
ebrus 0:6bc4ac881c8e 6901 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
ebrus 0:6bc4ac881c8e 6902
ebrus 0:6bc4ac881c8e 6903 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
ebrus 0:6bc4ac881c8e 6904 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
ebrus 0:6bc4ac881c8e 6905 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
ebrus 0:6bc4ac881c8e 6906 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
ebrus 0:6bc4ac881c8e 6907 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
ebrus 0:6bc4ac881c8e 6908
ebrus 0:6bc4ac881c8e 6909 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
ebrus 0:6bc4ac881c8e 6910 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
ebrus 0:6bc4ac881c8e 6911
ebrus 0:6bc4ac881c8e 6912 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
ebrus 0:6bc4ac881c8e 6913 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
ebrus 0:6bc4ac881c8e 6914
ebrus 0:6bc4ac881c8e 6915 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
ebrus 0:6bc4ac881c8e 6916 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
ebrus 0:6bc4ac881c8e 6917
ebrus 0:6bc4ac881c8e 6918 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
ebrus 0:6bc4ac881c8e 6919 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
ebrus 0:6bc4ac881c8e 6920
ebrus 0:6bc4ac881c8e 6921 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6922 /* */
ebrus 0:6bc4ac881c8e 6923 /* USB_OTG */
ebrus 0:6bc4ac881c8e 6924 /* */
ebrus 0:6bc4ac881c8e 6925 /******************************************************************************/
ebrus 0:6bc4ac881c8e 6926 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
ebrus 0:6bc4ac881c8e 6927 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
ebrus 0:6bc4ac881c8e 6928 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
ebrus 0:6bc4ac881c8e 6929 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
ebrus 0:6bc4ac881c8e 6930 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
ebrus 0:6bc4ac881c8e 6931 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
ebrus 0:6bc4ac881c8e 6932 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
ebrus 0:6bc4ac881c8e 6933 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
ebrus 0:6bc4ac881c8e 6934 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
ebrus 0:6bc4ac881c8e 6935 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
ebrus 0:6bc4ac881c8e 6936 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
ebrus 0:6bc4ac881c8e 6937
ebrus 0:6bc4ac881c8e 6938 /******************** Bit definition forUSB_OTG_HCFG register ********************/
ebrus 0:6bc4ac881c8e 6939
ebrus 0:6bc4ac881c8e 6940 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
ebrus 0:6bc4ac881c8e 6941 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6942 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6943 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
ebrus 0:6bc4ac881c8e 6944
ebrus 0:6bc4ac881c8e 6945 /******************** Bit definition forUSB_OTG_DCFG register ********************/
ebrus 0:6bc4ac881c8e 6946
ebrus 0:6bc4ac881c8e 6947 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
ebrus 0:6bc4ac881c8e 6948 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6949 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6950 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
ebrus 0:6bc4ac881c8e 6951
ebrus 0:6bc4ac881c8e 6952 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
ebrus 0:6bc4ac881c8e 6953 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6954 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6955 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6956 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 6957 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 6958 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 6959 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 6960
ebrus 0:6bc4ac881c8e 6961 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
ebrus 0:6bc4ac881c8e 6962 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6963 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6964
ebrus 0:6bc4ac881c8e 6965 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
ebrus 0:6bc4ac881c8e 6966 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6967 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6968
ebrus 0:6bc4ac881c8e 6969 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
ebrus 0:6bc4ac881c8e 6970 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
ebrus 0:6bc4ac881c8e 6971 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
ebrus 0:6bc4ac881c8e 6972 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
ebrus 0:6bc4ac881c8e 6973
ebrus 0:6bc4ac881c8e 6974 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
ebrus 0:6bc4ac881c8e 6975 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
ebrus 0:6bc4ac881c8e 6976 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
ebrus 0:6bc4ac881c8e 6977 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
ebrus 0:6bc4ac881c8e 6978 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
ebrus 0:6bc4ac881c8e 6979 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
ebrus 0:6bc4ac881c8e 6980 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
ebrus 0:6bc4ac881c8e 6981
ebrus 0:6bc4ac881c8e 6982 /******************** Bit definition forUSB_OTG_DCTL register ********************/
ebrus 0:6bc4ac881c8e 6983 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
ebrus 0:6bc4ac881c8e 6984 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
ebrus 0:6bc4ac881c8e 6985 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
ebrus 0:6bc4ac881c8e 6986 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
ebrus 0:6bc4ac881c8e 6987
ebrus 0:6bc4ac881c8e 6988 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
ebrus 0:6bc4ac881c8e 6989 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 6990 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 6991 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 6992 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
ebrus 0:6bc4ac881c8e 6993 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
ebrus 0:6bc4ac881c8e 6994 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
ebrus 0:6bc4ac881c8e 6995 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
ebrus 0:6bc4ac881c8e 6996 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
ebrus 0:6bc4ac881c8e 6997
ebrus 0:6bc4ac881c8e 6998 /******************** Bit definition forUSB_OTG_HFIR register ********************/
ebrus 0:6bc4ac881c8e 6999 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
ebrus 0:6bc4ac881c8e 7000
ebrus 0:6bc4ac881c8e 7001 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
ebrus 0:6bc4ac881c8e 7002 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
ebrus 0:6bc4ac881c8e 7003 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
ebrus 0:6bc4ac881c8e 7004
ebrus 0:6bc4ac881c8e 7005 /******************** Bit definition forUSB_OTG_DSTS register ********************/
ebrus 0:6bc4ac881c8e 7006 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
ebrus 0:6bc4ac881c8e 7007
ebrus 0:6bc4ac881c8e 7008 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
ebrus 0:6bc4ac881c8e 7009 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7010 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7011 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
ebrus 0:6bc4ac881c8e 7012 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
ebrus 0:6bc4ac881c8e 7013
ebrus 0:6bc4ac881c8e 7014 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
ebrus 0:6bc4ac881c8e 7015 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
ebrus 0:6bc4ac881c8e 7016
ebrus 0:6bc4ac881c8e 7017 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
ebrus 0:6bc4ac881c8e 7018 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7019 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7020 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7021 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7022 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
ebrus 0:6bc4ac881c8e 7023 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
ebrus 0:6bc4ac881c8e 7024 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
ebrus 0:6bc4ac881c8e 7025
ebrus 0:6bc4ac881c8e 7026 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
ebrus 0:6bc4ac881c8e 7027
ebrus 0:6bc4ac881c8e 7028 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
ebrus 0:6bc4ac881c8e 7029 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7030 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7031 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7032 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
ebrus 0:6bc4ac881c8e 7033 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
ebrus 0:6bc4ac881c8e 7034 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
ebrus 0:6bc4ac881c8e 7035
ebrus 0:6bc4ac881c8e 7036 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
ebrus 0:6bc4ac881c8e 7037 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7038 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7039 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7040 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7041 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
ebrus 0:6bc4ac881c8e 7042 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
ebrus 0:6bc4ac881c8e 7043 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
ebrus 0:6bc4ac881c8e 7044 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
ebrus 0:6bc4ac881c8e 7045 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
ebrus 0:6bc4ac881c8e 7046 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
ebrus 0:6bc4ac881c8e 7047 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
ebrus 0:6bc4ac881c8e 7048 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
ebrus 0:6bc4ac881c8e 7049 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
ebrus 0:6bc4ac881c8e 7050 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
ebrus 0:6bc4ac881c8e 7051 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
ebrus 0:6bc4ac881c8e 7052 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
ebrus 0:6bc4ac881c8e 7053 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
ebrus 0:6bc4ac881c8e 7054
ebrus 0:6bc4ac881c8e 7055 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
ebrus 0:6bc4ac881c8e 7056 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
ebrus 0:6bc4ac881c8e 7057 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
ebrus 0:6bc4ac881c8e 7058 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
ebrus 0:6bc4ac881c8e 7059 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
ebrus 0:6bc4ac881c8e 7060 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
ebrus 0:6bc4ac881c8e 7061
ebrus 0:6bc4ac881c8e 7062 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
ebrus 0:6bc4ac881c8e 7063 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7064 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7065 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7066 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7067 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7068 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
ebrus 0:6bc4ac881c8e 7069 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
ebrus 0:6bc4ac881c8e 7070
ebrus 0:6bc4ac881c8e 7071 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
ebrus 0:6bc4ac881c8e 7072 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
ebrus 0:6bc4ac881c8e 7073 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
ebrus 0:6bc4ac881c8e 7074 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
ebrus 0:6bc4ac881c8e 7075 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
ebrus 0:6bc4ac881c8e 7076 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
ebrus 0:6bc4ac881c8e 7077 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
ebrus 0:6bc4ac881c8e 7078 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
ebrus 0:6bc4ac881c8e 7079 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
ebrus 0:6bc4ac881c8e 7080
ebrus 0:6bc4ac881c8e 7081 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
ebrus 0:6bc4ac881c8e 7082 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
ebrus 0:6bc4ac881c8e 7083
ebrus 0:6bc4ac881c8e 7084 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
ebrus 0:6bc4ac881c8e 7085 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7086 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7087 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7088 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7089 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7090 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7091 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7092 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 7093
ebrus 0:6bc4ac881c8e 7094 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
ebrus 0:6bc4ac881c8e 7095 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7096 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7097 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7098 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7099 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7100 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7101 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7102 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 7103
ebrus 0:6bc4ac881c8e 7104 /******************** Bit definition forUSB_OTG_HAINT register ********************/
ebrus 0:6bc4ac881c8e 7105 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
ebrus 0:6bc4ac881c8e 7106
ebrus 0:6bc4ac881c8e 7107 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
ebrus 0:6bc4ac881c8e 7108 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
ebrus 0:6bc4ac881c8e 7109 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
ebrus 0:6bc4ac881c8e 7110 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
ebrus 0:6bc4ac881c8e 7111 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
ebrus 0:6bc4ac881c8e 7112 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
ebrus 0:6bc4ac881c8e 7113 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
ebrus 0:6bc4ac881c8e 7114 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
ebrus 0:6bc4ac881c8e 7115
ebrus 0:6bc4ac881c8e 7116 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
ebrus 0:6bc4ac881c8e 7117 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
ebrus 0:6bc4ac881c8e 7118 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
ebrus 0:6bc4ac881c8e 7119 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
ebrus 0:6bc4ac881c8e 7120 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
ebrus 0:6bc4ac881c8e 7121 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
ebrus 0:6bc4ac881c8e 7122 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
ebrus 0:6bc4ac881c8e 7123 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
ebrus 0:6bc4ac881c8e 7124 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
ebrus 0:6bc4ac881c8e 7125 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
ebrus 0:6bc4ac881c8e 7126 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
ebrus 0:6bc4ac881c8e 7127 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
ebrus 0:6bc4ac881c8e 7128 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
ebrus 0:6bc4ac881c8e 7129 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
ebrus 0:6bc4ac881c8e 7130 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
ebrus 0:6bc4ac881c8e 7131 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
ebrus 0:6bc4ac881c8e 7132 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
ebrus 0:6bc4ac881c8e 7133 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
ebrus 0:6bc4ac881c8e 7134 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
ebrus 0:6bc4ac881c8e 7135 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
ebrus 0:6bc4ac881c8e 7136 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
ebrus 0:6bc4ac881c8e 7137 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
ebrus 0:6bc4ac881c8e 7138 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
ebrus 0:6bc4ac881c8e 7139 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
ebrus 0:6bc4ac881c8e 7140 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
ebrus 0:6bc4ac881c8e 7141 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
ebrus 0:6bc4ac881c8e 7142 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
ebrus 0:6bc4ac881c8e 7143
ebrus 0:6bc4ac881c8e 7144 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
ebrus 0:6bc4ac881c8e 7145 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
ebrus 0:6bc4ac881c8e 7146 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
ebrus 0:6bc4ac881c8e 7147 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
ebrus 0:6bc4ac881c8e 7148 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
ebrus 0:6bc4ac881c8e 7149 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
ebrus 0:6bc4ac881c8e 7150 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
ebrus 0:6bc4ac881c8e 7151 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
ebrus 0:6bc4ac881c8e 7152 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
ebrus 0:6bc4ac881c8e 7153 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
ebrus 0:6bc4ac881c8e 7154 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
ebrus 0:6bc4ac881c8e 7155 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
ebrus 0:6bc4ac881c8e 7156 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
ebrus 0:6bc4ac881c8e 7157 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
ebrus 0:6bc4ac881c8e 7158 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
ebrus 0:6bc4ac881c8e 7159 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
ebrus 0:6bc4ac881c8e 7160 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
ebrus 0:6bc4ac881c8e 7161 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
ebrus 0:6bc4ac881c8e 7162 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
ebrus 0:6bc4ac881c8e 7163 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
ebrus 0:6bc4ac881c8e 7164 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
ebrus 0:6bc4ac881c8e 7165 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
ebrus 0:6bc4ac881c8e 7166 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
ebrus 0:6bc4ac881c8e 7167 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
ebrus 0:6bc4ac881c8e 7168 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
ebrus 0:6bc4ac881c8e 7169 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
ebrus 0:6bc4ac881c8e 7170 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
ebrus 0:6bc4ac881c8e 7171
ebrus 0:6bc4ac881c8e 7172 /******************** Bit definition forUSB_OTG_DAINT register ********************/
ebrus 0:6bc4ac881c8e 7173 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
ebrus 0:6bc4ac881c8e 7174 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
ebrus 0:6bc4ac881c8e 7175
ebrus 0:6bc4ac881c8e 7176 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
ebrus 0:6bc4ac881c8e 7177 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
ebrus 0:6bc4ac881c8e 7178
ebrus 0:6bc4ac881c8e 7179 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
ebrus 0:6bc4ac881c8e 7180 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
ebrus 0:6bc4ac881c8e 7181 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
ebrus 0:6bc4ac881c8e 7182 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
ebrus 0:6bc4ac881c8e 7183 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
ebrus 0:6bc4ac881c8e 7184
ebrus 0:6bc4ac881c8e 7185 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
ebrus 0:6bc4ac881c8e 7186 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
ebrus 0:6bc4ac881c8e 7187 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
ebrus 0:6bc4ac881c8e 7188
ebrus 0:6bc4ac881c8e 7189 /******************** Bit definition for OTG register ********************/
ebrus 0:6bc4ac881c8e 7190
ebrus 0:6bc4ac881c8e 7191 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
ebrus 0:6bc4ac881c8e 7192 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7193 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7194 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7195 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7196 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
ebrus 0:6bc4ac881c8e 7197
ebrus 0:6bc4ac881c8e 7198 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
ebrus 0:6bc4ac881c8e 7199 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7200 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7201
ebrus 0:6bc4ac881c8e 7202 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
ebrus 0:6bc4ac881c8e 7203 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7204 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7205 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7206 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7207
ebrus 0:6bc4ac881c8e 7208 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
ebrus 0:6bc4ac881c8e 7209 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7210 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7211 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7212 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7213
ebrus 0:6bc4ac881c8e 7214 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
ebrus 0:6bc4ac881c8e 7215 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7216 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7217 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7218 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7219
ebrus 0:6bc4ac881c8e 7220 /******************** Bit definition for OTG register ********************/
ebrus 0:6bc4ac881c8e 7221
ebrus 0:6bc4ac881c8e 7222 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
ebrus 0:6bc4ac881c8e 7223 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7224 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7225 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7226 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7227 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
ebrus 0:6bc4ac881c8e 7228
ebrus 0:6bc4ac881c8e 7229 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
ebrus 0:6bc4ac881c8e 7230 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7231 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7232
ebrus 0:6bc4ac881c8e 7233 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
ebrus 0:6bc4ac881c8e 7234 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7235 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7236 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7237 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7238
ebrus 0:6bc4ac881c8e 7239 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
ebrus 0:6bc4ac881c8e 7240 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7241 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7242 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7243 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7244
ebrus 0:6bc4ac881c8e 7245 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
ebrus 0:6bc4ac881c8e 7246 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7247 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7248 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7249 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7250
ebrus 0:6bc4ac881c8e 7251 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
ebrus 0:6bc4ac881c8e 7252 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
ebrus 0:6bc4ac881c8e 7253
ebrus 0:6bc4ac881c8e 7254 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
ebrus 0:6bc4ac881c8e 7255 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
ebrus 0:6bc4ac881c8e 7256
ebrus 0:6bc4ac881c8e 7257 /******************** Bit definition for OTG register ********************/
ebrus 0:6bc4ac881c8e 7258 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
ebrus 0:6bc4ac881c8e 7259 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
ebrus 0:6bc4ac881c8e 7260 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
ebrus 0:6bc4ac881c8e 7261 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
ebrus 0:6bc4ac881c8e 7262
ebrus 0:6bc4ac881c8e 7263 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
ebrus 0:6bc4ac881c8e 7264 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
ebrus 0:6bc4ac881c8e 7265
ebrus 0:6bc4ac881c8e 7266 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
ebrus 0:6bc4ac881c8e 7267 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
ebrus 0:6bc4ac881c8e 7268
ebrus 0:6bc4ac881c8e 7269 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
ebrus 0:6bc4ac881c8e 7270 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7271 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7272 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7273 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7274 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7275 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7276 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7277 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 7278
ebrus 0:6bc4ac881c8e 7279 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
ebrus 0:6bc4ac881c8e 7280 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7281 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7282 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7283 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7284 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7285 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7286 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7287
ebrus 0:6bc4ac881c8e 7288 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
ebrus 0:6bc4ac881c8e 7289 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
ebrus 0:6bc4ac881c8e 7290 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
ebrus 0:6bc4ac881c8e 7291
ebrus 0:6bc4ac881c8e 7292 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
ebrus 0:6bc4ac881c8e 7293 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7294 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7295 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7296 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7297 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7298 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7299 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7300 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 7301 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
ebrus 0:6bc4ac881c8e 7302 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
ebrus 0:6bc4ac881c8e 7303
ebrus 0:6bc4ac881c8e 7304 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
ebrus 0:6bc4ac881c8e 7305 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7306 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7307 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7308 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7309 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7310 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7311 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7312 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
ebrus 0:6bc4ac881c8e 7313 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
ebrus 0:6bc4ac881c8e 7314 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
ebrus 0:6bc4ac881c8e 7315
ebrus 0:6bc4ac881c8e 7316 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
ebrus 0:6bc4ac881c8e 7317 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
ebrus 0:6bc4ac881c8e 7318
ebrus 0:6bc4ac881c8e 7319 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
ebrus 0:6bc4ac881c8e 7320 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
ebrus 0:6bc4ac881c8e 7321 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
ebrus 0:6bc4ac881c8e 7322
ebrus 0:6bc4ac881c8e 7323 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
ebrus 0:6bc4ac881c8e 7324 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
ebrus 0:6bc4ac881c8e 7325 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
ebrus 0:6bc4ac881c8e 7326 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
ebrus 0:6bc4ac881c8e 7327 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
ebrus 0:6bc4ac881c8e 7328 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
ebrus 0:6bc4ac881c8e 7329 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
ebrus 0:6bc4ac881c8e 7330
ebrus 0:6bc4ac881c8e 7331 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
ebrus 0:6bc4ac881c8e 7332 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
ebrus 0:6bc4ac881c8e 7333 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
ebrus 0:6bc4ac881c8e 7334
ebrus 0:6bc4ac881c8e 7335 /******************** Bit definition forUSB_OTG_CID register ********************/
ebrus 0:6bc4ac881c8e 7336 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
ebrus 0:6bc4ac881c8e 7337
ebrus 0:6bc4ac881c8e 7338 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
ebrus 0:6bc4ac881c8e 7339 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
ebrus 0:6bc4ac881c8e 7340 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
ebrus 0:6bc4ac881c8e 7341 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
ebrus 0:6bc4ac881c8e 7342 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
ebrus 0:6bc4ac881c8e 7343 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
ebrus 0:6bc4ac881c8e 7344 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
ebrus 0:6bc4ac881c8e 7345 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
ebrus 0:6bc4ac881c8e 7346 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
ebrus 0:6bc4ac881c8e 7347 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
ebrus 0:6bc4ac881c8e 7348
ebrus 0:6bc4ac881c8e 7349 /******************** Bit definition forUSB_OTG_HPRT register ********************/
ebrus 0:6bc4ac881c8e 7350 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
ebrus 0:6bc4ac881c8e 7351 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
ebrus 0:6bc4ac881c8e 7352 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
ebrus 0:6bc4ac881c8e 7353 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
ebrus 0:6bc4ac881c8e 7354 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
ebrus 0:6bc4ac881c8e 7355 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
ebrus 0:6bc4ac881c8e 7356 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
ebrus 0:6bc4ac881c8e 7357 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
ebrus 0:6bc4ac881c8e 7358 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
ebrus 0:6bc4ac881c8e 7359
ebrus 0:6bc4ac881c8e 7360 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
ebrus 0:6bc4ac881c8e 7361 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7362 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7363 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
ebrus 0:6bc4ac881c8e 7364
ebrus 0:6bc4ac881c8e 7365 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
ebrus 0:6bc4ac881c8e 7366 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7367 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7368 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7369 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7370
ebrus 0:6bc4ac881c8e 7371 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
ebrus 0:6bc4ac881c8e 7372 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7373 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7374
ebrus 0:6bc4ac881c8e 7375 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
ebrus 0:6bc4ac881c8e 7376 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
ebrus 0:6bc4ac881c8e 7377 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
ebrus 0:6bc4ac881c8e 7378 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
ebrus 0:6bc4ac881c8e 7379 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
ebrus 0:6bc4ac881c8e 7380 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
ebrus 0:6bc4ac881c8e 7381 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
ebrus 0:6bc4ac881c8e 7382 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
ebrus 0:6bc4ac881c8e 7383 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
ebrus 0:6bc4ac881c8e 7384 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
ebrus 0:6bc4ac881c8e 7385 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
ebrus 0:6bc4ac881c8e 7386 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
ebrus 0:6bc4ac881c8e 7387
ebrus 0:6bc4ac881c8e 7388 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
ebrus 0:6bc4ac881c8e 7389 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
ebrus 0:6bc4ac881c8e 7390 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
ebrus 0:6bc4ac881c8e 7391
ebrus 0:6bc4ac881c8e 7392 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
ebrus 0:6bc4ac881c8e 7393 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
ebrus 0:6bc4ac881c8e 7394 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
ebrus 0:6bc4ac881c8e 7395 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
ebrus 0:6bc4ac881c8e 7396 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
ebrus 0:6bc4ac881c8e 7397
ebrus 0:6bc4ac881c8e 7398 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
ebrus 0:6bc4ac881c8e 7399 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7400 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7401 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
ebrus 0:6bc4ac881c8e 7402
ebrus 0:6bc4ac881c8e 7403 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
ebrus 0:6bc4ac881c8e 7404 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7405 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7406 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7407 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7408 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
ebrus 0:6bc4ac881c8e 7409 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
ebrus 0:6bc4ac881c8e 7410 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
ebrus 0:6bc4ac881c8e 7411 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
ebrus 0:6bc4ac881c8e 7412 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
ebrus 0:6bc4ac881c8e 7413 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
ebrus 0:6bc4ac881c8e 7414
ebrus 0:6bc4ac881c8e 7415 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
ebrus 0:6bc4ac881c8e 7416 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
ebrus 0:6bc4ac881c8e 7417
ebrus 0:6bc4ac881c8e 7418 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
ebrus 0:6bc4ac881c8e 7419 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7420 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7421 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7422 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7423 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
ebrus 0:6bc4ac881c8e 7424 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
ebrus 0:6bc4ac881c8e 7425
ebrus 0:6bc4ac881c8e 7426 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
ebrus 0:6bc4ac881c8e 7427 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7428 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7429
ebrus 0:6bc4ac881c8e 7430 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
ebrus 0:6bc4ac881c8e 7431 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7432 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7433
ebrus 0:6bc4ac881c8e 7434 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
ebrus 0:6bc4ac881c8e 7435 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7436 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7437 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7438 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7439 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7440 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7441 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7442 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
ebrus 0:6bc4ac881c8e 7443 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
ebrus 0:6bc4ac881c8e 7444 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
ebrus 0:6bc4ac881c8e 7445
ebrus 0:6bc4ac881c8e 7446 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
ebrus 0:6bc4ac881c8e 7447
ebrus 0:6bc4ac881c8e 7448 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
ebrus 0:6bc4ac881c8e 7449 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7450 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7451 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7452 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7453 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7454 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7455 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7456
ebrus 0:6bc4ac881c8e 7457 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
ebrus 0:6bc4ac881c8e 7458 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7459 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7460 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
ebrus 0:6bc4ac881c8e 7461 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
ebrus 0:6bc4ac881c8e 7462 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
ebrus 0:6bc4ac881c8e 7463 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
ebrus 0:6bc4ac881c8e 7464 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
ebrus 0:6bc4ac881c8e 7465
ebrus 0:6bc4ac881c8e 7466 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
ebrus 0:6bc4ac881c8e 7467 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7468 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7469 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
ebrus 0:6bc4ac881c8e 7470 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
ebrus 0:6bc4ac881c8e 7471
ebrus 0:6bc4ac881c8e 7472 /******************** Bit definition forUSB_OTG_HCINT register ********************/
ebrus 0:6bc4ac881c8e 7473 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
ebrus 0:6bc4ac881c8e 7474 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
ebrus 0:6bc4ac881c8e 7475 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
ebrus 0:6bc4ac881c8e 7476 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
ebrus 0:6bc4ac881c8e 7477 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
ebrus 0:6bc4ac881c8e 7478 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
ebrus 0:6bc4ac881c8e 7479 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
ebrus 0:6bc4ac881c8e 7480 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
ebrus 0:6bc4ac881c8e 7481 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
ebrus 0:6bc4ac881c8e 7482 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
ebrus 0:6bc4ac881c8e 7483 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
ebrus 0:6bc4ac881c8e 7484
ebrus 0:6bc4ac881c8e 7485 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
ebrus 0:6bc4ac881c8e 7486 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
ebrus 0:6bc4ac881c8e 7487 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
ebrus 0:6bc4ac881c8e 7488 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
ebrus 0:6bc4ac881c8e 7489 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
ebrus 0:6bc4ac881c8e 7490 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
ebrus 0:6bc4ac881c8e 7491 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
ebrus 0:6bc4ac881c8e 7492 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
ebrus 0:6bc4ac881c8e 7493 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
ebrus 0:6bc4ac881c8e 7494 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
ebrus 0:6bc4ac881c8e 7495 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
ebrus 0:6bc4ac881c8e 7496 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
ebrus 0:6bc4ac881c8e 7497
ebrus 0:6bc4ac881c8e 7498 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
ebrus 0:6bc4ac881c8e 7499 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
ebrus 0:6bc4ac881c8e 7500 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
ebrus 0:6bc4ac881c8e 7501 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
ebrus 0:6bc4ac881c8e 7502 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
ebrus 0:6bc4ac881c8e 7503 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
ebrus 0:6bc4ac881c8e 7504 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
ebrus 0:6bc4ac881c8e 7505 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
ebrus 0:6bc4ac881c8e 7506 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
ebrus 0:6bc4ac881c8e 7507 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
ebrus 0:6bc4ac881c8e 7508 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
ebrus 0:6bc4ac881c8e 7509 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
ebrus 0:6bc4ac881c8e 7510
ebrus 0:6bc4ac881c8e 7511 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
ebrus 0:6bc4ac881c8e 7512
ebrus 0:6bc4ac881c8e 7513 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
ebrus 0:6bc4ac881c8e 7514 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
ebrus 0:6bc4ac881c8e 7515 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
ebrus 0:6bc4ac881c8e 7516 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
ebrus 0:6bc4ac881c8e 7517 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
ebrus 0:6bc4ac881c8e 7518 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
ebrus 0:6bc4ac881c8e 7519 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
ebrus 0:6bc4ac881c8e 7520 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
ebrus 0:6bc4ac881c8e 7521 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7522 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7523
ebrus 0:6bc4ac881c8e 7524 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
ebrus 0:6bc4ac881c8e 7525 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
ebrus 0:6bc4ac881c8e 7526
ebrus 0:6bc4ac881c8e 7527 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
ebrus 0:6bc4ac881c8e 7528 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
ebrus 0:6bc4ac881c8e 7529
ebrus 0:6bc4ac881c8e 7530 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
ebrus 0:6bc4ac881c8e 7531 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
ebrus 0:6bc4ac881c8e 7532
ebrus 0:6bc4ac881c8e 7533 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
ebrus 0:6bc4ac881c8e 7534 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
ebrus 0:6bc4ac881c8e 7535 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
ebrus 0:6bc4ac881c8e 7536
ebrus 0:6bc4ac881c8e 7537 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
ebrus 0:6bc4ac881c8e 7538
ebrus 0:6bc4ac881c8e 7539 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7540 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
ebrus 0:6bc4ac881c8e 7541 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
ebrus 0:6bc4ac881c8e 7542 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
ebrus 0:6bc4ac881c8e 7543 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
ebrus 0:6bc4ac881c8e 7544 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
ebrus 0:6bc4ac881c8e 7545 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7546 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7547 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
ebrus 0:6bc4ac881c8e 7548 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
ebrus 0:6bc4ac881c8e 7549 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
ebrus 0:6bc4ac881c8e 7550 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
ebrus 0:6bc4ac881c8e 7551 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
ebrus 0:6bc4ac881c8e 7552 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
ebrus 0:6bc4ac881c8e 7553
ebrus 0:6bc4ac881c8e 7554 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
ebrus 0:6bc4ac881c8e 7555 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
ebrus 0:6bc4ac881c8e 7556 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
ebrus 0:6bc4ac881c8e 7557 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
ebrus 0:6bc4ac881c8e 7558 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
ebrus 0:6bc4ac881c8e 7559 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
ebrus 0:6bc4ac881c8e 7560 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
ebrus 0:6bc4ac881c8e 7561
ebrus 0:6bc4ac881c8e 7562 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
ebrus 0:6bc4ac881c8e 7563
ebrus 0:6bc4ac881c8e 7564 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
ebrus 0:6bc4ac881c8e 7565 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
ebrus 0:6bc4ac881c8e 7566
ebrus 0:6bc4ac881c8e 7567 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
ebrus 0:6bc4ac881c8e 7568 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7569 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7570
ebrus 0:6bc4ac881c8e 7571 /******************** Bit definition for PCGCCTL register ********************/
ebrus 0:6bc4ac881c8e 7572 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
ebrus 0:6bc4ac881c8e 7573 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
ebrus 0:6bc4ac881c8e 7574 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
ebrus 0:6bc4ac881c8e 7575
ebrus 0:6bc4ac881c8e 7576 /**
ebrus 0:6bc4ac881c8e 7577 * @}
ebrus 0:6bc4ac881c8e 7578 */
ebrus 0:6bc4ac881c8e 7579
ebrus 0:6bc4ac881c8e 7580 /**
ebrus 0:6bc4ac881c8e 7581 * @}
ebrus 0:6bc4ac881c8e 7582 */
ebrus 0:6bc4ac881c8e 7583
ebrus 0:6bc4ac881c8e 7584 /** @addtogroup Exported_macros
ebrus 0:6bc4ac881c8e 7585 * @{
ebrus 0:6bc4ac881c8e 7586 */
ebrus 0:6bc4ac881c8e 7587
ebrus 0:6bc4ac881c8e 7588 /******************************* ADC Instances ********************************/
ebrus 0:6bc4ac881c8e 7589 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
ebrus 0:6bc4ac881c8e 7590 ((INSTANCE) == ADC2) || \
ebrus 0:6bc4ac881c8e 7591 ((INSTANCE) == ADC3))
ebrus 0:6bc4ac881c8e 7592
ebrus 0:6bc4ac881c8e 7593 /******************************* CAN Instances ********************************/
ebrus 0:6bc4ac881c8e 7594 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
ebrus 0:6bc4ac881c8e 7595 ((INSTANCE) == CAN2))
ebrus 0:6bc4ac881c8e 7596
ebrus 0:6bc4ac881c8e 7597 /******************************* CRC Instances ********************************/
ebrus 0:6bc4ac881c8e 7598 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
ebrus 0:6bc4ac881c8e 7599
ebrus 0:6bc4ac881c8e 7600 /******************************* DAC Instances ********************************/
ebrus 0:6bc4ac881c8e 7601 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
ebrus 0:6bc4ac881c8e 7602
ebrus 0:6bc4ac881c8e 7603 /******************************* DCMI Instances *******************************/
ebrus 0:6bc4ac881c8e 7604 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
ebrus 0:6bc4ac881c8e 7605
ebrus 0:6bc4ac881c8e 7606 /******************************** DMA Instances *******************************/
ebrus 0:6bc4ac881c8e 7607 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
ebrus 0:6bc4ac881c8e 7608 ((INSTANCE) == DMA1_Stream1) || \
ebrus 0:6bc4ac881c8e 7609 ((INSTANCE) == DMA1_Stream2) || \
ebrus 0:6bc4ac881c8e 7610 ((INSTANCE) == DMA1_Stream3) || \
ebrus 0:6bc4ac881c8e 7611 ((INSTANCE) == DMA1_Stream4) || \
ebrus 0:6bc4ac881c8e 7612 ((INSTANCE) == DMA1_Stream5) || \
ebrus 0:6bc4ac881c8e 7613 ((INSTANCE) == DMA1_Stream6) || \
ebrus 0:6bc4ac881c8e 7614 ((INSTANCE) == DMA1_Stream7) || \
ebrus 0:6bc4ac881c8e 7615 ((INSTANCE) == DMA2_Stream0) || \
ebrus 0:6bc4ac881c8e 7616 ((INSTANCE) == DMA2_Stream1) || \
ebrus 0:6bc4ac881c8e 7617 ((INSTANCE) == DMA2_Stream2) || \
ebrus 0:6bc4ac881c8e 7618 ((INSTANCE) == DMA2_Stream3) || \
ebrus 0:6bc4ac881c8e 7619 ((INSTANCE) == DMA2_Stream4) || \
ebrus 0:6bc4ac881c8e 7620 ((INSTANCE) == DMA2_Stream5) || \
ebrus 0:6bc4ac881c8e 7621 ((INSTANCE) == DMA2_Stream6) || \
ebrus 0:6bc4ac881c8e 7622 ((INSTANCE) == DMA2_Stream7))
ebrus 0:6bc4ac881c8e 7623
ebrus 0:6bc4ac881c8e 7624 /******************************* GPIO Instances *******************************/
ebrus 0:6bc4ac881c8e 7625 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
ebrus 0:6bc4ac881c8e 7626 ((INSTANCE) == GPIOB) || \
ebrus 0:6bc4ac881c8e 7627 ((INSTANCE) == GPIOC) || \
ebrus 0:6bc4ac881c8e 7628 ((INSTANCE) == GPIOD) || \
ebrus 0:6bc4ac881c8e 7629 ((INSTANCE) == GPIOE) || \
ebrus 0:6bc4ac881c8e 7630 ((INSTANCE) == GPIOF) || \
ebrus 0:6bc4ac881c8e 7631 ((INSTANCE) == GPIOG) || \
ebrus 0:6bc4ac881c8e 7632 ((INSTANCE) == GPIOH) || \
ebrus 0:6bc4ac881c8e 7633 ((INSTANCE) == GPIOI))
ebrus 0:6bc4ac881c8e 7634
ebrus 0:6bc4ac881c8e 7635 /******************************** I2C Instances *******************************/
ebrus 0:6bc4ac881c8e 7636 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
ebrus 0:6bc4ac881c8e 7637 ((INSTANCE) == I2C2) || \
ebrus 0:6bc4ac881c8e 7638 ((INSTANCE) == I2C3))
ebrus 0:6bc4ac881c8e 7639
ebrus 0:6bc4ac881c8e 7640 /******************************** I2S Instances *******************************/
ebrus 0:6bc4ac881c8e 7641 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
ebrus 0:6bc4ac881c8e 7642 ((INSTANCE) == SPI3))
ebrus 0:6bc4ac881c8e 7643
ebrus 0:6bc4ac881c8e 7644 /*************************** I2S Extended Instances ***************************/
ebrus 0:6bc4ac881c8e 7645 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
ebrus 0:6bc4ac881c8e 7646 ((INSTANCE) == SPI3) || \
ebrus 0:6bc4ac881c8e 7647 ((INSTANCE) == I2S2ext) || \
ebrus 0:6bc4ac881c8e 7648 ((INSTANCE) == I2S3ext))
ebrus 0:6bc4ac881c8e 7649
ebrus 0:6bc4ac881c8e 7650 /******************************* RNG Instances ********************************/
ebrus 0:6bc4ac881c8e 7651 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
ebrus 0:6bc4ac881c8e 7652
ebrus 0:6bc4ac881c8e 7653 /****************************** RTC Instances *********************************/
ebrus 0:6bc4ac881c8e 7654 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
ebrus 0:6bc4ac881c8e 7655
ebrus 0:6bc4ac881c8e 7656 /******************************** SPI Instances *******************************/
ebrus 0:6bc4ac881c8e 7657 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
ebrus 0:6bc4ac881c8e 7658 ((INSTANCE) == SPI2) || \
ebrus 0:6bc4ac881c8e 7659 ((INSTANCE) == SPI3))
ebrus 0:6bc4ac881c8e 7660
ebrus 0:6bc4ac881c8e 7661 /*************************** SPI Extended Instances ***************************/
ebrus 0:6bc4ac881c8e 7662 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
ebrus 0:6bc4ac881c8e 7663 ((INSTANCE) == SPI2) || \
ebrus 0:6bc4ac881c8e 7664 ((INSTANCE) == SPI3) || \
ebrus 0:6bc4ac881c8e 7665 ((INSTANCE) == I2S2ext) || \
ebrus 0:6bc4ac881c8e 7666 ((INSTANCE) == I2S3ext))
ebrus 0:6bc4ac881c8e 7667
ebrus 0:6bc4ac881c8e 7668 /****************** TIM Instances : All supported instances *******************/
ebrus 0:6bc4ac881c8e 7669 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7670 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7671 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7672 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7673 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7674 ((INSTANCE) == TIM6) || \
ebrus 0:6bc4ac881c8e 7675 ((INSTANCE) == TIM7) || \
ebrus 0:6bc4ac881c8e 7676 ((INSTANCE) == TIM8) || \
ebrus 0:6bc4ac881c8e 7677 ((INSTANCE) == TIM9) || \
ebrus 0:6bc4ac881c8e 7678 ((INSTANCE) == TIM10) || \
ebrus 0:6bc4ac881c8e 7679 ((INSTANCE) == TIM11) || \
ebrus 0:6bc4ac881c8e 7680 ((INSTANCE) == TIM12) || \
ebrus 0:6bc4ac881c8e 7681 ((INSTANCE) == TIM13) || \
ebrus 0:6bc4ac881c8e 7682 ((INSTANCE) == TIM14))
ebrus 0:6bc4ac881c8e 7683
ebrus 0:6bc4ac881c8e 7684 /************* TIM Instances : at least 1 capture/compare channel *************/
ebrus 0:6bc4ac881c8e 7685 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7686 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7687 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7688 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7689 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7690 ((INSTANCE) == TIM8) || \
ebrus 0:6bc4ac881c8e 7691 ((INSTANCE) == TIM9) || \
ebrus 0:6bc4ac881c8e 7692 ((INSTANCE) == TIM10) || \
ebrus 0:6bc4ac881c8e 7693 ((INSTANCE) == TIM11) || \
ebrus 0:6bc4ac881c8e 7694 ((INSTANCE) == TIM12) || \
ebrus 0:6bc4ac881c8e 7695 ((INSTANCE) == TIM13) || \
ebrus 0:6bc4ac881c8e 7696 ((INSTANCE) == TIM14))
ebrus 0:6bc4ac881c8e 7697
ebrus 0:6bc4ac881c8e 7698 /************ TIM Instances : at least 2 capture/compare channels *************/
ebrus 0:6bc4ac881c8e 7699 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7700 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7701 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7702 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7703 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7704 ((INSTANCE) == TIM8) || \
ebrus 0:6bc4ac881c8e 7705 ((INSTANCE) == TIM9) || \
ebrus 0:6bc4ac881c8e 7706 ((INSTANCE) == TIM12))
ebrus 0:6bc4ac881c8e 7707
ebrus 0:6bc4ac881c8e 7708 /************ TIM Instances : at least 3 capture/compare channels *************/
ebrus 0:6bc4ac881c8e 7709 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7710 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7711 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7712 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7713 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7714 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7715
ebrus 0:6bc4ac881c8e 7716 /************ TIM Instances : at least 4 capture/compare channels *************/
ebrus 0:6bc4ac881c8e 7717 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7718 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7719 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7720 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7721 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7722 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7723
ebrus 0:6bc4ac881c8e 7724 /******************** TIM Instances : Advanced-control timers *****************/
ebrus 0:6bc4ac881c8e 7725 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7726 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7727
ebrus 0:6bc4ac881c8e 7728 /******************* TIM Instances : Timer input XOR function *****************/
ebrus 0:6bc4ac881c8e 7729 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7730 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7731 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7732 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7733 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7734 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7735
ebrus 0:6bc4ac881c8e 7736 /****************** TIM Instances : DMA requests generation (UDE) *************/
ebrus 0:6bc4ac881c8e 7737 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7738 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7739 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7740 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7741 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7742 ((INSTANCE) == TIM6) || \
ebrus 0:6bc4ac881c8e 7743 ((INSTANCE) == TIM7) || \
ebrus 0:6bc4ac881c8e 7744 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7745
ebrus 0:6bc4ac881c8e 7746 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
ebrus 0:6bc4ac881c8e 7747 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7748 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7749 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7750 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7751 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7752 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7753
ebrus 0:6bc4ac881c8e 7754 /************ TIM Instances : DMA requests generation (COMDE) *****************/
ebrus 0:6bc4ac881c8e 7755 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7756 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7757 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7758 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7759 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7760 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7761
ebrus 0:6bc4ac881c8e 7762 /******************** TIM Instances : DMA burst feature ***********************/
ebrus 0:6bc4ac881c8e 7763 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7764 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7765 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7766 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7767 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7768 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7769
ebrus 0:6bc4ac881c8e 7770 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
ebrus 0:6bc4ac881c8e 7771 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7772 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7773 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7774 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7775 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7776 ((INSTANCE) == TIM6) || \
ebrus 0:6bc4ac881c8e 7777 ((INSTANCE) == TIM7) || \
ebrus 0:6bc4ac881c8e 7778 ((INSTANCE) == TIM8) || \
ebrus 0:6bc4ac881c8e 7779 ((INSTANCE) == TIM9) || \
ebrus 0:6bc4ac881c8e 7780 ((INSTANCE) == TIM12))
ebrus 0:6bc4ac881c8e 7781
ebrus 0:6bc4ac881c8e 7782 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
ebrus 0:6bc4ac881c8e 7783 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7784 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7785 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7786 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7787 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7788 ((INSTANCE) == TIM8) || \
ebrus 0:6bc4ac881c8e 7789 ((INSTANCE) == TIM9) || \
ebrus 0:6bc4ac881c8e 7790 ((INSTANCE) == TIM12))
ebrus 0:6bc4ac881c8e 7791
ebrus 0:6bc4ac881c8e 7792 /********************** TIM Instances : 32 bit Counter ************************/
ebrus 0:6bc4ac881c8e 7793 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7794 ((INSTANCE) == TIM5))
ebrus 0:6bc4ac881c8e 7795
ebrus 0:6bc4ac881c8e 7796 /***************** TIM Instances : external trigger input availabe ************/
ebrus 0:6bc4ac881c8e 7797 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
ebrus 0:6bc4ac881c8e 7798 ((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7799 ((INSTANCE) == TIM3) || \
ebrus 0:6bc4ac881c8e 7800 ((INSTANCE) == TIM4) || \
ebrus 0:6bc4ac881c8e 7801 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7802 ((INSTANCE) == TIM8))
ebrus 0:6bc4ac881c8e 7803
ebrus 0:6bc4ac881c8e 7804 /****************** TIM Instances : remapping capability **********************/
ebrus 0:6bc4ac881c8e 7805 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
ebrus 0:6bc4ac881c8e 7806 ((INSTANCE) == TIM5) || \
ebrus 0:6bc4ac881c8e 7807 ((INSTANCE) == TIM11))
ebrus 0:6bc4ac881c8e 7808
ebrus 0:6bc4ac881c8e 7809 /******************* TIM Instances : output(s) available **********************/
ebrus 0:6bc4ac881c8e 7810 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
ebrus 0:6bc4ac881c8e 7811 ((((INSTANCE) == TIM1) && \
ebrus 0:6bc4ac881c8e 7812 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7813 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7814 ((CHANNEL) == TIM_CHANNEL_3) || \
ebrus 0:6bc4ac881c8e 7815 ((CHANNEL) == TIM_CHANNEL_4))) \
ebrus 0:6bc4ac881c8e 7816 || \
ebrus 0:6bc4ac881c8e 7817 (((INSTANCE) == TIM2) && \
ebrus 0:6bc4ac881c8e 7818 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7819 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7820 ((CHANNEL) == TIM_CHANNEL_3) || \
ebrus 0:6bc4ac881c8e 7821 ((CHANNEL) == TIM_CHANNEL_4))) \
ebrus 0:6bc4ac881c8e 7822 || \
ebrus 0:6bc4ac881c8e 7823 (((INSTANCE) == TIM3) && \
ebrus 0:6bc4ac881c8e 7824 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7825 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7826 ((CHANNEL) == TIM_CHANNEL_3) || \
ebrus 0:6bc4ac881c8e 7827 ((CHANNEL) == TIM_CHANNEL_4))) \
ebrus 0:6bc4ac881c8e 7828 || \
ebrus 0:6bc4ac881c8e 7829 (((INSTANCE) == TIM4) && \
ebrus 0:6bc4ac881c8e 7830 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7831 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7832 ((CHANNEL) == TIM_CHANNEL_3) || \
ebrus 0:6bc4ac881c8e 7833 ((CHANNEL) == TIM_CHANNEL_4))) \
ebrus 0:6bc4ac881c8e 7834 || \
ebrus 0:6bc4ac881c8e 7835 (((INSTANCE) == TIM5) && \
ebrus 0:6bc4ac881c8e 7836 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7837 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7838 ((CHANNEL) == TIM_CHANNEL_3) || \
ebrus 0:6bc4ac881c8e 7839 ((CHANNEL) == TIM_CHANNEL_4))) \
ebrus 0:6bc4ac881c8e 7840 || \
ebrus 0:6bc4ac881c8e 7841 (((INSTANCE) == TIM8) && \
ebrus 0:6bc4ac881c8e 7842 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7843 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7844 ((CHANNEL) == TIM_CHANNEL_3) || \
ebrus 0:6bc4ac881c8e 7845 ((CHANNEL) == TIM_CHANNEL_4))) \
ebrus 0:6bc4ac881c8e 7846 || \
ebrus 0:6bc4ac881c8e 7847 (((INSTANCE) == TIM9) && \
ebrus 0:6bc4ac881c8e 7848 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7849 ((CHANNEL) == TIM_CHANNEL_2))) \
ebrus 0:6bc4ac881c8e 7850 || \
ebrus 0:6bc4ac881c8e 7851 (((INSTANCE) == TIM10) && \
ebrus 0:6bc4ac881c8e 7852 (((CHANNEL) == TIM_CHANNEL_1))) \
ebrus 0:6bc4ac881c8e 7853 || \
ebrus 0:6bc4ac881c8e 7854 (((INSTANCE) == TIM11) && \
ebrus 0:6bc4ac881c8e 7855 (((CHANNEL) == TIM_CHANNEL_1))) \
ebrus 0:6bc4ac881c8e 7856 || \
ebrus 0:6bc4ac881c8e 7857 (((INSTANCE) == TIM12) && \
ebrus 0:6bc4ac881c8e 7858 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7859 ((CHANNEL) == TIM_CHANNEL_2))) \
ebrus 0:6bc4ac881c8e 7860 || \
ebrus 0:6bc4ac881c8e 7861 (((INSTANCE) == TIM13) && \
ebrus 0:6bc4ac881c8e 7862 (((CHANNEL) == TIM_CHANNEL_1))) \
ebrus 0:6bc4ac881c8e 7863 || \
ebrus 0:6bc4ac881c8e 7864 (((INSTANCE) == TIM14) && \
ebrus 0:6bc4ac881c8e 7865 (((CHANNEL) == TIM_CHANNEL_1))))
ebrus 0:6bc4ac881c8e 7866
ebrus 0:6bc4ac881c8e 7867 /************ TIM Instances : complementary output(s) available ***************/
ebrus 0:6bc4ac881c8e 7868 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
ebrus 0:6bc4ac881c8e 7869 ((((INSTANCE) == TIM1) && \
ebrus 0:6bc4ac881c8e 7870 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7871 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7872 ((CHANNEL) == TIM_CHANNEL_3))) \
ebrus 0:6bc4ac881c8e 7873 || \
ebrus 0:6bc4ac881c8e 7874 (((INSTANCE) == TIM8) && \
ebrus 0:6bc4ac881c8e 7875 (((CHANNEL) == TIM_CHANNEL_1) || \
ebrus 0:6bc4ac881c8e 7876 ((CHANNEL) == TIM_CHANNEL_2) || \
ebrus 0:6bc4ac881c8e 7877 ((CHANNEL) == TIM_CHANNEL_3))))
ebrus 0:6bc4ac881c8e 7878
ebrus 0:6bc4ac881c8e 7879 /******************** USART Instances : Synchronous mode **********************/
ebrus 0:6bc4ac881c8e 7880 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ebrus 0:6bc4ac881c8e 7881 ((INSTANCE) == USART2) || \
ebrus 0:6bc4ac881c8e 7882 ((INSTANCE) == USART3) || \
ebrus 0:6bc4ac881c8e 7883 ((INSTANCE) == USART6))
ebrus 0:6bc4ac881c8e 7884
ebrus 0:6bc4ac881c8e 7885 /******************** UART Instances : Asynchronous mode **********************/
ebrus 0:6bc4ac881c8e 7886 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ebrus 0:6bc4ac881c8e 7887 ((INSTANCE) == USART2) || \
ebrus 0:6bc4ac881c8e 7888 ((INSTANCE) == USART3) || \
ebrus 0:6bc4ac881c8e 7889 ((INSTANCE) == UART4) || \
ebrus 0:6bc4ac881c8e 7890 ((INSTANCE) == UART5) || \
ebrus 0:6bc4ac881c8e 7891 ((INSTANCE) == USART6))
ebrus 0:6bc4ac881c8e 7892
ebrus 0:6bc4ac881c8e 7893 /****************** UART Instances : Hardware Flow control ********************/
ebrus 0:6bc4ac881c8e 7894 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ebrus 0:6bc4ac881c8e 7895 ((INSTANCE) == USART2) || \
ebrus 0:6bc4ac881c8e 7896 ((INSTANCE) == USART3) || \
ebrus 0:6bc4ac881c8e 7897 ((INSTANCE) == USART6))
ebrus 0:6bc4ac881c8e 7898
ebrus 0:6bc4ac881c8e 7899 /********************* UART Instances : Smard card mode ***********************/
ebrus 0:6bc4ac881c8e 7900 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ebrus 0:6bc4ac881c8e 7901 ((INSTANCE) == USART2) || \
ebrus 0:6bc4ac881c8e 7902 ((INSTANCE) == USART3) || \
ebrus 0:6bc4ac881c8e 7903 ((INSTANCE) == USART6))
ebrus 0:6bc4ac881c8e 7904
ebrus 0:6bc4ac881c8e 7905 /*********************** UART Instances : IRDA mode ***************************/
ebrus 0:6bc4ac881c8e 7906 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ebrus 0:6bc4ac881c8e 7907 ((INSTANCE) == USART2) || \
ebrus 0:6bc4ac881c8e 7908 ((INSTANCE) == USART3) || \
ebrus 0:6bc4ac881c8e 7909 ((INSTANCE) == UART4) || \
ebrus 0:6bc4ac881c8e 7910 ((INSTANCE) == UART5) || \
ebrus 0:6bc4ac881c8e 7911 ((INSTANCE) == USART6))
ebrus 0:6bc4ac881c8e 7912
ebrus 0:6bc4ac881c8e 7913 /****************************** IWDG Instances ********************************/
ebrus 0:6bc4ac881c8e 7914 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
ebrus 0:6bc4ac881c8e 7915
ebrus 0:6bc4ac881c8e 7916 /****************************** WWDG Instances ********************************/
ebrus 0:6bc4ac881c8e 7917 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
ebrus 0:6bc4ac881c8e 7918
ebrus 0:6bc4ac881c8e 7919 /******************************************************************************/
ebrus 0:6bc4ac881c8e 7920 /* For a painless codes migration between the STM32F4xx device product */
ebrus 0:6bc4ac881c8e 7921 /* lines, the aliases defined below are put in place to overcome the */
ebrus 0:6bc4ac881c8e 7922 /* differences in the interrupt handlers and IRQn definitions. */
ebrus 0:6bc4ac881c8e 7923 /* No need to update developed interrupt code when moving across */
ebrus 0:6bc4ac881c8e 7924 /* product lines within the same STM32F4 Family */
ebrus 0:6bc4ac881c8e 7925 /******************************************************************************/
ebrus 0:6bc4ac881c8e 7926
ebrus 0:6bc4ac881c8e 7927 /* Aliases for __IRQn */
ebrus 0:6bc4ac881c8e 7928 #define FMC_IRQn FSMC_IRQn
ebrus 0:6bc4ac881c8e 7929
ebrus 0:6bc4ac881c8e 7930 /* Aliases for __IRQHandler */
ebrus 0:6bc4ac881c8e 7931 #define FMC_IRQHandler FSMC_IRQHandler
ebrus 0:6bc4ac881c8e 7932
ebrus 0:6bc4ac881c8e 7933 /**
ebrus 0:6bc4ac881c8e 7934 * @}
ebrus 0:6bc4ac881c8e 7935 */
ebrus 0:6bc4ac881c8e 7936
ebrus 0:6bc4ac881c8e 7937 /**
ebrus 0:6bc4ac881c8e 7938 * @}
ebrus 0:6bc4ac881c8e 7939 */
ebrus 0:6bc4ac881c8e 7940
ebrus 0:6bc4ac881c8e 7941 /**
ebrus 0:6bc4ac881c8e 7942 * @}
ebrus 0:6bc4ac881c8e 7943 */
ebrus 0:6bc4ac881c8e 7944
ebrus 0:6bc4ac881c8e 7945 #ifdef __cplusplus
ebrus 0:6bc4ac881c8e 7946 }
ebrus 0:6bc4ac881c8e 7947 #endif /* __cplusplus */
ebrus 0:6bc4ac881c8e 7948
ebrus 0:6bc4ac881c8e 7949 #endif /* __STM32F407xx_H */
ebrus 0:6bc4ac881c8e 7950
ebrus 0:6bc4ac881c8e 7951
ebrus 0:6bc4ac881c8e 7952
ebrus 0:6bc4ac881c8e 7953 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/