Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:6bc4ac881c8e 1 /*
ebrus 0:6bc4ac881c8e 2 * LPC43xx/LPC18xx MCU header
ebrus 0:6bc4ac881c8e 3 *
ebrus 0:6bc4ac881c8e 4 * Copyright(C) NXP Semiconductors, 2012
ebrus 0:6bc4ac881c8e 5 * All rights reserved.
ebrus 0:6bc4ac881c8e 6 *
ebrus 0:6bc4ac881c8e 7 * Software that is described herein is for illustrative purposes only
ebrus 0:6bc4ac881c8e 8 * which provides customers with programming information regarding the
ebrus 0:6bc4ac881c8e 9 * LPC products. This software is supplied "AS IS" without any warranties of
ebrus 0:6bc4ac881c8e 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
ebrus 0:6bc4ac881c8e 11 * all warranties, express or implied, including all implied warranties of
ebrus 0:6bc4ac881c8e 12 * merchantability, fitness for a particular purpose and non-infringement of
ebrus 0:6bc4ac881c8e 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
ebrus 0:6bc4ac881c8e 14 * or liability for the use of the software, conveys no license or rights under any
ebrus 0:6bc4ac881c8e 15 * patent, copyright, mask work right, or any other intellectual property rights in
ebrus 0:6bc4ac881c8e 16 * or to any products. NXP Semiconductors reserves the right to make changes
ebrus 0:6bc4ac881c8e 17 * in the software without notification. NXP Semiconductors also makes no
ebrus 0:6bc4ac881c8e 18 * representation or warranty that such application will be suitable for the
ebrus 0:6bc4ac881c8e 19 * specified use without further testing or modification.
ebrus 0:6bc4ac881c8e 20 *
ebrus 0:6bc4ac881c8e 21 * Permission to use, copy, modify, and distribute this software and its
ebrus 0:6bc4ac881c8e 22 * documentation is hereby granted, under NXP Semiconductors' and its
ebrus 0:6bc4ac881c8e 23 * licensor's relevant copyrights in the software, without fee, provided that it
ebrus 0:6bc4ac881c8e 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
ebrus 0:6bc4ac881c8e 25 * copyright, permission, and disclaimer notice must appear in all copies of
ebrus 0:6bc4ac881c8e 26 * this code.
ebrus 0:6bc4ac881c8e 27 *
ebrus 0:6bc4ac881c8e 28 * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
ebrus 0:6bc4ac881c8e 29 * 05/15/13 Micromint USA <support@micromint.com>
ebrus 0:6bc4ac881c8e 30 */
ebrus 0:6bc4ac881c8e 31
ebrus 0:6bc4ac881c8e 32 #ifndef __LPC43XX_H
ebrus 0:6bc4ac881c8e 33 #define __LPC43XX_H
ebrus 0:6bc4ac881c8e 34
ebrus 0:6bc4ac881c8e 35 #ifdef __cplusplus
ebrus 0:6bc4ac881c8e 36 extern "C" {
ebrus 0:6bc4ac881c8e 37 #endif
ebrus 0:6bc4ac881c8e 38
ebrus 0:6bc4ac881c8e 39 /* Treat __CORE_Mx as CORE_Mx */
ebrus 0:6bc4ac881c8e 40 #if defined(__CORTEX_M0) && !defined(CORE_M0)
ebrus 0:6bc4ac881c8e 41 #define CORE_M0
ebrus 0:6bc4ac881c8e 42 #endif
ebrus 0:6bc4ac881c8e 43 #if defined(__CORTEX_M3) && !defined(CORE_M3)
ebrus 0:6bc4ac881c8e 44 #define CORE_M3
ebrus 0:6bc4ac881c8e 45 #endif
ebrus 0:6bc4ac881c8e 46 /* Default to M4 core if no core explicitly declared */
ebrus 0:6bc4ac881c8e 47 #if !defined(CORE_M0) && !defined(CORE_M3)
ebrus 0:6bc4ac881c8e 48 #define CORE_M4
ebrus 0:6bc4ac881c8e 49 #endif
ebrus 0:6bc4ac881c8e 50
ebrus 0:6bc4ac881c8e 51 /* Define LPC18XX or LPC43XX according to core type */
ebrus 0:6bc4ac881c8e 52 #if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
ebrus 0:6bc4ac881c8e 53 #define __LPC43XX__
ebrus 0:6bc4ac881c8e 54 #endif
ebrus 0:6bc4ac881c8e 55 #if defined(CORE_M3) && !defined(__LPC18XX__)
ebrus 0:6bc4ac881c8e 56 #define __LPC18XX__
ebrus 0:6bc4ac881c8e 57 #endif
ebrus 0:6bc4ac881c8e 58
ebrus 0:6bc4ac881c8e 59 /* Start of section using anonymous unions */
ebrus 0:6bc4ac881c8e 60 #if defined(__ARMCC_VERSION)
ebrus 0:6bc4ac881c8e 61 // Kill warning "#pragma push with no matching #pragma pop"
ebrus 0:6bc4ac881c8e 62 #pragma diag_suppress 2525
ebrus 0:6bc4ac881c8e 63 #pragma push
ebrus 0:6bc4ac881c8e 64 #pragma anon_unions
ebrus 0:6bc4ac881c8e 65 #elif defined(__CWCC__)
ebrus 0:6bc4ac881c8e 66 #pragma push
ebrus 0:6bc4ac881c8e 67 #pragma cpp_extensions on
ebrus 0:6bc4ac881c8e 68 #elif defined(__IAR_SYSTEMS_ICC__)
ebrus 0:6bc4ac881c8e 69 //#pragma push // FIXME not usable for IAR
ebrus 0:6bc4ac881c8e 70 #pragma language=extended
ebrus 0:6bc4ac881c8e 71 #else /* defined(__GNUC__) and others */
ebrus 0:6bc4ac881c8e 72 /* Assume anonymous unions are enabled by default */
ebrus 0:6bc4ac881c8e 73 #endif
ebrus 0:6bc4ac881c8e 74
ebrus 0:6bc4ac881c8e 75 #if defined(CORE_M4)
ebrus 0:6bc4ac881c8e 76 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 77 * LPC43xx (M4 Core) Cortex CMSIS definitions
ebrus 0:6bc4ac881c8e 78 */
ebrus 0:6bc4ac881c8e 79
ebrus 0:6bc4ac881c8e 80 #define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
ebrus 0:6bc4ac881c8e 81 #define __MPU_PRESENT 1 /* MPU present or not */
ebrus 0:6bc4ac881c8e 82 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
ebrus 0:6bc4ac881c8e 83 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
ebrus 0:6bc4ac881c8e 84 #define __FPU_PRESENT 1 /* FPU present or not */
ebrus 0:6bc4ac881c8e 85 #define CHIP_LPC43XX /* LPCOPEN compatibility */
ebrus 0:6bc4ac881c8e 86
ebrus 0:6bc4ac881c8e 87 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 88 * LPC43xx peripheral interrupt numbers
ebrus 0:6bc4ac881c8e 89 */
ebrus 0:6bc4ac881c8e 90
ebrus 0:6bc4ac881c8e 91 typedef enum {
ebrus 0:6bc4ac881c8e 92 /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
ebrus 0:6bc4ac881c8e 93 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:6bc4ac881c8e 94 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:6bc4ac881c8e 95 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
ebrus 0:6bc4ac881c8e 96 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
ebrus 0:6bc4ac881c8e 97 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
ebrus 0:6bc4ac881c8e 98 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
ebrus 0:6bc4ac881c8e 99 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
ebrus 0:6bc4ac881c8e 100 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
ebrus 0:6bc4ac881c8e 101 PendSV_IRQn = -2,/* 14 Pendable request for system service */
ebrus 0:6bc4ac881c8e 102 SysTick_IRQn = -1,/* 15 System Tick Timer */
ebrus 0:6bc4ac881c8e 103
ebrus 0:6bc4ac881c8e 104 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
ebrus 0:6bc4ac881c8e 105 DAC_IRQn = 0,/* 0 DAC */
ebrus 0:6bc4ac881c8e 106 M0CORE_IRQn = 1,/* 1 M0a */
ebrus 0:6bc4ac881c8e 107 DMA_IRQn = 2,/* 2 DMA */
ebrus 0:6bc4ac881c8e 108 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
ebrus 0:6bc4ac881c8e 109 RESERVED2_IRQn = 4,
ebrus 0:6bc4ac881c8e 110 ETHERNET_IRQn = 5,/* 5 ETHERNET */
ebrus 0:6bc4ac881c8e 111 SDIO_IRQn = 6,/* 6 SDIO */
ebrus 0:6bc4ac881c8e 112 LCD_IRQn = 7,/* 7 LCD */
ebrus 0:6bc4ac881c8e 113 USB0_IRQn = 8,/* 8 USB0 */
ebrus 0:6bc4ac881c8e 114 USB1_IRQn = 9,/* 9 USB1 */
ebrus 0:6bc4ac881c8e 115 SCT_IRQn = 10,/* 10 SCT */
ebrus 0:6bc4ac881c8e 116 RITIMER_IRQn = 11,/* 11 RITIMER */
ebrus 0:6bc4ac881c8e 117 TIMER0_IRQn = 12,/* 12 TIMER0 */
ebrus 0:6bc4ac881c8e 118 TIMER1_IRQn = 13,/* 13 TIMER1 */
ebrus 0:6bc4ac881c8e 119 TIMER2_IRQn = 14,/* 14 TIMER2 */
ebrus 0:6bc4ac881c8e 120 TIMER3_IRQn = 15,/* 15 TIMER3 */
ebrus 0:6bc4ac881c8e 121 MCPWM_IRQn = 16,/* 16 MCPWM */
ebrus 0:6bc4ac881c8e 122 ADC0_IRQn = 17,/* 17 ADC0 */
ebrus 0:6bc4ac881c8e 123 I2C0_IRQn = 18,/* 18 I2C0 */
ebrus 0:6bc4ac881c8e 124 I2C1_IRQn = 19,/* 19 I2C1 */
ebrus 0:6bc4ac881c8e 125 SPI_INT_IRQn = 20,/* 20 SPI_INT */
ebrus 0:6bc4ac881c8e 126 ADC1_IRQn = 21,/* 21 ADC1 */
ebrus 0:6bc4ac881c8e 127 SSP0_IRQn = 22,/* 22 SSP0 */
ebrus 0:6bc4ac881c8e 128 SSP1_IRQn = 23,/* 23 SSP1 */
ebrus 0:6bc4ac881c8e 129 USART0_IRQn = 24,/* 24 USART0 */
ebrus 0:6bc4ac881c8e 130 UART1_IRQn = 25,/* 25 UART1 */
ebrus 0:6bc4ac881c8e 131 USART2_IRQn = 26,/* 26 USART2 */
ebrus 0:6bc4ac881c8e 132 USART3_IRQn = 27,/* 27 USART3 */
ebrus 0:6bc4ac881c8e 133 I2S0_IRQn = 28,/* 28 I2S0 */
ebrus 0:6bc4ac881c8e 134 I2S1_IRQn = 29,/* 29 I2S1 */
ebrus 0:6bc4ac881c8e 135 RESERVED4_IRQn = 30,
ebrus 0:6bc4ac881c8e 136 SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
ebrus 0:6bc4ac881c8e 137 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
ebrus 0:6bc4ac881c8e 138 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
ebrus 0:6bc4ac881c8e 139 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
ebrus 0:6bc4ac881c8e 140 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
ebrus 0:6bc4ac881c8e 141 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
ebrus 0:6bc4ac881c8e 142 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
ebrus 0:6bc4ac881c8e 143 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
ebrus 0:6bc4ac881c8e 144 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
ebrus 0:6bc4ac881c8e 145 GINT0_IRQn = 40,/* 40 GINT0 */
ebrus 0:6bc4ac881c8e 146 GINT1_IRQn = 41,/* 41 GINT1 */
ebrus 0:6bc4ac881c8e 147 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
ebrus 0:6bc4ac881c8e 148 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
ebrus 0:6bc4ac881c8e 149 RESERVED6_IRQn = 44,
ebrus 0:6bc4ac881c8e 150 RESERVED7_IRQn = 45,/* 45 VADC */
ebrus 0:6bc4ac881c8e 151 ATIMER_IRQn = 46,/* 46 ATIMER */
ebrus 0:6bc4ac881c8e 152 RTC_IRQn = 47,/* 47 RTC */
ebrus 0:6bc4ac881c8e 153 RESERVED8_IRQn = 48,
ebrus 0:6bc4ac881c8e 154 WWDT_IRQn = 49,/* 49 WWDT */
ebrus 0:6bc4ac881c8e 155 RESERVED9_IRQn = 50,
ebrus 0:6bc4ac881c8e 156 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
ebrus 0:6bc4ac881c8e 157 QEI_IRQn = 52,/* 52 QEI */
ebrus 0:6bc4ac881c8e 158 } IRQn_Type;
ebrus 0:6bc4ac881c8e 159
ebrus 0:6bc4ac881c8e 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
ebrus 0:6bc4ac881c8e 161
ebrus 0:6bc4ac881c8e 162 #elif defined(CORE_M3)
ebrus 0:6bc4ac881c8e 163 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 164 * LPC18xx (M3 Core) Cortex CMSIS definitions
ebrus 0:6bc4ac881c8e 165 */
ebrus 0:6bc4ac881c8e 166 #define __MPU_PRESENT 1 /* MPU present or not */
ebrus 0:6bc4ac881c8e 167 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
ebrus 0:6bc4ac881c8e 168 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
ebrus 0:6bc4ac881c8e 169 #define __FPU_PRESENT 0 /* FPU present or not */
ebrus 0:6bc4ac881c8e 170 #define CHIP_LPC18XX /* LPCOPEN compatibility */
ebrus 0:6bc4ac881c8e 171
ebrus 0:6bc4ac881c8e 172 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 173 * LPC18xx peripheral interrupt numbers
ebrus 0:6bc4ac881c8e 174 */
ebrus 0:6bc4ac881c8e 175
ebrus 0:6bc4ac881c8e 176 typedef enum {
ebrus 0:6bc4ac881c8e 177 /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
ebrus 0:6bc4ac881c8e 178 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:6bc4ac881c8e 179 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:6bc4ac881c8e 180 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
ebrus 0:6bc4ac881c8e 181 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
ebrus 0:6bc4ac881c8e 182 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
ebrus 0:6bc4ac881c8e 183 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
ebrus 0:6bc4ac881c8e 184 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
ebrus 0:6bc4ac881c8e 185 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
ebrus 0:6bc4ac881c8e 186 PendSV_IRQn = -2,/* 14 Pendable request for system service */
ebrus 0:6bc4ac881c8e 187 SysTick_IRQn = -1,/* 15 System Tick Timer */
ebrus 0:6bc4ac881c8e 188
ebrus 0:6bc4ac881c8e 189 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
ebrus 0:6bc4ac881c8e 190 DAC_IRQn = 0,/* 0 DAC */
ebrus 0:6bc4ac881c8e 191 RESERVED0_IRQn = 1,
ebrus 0:6bc4ac881c8e 192 DMA_IRQn = 2,/* 2 DMA */
ebrus 0:6bc4ac881c8e 193 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
ebrus 0:6bc4ac881c8e 194 RESERVED2_IRQn = 4,
ebrus 0:6bc4ac881c8e 195 ETHERNET_IRQn = 5,/* 5 ETHERNET */
ebrus 0:6bc4ac881c8e 196 SDIO_IRQn = 6,/* 6 SDIO */
ebrus 0:6bc4ac881c8e 197 LCD_IRQn = 7,/* 7 LCD */
ebrus 0:6bc4ac881c8e 198 USB0_IRQn = 8,/* 8 USB0 */
ebrus 0:6bc4ac881c8e 199 USB1_IRQn = 9,/* 9 USB1 */
ebrus 0:6bc4ac881c8e 200 SCT_IRQn = 10,/* 10 SCT */
ebrus 0:6bc4ac881c8e 201 RITIMER_IRQn = 11,/* 11 RITIMER */
ebrus 0:6bc4ac881c8e 202 TIMER0_IRQn = 12,/* 12 TIMER0 */
ebrus 0:6bc4ac881c8e 203 TIMER1_IRQn = 13,/* 13 TIMER1 */
ebrus 0:6bc4ac881c8e 204 TIMER2_IRQn = 14,/* 14 TIMER2 */
ebrus 0:6bc4ac881c8e 205 TIMER3_IRQn = 15,/* 15 TIMER3 */
ebrus 0:6bc4ac881c8e 206 MCPWM_IRQn = 16,/* 16 MCPWM */
ebrus 0:6bc4ac881c8e 207 ADC0_IRQn = 17,/* 17 ADC0 */
ebrus 0:6bc4ac881c8e 208 I2C0_IRQn = 18,/* 18 I2C0 */
ebrus 0:6bc4ac881c8e 209 I2C1_IRQn = 19,/* 19 I2C1 */
ebrus 0:6bc4ac881c8e 210 RESERVED3_IRQn = 20,
ebrus 0:6bc4ac881c8e 211 ADC1_IRQn = 21,/* 21 ADC1 */
ebrus 0:6bc4ac881c8e 212 SSP0_IRQn = 22,/* 22 SSP0 */
ebrus 0:6bc4ac881c8e 213 SSP1_IRQn = 23,/* 23 SSP1 */
ebrus 0:6bc4ac881c8e 214 USART0_IRQn = 24,/* 24 USART0 */
ebrus 0:6bc4ac881c8e 215 UART1_IRQn = 25,/* 25 UART1 */
ebrus 0:6bc4ac881c8e 216 USART2_IRQn = 26,/* 26 USART2 */
ebrus 0:6bc4ac881c8e 217 USART3_IRQn = 27,/* 27 USART3 */
ebrus 0:6bc4ac881c8e 218 I2S0_IRQn = 28,/* 28 I2S0 */
ebrus 0:6bc4ac881c8e 219 I2S1_IRQn = 29,/* 29 I2S1 */
ebrus 0:6bc4ac881c8e 220 RESERVED4_IRQn = 30,
ebrus 0:6bc4ac881c8e 221 RESERVED5_IRQn = 31,
ebrus 0:6bc4ac881c8e 222 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
ebrus 0:6bc4ac881c8e 223 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
ebrus 0:6bc4ac881c8e 224 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
ebrus 0:6bc4ac881c8e 225 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
ebrus 0:6bc4ac881c8e 226 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
ebrus 0:6bc4ac881c8e 227 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
ebrus 0:6bc4ac881c8e 228 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
ebrus 0:6bc4ac881c8e 229 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
ebrus 0:6bc4ac881c8e 230 GINT0_IRQn = 40,/* 40 GINT0 */
ebrus 0:6bc4ac881c8e 231 GINT1_IRQn = 41,/* 41 GINT1 */
ebrus 0:6bc4ac881c8e 232 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
ebrus 0:6bc4ac881c8e 233 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
ebrus 0:6bc4ac881c8e 234 RESERVED6_IRQn = 44,
ebrus 0:6bc4ac881c8e 235 RESERVED7_IRQn = 45,/* 45 VADC */
ebrus 0:6bc4ac881c8e 236 ATIMER_IRQn = 46,/* 46 ATIMER */
ebrus 0:6bc4ac881c8e 237 RTC_IRQn = 47,/* 47 RTC */
ebrus 0:6bc4ac881c8e 238 RESERVED8_IRQn = 48,
ebrus 0:6bc4ac881c8e 239 WWDT_IRQn = 49,/* 49 WWDT */
ebrus 0:6bc4ac881c8e 240 RESERVED9_IRQn = 50,
ebrus 0:6bc4ac881c8e 241 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
ebrus 0:6bc4ac881c8e 242 QEI_IRQn = 52,/* 52 QEI */
ebrus 0:6bc4ac881c8e 243 } IRQn_Type;
ebrus 0:6bc4ac881c8e 244
ebrus 0:6bc4ac881c8e 245 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
ebrus 0:6bc4ac881c8e 246
ebrus 0:6bc4ac881c8e 247 #elif defined(CORE_M0)
ebrus 0:6bc4ac881c8e 248 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 249 * LPC43xx (M0 Core) Cortex CMSIS definitions
ebrus 0:6bc4ac881c8e 250 */
ebrus 0:6bc4ac881c8e 251
ebrus 0:6bc4ac881c8e 252 #define __MPU_PRESENT 0 /* MPU present or not */
ebrus 0:6bc4ac881c8e 253 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
ebrus 0:6bc4ac881c8e 254 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
ebrus 0:6bc4ac881c8e 255 #define __FPU_PRESENT 0 /* FPU present or not */
ebrus 0:6bc4ac881c8e 256 #define CHIP_LPC43XX /* LPCOPEN compatibility */
ebrus 0:6bc4ac881c8e 257
ebrus 0:6bc4ac881c8e 258 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 259 * LPC43xx (M0 Core) peripheral interrupt numbers
ebrus 0:6bc4ac881c8e 260 */
ebrus 0:6bc4ac881c8e 261
ebrus 0:6bc4ac881c8e 262 typedef enum {
ebrus 0:6bc4ac881c8e 263 /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
ebrus 0:6bc4ac881c8e 264 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:6bc4ac881c8e 265 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:6bc4ac881c8e 266 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
ebrus 0:6bc4ac881c8e 267 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
ebrus 0:6bc4ac881c8e 268 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
ebrus 0:6bc4ac881c8e 269 PendSV_IRQn = -2,/* 14 Pendable request for system service */
ebrus 0:6bc4ac881c8e 270 SysTick_IRQn = -1,/* 15 System Tick Timer */
ebrus 0:6bc4ac881c8e 271
ebrus 0:6bc4ac881c8e 272 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
ebrus 0:6bc4ac881c8e 273 DAC_IRQn = 0,/* 0 DAC */
ebrus 0:6bc4ac881c8e 274 M0_M4CORE_IRQn = 1,/* 1 M0a */
ebrus 0:6bc4ac881c8e 275 DMA_IRQn = 2,/* 2 DMA r */
ebrus 0:6bc4ac881c8e 276 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
ebrus 0:6bc4ac881c8e 277 FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
ebrus 0:6bc4ac881c8e 278 ETHERNET_IRQn = 5,/* 5 ETHERNET */
ebrus 0:6bc4ac881c8e 279 SDIO_IRQn = 6,/* 6 SDIO */
ebrus 0:6bc4ac881c8e 280 LCD_IRQn = 7,/* 7 LCD */
ebrus 0:6bc4ac881c8e 281 USB0_IRQn = 8,/* 8 USB0 */
ebrus 0:6bc4ac881c8e 282 USB1_IRQn = 9,/* 9 USB1 */
ebrus 0:6bc4ac881c8e 283 SCT_IRQn = 10,/* 10 SCT */
ebrus 0:6bc4ac881c8e 284 RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
ebrus 0:6bc4ac881c8e 285 TIMER0_IRQn = 12,/* 12 TIMER0 */
ebrus 0:6bc4ac881c8e 286 GINT1_IRQn = 13,/* 13 GINT1 */
ebrus 0:6bc4ac881c8e 287 PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
ebrus 0:6bc4ac881c8e 288 TIMER3_IRQn = 15,/* 15 TIMER3 */
ebrus 0:6bc4ac881c8e 289 MCPWM_IRQn = 16,/* 16 MCPWM */
ebrus 0:6bc4ac881c8e 290 ADC0_IRQn = 17,/* 17 ADC0 */
ebrus 0:6bc4ac881c8e 291 I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
ebrus 0:6bc4ac881c8e 292 SGPIO_INT_IRQn = 19,/* 19 SGPIO */
ebrus 0:6bc4ac881c8e 293 SPI_INT_IRQn = 20,/* 20 SPI_INT */
ebrus 0:6bc4ac881c8e 294 ADC1_IRQn = 21,/* 21 ADC1 */
ebrus 0:6bc4ac881c8e 295 SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
ebrus 0:6bc4ac881c8e 296 EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
ebrus 0:6bc4ac881c8e 297 USART0_IRQn = 24,/* 24 USART0 */
ebrus 0:6bc4ac881c8e 298 UART1_IRQn = 25,/* 25 UART1 */
ebrus 0:6bc4ac881c8e 299 USART2_IRQn = 26,/* 26 USART2 */
ebrus 0:6bc4ac881c8e 300 USART3_IRQn = 27,/* 27 USART3 */
ebrus 0:6bc4ac881c8e 301 I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
ebrus 0:6bc4ac881c8e 302 C_CAN0_IRQn = 29,/* 29 C_CAN0 */
ebrus 0:6bc4ac881c8e 303 I2S1_IRQn = 29,/* 29 I2S1 */
ebrus 0:6bc4ac881c8e 304 RESERVED2_IRQn = 30,
ebrus 0:6bc4ac881c8e 305 RESERVED3_IRQn = 31,
ebrus 0:6bc4ac881c8e 306 } IRQn_Type;
ebrus 0:6bc4ac881c8e 307
ebrus 0:6bc4ac881c8e 308 #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
ebrus 0:6bc4ac881c8e 309 #else
ebrus 0:6bc4ac881c8e 310 #error Please #define CORE_M0, CORE_M3 or CORE_M4
ebrus 0:6bc4ac881c8e 311 #endif
ebrus 0:6bc4ac881c8e 312
ebrus 0:6bc4ac881c8e 313 #include "system_LPC43xx.h"
ebrus 0:6bc4ac881c8e 314
ebrus 0:6bc4ac881c8e 315 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 316 * State Configurable Timer register block structure
ebrus 0:6bc4ac881c8e 317 */
ebrus 0:6bc4ac881c8e 318 #define LPC_SCT_BASE 0x40000000
ebrus 0:6bc4ac881c8e 319 #define CONFIG_SCT_nEV (16) /* Number of events */
ebrus 0:6bc4ac881c8e 320 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
ebrus 0:6bc4ac881c8e 321 #define CONFIG_SCT_nOU (16) /* Number of outputs */
ebrus 0:6bc4ac881c8e 322
ebrus 0:6bc4ac881c8e 323 typedef struct {
ebrus 0:6bc4ac881c8e 324 __IO uint32_t CONFIG; /* Configuration Register */
ebrus 0:6bc4ac881c8e 325 union {
ebrus 0:6bc4ac881c8e 326 __IO uint32_t CTRL_U; /* Control Register */
ebrus 0:6bc4ac881c8e 327 struct {
ebrus 0:6bc4ac881c8e 328 __IO uint16_t CTRL_L; /* Low control register */
ebrus 0:6bc4ac881c8e 329 __IO uint16_t CTRL_H; /* High control register */
ebrus 0:6bc4ac881c8e 330 };
ebrus 0:6bc4ac881c8e 331
ebrus 0:6bc4ac881c8e 332 };
ebrus 0:6bc4ac881c8e 333
ebrus 0:6bc4ac881c8e 334 __IO uint16_t LIMIT_L; /* limit register for counter L */
ebrus 0:6bc4ac881c8e 335 __IO uint16_t LIMIT_H; /* limit register for counter H */
ebrus 0:6bc4ac881c8e 336 __IO uint16_t HALT_L; /* halt register for counter L */
ebrus 0:6bc4ac881c8e 337 __IO uint16_t HALT_H; /* halt register for counter H */
ebrus 0:6bc4ac881c8e 338 __IO uint16_t STOP_L; /* stop register for counter L */
ebrus 0:6bc4ac881c8e 339 __IO uint16_t STOP_H; /* stop register for counter H */
ebrus 0:6bc4ac881c8e 340 __IO uint16_t START_L; /* start register for counter L */
ebrus 0:6bc4ac881c8e 341 __IO uint16_t START_H; /* start register for counter H */
ebrus 0:6bc4ac881c8e 342 uint32_t RESERVED1[10]; /* 0x03C reserved */
ebrus 0:6bc4ac881c8e 343 union {
ebrus 0:6bc4ac881c8e 344 __IO uint32_t COUNT_U; /* counter register */
ebrus 0:6bc4ac881c8e 345 struct {
ebrus 0:6bc4ac881c8e 346 __IO uint16_t COUNT_L; /* counter register for counter L */
ebrus 0:6bc4ac881c8e 347 __IO uint16_t COUNT_H; /* counter register for counter H */
ebrus 0:6bc4ac881c8e 348 };
ebrus 0:6bc4ac881c8e 349
ebrus 0:6bc4ac881c8e 350 };
ebrus 0:6bc4ac881c8e 351
ebrus 0:6bc4ac881c8e 352 __IO uint16_t STATE_L; /* state register for counter L */
ebrus 0:6bc4ac881c8e 353 __IO uint16_t STATE_H; /* state register for counter H */
ebrus 0:6bc4ac881c8e 354 __I uint32_t INPUT; /* input register */
ebrus 0:6bc4ac881c8e 355 __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
ebrus 0:6bc4ac881c8e 356 __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
ebrus 0:6bc4ac881c8e 357 __IO uint32_t OUTPUT; /* output register */
ebrus 0:6bc4ac881c8e 358 __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
ebrus 0:6bc4ac881c8e 359 __IO uint32_t RES; /* conflict resolution register */
ebrus 0:6bc4ac881c8e 360 __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
ebrus 0:6bc4ac881c8e 361 __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
ebrus 0:6bc4ac881c8e 362 uint32_t RESERVED2[35];
ebrus 0:6bc4ac881c8e 363 __IO uint32_t EVEN; /* event enable register */
ebrus 0:6bc4ac881c8e 364 __IO uint32_t EVFLAG; /* event flag register */
ebrus 0:6bc4ac881c8e 365 __IO uint32_t CONEN; /* conflict enable register */
ebrus 0:6bc4ac881c8e 366 __IO uint32_t CONFLAG; /* conflict flag register */
ebrus 0:6bc4ac881c8e 367 union {
ebrus 0:6bc4ac881c8e 368 __IO union { /* ... Match / Capture value */
ebrus 0:6bc4ac881c8e 369 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
ebrus 0:6bc4ac881c8e 370 struct {
ebrus 0:6bc4ac881c8e 371 uint16_t L; /* SCTMATCH[i].L Access to L value */
ebrus 0:6bc4ac881c8e 372 uint16_t H; /* SCTMATCH[i].H Access to H value */
ebrus 0:6bc4ac881c8e 373 };
ebrus 0:6bc4ac881c8e 374
ebrus 0:6bc4ac881c8e 375 } MATCH[CONFIG_SCT_nRG];
ebrus 0:6bc4ac881c8e 376
ebrus 0:6bc4ac881c8e 377 __I union {
ebrus 0:6bc4ac881c8e 378 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
ebrus 0:6bc4ac881c8e 379 struct {
ebrus 0:6bc4ac881c8e 380 uint16_t L; /* SCTCAP[i].L Access to L value */
ebrus 0:6bc4ac881c8e 381 uint16_t H; /* SCTCAP[i].H Access to H value */
ebrus 0:6bc4ac881c8e 382 };
ebrus 0:6bc4ac881c8e 383
ebrus 0:6bc4ac881c8e 384 } CAP[CONFIG_SCT_nRG];
ebrus 0:6bc4ac881c8e 385
ebrus 0:6bc4ac881c8e 386 };
ebrus 0:6bc4ac881c8e 387
ebrus 0:6bc4ac881c8e 388 uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
ebrus 0:6bc4ac881c8e 389 union {
ebrus 0:6bc4ac881c8e 390 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
ebrus 0:6bc4ac881c8e 391 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
ebrus 0:6bc4ac881c8e 392 };
ebrus 0:6bc4ac881c8e 393
ebrus 0:6bc4ac881c8e 394 uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
ebrus 0:6bc4ac881c8e 395 union {
ebrus 0:6bc4ac881c8e 396 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
ebrus 0:6bc4ac881c8e 397 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
ebrus 0:6bc4ac881c8e 398 };
ebrus 0:6bc4ac881c8e 399
ebrus 0:6bc4ac881c8e 400 uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
ebrus 0:6bc4ac881c8e 401 union {
ebrus 0:6bc4ac881c8e 402 __IO union { /* 0x200-... Match Reload / Capture Control value */
ebrus 0:6bc4ac881c8e 403 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
ebrus 0:6bc4ac881c8e 404 struct {
ebrus 0:6bc4ac881c8e 405 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
ebrus 0:6bc4ac881c8e 406 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
ebrus 0:6bc4ac881c8e 407 };
ebrus 0:6bc4ac881c8e 408
ebrus 0:6bc4ac881c8e 409 } MATCHREL[CONFIG_SCT_nRG];
ebrus 0:6bc4ac881c8e 410
ebrus 0:6bc4ac881c8e 411 __IO union {
ebrus 0:6bc4ac881c8e 412 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
ebrus 0:6bc4ac881c8e 413 struct {
ebrus 0:6bc4ac881c8e 414 uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
ebrus 0:6bc4ac881c8e 415 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
ebrus 0:6bc4ac881c8e 416 };
ebrus 0:6bc4ac881c8e 417
ebrus 0:6bc4ac881c8e 418 } CAPCTRL[CONFIG_SCT_nRG];
ebrus 0:6bc4ac881c8e 419
ebrus 0:6bc4ac881c8e 420 };
ebrus 0:6bc4ac881c8e 421
ebrus 0:6bc4ac881c8e 422 uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
ebrus 0:6bc4ac881c8e 423 union {
ebrus 0:6bc4ac881c8e 424 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
ebrus 0:6bc4ac881c8e 425 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
ebrus 0:6bc4ac881c8e 426 };
ebrus 0:6bc4ac881c8e 427
ebrus 0:6bc4ac881c8e 428 uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
ebrus 0:6bc4ac881c8e 429 union {
ebrus 0:6bc4ac881c8e 430 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
ebrus 0:6bc4ac881c8e 431 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
ebrus 0:6bc4ac881c8e 432 };
ebrus 0:6bc4ac881c8e 433
ebrus 0:6bc4ac881c8e 434 uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
ebrus 0:6bc4ac881c8e 435 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
ebrus 0:6bc4ac881c8e 436 uint32_t STATE; /* Event State Register */
ebrus 0:6bc4ac881c8e 437 uint32_t CTRL; /* Event Control Register */
ebrus 0:6bc4ac881c8e 438 } EVENT[CONFIG_SCT_nEV];
ebrus 0:6bc4ac881c8e 439
ebrus 0:6bc4ac881c8e 440 uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
ebrus 0:6bc4ac881c8e 441 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
ebrus 0:6bc4ac881c8e 442 uint32_t SET; /* Output n Set Register */
ebrus 0:6bc4ac881c8e 443 uint32_t CLR; /* Output n Clear Register */
ebrus 0:6bc4ac881c8e 444 } OUT[CONFIG_SCT_nOU];
ebrus 0:6bc4ac881c8e 445
ebrus 0:6bc4ac881c8e 446 uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
ebrus 0:6bc4ac881c8e 447 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
ebrus 0:6bc4ac881c8e 448 } LPC_SCT_T;
ebrus 0:6bc4ac881c8e 449
ebrus 0:6bc4ac881c8e 450 /* Macro defines for SCT configuration register */
ebrus 0:6bc4ac881c8e 451 #define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
ebrus 0:6bc4ac881c8e 452 #define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
ebrus 0:6bc4ac881c8e 453
ebrus 0:6bc4ac881c8e 454 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
ebrus 0:6bc4ac881c8e 455 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
ebrus 0:6bc4ac881c8e 456 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
ebrus 0:6bc4ac881c8e 457 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
ebrus 0:6bc4ac881c8e 458
ebrus 0:6bc4ac881c8e 459 #define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
ebrus 0:6bc4ac881c8e 460 #define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
ebrus 0:6bc4ac881c8e 461
ebrus 0:6bc4ac881c8e 462 /* Macro defines for SCT control register */
ebrus 0:6bc4ac881c8e 463 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
ebrus 0:6bc4ac881c8e 464 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
ebrus 0:6bc4ac881c8e 465
ebrus 0:6bc4ac881c8e 466 #define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
ebrus 0:6bc4ac881c8e 467 #define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
ebrus 0:6bc4ac881c8e 468 #define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
ebrus 0:6bc4ac881c8e 469 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
ebrus 0:6bc4ac881c8e 470 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
ebrus 0:6bc4ac881c8e 471
ebrus 0:6bc4ac881c8e 472 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
ebrus 0:6bc4ac881c8e 473 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
ebrus 0:6bc4ac881c8e 474 #define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
ebrus 0:6bc4ac881c8e 475 #define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
ebrus 0:6bc4ac881c8e 476 #define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
ebrus 0:6bc4ac881c8e 477 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
ebrus 0:6bc4ac881c8e 478 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
ebrus 0:6bc4ac881c8e 479
ebrus 0:6bc4ac881c8e 480 /* Macro defines for SCT Conflict resolution register */
ebrus 0:6bc4ac881c8e 481 #define SCT_RES_NOCHANGE (0)
ebrus 0:6bc4ac881c8e 482 #define SCT_RES_SET_OUTPUT (1)
ebrus 0:6bc4ac881c8e 483 #define SCT_RES_CLEAR_OUTPUT (2)
ebrus 0:6bc4ac881c8e 484 #define SCT_RES_TOGGLE_OUTPUT (3)
ebrus 0:6bc4ac881c8e 485
ebrus 0:6bc4ac881c8e 486 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 487 * GPDMA Channel register block structure
ebrus 0:6bc4ac881c8e 488 */
ebrus 0:6bc4ac881c8e 489 #define LPC_GPDMA_BASE 0x40002000
ebrus 0:6bc4ac881c8e 490
ebrus 0:6bc4ac881c8e 491 typedef struct {
ebrus 0:6bc4ac881c8e 492 __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
ebrus 0:6bc4ac881c8e 493 __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
ebrus 0:6bc4ac881c8e 494 __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
ebrus 0:6bc4ac881c8e 495 __IO uint32_t CONTROL; /* DMA Channel Control Register */
ebrus 0:6bc4ac881c8e 496 __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
ebrus 0:6bc4ac881c8e 497 __I uint32_t RESERVED1[3];
ebrus 0:6bc4ac881c8e 498 } LPC_GPDMA_CH_T;
ebrus 0:6bc4ac881c8e 499
ebrus 0:6bc4ac881c8e 500 #define GPDMA_CHANNELS 8
ebrus 0:6bc4ac881c8e 501
ebrus 0:6bc4ac881c8e 502 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 503 * GPDMA register block
ebrus 0:6bc4ac881c8e 504 */
ebrus 0:6bc4ac881c8e 505 typedef struct { /* GPDMA Structure */
ebrus 0:6bc4ac881c8e 506 __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
ebrus 0:6bc4ac881c8e 507 __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
ebrus 0:6bc4ac881c8e 508 __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
ebrus 0:6bc4ac881c8e 509 __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
ebrus 0:6bc4ac881c8e 510 __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
ebrus 0:6bc4ac881c8e 511 __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
ebrus 0:6bc4ac881c8e 512 __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
ebrus 0:6bc4ac881c8e 513 __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
ebrus 0:6bc4ac881c8e 514 __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
ebrus 0:6bc4ac881c8e 515 __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
ebrus 0:6bc4ac881c8e 516 __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
ebrus 0:6bc4ac881c8e 517 __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
ebrus 0:6bc4ac881c8e 518 __IO uint32_t CONFIG; /* DMA Configuration Register */
ebrus 0:6bc4ac881c8e 519 __IO uint32_t SYNC; /* DMA Synchronization Register */
ebrus 0:6bc4ac881c8e 520 __I uint32_t RESERVED0[50];
ebrus 0:6bc4ac881c8e 521 LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
ebrus 0:6bc4ac881c8e 522 } LPC_GPDMA_T;
ebrus 0:6bc4ac881c8e 523
ebrus 0:6bc4ac881c8e 524 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 525 * SPIFI register block structure
ebrus 0:6bc4ac881c8e 526 */
ebrus 0:6bc4ac881c8e 527 #define LPC_SPIFI_BASE 0x40003000
ebrus 0:6bc4ac881c8e 528
ebrus 0:6bc4ac881c8e 529 typedef struct { /* SPIFI Structure */
ebrus 0:6bc4ac881c8e 530 __IO uint32_t CTRL; /* Control register */
ebrus 0:6bc4ac881c8e 531 __IO uint32_t CMD; /* Command register */
ebrus 0:6bc4ac881c8e 532 __IO uint32_t ADDR; /* Address register */
ebrus 0:6bc4ac881c8e 533 __IO uint32_t IDATA; /* Intermediate data register */
ebrus 0:6bc4ac881c8e 534 __IO uint32_t CLIMIT; /* Cache limit register */
ebrus 0:6bc4ac881c8e 535 union {
ebrus 0:6bc4ac881c8e 536 __IO uint32_t DATA;
ebrus 0:6bc4ac881c8e 537 __IO uint16_t DATA_HWORD;
ebrus 0:6bc4ac881c8e 538 __IO uint8_t DATA_BYTE;
ebrus 0:6bc4ac881c8e 539 }; /* Data register */
ebrus 0:6bc4ac881c8e 540 __IO uint32_t MCMD; /* Memory command register */
ebrus 0:6bc4ac881c8e 541 __IO uint32_t STAT; /* Status register */
ebrus 0:6bc4ac881c8e 542 } LPC_SPIFI_T;
ebrus 0:6bc4ac881c8e 543
ebrus 0:6bc4ac881c8e 544 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 545 * SD/MMC & SDIO register block structure
ebrus 0:6bc4ac881c8e 546 */
ebrus 0:6bc4ac881c8e 547 #define LPC_SDMMC_BASE 0x40004000
ebrus 0:6bc4ac881c8e 548
ebrus 0:6bc4ac881c8e 549 typedef struct { /* SDMMC Structure */
ebrus 0:6bc4ac881c8e 550 __IO uint32_t CTRL; /* Control Register */
ebrus 0:6bc4ac881c8e 551 __IO uint32_t PWREN; /* Power Enable Register */
ebrus 0:6bc4ac881c8e 552 __IO uint32_t CLKDIV; /* Clock Divider Register */
ebrus 0:6bc4ac881c8e 553 __IO uint32_t CLKSRC; /* SD Clock Source Register */
ebrus 0:6bc4ac881c8e 554 __IO uint32_t CLKENA; /* Clock Enable Register */
ebrus 0:6bc4ac881c8e 555 __IO uint32_t TMOUT; /* Timeout Register */
ebrus 0:6bc4ac881c8e 556 __IO uint32_t CTYPE; /* Card Type Register */
ebrus 0:6bc4ac881c8e 557 __IO uint32_t BLKSIZ; /* Block Size Register */
ebrus 0:6bc4ac881c8e 558 __IO uint32_t BYTCNT; /* Byte Count Register */
ebrus 0:6bc4ac881c8e 559 __IO uint32_t INTMASK; /* Interrupt Mask Register */
ebrus 0:6bc4ac881c8e 560 __IO uint32_t CMDARG; /* Command Argument Register */
ebrus 0:6bc4ac881c8e 561 __IO uint32_t CMD; /* Command Register */
ebrus 0:6bc4ac881c8e 562 __I uint32_t RESP0; /* Response Register 0 */
ebrus 0:6bc4ac881c8e 563 __I uint32_t RESP1; /* Response Register 1 */
ebrus 0:6bc4ac881c8e 564 __I uint32_t RESP2; /* Response Register 2 */
ebrus 0:6bc4ac881c8e 565 __I uint32_t RESP3; /* Response Register 3 */
ebrus 0:6bc4ac881c8e 566 __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
ebrus 0:6bc4ac881c8e 567 __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
ebrus 0:6bc4ac881c8e 568 __I uint32_t STATUS; /* Status Register */
ebrus 0:6bc4ac881c8e 569 __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
ebrus 0:6bc4ac881c8e 570 __I uint32_t CDETECT; /* Card Detect Register */
ebrus 0:6bc4ac881c8e 571 __I uint32_t WRTPRT; /* Write Protect Register */
ebrus 0:6bc4ac881c8e 572 __IO uint32_t GPIO; /* General Purpose Input/Output Register */
ebrus 0:6bc4ac881c8e 573 __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
ebrus 0:6bc4ac881c8e 574 __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
ebrus 0:6bc4ac881c8e 575 __IO uint32_t DEBNCE; /* Debounce Count Register */
ebrus 0:6bc4ac881c8e 576 __IO uint32_t USRID; /* User ID Register */
ebrus 0:6bc4ac881c8e 577 __I uint32_t VERID; /* Version ID Register */
ebrus 0:6bc4ac881c8e 578 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 579 __IO uint32_t UHS_REG; /* UHS-1 Register */
ebrus 0:6bc4ac881c8e 580 __IO uint32_t RST_N; /* Hardware Reset */
ebrus 0:6bc4ac881c8e 581 __I uint32_t RESERVED1;
ebrus 0:6bc4ac881c8e 582 __IO uint32_t BMOD; /* Bus Mode Register */
ebrus 0:6bc4ac881c8e 583 __O uint32_t PLDMND; /* Poll Demand Register */
ebrus 0:6bc4ac881c8e 584 __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
ebrus 0:6bc4ac881c8e 585 __IO uint32_t IDSTS; /* Internal DMAC Status Register */
ebrus 0:6bc4ac881c8e 586 __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
ebrus 0:6bc4ac881c8e 587 __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
ebrus 0:6bc4ac881c8e 588 __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
ebrus 0:6bc4ac881c8e 589 } LPC_SDMMC_T;
ebrus 0:6bc4ac881c8e 590
ebrus 0:6bc4ac881c8e 591 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 592 * External Memory Controller (EMC) register block structure
ebrus 0:6bc4ac881c8e 593 */
ebrus 0:6bc4ac881c8e 594 #define LPC_EMC_BASE 0x40005000
ebrus 0:6bc4ac881c8e 595
ebrus 0:6bc4ac881c8e 596 typedef struct { /* EMC Structure */
ebrus 0:6bc4ac881c8e 597 __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
ebrus 0:6bc4ac881c8e 598 __I uint32_t STATUS; /* Provides EMC status information. */
ebrus 0:6bc4ac881c8e 599 __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
ebrus 0:6bc4ac881c8e 600 __I uint32_t RESERVED0[5];
ebrus 0:6bc4ac881c8e 601 __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
ebrus 0:6bc4ac881c8e 602 __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
ebrus 0:6bc4ac881c8e 603 __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
ebrus 0:6bc4ac881c8e 604 __I uint32_t RESERVED1;
ebrus 0:6bc4ac881c8e 605 __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
ebrus 0:6bc4ac881c8e 606 __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
ebrus 0:6bc4ac881c8e 607 __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
ebrus 0:6bc4ac881c8e 608 __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
ebrus 0:6bc4ac881c8e 609 __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
ebrus 0:6bc4ac881c8e 610 __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
ebrus 0:6bc4ac881c8e 611 __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
ebrus 0:6bc4ac881c8e 612 __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
ebrus 0:6bc4ac881c8e 613 __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
ebrus 0:6bc4ac881c8e 614 __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
ebrus 0:6bc4ac881c8e 615 __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
ebrus 0:6bc4ac881c8e 616 __I uint32_t RESERVED2[9];
ebrus 0:6bc4ac881c8e 617 __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
ebrus 0:6bc4ac881c8e 618 __I uint32_t RESERVED3[31];
ebrus 0:6bc4ac881c8e 619 __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 620 __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 621 __I uint32_t RESERVED4[6];
ebrus 0:6bc4ac881c8e 622 __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 623 __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 624 __I uint32_t RESERVED5[6];
ebrus 0:6bc4ac881c8e 625 __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 626 __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 627 __I uint32_t RESERVED6[6];
ebrus 0:6bc4ac881c8e 628 __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 629 __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:6bc4ac881c8e 630 __I uint32_t RESERVED7[38];
ebrus 0:6bc4ac881c8e 631 __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
ebrus 0:6bc4ac881c8e 632 __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
ebrus 0:6bc4ac881c8e 633 __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:6bc4ac881c8e 634 __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
ebrus 0:6bc4ac881c8e 635 __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:6bc4ac881c8e 636 __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
ebrus 0:6bc4ac881c8e 637 __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
ebrus 0:6bc4ac881c8e 638 __I uint32_t RESERVED8;
ebrus 0:6bc4ac881c8e 639 __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
ebrus 0:6bc4ac881c8e 640 __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
ebrus 0:6bc4ac881c8e 641 __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:6bc4ac881c8e 642 __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
ebrus 0:6bc4ac881c8e 643 __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:6bc4ac881c8e 644 __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
ebrus 0:6bc4ac881c8e 645 __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
ebrus 0:6bc4ac881c8e 646 __I uint32_t RESERVED9;
ebrus 0:6bc4ac881c8e 647 __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
ebrus 0:6bc4ac881c8e 648 __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
ebrus 0:6bc4ac881c8e 649 __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:6bc4ac881c8e 650 __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
ebrus 0:6bc4ac881c8e 651 __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:6bc4ac881c8e 652 __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
ebrus 0:6bc4ac881c8e 653 __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
ebrus 0:6bc4ac881c8e 654 __I uint32_t RESERVED10;
ebrus 0:6bc4ac881c8e 655 __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
ebrus 0:6bc4ac881c8e 656 __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
ebrus 0:6bc4ac881c8e 657 __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:6bc4ac881c8e 658 __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
ebrus 0:6bc4ac881c8e 659 __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:6bc4ac881c8e 660 __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
ebrus 0:6bc4ac881c8e 661 __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
ebrus 0:6bc4ac881c8e 662 } LPC_EMC_T;
ebrus 0:6bc4ac881c8e 663
ebrus 0:6bc4ac881c8e 664 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 665 * USB High-Speed register block structure
ebrus 0:6bc4ac881c8e 666 */
ebrus 0:6bc4ac881c8e 667 #define LPC_USB0_BASE 0x40006000
ebrus 0:6bc4ac881c8e 668 #define LPC_USB1_BASE 0x40007000
ebrus 0:6bc4ac881c8e 669
ebrus 0:6bc4ac881c8e 670 typedef struct { /* USB Structure */
ebrus 0:6bc4ac881c8e 671 __I uint32_t RESERVED0[64];
ebrus 0:6bc4ac881c8e 672 __I uint32_t CAPLENGTH; /* Capability register length */
ebrus 0:6bc4ac881c8e 673 __I uint32_t HCSPARAMS; /* Host controller structural parameters */
ebrus 0:6bc4ac881c8e 674 __I uint32_t HCCPARAMS; /* Host controller capability parameters */
ebrus 0:6bc4ac881c8e 675 __I uint32_t RESERVED1[5];
ebrus 0:6bc4ac881c8e 676 __I uint32_t DCIVERSION; /* Device interface version number */
ebrus 0:6bc4ac881c8e 677 __I uint32_t RESERVED2[7];
ebrus 0:6bc4ac881c8e 678 union {
ebrus 0:6bc4ac881c8e 679 __IO uint32_t USBCMD_H; /* USB command (host mode) */
ebrus 0:6bc4ac881c8e 680 __IO uint32_t USBCMD_D; /* USB command (device mode) */
ebrus 0:6bc4ac881c8e 681 };
ebrus 0:6bc4ac881c8e 682
ebrus 0:6bc4ac881c8e 683 union {
ebrus 0:6bc4ac881c8e 684 __IO uint32_t USBSTS_H; /* USB status (host mode) */
ebrus 0:6bc4ac881c8e 685 __IO uint32_t USBSTS_D; /* USB status (device mode) */
ebrus 0:6bc4ac881c8e 686 };
ebrus 0:6bc4ac881c8e 687
ebrus 0:6bc4ac881c8e 688 union {
ebrus 0:6bc4ac881c8e 689 __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
ebrus 0:6bc4ac881c8e 690 __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
ebrus 0:6bc4ac881c8e 691 };
ebrus 0:6bc4ac881c8e 692
ebrus 0:6bc4ac881c8e 693 union {
ebrus 0:6bc4ac881c8e 694 __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
ebrus 0:6bc4ac881c8e 695 __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
ebrus 0:6bc4ac881c8e 696 };
ebrus 0:6bc4ac881c8e 697
ebrus 0:6bc4ac881c8e 698 __I uint32_t RESERVED3;
ebrus 0:6bc4ac881c8e 699 union {
ebrus 0:6bc4ac881c8e 700 __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
ebrus 0:6bc4ac881c8e 701 __IO uint32_t DEVICEADDR; /* USB device address */
ebrus 0:6bc4ac881c8e 702 };
ebrus 0:6bc4ac881c8e 703
ebrus 0:6bc4ac881c8e 704 union {
ebrus 0:6bc4ac881c8e 705 __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
ebrus 0:6bc4ac881c8e 706 __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
ebrus 0:6bc4ac881c8e 707 };
ebrus 0:6bc4ac881c8e 708
ebrus 0:6bc4ac881c8e 709 __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
ebrus 0:6bc4ac881c8e 710 __IO uint32_t BURSTSIZE; /* Programmable burst size */
ebrus 0:6bc4ac881c8e 711 __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
ebrus 0:6bc4ac881c8e 712 __I uint32_t RESERVED4[2];
ebrus 0:6bc4ac881c8e 713 __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
ebrus 0:6bc4ac881c8e 714 __IO uint32_t BINTERVAL; /* Length of virtual frame */
ebrus 0:6bc4ac881c8e 715 __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
ebrus 0:6bc4ac881c8e 716 __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
ebrus 0:6bc4ac881c8e 717 __I uint32_t RESERVED5;
ebrus 0:6bc4ac881c8e 718 union {
ebrus 0:6bc4ac881c8e 719 __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
ebrus 0:6bc4ac881c8e 720 __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
ebrus 0:6bc4ac881c8e 721 };
ebrus 0:6bc4ac881c8e 722
ebrus 0:6bc4ac881c8e 723 __I uint32_t RESERVED6[7];
ebrus 0:6bc4ac881c8e 724 __IO uint32_t OTGSC; /* OTG status and control */
ebrus 0:6bc4ac881c8e 725 union {
ebrus 0:6bc4ac881c8e 726 __IO uint32_t USBMODE_H; /* USB mode (host mode) */
ebrus 0:6bc4ac881c8e 727 __IO uint32_t USBMODE_D; /* USB mode (device mode) */
ebrus 0:6bc4ac881c8e 728 };
ebrus 0:6bc4ac881c8e 729
ebrus 0:6bc4ac881c8e 730 __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
ebrus 0:6bc4ac881c8e 731 __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
ebrus 0:6bc4ac881c8e 732 __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
ebrus 0:6bc4ac881c8e 733 __I uint32_t ENDPTSTAT; /* Endpoint status */
ebrus 0:6bc4ac881c8e 734 __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
ebrus 0:6bc4ac881c8e 735 __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
ebrus 0:6bc4ac881c8e 736 } LPC_USBHS_T;
ebrus 0:6bc4ac881c8e 737
ebrus 0:6bc4ac881c8e 738 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 739 * LCD Controller register block structure
ebrus 0:6bc4ac881c8e 740 */
ebrus 0:6bc4ac881c8e 741 #define LPC_LCD_BASE 0x40008000
ebrus 0:6bc4ac881c8e 742
ebrus 0:6bc4ac881c8e 743 typedef struct { /* LCD Structure */
ebrus 0:6bc4ac881c8e 744 __IO uint32_t TIMH; /* Horizontal Timing Control register */
ebrus 0:6bc4ac881c8e 745 __IO uint32_t TIMV; /* Vertical Timing Control register */
ebrus 0:6bc4ac881c8e 746 __IO uint32_t POL; /* Clock and Signal Polarity Control register */
ebrus 0:6bc4ac881c8e 747 __IO uint32_t LE; /* Line End Control register */
ebrus 0:6bc4ac881c8e 748 __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
ebrus 0:6bc4ac881c8e 749 __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
ebrus 0:6bc4ac881c8e 750 __IO uint32_t CTRL; /* LCD Control register */
ebrus 0:6bc4ac881c8e 751 __IO uint32_t INTMSK; /* Interrupt Mask register */
ebrus 0:6bc4ac881c8e 752 __I uint32_t INTRAW; /* Raw Interrupt Status register */
ebrus 0:6bc4ac881c8e 753 __I uint32_t INTSTAT; /* Masked Interrupt Status register */
ebrus 0:6bc4ac881c8e 754 __O uint32_t INTCLR; /* Interrupt Clear register */
ebrus 0:6bc4ac881c8e 755 __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
ebrus 0:6bc4ac881c8e 756 __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
ebrus 0:6bc4ac881c8e 757 __I uint32_t RESERVED0[115];
ebrus 0:6bc4ac881c8e 758 __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
ebrus 0:6bc4ac881c8e 759 __I uint32_t RESERVED1[256];
ebrus 0:6bc4ac881c8e 760 __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
ebrus 0:6bc4ac881c8e 761 __IO uint32_t CRSR_CTRL; /* Cursor Control register */
ebrus 0:6bc4ac881c8e 762 __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
ebrus 0:6bc4ac881c8e 763 __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
ebrus 0:6bc4ac881c8e 764 __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
ebrus 0:6bc4ac881c8e 765 __IO uint32_t CRSR_XY; /* Cursor XY Position register */
ebrus 0:6bc4ac881c8e 766 __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
ebrus 0:6bc4ac881c8e 767 __I uint32_t RESERVED2[2];
ebrus 0:6bc4ac881c8e 768 __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
ebrus 0:6bc4ac881c8e 769 __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
ebrus 0:6bc4ac881c8e 770 __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
ebrus 0:6bc4ac881c8e 771 __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
ebrus 0:6bc4ac881c8e 772 } LPC_LCD_T;
ebrus 0:6bc4ac881c8e 773
ebrus 0:6bc4ac881c8e 774 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 775 * EEPROM register block structure
ebrus 0:6bc4ac881c8e 776 */
ebrus 0:6bc4ac881c8e 777 #define LPC_EEPROM_BASE 0x4000E000
ebrus 0:6bc4ac881c8e 778
ebrus 0:6bc4ac881c8e 779 typedef struct { /* EEPROM Structure */
ebrus 0:6bc4ac881c8e 780 __IO uint32_t CMD; /* EEPROM command register */
ebrus 0:6bc4ac881c8e 781 uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 782 __IO uint32_t RWSTATE; /* EEPROM read wait state register */
ebrus 0:6bc4ac881c8e 783 __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
ebrus 0:6bc4ac881c8e 784 __IO uint32_t WSTATE; /* EEPROM wait state register */
ebrus 0:6bc4ac881c8e 785 __IO uint32_t CLKDIV; /* EEPROM clock divider register */
ebrus 0:6bc4ac881c8e 786 __IO uint32_t PWRDWN; /* EEPROM power-down register */
ebrus 0:6bc4ac881c8e 787 uint32_t RESERVED2[1007];
ebrus 0:6bc4ac881c8e 788 __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
ebrus 0:6bc4ac881c8e 789 __O uint32_t INTENSET; /* EEPROM interrupt enable set */
ebrus 0:6bc4ac881c8e 790 __I uint32_t INTSTAT; /* EEPROM interrupt status */
ebrus 0:6bc4ac881c8e 791 __I uint32_t INTEN; /* EEPROM interrupt enable */
ebrus 0:6bc4ac881c8e 792 __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
ebrus 0:6bc4ac881c8e 793 __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
ebrus 0:6bc4ac881c8e 794 } LPC_EEPROM_T;
ebrus 0:6bc4ac881c8e 795
ebrus 0:6bc4ac881c8e 796 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 797 * 10/100 MII & RMII Ethernet with timestamping register block structure
ebrus 0:6bc4ac881c8e 798 */
ebrus 0:6bc4ac881c8e 799 #define LPC_ETHERNET_BASE 0x40010000
ebrus 0:6bc4ac881c8e 800
ebrus 0:6bc4ac881c8e 801 typedef struct { /* ETHERNET Structure */
ebrus 0:6bc4ac881c8e 802 __IO uint32_t MAC_CONFIG; /* MAC configuration register */
ebrus 0:6bc4ac881c8e 803 __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
ebrus 0:6bc4ac881c8e 804 __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
ebrus 0:6bc4ac881c8e 805 __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
ebrus 0:6bc4ac881c8e 806 __IO uint32_t MAC_MII_ADDR; /* MII address register */
ebrus 0:6bc4ac881c8e 807 __IO uint32_t MAC_MII_DATA; /* MII data register */
ebrus 0:6bc4ac881c8e 808 __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
ebrus 0:6bc4ac881c8e 809 __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
ebrus 0:6bc4ac881c8e 810 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 811 __I uint32_t MAC_DEBUG; /* Debug register */
ebrus 0:6bc4ac881c8e 812 __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
ebrus 0:6bc4ac881c8e 813 __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
ebrus 0:6bc4ac881c8e 814 __I uint32_t RESERVED1[2];
ebrus 0:6bc4ac881c8e 815 __I uint32_t MAC_INTR; /* Interrupt status register */
ebrus 0:6bc4ac881c8e 816 __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
ebrus 0:6bc4ac881c8e 817 __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
ebrus 0:6bc4ac881c8e 818 __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
ebrus 0:6bc4ac881c8e 819 __I uint32_t RESERVED2[430];
ebrus 0:6bc4ac881c8e 820 __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
ebrus 0:6bc4ac881c8e 821 __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
ebrus 0:6bc4ac881c8e 822 __I uint32_t SECONDS; /* System time seconds register */
ebrus 0:6bc4ac881c8e 823 __I uint32_t NANOSECONDS; /* System time nanoseconds register */
ebrus 0:6bc4ac881c8e 824 __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
ebrus 0:6bc4ac881c8e 825 __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
ebrus 0:6bc4ac881c8e 826 __IO uint32_t ADDEND; /* Time stamp addend register */
ebrus 0:6bc4ac881c8e 827 __IO uint32_t TARGETSECONDS; /* Target time seconds register */
ebrus 0:6bc4ac881c8e 828 __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
ebrus 0:6bc4ac881c8e 829 __IO uint32_t HIGHWORD; /* System time higher word seconds register */
ebrus 0:6bc4ac881c8e 830 __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
ebrus 0:6bc4ac881c8e 831 __IO uint32_t PPSCTRL; /* PPS control register */
ebrus 0:6bc4ac881c8e 832 __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
ebrus 0:6bc4ac881c8e 833 __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
ebrus 0:6bc4ac881c8e 834 __I uint32_t RESERVED3[562];
ebrus 0:6bc4ac881c8e 835 __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
ebrus 0:6bc4ac881c8e 836 __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
ebrus 0:6bc4ac881c8e 837 __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
ebrus 0:6bc4ac881c8e 838 __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
ebrus 0:6bc4ac881c8e 839 __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
ebrus 0:6bc4ac881c8e 840 __IO uint32_t DMA_STAT; /* Status register */
ebrus 0:6bc4ac881c8e 841 __IO uint32_t DMA_OP_MODE; /* Operation mode register */
ebrus 0:6bc4ac881c8e 842 __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
ebrus 0:6bc4ac881c8e 843 __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
ebrus 0:6bc4ac881c8e 844 __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
ebrus 0:6bc4ac881c8e 845 __I uint32_t RESERVED4[8];
ebrus 0:6bc4ac881c8e 846 __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
ebrus 0:6bc4ac881c8e 847 __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
ebrus 0:6bc4ac881c8e 848 __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
ebrus 0:6bc4ac881c8e 849 __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
ebrus 0:6bc4ac881c8e 850 } LPC_ENET_T;
ebrus 0:6bc4ac881c8e 851
ebrus 0:6bc4ac881c8e 852 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 853 * Alarm Timer register block structure
ebrus 0:6bc4ac881c8e 854 */
ebrus 0:6bc4ac881c8e 855 #define LPC_ATIMER_BASE 0x40040000
ebrus 0:6bc4ac881c8e 856
ebrus 0:6bc4ac881c8e 857 typedef struct { /* ATIMER Structure */
ebrus 0:6bc4ac881c8e 858 __IO uint32_t DOWNCOUNTER; /* Downcounter register */
ebrus 0:6bc4ac881c8e 859 __IO uint32_t PRESET; /* Preset value register */
ebrus 0:6bc4ac881c8e 860 __I uint32_t RESERVED0[1012];
ebrus 0:6bc4ac881c8e 861 __O uint32_t CLR_EN; /* Interrupt clear enable register */
ebrus 0:6bc4ac881c8e 862 __O uint32_t SET_EN; /* Interrupt set enable register */
ebrus 0:6bc4ac881c8e 863 __I uint32_t STATUS; /* Status register */
ebrus 0:6bc4ac881c8e 864 __I uint32_t ENABLE; /* Enable register */
ebrus 0:6bc4ac881c8e 865 __O uint32_t CLR_STAT; /* Clear register */
ebrus 0:6bc4ac881c8e 866 __O uint32_t SET_STAT; /* Set register */
ebrus 0:6bc4ac881c8e 867 } LPC_ATIMER_T;
ebrus 0:6bc4ac881c8e 868
ebrus 0:6bc4ac881c8e 869 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 870 * Register File register block structure
ebrus 0:6bc4ac881c8e 871 */
ebrus 0:6bc4ac881c8e 872 #define LPC_REGFILE_BASE 0x40041000
ebrus 0:6bc4ac881c8e 873
ebrus 0:6bc4ac881c8e 874 typedef struct {
ebrus 0:6bc4ac881c8e 875 __IO uint32_t REGFILE[64]; /* General purpose storage register */
ebrus 0:6bc4ac881c8e 876 } LPC_REGFILE_T;
ebrus 0:6bc4ac881c8e 877
ebrus 0:6bc4ac881c8e 878 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 879 * Power Management Controller register block structure
ebrus 0:6bc4ac881c8e 880 */
ebrus 0:6bc4ac881c8e 881 #define LPC_PMC_BASE 0x40042000
ebrus 0:6bc4ac881c8e 882
ebrus 0:6bc4ac881c8e 883 typedef struct { /* PMC Structure */
ebrus 0:6bc4ac881c8e 884 __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
ebrus 0:6bc4ac881c8e 885 __I uint32_t RESERVED0[6];
ebrus 0:6bc4ac881c8e 886 __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
ebrus 0:6bc4ac881c8e 887 } LPC_PMC_T;
ebrus 0:6bc4ac881c8e 888
ebrus 0:6bc4ac881c8e 889 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 890 * CREG Register Block
ebrus 0:6bc4ac881c8e 891 */
ebrus 0:6bc4ac881c8e 892 #define LPC_CREG_BASE 0x40043000
ebrus 0:6bc4ac881c8e 893
ebrus 0:6bc4ac881c8e 894 typedef struct { /* CREG Structure */
ebrus 0:6bc4ac881c8e 895 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 896 __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
ebrus 0:6bc4ac881c8e 897 __I uint32_t RESERVED1[62];
ebrus 0:6bc4ac881c8e 898 __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
ebrus 0:6bc4ac881c8e 899 #if defined(CHIP_LPC18XX)
ebrus 0:6bc4ac881c8e 900 __I uint32_t RESERVED2[5];
ebrus 0:6bc4ac881c8e 901 #else
ebrus 0:6bc4ac881c8e 902 __I uint32_t RESERVED2;
ebrus 0:6bc4ac881c8e 903 __I uint32_t CREG1; /* Configuration Register 1 */
ebrus 0:6bc4ac881c8e 904 __I uint32_t CREG2; /* Configuration Register 2 */
ebrus 0:6bc4ac881c8e 905 __I uint32_t CREG3; /* Configuration Register 3 */
ebrus 0:6bc4ac881c8e 906 __I uint32_t CREG4; /* Configuration Register 4 */
ebrus 0:6bc4ac881c8e 907 #endif
ebrus 0:6bc4ac881c8e 908 __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
ebrus 0:6bc4ac881c8e 909 __IO uint32_t DMAMUX; /* DMA muxing control */
ebrus 0:6bc4ac881c8e 910 __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
ebrus 0:6bc4ac881c8e 911 __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
ebrus 0:6bc4ac881c8e 912 __IO uint32_t ETBCFG; /* ETB RAM configuration */
ebrus 0:6bc4ac881c8e 913 __IO uint32_t CREG6; /* Chip configuration register 6. */
ebrus 0:6bc4ac881c8e 914 #if defined(CHIP_LPC18XX)
ebrus 0:6bc4ac881c8e 915 __I uint32_t RESERVED4[52];
ebrus 0:6bc4ac881c8e 916 #else
ebrus 0:6bc4ac881c8e 917 __IO uint32_t M4TXEVENT; /* M4 IPC event register */
ebrus 0:6bc4ac881c8e 918 __I uint32_t RESERVED4[51];
ebrus 0:6bc4ac881c8e 919 #endif
ebrus 0:6bc4ac881c8e 920 __I uint32_t CHIPID; /* Part ID */
ebrus 0:6bc4ac881c8e 921 #if defined(CHIP_LPC18XX)
ebrus 0:6bc4ac881c8e 922 __I uint32_t RESERVED5[191];
ebrus 0:6bc4ac881c8e 923 #else
ebrus 0:6bc4ac881c8e 924 __I uint32_t RESERVED5[127];
ebrus 0:6bc4ac881c8e 925 __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
ebrus 0:6bc4ac881c8e 926 __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
ebrus 0:6bc4ac881c8e 927 __I uint32_t RESERVED6[62];
ebrus 0:6bc4ac881c8e 928 #endif
ebrus 0:6bc4ac881c8e 929 __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
ebrus 0:6bc4ac881c8e 930 __I uint32_t RESERVED7[63];
ebrus 0:6bc4ac881c8e 931 __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
ebrus 0:6bc4ac881c8e 932 } LPC_CREG_T;
ebrus 0:6bc4ac881c8e 933
ebrus 0:6bc4ac881c8e 934 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 935 * Event Router register structure
ebrus 0:6bc4ac881c8e 936 */
ebrus 0:6bc4ac881c8e 937 #define LPC_EVRT_BASE 0x40044000
ebrus 0:6bc4ac881c8e 938
ebrus 0:6bc4ac881c8e 939 typedef struct { /* EVENTROUTER Structure */
ebrus 0:6bc4ac881c8e 940 __IO uint32_t HILO; /* Level configuration register */
ebrus 0:6bc4ac881c8e 941 __IO uint32_t EDGE; /* Edge configuration */
ebrus 0:6bc4ac881c8e 942 __I uint32_t RESERVED0[1012];
ebrus 0:6bc4ac881c8e 943 __O uint32_t CLR_EN; /* Event clear enable register */
ebrus 0:6bc4ac881c8e 944 __O uint32_t SET_EN; /* Event set enable register */
ebrus 0:6bc4ac881c8e 945 __I uint32_t STATUS; /* Status register */
ebrus 0:6bc4ac881c8e 946 __I uint32_t ENABLE; /* Enable register */
ebrus 0:6bc4ac881c8e 947 __O uint32_t CLR_STAT; /* Clear register */
ebrus 0:6bc4ac881c8e 948 __O uint32_t SET_STAT; /* Set register */
ebrus 0:6bc4ac881c8e 949 } LPC_EVRT_T;
ebrus 0:6bc4ac881c8e 950
ebrus 0:6bc4ac881c8e 951 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 952 * Real Time Clock register block structure
ebrus 0:6bc4ac881c8e 953 */
ebrus 0:6bc4ac881c8e 954 #define LPC_RTC_BASE 0x40046000
ebrus 0:6bc4ac881c8e 955 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
ebrus 0:6bc4ac881c8e 956
ebrus 0:6bc4ac881c8e 957 typedef enum RTC_TIMEINDEX {
ebrus 0:6bc4ac881c8e 958 RTC_TIMETYPE_SECOND, /* Second */
ebrus 0:6bc4ac881c8e 959 RTC_TIMETYPE_MINUTE, /* Month */
ebrus 0:6bc4ac881c8e 960 RTC_TIMETYPE_HOUR, /* Hour */
ebrus 0:6bc4ac881c8e 961 RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
ebrus 0:6bc4ac881c8e 962 RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
ebrus 0:6bc4ac881c8e 963 RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
ebrus 0:6bc4ac881c8e 964 RTC_TIMETYPE_MONTH, /* Month */
ebrus 0:6bc4ac881c8e 965 RTC_TIMETYPE_YEAR, /* Year */
ebrus 0:6bc4ac881c8e 966 RTC_TIMETYPE_LAST
ebrus 0:6bc4ac881c8e 967 } RTC_TIMEINDEX_T;
ebrus 0:6bc4ac881c8e 968
ebrus 0:6bc4ac881c8e 969 #if RTC_EV_SUPPORT
ebrus 0:6bc4ac881c8e 970 typedef enum LPC_RTC_EV_CHANNEL {
ebrus 0:6bc4ac881c8e 971 RTC_EV_CHANNEL_1 = 0,
ebrus 0:6bc4ac881c8e 972 RTC_EV_CHANNEL_2,
ebrus 0:6bc4ac881c8e 973 RTC_EV_CHANNEL_3,
ebrus 0:6bc4ac881c8e 974 RTC_EV_CHANNEL_NUM,
ebrus 0:6bc4ac881c8e 975 } LPC_RTC_EV_CHANNEL_T;
ebrus 0:6bc4ac881c8e 976 #endif /*RTC_EV_SUPPORT*/
ebrus 0:6bc4ac881c8e 977
ebrus 0:6bc4ac881c8e 978 typedef struct { /* RTC Structure */
ebrus 0:6bc4ac881c8e 979 __IO uint32_t ILR; /* Interrupt Location Register */
ebrus 0:6bc4ac881c8e 980 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 981 __IO uint32_t CCR; /* Clock Control Register */
ebrus 0:6bc4ac881c8e 982 __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
ebrus 0:6bc4ac881c8e 983 __IO uint32_t AMR; /* Alarm Mask Register */
ebrus 0:6bc4ac881c8e 984 __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
ebrus 0:6bc4ac881c8e 985 __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
ebrus 0:6bc4ac881c8e 986 __IO uint32_t CALIBRATION; /* Calibration Value Register */
ebrus 0:6bc4ac881c8e 987 __I uint32_t RESERVED1[7];
ebrus 0:6bc4ac881c8e 988 __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
ebrus 0:6bc4ac881c8e 989 #if RTC_EV_SUPPORT
ebrus 0:6bc4ac881c8e 990 __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
ebrus 0:6bc4ac881c8e 991 __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
ebrus 0:6bc4ac881c8e 992 __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
ebrus 0:6bc4ac881c8e 993 __I uint32_t RESERVED2;
ebrus 0:6bc4ac881c8e 994 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
ebrus 0:6bc4ac881c8e 995 __I uint32_t RESERVED3;
ebrus 0:6bc4ac881c8e 996 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
ebrus 0:6bc4ac881c8e 997 #endif /*RTC_EV_SUPPORT*/
ebrus 0:6bc4ac881c8e 998 } LPC_RTC_T;
ebrus 0:6bc4ac881c8e 999
ebrus 0:6bc4ac881c8e 1000 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1001 * LPC18XX/43XX CGU register block structure
ebrus 0:6bc4ac881c8e 1002 */
ebrus 0:6bc4ac881c8e 1003 #define LPC_CGU_BASE 0x40050000
ebrus 0:6bc4ac881c8e 1004 #define LPC_CCU1_BASE 0x40051000
ebrus 0:6bc4ac881c8e 1005 #define LPC_CCU2_BASE 0x40052000
ebrus 0:6bc4ac881c8e 1006 /*
ebrus 0:6bc4ac881c8e 1007 * Input clocks for the CGU and can come from both external (crystal) and
ebrus 0:6bc4ac881c8e 1008 * internal (PLL) sources. Can be routed to the base clocks.
ebrus 0:6bc4ac881c8e 1009 */
ebrus 0:6bc4ac881c8e 1010 typedef enum CGU_CLKIN {
ebrus 0:6bc4ac881c8e 1011 CLKIN_32K, /* External 32KHz input */
ebrus 0:6bc4ac881c8e 1012 CLKIN_IRC, /* Internal IRC (12MHz) input */
ebrus 0:6bc4ac881c8e 1013 CLKIN_ENET_RX, /* External ENET_RX pin input */
ebrus 0:6bc4ac881c8e 1014 CLKIN_ENET_TX, /* External ENET_TX pin input */
ebrus 0:6bc4ac881c8e 1015 CLKIN_CLKIN, /* External GPCLKIN pin input */
ebrus 0:6bc4ac881c8e 1016 CLKIN_RESERVED1,
ebrus 0:6bc4ac881c8e 1017 CLKIN_CRYSTAL, /* External (main) crystal pin input */
ebrus 0:6bc4ac881c8e 1018 CLKIN_USBPLL, /* Internal USB PLL input */
ebrus 0:6bc4ac881c8e 1019 CLKIN_AUDIOPLL, /* Internal Audio PLL input */
ebrus 0:6bc4ac881c8e 1020 CLKIN_MAINPLL, /* Internal Main PLL input */
ebrus 0:6bc4ac881c8e 1021 CLKIN_RESERVED2,
ebrus 0:6bc4ac881c8e 1022 CLKIN_RESERVED3,
ebrus 0:6bc4ac881c8e 1023 CLKIN_IDIVA, /* Internal divider A input */
ebrus 0:6bc4ac881c8e 1024 CLKIN_IDIVB, /* Internal divider B input */
ebrus 0:6bc4ac881c8e 1025 CLKIN_IDIVC, /* Internal divider C input */
ebrus 0:6bc4ac881c8e 1026 CLKIN_IDIVD, /* Internal divider D input */
ebrus 0:6bc4ac881c8e 1027 CLKIN_IDIVE, /* Internal divider E input */
ebrus 0:6bc4ac881c8e 1028 CLKINPUT_PD /* External 32KHz input */
ebrus 0:6bc4ac881c8e 1029 } CGU_CLKIN_T;
ebrus 0:6bc4ac881c8e 1030
ebrus 0:6bc4ac881c8e 1031 #define CLKIN_PLL0USB CLKIN_USBPLL
ebrus 0:6bc4ac881c8e 1032 #define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
ebrus 0:6bc4ac881c8e 1033 #define CLKIN_PLL1 CLKIN_MAINPLL
ebrus 0:6bc4ac881c8e 1034
ebrus 0:6bc4ac881c8e 1035 /*
ebrus 0:6bc4ac881c8e 1036 * CGU base clocks are clocks that are associated with a single input clock
ebrus 0:6bc4ac881c8e 1037 * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
ebrus 0:6bc4ac881c8e 1038 * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
ebrus 0:6bc4ac881c8e 1039 * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
ebrus 0:6bc4ac881c8e 1040 * CLK_PERIPH_SGPIO periphral clocks.
ebrus 0:6bc4ac881c8e 1041 */
ebrus 0:6bc4ac881c8e 1042 typedef enum CGU_BASE_CLK {
ebrus 0:6bc4ac881c8e 1043 CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
ebrus 0:6bc4ac881c8e 1044 CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
ebrus 0:6bc4ac881c8e 1045 #if defined(CHIP_LPC43XX)
ebrus 0:6bc4ac881c8e 1046 CLK_BASE_PERIPH, /* Base clock for SGPIO */
ebrus 0:6bc4ac881c8e 1047 #else
ebrus 0:6bc4ac881c8e 1048 CLK_BASE_RESERVED1,
ebrus 0:6bc4ac881c8e 1049 #endif
ebrus 0:6bc4ac881c8e 1050 CLK_BASE_USB1, /* Base USB clock for USB1 */
ebrus 0:6bc4ac881c8e 1051 CLK_BASE_MX, /* Base clock for CPU core */
ebrus 0:6bc4ac881c8e 1052 CLK_BASE_SPIFI, /* Base clock for SPIFI */
ebrus 0:6bc4ac881c8e 1053 #if defined(CHIP_LPC43XX)
ebrus 0:6bc4ac881c8e 1054 CLK_BASE_SPI, /* Base clock for SPI */
ebrus 0:6bc4ac881c8e 1055 #else
ebrus 0:6bc4ac881c8e 1056 CLK_BASE_RESERVED2,
ebrus 0:6bc4ac881c8e 1057 #endif
ebrus 0:6bc4ac881c8e 1058 CLK_BASE_PHY_RX, /* Base clock for PHY RX */
ebrus 0:6bc4ac881c8e 1059 CLK_BASE_PHY_TX, /* Base clock for PHY TX */
ebrus 0:6bc4ac881c8e 1060 CLK_BASE_APB1, /* Base clock for APB1 group */
ebrus 0:6bc4ac881c8e 1061 CLK_BASE_APB3, /* Base clock for APB3 group */
ebrus 0:6bc4ac881c8e 1062 CLK_BASE_LCD, /* Base clock for LCD pixel clock */
ebrus 0:6bc4ac881c8e 1063 #if defined(CHIP_LPC43XX)
ebrus 0:6bc4ac881c8e 1064 CLK_BASE_VADC, /* Base clock for VADC */
ebrus 0:6bc4ac881c8e 1065 #else
ebrus 0:6bc4ac881c8e 1066 CLK_BASE_RESERVED3,
ebrus 0:6bc4ac881c8e 1067 #endif
ebrus 0:6bc4ac881c8e 1068 CLK_BASE_SDIO, /* Base clock for SDIO */
ebrus 0:6bc4ac881c8e 1069 CLK_BASE_SSP0, /* Base clock for SSP0 */
ebrus 0:6bc4ac881c8e 1070 CLK_BASE_SSP1, /* Base clock for SSP1 */
ebrus 0:6bc4ac881c8e 1071 CLK_BASE_UART0, /* Base clock for UART0 */
ebrus 0:6bc4ac881c8e 1072 CLK_BASE_UART1, /* Base clock for UART1 */
ebrus 0:6bc4ac881c8e 1073 CLK_BASE_UART2, /* Base clock for UART2 */
ebrus 0:6bc4ac881c8e 1074 CLK_BASE_UART3, /* Base clock for UART3 */
ebrus 0:6bc4ac881c8e 1075 CLK_BASE_OUT, /* Base clock for CLKOUT pin */
ebrus 0:6bc4ac881c8e 1076 CLK_BASE_RESERVED4,
ebrus 0:6bc4ac881c8e 1077 CLK_BASE_RESERVED5,
ebrus 0:6bc4ac881c8e 1078 CLK_BASE_RESERVED6,
ebrus 0:6bc4ac881c8e 1079 CLK_BASE_RESERVED7,
ebrus 0:6bc4ac881c8e 1080 CLK_BASE_APLL, /* Base clock for audio PLL */
ebrus 0:6bc4ac881c8e 1081 CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
ebrus 0:6bc4ac881c8e 1082 CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
ebrus 0:6bc4ac881c8e 1083 CLK_BASE_LAST,
ebrus 0:6bc4ac881c8e 1084 CLK_BASE_NONE = CLK_BASE_LAST
ebrus 0:6bc4ac881c8e 1085 } CGU_BASE_CLK_T;
ebrus 0:6bc4ac881c8e 1086
ebrus 0:6bc4ac881c8e 1087 /*
ebrus 0:6bc4ac881c8e 1088 * CGU dividers provide an extra clock state where a specific clock can be
ebrus 0:6bc4ac881c8e 1089 * divided before being routed to a peripheral group. A divider accepts an
ebrus 0:6bc4ac881c8e 1090 * input clock and then divides it. To use the divided clock for a base clock
ebrus 0:6bc4ac881c8e 1091 * group, use the divider as the input clock for the base clock (for example,
ebrus 0:6bc4ac881c8e 1092 * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
ebrus 0:6bc4ac881c8e 1093 */
ebrus 0:6bc4ac881c8e 1094 typedef enum CGU_IDIV {
ebrus 0:6bc4ac881c8e 1095 CLK_IDIV_A, /* CGU clock divider A */
ebrus 0:6bc4ac881c8e 1096 CLK_IDIV_B, /* CGU clock divider B */
ebrus 0:6bc4ac881c8e 1097 CLK_IDIV_C, /* CGU clock divider A */
ebrus 0:6bc4ac881c8e 1098 CLK_IDIV_D, /* CGU clock divider D */
ebrus 0:6bc4ac881c8e 1099 CLK_IDIV_E, /* CGU clock divider E */
ebrus 0:6bc4ac881c8e 1100 CLK_IDIV_LAST
ebrus 0:6bc4ac881c8e 1101 } CGU_IDIV_T;
ebrus 0:6bc4ac881c8e 1102
ebrus 0:6bc4ac881c8e 1103 /*
ebrus 0:6bc4ac881c8e 1104 * Peripheral clocks are individual clocks routed to peripherals. Although
ebrus 0:6bc4ac881c8e 1105 * multiple peripherals may share a same base clock, each peripheral's clock
ebrus 0:6bc4ac881c8e 1106 * can be enabled or disabled individually. Some peripheral clocks also have
ebrus 0:6bc4ac881c8e 1107 * additional dividers associated with them.
ebrus 0:6bc4ac881c8e 1108 */
ebrus 0:6bc4ac881c8e 1109 typedef enum CCU_CLK {
ebrus 0:6bc4ac881c8e 1110 /* CCU1 clocks */
ebrus 0:6bc4ac881c8e 1111 CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
ebrus 0:6bc4ac881c8e 1112 CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:6bc4ac881c8e 1113 CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
ebrus 0:6bc4ac881c8e 1114 CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:6bc4ac881c8e 1115 CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:6bc4ac881c8e 1116 CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:6bc4ac881c8e 1117 CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
ebrus 0:6bc4ac881c8e 1118 CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:6bc4ac881c8e 1119 CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:6bc4ac881c8e 1120 CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:6bc4ac881c8e 1121 CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:6bc4ac881c8e 1122 CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
ebrus 0:6bc4ac881c8e 1123 CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1124 CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1125 CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1126 CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1127 CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1128 CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1129 CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1130 CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1131 CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1132 CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1133 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
ebrus 0:6bc4ac881c8e 1134 CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1135 CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1136 CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1137 CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1138 CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1139 #if defined(CHIP_LPC43XX)
ebrus 0:6bc4ac881c8e 1140 CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1141 CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1142 #else
ebrus 0:6bc4ac881c8e 1143 CLK_RESERVED1,
ebrus 0:6bc4ac881c8e 1144 CLK_RESERVED2,
ebrus 0:6bc4ac881c8e 1145 #endif
ebrus 0:6bc4ac881c8e 1146 CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1147 CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1148 CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1149 CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1150 CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1151 CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1152 CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1153 CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1154 CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1155 CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1156 CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1157 CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1158 CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1159 CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1160 CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1161 CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:6bc4ac881c8e 1162 #if defined(CHIP_LPC43XX)
ebrus 0:6bc4ac881c8e 1163 CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
ebrus 0:6bc4ac881c8e 1164 CLK_RESERVED3,
ebrus 0:6bc4ac881c8e 1165 CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
ebrus 0:6bc4ac881c8e 1166 CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
ebrus 0:6bc4ac881c8e 1167 #else
ebrus 0:6bc4ac881c8e 1168 CLK_RESERVED3 = 192,
ebrus 0:6bc4ac881c8e 1169 CLK_RESERVED3A,
ebrus 0:6bc4ac881c8e 1170 CLK_RESERVED4,
ebrus 0:6bc4ac881c8e 1171 CLK_RESERVED5,
ebrus 0:6bc4ac881c8e 1172 #endif
ebrus 0:6bc4ac881c8e 1173 CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
ebrus 0:6bc4ac881c8e 1174 CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
ebrus 0:6bc4ac881c8e 1175 #if defined(CHIP_LPC43XX)
ebrus 0:6bc4ac881c8e 1176 CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
ebrus 0:6bc4ac881c8e 1177 CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
ebrus 0:6bc4ac881c8e 1178 #else
ebrus 0:6bc4ac881c8e 1179 CLK_RESERVED7 = 320,
ebrus 0:6bc4ac881c8e 1180 CLK_RESERVED8,
ebrus 0:6bc4ac881c8e 1181 #endif
ebrus 0:6bc4ac881c8e 1182 CLK_CCU1_LAST,
ebrus 0:6bc4ac881c8e 1183
ebrus 0:6bc4ac881c8e 1184 /* CCU2 clocks */
ebrus 0:6bc4ac881c8e 1185 CLK_CCU2_START,
ebrus 0:6bc4ac881c8e 1186 CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
ebrus 0:6bc4ac881c8e 1187 RESERVED_ALIGNB = CLK_CCU2_START + 31,
ebrus 0:6bc4ac881c8e 1188 CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
ebrus 0:6bc4ac881c8e 1189 RESERVED_ALIGNC = CLK_CCU2_START + 63,
ebrus 0:6bc4ac881c8e 1190 CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
ebrus 0:6bc4ac881c8e 1191 RESERVED_ALIGND = CLK_CCU2_START + 95,
ebrus 0:6bc4ac881c8e 1192 CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
ebrus 0:6bc4ac881c8e 1193 RESERVED_ALIGNE = CLK_CCU2_START + 127,
ebrus 0:6bc4ac881c8e 1194 CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
ebrus 0:6bc4ac881c8e 1195 RESERVED_ALIGNF = CLK_CCU2_START + 159,
ebrus 0:6bc4ac881c8e 1196 CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
ebrus 0:6bc4ac881c8e 1197 RESERVED_ALIGNG = CLK_CCU2_START + 191,
ebrus 0:6bc4ac881c8e 1198 CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
ebrus 0:6bc4ac881c8e 1199 RESERVED_ALIGNH = CLK_CCU2_START + 223,
ebrus 0:6bc4ac881c8e 1200 CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
ebrus 0:6bc4ac881c8e 1201 CLK_CCU2_LAST
ebrus 0:6bc4ac881c8e 1202 } CCU_CLK_T;
ebrus 0:6bc4ac881c8e 1203
ebrus 0:6bc4ac881c8e 1204 /*
ebrus 0:6bc4ac881c8e 1205 * Audio or USB PLL selection
ebrus 0:6bc4ac881c8e 1206 */
ebrus 0:6bc4ac881c8e 1207 typedef enum CGU_USB_AUDIO_PLL {
ebrus 0:6bc4ac881c8e 1208 CGU_USB_PLL,
ebrus 0:6bc4ac881c8e 1209 CGU_AUDIO_PLL
ebrus 0:6bc4ac881c8e 1210 } CGU_USB_AUDIO_PLL_T;
ebrus 0:6bc4ac881c8e 1211
ebrus 0:6bc4ac881c8e 1212 /*
ebrus 0:6bc4ac881c8e 1213 * PLL register block
ebrus 0:6bc4ac881c8e 1214 */
ebrus 0:6bc4ac881c8e 1215 typedef struct {
ebrus 0:6bc4ac881c8e 1216 __I uint32_t PLL_STAT; /* PLL status register */
ebrus 0:6bc4ac881c8e 1217 __IO uint32_t PLL_CTRL; /* PLL control register */
ebrus 0:6bc4ac881c8e 1218 __IO uint32_t PLL_MDIV; /* PLL M-divider register */
ebrus 0:6bc4ac881c8e 1219 __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
ebrus 0:6bc4ac881c8e 1220 } CGU_PLL_REG_T;
ebrus 0:6bc4ac881c8e 1221
ebrus 0:6bc4ac881c8e 1222 typedef struct { /* (@ 0x40050000) CGU Structure */
ebrus 0:6bc4ac881c8e 1223 __I uint32_t RESERVED0[5];
ebrus 0:6bc4ac881c8e 1224 __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
ebrus 0:6bc4ac881c8e 1225 __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
ebrus 0:6bc4ac881c8e 1226 CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
ebrus 0:6bc4ac881c8e 1227 __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
ebrus 0:6bc4ac881c8e 1228 __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
ebrus 0:6bc4ac881c8e 1229 __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
ebrus 0:6bc4ac881c8e 1230 __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
ebrus 0:6bc4ac881c8e 1231 __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
ebrus 0:6bc4ac881c8e 1232 } LPC_CGU_T;
ebrus 0:6bc4ac881c8e 1233
ebrus 0:6bc4ac881c8e 1234 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1235 * CCU clock config/status register pair
ebrus 0:6bc4ac881c8e 1236 */
ebrus 0:6bc4ac881c8e 1237 typedef struct {
ebrus 0:6bc4ac881c8e 1238 __IO uint32_t CFG; /* CCU clock configuration register */
ebrus 0:6bc4ac881c8e 1239 __I uint32_t STAT; /* CCU clock status register */
ebrus 0:6bc4ac881c8e 1240 } CCU_CFGSTAT_T;
ebrus 0:6bc4ac881c8e 1241
ebrus 0:6bc4ac881c8e 1242 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1243 * CCU1 register block structure
ebrus 0:6bc4ac881c8e 1244 */
ebrus 0:6bc4ac881c8e 1245 typedef struct { /* (@ 0x40051000) CCU1 Structure */
ebrus 0:6bc4ac881c8e 1246 __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
ebrus 0:6bc4ac881c8e 1247 __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
ebrus 0:6bc4ac881c8e 1248 __I uint32_t RESERVED0[62];
ebrus 0:6bc4ac881c8e 1249 CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
ebrus 0:6bc4ac881c8e 1250 } LPC_CCU1_T;
ebrus 0:6bc4ac881c8e 1251
ebrus 0:6bc4ac881c8e 1252 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1253 * CCU2 register block structure
ebrus 0:6bc4ac881c8e 1254 */
ebrus 0:6bc4ac881c8e 1255 typedef struct { /* (@ 0x40052000) CCU2 Structure */
ebrus 0:6bc4ac881c8e 1256 __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
ebrus 0:6bc4ac881c8e 1257 __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
ebrus 0:6bc4ac881c8e 1258 __I uint32_t RESERVED0[62];
ebrus 0:6bc4ac881c8e 1259 CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
ebrus 0:6bc4ac881c8e 1260 } LPC_CCU2_T;
ebrus 0:6bc4ac881c8e 1261
ebrus 0:6bc4ac881c8e 1262 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1263 * RGU register structure
ebrus 0:6bc4ac881c8e 1264 */
ebrus 0:6bc4ac881c8e 1265 #define LPC_RGU_BASE 0x40053000
ebrus 0:6bc4ac881c8e 1266
ebrus 0:6bc4ac881c8e 1267 typedef enum RGU_RST {
ebrus 0:6bc4ac881c8e 1268 RGU_CORE_RST,
ebrus 0:6bc4ac881c8e 1269 RGU_PERIPH_RST,
ebrus 0:6bc4ac881c8e 1270 RGU_MASTER_RST,
ebrus 0:6bc4ac881c8e 1271 RGU_WWDT_RST = 4,
ebrus 0:6bc4ac881c8e 1272 RGU_CREG_RST,
ebrus 0:6bc4ac881c8e 1273 RGU_BUS_RST = 8,
ebrus 0:6bc4ac881c8e 1274 RGU_SCU_RST,
ebrus 0:6bc4ac881c8e 1275 RGU_M3_RST = 13,
ebrus 0:6bc4ac881c8e 1276 RGU_LCD_RST = 16,
ebrus 0:6bc4ac881c8e 1277 RGU_USB0_RST,
ebrus 0:6bc4ac881c8e 1278 RGU_USB1_RST,
ebrus 0:6bc4ac881c8e 1279 RGU_DMA_RST,
ebrus 0:6bc4ac881c8e 1280 RGU_SDIO_RST,
ebrus 0:6bc4ac881c8e 1281 RGU_EMC_RST,
ebrus 0:6bc4ac881c8e 1282 RGU_ETHERNET_RST,
ebrus 0:6bc4ac881c8e 1283 RGU_FLASHA_RST = 25,
ebrus 0:6bc4ac881c8e 1284 RGU_EEPROM_RST = 27,
ebrus 0:6bc4ac881c8e 1285 RGU_GPIO_RST,
ebrus 0:6bc4ac881c8e 1286 RGU_FLASHB_RST,
ebrus 0:6bc4ac881c8e 1287 RGU_TIMER0_RST = 32,
ebrus 0:6bc4ac881c8e 1288 RGU_TIMER1_RST,
ebrus 0:6bc4ac881c8e 1289 RGU_TIMER2_RST,
ebrus 0:6bc4ac881c8e 1290 RGU_TIMER3_RST,
ebrus 0:6bc4ac881c8e 1291 RGU_RITIMER_RST,
ebrus 0:6bc4ac881c8e 1292 RGU_SCT_RST,
ebrus 0:6bc4ac881c8e 1293 RGU_MOTOCONPWM_RST,
ebrus 0:6bc4ac881c8e 1294 RGU_QEI_RST,
ebrus 0:6bc4ac881c8e 1295 RGU_ADC0_RST,
ebrus 0:6bc4ac881c8e 1296 RGU_ADC1_RST,
ebrus 0:6bc4ac881c8e 1297 RGU_DAC_RST,
ebrus 0:6bc4ac881c8e 1298 RGU_UART0_RST = 44,
ebrus 0:6bc4ac881c8e 1299 RGU_UART1_RST,
ebrus 0:6bc4ac881c8e 1300 RGU_UART2_RST,
ebrus 0:6bc4ac881c8e 1301 RGU_UART3_RST,
ebrus 0:6bc4ac881c8e 1302 RGU_I2C0_RST,
ebrus 0:6bc4ac881c8e 1303 RGU_I2C1_RST,
ebrus 0:6bc4ac881c8e 1304 RGU_SSP0_RST,
ebrus 0:6bc4ac881c8e 1305 RGU_SSP1_RST,
ebrus 0:6bc4ac881c8e 1306 RGU_I2S_RST,
ebrus 0:6bc4ac881c8e 1307 RGU_SPIFI_RST,
ebrus 0:6bc4ac881c8e 1308 RGU_CAN1_RST,
ebrus 0:6bc4ac881c8e 1309 RGU_CAN0_RST,
ebrus 0:6bc4ac881c8e 1310 #ifdef CHIP_LPC43XX
ebrus 0:6bc4ac881c8e 1311 RGU_M0APP_RST,
ebrus 0:6bc4ac881c8e 1312 RGU_SGPIO_RST,
ebrus 0:6bc4ac881c8e 1313 RGU_SPI_RST,
ebrus 0:6bc4ac881c8e 1314 #endif
ebrus 0:6bc4ac881c8e 1315 RGU_LAST_RST = 63,
ebrus 0:6bc4ac881c8e 1316 } RGU_RST_T;
ebrus 0:6bc4ac881c8e 1317
ebrus 0:6bc4ac881c8e 1318 typedef struct { /* RGU Structure */
ebrus 0:6bc4ac881c8e 1319 __I uint32_t RESERVED0[64];
ebrus 0:6bc4ac881c8e 1320 __O uint32_t RESET_CTRL0; /* Reset control register 0 */
ebrus 0:6bc4ac881c8e 1321 __O uint32_t RESET_CTRL1; /* Reset control register 1 */
ebrus 0:6bc4ac881c8e 1322 __I uint32_t RESERVED1[2];
ebrus 0:6bc4ac881c8e 1323 __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
ebrus 0:6bc4ac881c8e 1324 __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
ebrus 0:6bc4ac881c8e 1325 __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
ebrus 0:6bc4ac881c8e 1326 __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
ebrus 0:6bc4ac881c8e 1327 __I uint32_t RESERVED2[12];
ebrus 0:6bc4ac881c8e 1328 __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
ebrus 0:6bc4ac881c8e 1329 __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
ebrus 0:6bc4ac881c8e 1330 __I uint32_t RESERVED3[170];
ebrus 0:6bc4ac881c8e 1331 __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
ebrus 0:6bc4ac881c8e 1332 } LPC_RGU_T;
ebrus 0:6bc4ac881c8e 1333
ebrus 0:6bc4ac881c8e 1334 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1335 * Windowed Watchdog register block structure
ebrus 0:6bc4ac881c8e 1336 */
ebrus 0:6bc4ac881c8e 1337 #define LPC_WWDT_BASE 0x40080000
ebrus 0:6bc4ac881c8e 1338
ebrus 0:6bc4ac881c8e 1339 typedef struct { /* WWDT Structure */
ebrus 0:6bc4ac881c8e 1340 __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
ebrus 0:6bc4ac881c8e 1341 __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
ebrus 0:6bc4ac881c8e 1342 __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
ebrus 0:6bc4ac881c8e 1343 __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
ebrus 0:6bc4ac881c8e 1344 #ifdef WATCHDOG_CLKSEL_SUPPORT
ebrus 0:6bc4ac881c8e 1345 __IO uint32_t CLKSEL; /* Watchdog clock select register. */
ebrus 0:6bc4ac881c8e 1346 #else
ebrus 0:6bc4ac881c8e 1347 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 1348 #endif
ebrus 0:6bc4ac881c8e 1349 #ifdef WATCHDOG_WINDOW_SUPPORT
ebrus 0:6bc4ac881c8e 1350 __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
ebrus 0:6bc4ac881c8e 1351 __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
ebrus 0:6bc4ac881c8e 1352 #endif
ebrus 0:6bc4ac881c8e 1353 } LPC_WWDT_T;
ebrus 0:6bc4ac881c8e 1354
ebrus 0:6bc4ac881c8e 1355 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1356 * USART register block structure
ebrus 0:6bc4ac881c8e 1357 */
ebrus 0:6bc4ac881c8e 1358 #define LPC_USART0_BASE 0x40081000
ebrus 0:6bc4ac881c8e 1359 #define LPC_UART1_BASE 0x40082000
ebrus 0:6bc4ac881c8e 1360 #define LPC_USART2_BASE 0x400C1000
ebrus 0:6bc4ac881c8e 1361 #define LPC_USART3_BASE 0x400C2000
ebrus 0:6bc4ac881c8e 1362
ebrus 0:6bc4ac881c8e 1363 typedef struct { /* USARTn Structure */
ebrus 0:6bc4ac881c8e 1364
ebrus 0:6bc4ac881c8e 1365 union {
ebrus 0:6bc4ac881c8e 1366 __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
ebrus 0:6bc4ac881c8e 1367 __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
ebrus 0:6bc4ac881c8e 1368 __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
ebrus 0:6bc4ac881c8e 1369 };
ebrus 0:6bc4ac881c8e 1370
ebrus 0:6bc4ac881c8e 1371 union {
ebrus 0:6bc4ac881c8e 1372 __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
ebrus 0:6bc4ac881c8e 1373 __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
ebrus 0:6bc4ac881c8e 1374 };
ebrus 0:6bc4ac881c8e 1375
ebrus 0:6bc4ac881c8e 1376 union {
ebrus 0:6bc4ac881c8e 1377 __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
ebrus 0:6bc4ac881c8e 1378 __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
ebrus 0:6bc4ac881c8e 1379 };
ebrus 0:6bc4ac881c8e 1380
ebrus 0:6bc4ac881c8e 1381 __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
ebrus 0:6bc4ac881c8e 1382 __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
ebrus 0:6bc4ac881c8e 1383 __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
ebrus 0:6bc4ac881c8e 1384 __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
ebrus 0:6bc4ac881c8e 1385 __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
ebrus 0:6bc4ac881c8e 1386 __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
ebrus 0:6bc4ac881c8e 1387 __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
ebrus 0:6bc4ac881c8e 1388 __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
ebrus 0:6bc4ac881c8e 1389 __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
ebrus 0:6bc4ac881c8e 1390 __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
ebrus 0:6bc4ac881c8e 1391 uint32_t RESERVED0[3];
ebrus 0:6bc4ac881c8e 1392 __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
ebrus 0:6bc4ac881c8e 1393 __I uint32_t RESERVED1[1];
ebrus 0:6bc4ac881c8e 1394 __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
ebrus 0:6bc4ac881c8e 1395 __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
ebrus 0:6bc4ac881c8e 1396 __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
ebrus 0:6bc4ac881c8e 1397 __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
ebrus 0:6bc4ac881c8e 1398 union {
ebrus 0:6bc4ac881c8e 1399 __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
ebrus 0:6bc4ac881c8e 1400 __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
ebrus 0:6bc4ac881c8e 1401 };
ebrus 0:6bc4ac881c8e 1402
ebrus 0:6bc4ac881c8e 1403 __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
ebrus 0:6bc4ac881c8e 1404 } LPC_USART_T;
ebrus 0:6bc4ac881c8e 1405
ebrus 0:6bc4ac881c8e 1406 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1407 * SSP register block structure
ebrus 0:6bc4ac881c8e 1408 */
ebrus 0:6bc4ac881c8e 1409 #define LPC_SSP0_BASE 0x40083000
ebrus 0:6bc4ac881c8e 1410 #define LPC_SSP1_BASE 0x400C5000
ebrus 0:6bc4ac881c8e 1411
ebrus 0:6bc4ac881c8e 1412 typedef struct { /* SSPn Structure */
ebrus 0:6bc4ac881c8e 1413 __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
ebrus 0:6bc4ac881c8e 1414 __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
ebrus 0:6bc4ac881c8e 1415 __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
ebrus 0:6bc4ac881c8e 1416 __I uint32_t SR; /* Status Register */
ebrus 0:6bc4ac881c8e 1417 __IO uint32_t CPSR; /* Clock Prescale Register */
ebrus 0:6bc4ac881c8e 1418 __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
ebrus 0:6bc4ac881c8e 1419 __I uint32_t RIS; /* Raw Interrupt Status Register */
ebrus 0:6bc4ac881c8e 1420 __I uint32_t MIS; /* Masked Interrupt Status Register */
ebrus 0:6bc4ac881c8e 1421 __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
ebrus 0:6bc4ac881c8e 1422 __IO uint32_t DMACR; /* SSPn DMA control register */
ebrus 0:6bc4ac881c8e 1423 } LPC_SSP_T;
ebrus 0:6bc4ac881c8e 1424
ebrus 0:6bc4ac881c8e 1425 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1426 * 32-bit Standard timer register block structure
ebrus 0:6bc4ac881c8e 1427 */
ebrus 0:6bc4ac881c8e 1428 #define LPC_TIMER0_BASE 0x40084000
ebrus 0:6bc4ac881c8e 1429 #define LPC_TIMER1_BASE 0x40085000
ebrus 0:6bc4ac881c8e 1430 #define LPC_TIMER2_BASE 0x400C3000
ebrus 0:6bc4ac881c8e 1431 #define LPC_TIMER3_BASE 0x400C4000
ebrus 0:6bc4ac881c8e 1432
ebrus 0:6bc4ac881c8e 1433 typedef struct { /* TIMERn Structure */
ebrus 0:6bc4ac881c8e 1434 __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:6bc4ac881c8e 1435 __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:6bc4ac881c8e 1436 __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:6bc4ac881c8e 1437 __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:6bc4ac881c8e 1438 __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:6bc4ac881c8e 1439 __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:6bc4ac881c8e 1440 __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:6bc4ac881c8e 1441 __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:6bc4ac881c8e 1442 __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
ebrus 0:6bc4ac881c8e 1443 __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
ebrus 0:6bc4ac881c8e 1444 __I uint32_t RESERVED0[12];
ebrus 0:6bc4ac881c8e 1445 __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:6bc4ac881c8e 1446 } LPC_TIMER_T;
ebrus 0:6bc4ac881c8e 1447
ebrus 0:6bc4ac881c8e 1448 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1449 * System Control Unit register block
ebrus 0:6bc4ac881c8e 1450 */
ebrus 0:6bc4ac881c8e 1451 #define LPC_SCU_BASE 0x40086000
ebrus 0:6bc4ac881c8e 1452
ebrus 0:6bc4ac881c8e 1453 typedef struct {
ebrus 0:6bc4ac881c8e 1454 __IO uint32_t SFSP[16][32];
ebrus 0:6bc4ac881c8e 1455 __I uint32_t RESERVED0[256];
ebrus 0:6bc4ac881c8e 1456 __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
ebrus 0:6bc4ac881c8e 1457 __I uint32_t RESERVED16[28];
ebrus 0:6bc4ac881c8e 1458 __IO uint32_t SFSUSB; /* Pin configuration register for USB */
ebrus 0:6bc4ac881c8e 1459 __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
ebrus 0:6bc4ac881c8e 1460 __IO uint32_t ENAIO[3]; /* Analog function select registers */
ebrus 0:6bc4ac881c8e 1461 __I uint32_t RESERVED17[27];
ebrus 0:6bc4ac881c8e 1462 __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
ebrus 0:6bc4ac881c8e 1463 __I uint32_t RESERVED18[63];
ebrus 0:6bc4ac881c8e 1464 __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
ebrus 0:6bc4ac881c8e 1465 __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
ebrus 0:6bc4ac881c8e 1466 } LPC_SCU_T;
ebrus 0:6bc4ac881c8e 1467
ebrus 0:6bc4ac881c8e 1468 /*
ebrus 0:6bc4ac881c8e 1469 * SCU function and mode selection definitions
ebrus 0:6bc4ac881c8e 1470 * See the User Manual for specific modes and functions supoprted by the
ebrus 0:6bc4ac881c8e 1471 * various LPC18xx/43xx devices. Functionality can vary per device.
ebrus 0:6bc4ac881c8e 1472 */
ebrus 0:6bc4ac881c8e 1473 #define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
ebrus 0:6bc4ac881c8e 1474 #define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
ebrus 0:6bc4ac881c8e 1475 #define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
ebrus 0:6bc4ac881c8e 1476 #define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
ebrus 0:6bc4ac881c8e 1477 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
ebrus 0:6bc4ac881c8e 1478 #define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
ebrus 0:6bc4ac881c8e 1479 #define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
ebrus 0:6bc4ac881c8e 1480 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
ebrus 0:6bc4ac881c8e 1481 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
ebrus 0:6bc4ac881c8e 1482 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
ebrus 0:6bc4ac881c8e 1483 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
ebrus 0:6bc4ac881c8e 1484
ebrus 0:6bc4ac881c8e 1485 #define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
ebrus 0:6bc4ac881c8e 1486 #define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
ebrus 0:6bc4ac881c8e 1487 #define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
ebrus 0:6bc4ac881c8e 1488 #define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
ebrus 0:6bc4ac881c8e 1489 #define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
ebrus 0:6bc4ac881c8e 1490 #define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
ebrus 0:6bc4ac881c8e 1491 #define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
ebrus 0:6bc4ac881c8e 1492 #define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
ebrus 0:6bc4ac881c8e 1493
ebrus 0:6bc4ac881c8e 1494 /* Common SCU configurations */
ebrus 0:6bc4ac881c8e 1495 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
ebrus 0:6bc4ac881c8e 1496 #define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
ebrus 0:6bc4ac881c8e 1497 #define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
ebrus 0:6bc4ac881c8e 1498 #define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
ebrus 0:6bc4ac881c8e 1499
ebrus 0:6bc4ac881c8e 1500 /* Calculate SCU offset and register address from group and pin number */
ebrus 0:6bc4ac881c8e 1501 #define SCU_OFF(group, num) ((group << 7) + (num << 2))
ebrus 0:6bc4ac881c8e 1502 #define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
ebrus 0:6bc4ac881c8e 1503
ebrus 0:6bc4ac881c8e 1504 /**
ebrus 0:6bc4ac881c8e 1505 * SCU function and mode selection definitions (old)
ebrus 0:6bc4ac881c8e 1506 * For backwards compatibility.
ebrus 0:6bc4ac881c8e 1507 */
ebrus 0:6bc4ac881c8e 1508 #define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
ebrus 0:6bc4ac881c8e 1509 #define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
ebrus 0:6bc4ac881c8e 1510 #define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
ebrus 0:6bc4ac881c8e 1511 #define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
ebrus 0:6bc4ac881c8e 1512 #define MD_EHS (0x1 << 5) /* Enable fast slew rate */
ebrus 0:6bc4ac881c8e 1513 #define MD_EZI (0x1 << 6) /* Input buffer enable */
ebrus 0:6bc4ac881c8e 1514 #define MD_ZI (0x1 << 7) /* Disable input glitch filter */
ebrus 0:6bc4ac881c8e 1515 #define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
ebrus 0:6bc4ac881c8e 1516 #define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
ebrus 0:6bc4ac881c8e 1517 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
ebrus 0:6bc4ac881c8e 1518 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
ebrus 0:6bc4ac881c8e 1519 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
ebrus 0:6bc4ac881c8e 1520
ebrus 0:6bc4ac881c8e 1521 #define FUNC0 0x0 /* Pin function 0 */
ebrus 0:6bc4ac881c8e 1522 #define FUNC1 0x1 /* Pin function 1 */
ebrus 0:6bc4ac881c8e 1523 #define FUNC2 0x2 /* Pin function 2 */
ebrus 0:6bc4ac881c8e 1524 #define FUNC3 0x3 /* Pin function 3 */
ebrus 0:6bc4ac881c8e 1525 #define FUNC4 0x4 /* Pin function 4 */
ebrus 0:6bc4ac881c8e 1526 #define FUNC5 0x5 /* Pin function 5 */
ebrus 0:6bc4ac881c8e 1527 #define FUNC6 0x6 /* Pin function 6 */
ebrus 0:6bc4ac881c8e 1528 #define FUNC7 0x7 /* Pin function 7 */
ebrus 0:6bc4ac881c8e 1529
ebrus 0:6bc4ac881c8e 1530 #define PORT_OFFSET 0x80 /* Port offset definition */
ebrus 0:6bc4ac881c8e 1531 #define PIN_OFFSET 0x04 /* Pin offset definition */
ebrus 0:6bc4ac881c8e 1532
ebrus 0:6bc4ac881c8e 1533 /* Returns the SFSP register address in the SCU for a pin and port,
ebrus 0:6bc4ac881c8e 1534 recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
ebrus 0:6bc4ac881c8e 1535 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
ebrus 0:6bc4ac881c8e 1536 (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
ebrus 0:6bc4ac881c8e 1537
ebrus 0:6bc4ac881c8e 1538 /* Returns the address in the SCU for a SFSCLK clock register,
ebrus 0:6bc4ac881c8e 1539 recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
ebrus 0:6bc4ac881c8e 1540 #define LPC_SCU_CLK(LPC_SCU_BASE, c) \
ebrus 0:6bc4ac881c8e 1541 (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
ebrus 0:6bc4ac881c8e 1542
ebrus 0:6bc4ac881c8e 1543 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1544 * GPIO pin interrupt register block structure
ebrus 0:6bc4ac881c8e 1545 */
ebrus 0:6bc4ac881c8e 1546 #define LPC_GPIO_PIN_INT_BASE 0x40087000
ebrus 0:6bc4ac881c8e 1547
ebrus 0:6bc4ac881c8e 1548 typedef struct { /* GPIO_PIN_INT Structure */
ebrus 0:6bc4ac881c8e 1549 __IO uint32_t ISEL; /* Pin Interrupt Mode register */
ebrus 0:6bc4ac881c8e 1550 __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
ebrus 0:6bc4ac881c8e 1551 __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
ebrus 0:6bc4ac881c8e 1552 __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
ebrus 0:6bc4ac881c8e 1553 __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:6bc4ac881c8e 1554 __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:6bc4ac881c8e 1555 __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
ebrus 0:6bc4ac881c8e 1556 __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
ebrus 0:6bc4ac881c8e 1557 __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
ebrus 0:6bc4ac881c8e 1558 __IO uint32_t IST; /* Pin Interrupt Status register */
ebrus 0:6bc4ac881c8e 1559 } LPC_GPIOPININT_T;
ebrus 0:6bc4ac881c8e 1560
ebrus 0:6bc4ac881c8e 1561 typedef enum LPC_GPIOPININT_MODE {
ebrus 0:6bc4ac881c8e 1562 GPIOPININT_RISING_EDGE = 0x01,
ebrus 0:6bc4ac881c8e 1563 GPIOPININT_FALLING_EDGE = 0x02,
ebrus 0:6bc4ac881c8e 1564 GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
ebrus 0:6bc4ac881c8e 1565 GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
ebrus 0:6bc4ac881c8e 1566 } LPC_GPIOPININT_MODE_T;
ebrus 0:6bc4ac881c8e 1567
ebrus 0:6bc4ac881c8e 1568 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1569 * GPIO grouped interrupt register block structure
ebrus 0:6bc4ac881c8e 1570 */
ebrus 0:6bc4ac881c8e 1571 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
ebrus 0:6bc4ac881c8e 1572 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
ebrus 0:6bc4ac881c8e 1573
ebrus 0:6bc4ac881c8e 1574 typedef struct { /* GPIO_GROUP_INTn Structure */
ebrus 0:6bc4ac881c8e 1575 __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
ebrus 0:6bc4ac881c8e 1576 __I uint32_t RESERVED0[7];
ebrus 0:6bc4ac881c8e 1577 __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
ebrus 0:6bc4ac881c8e 1578 __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
ebrus 0:6bc4ac881c8e 1579 } LPC_GPIOGROUPINT_T;
ebrus 0:6bc4ac881c8e 1580
ebrus 0:6bc4ac881c8e 1581 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1582 * Motor Control PWM register block structure
ebrus 0:6bc4ac881c8e 1583 */
ebrus 0:6bc4ac881c8e 1584 #define LPC_MCPWM_BASE 0x400A0000
ebrus 0:6bc4ac881c8e 1585
ebrus 0:6bc4ac881c8e 1586 typedef struct { /* MCPWM Structure */
ebrus 0:6bc4ac881c8e 1587 __I uint32_t CON; /* PWM Control read address */
ebrus 0:6bc4ac881c8e 1588 __O uint32_t CON_SET; /* PWM Control set address */
ebrus 0:6bc4ac881c8e 1589 __O uint32_t CON_CLR; /* PWM Control clear address */
ebrus 0:6bc4ac881c8e 1590 __I uint32_t CAPCON; /* Capture Control read address */
ebrus 0:6bc4ac881c8e 1591 __O uint32_t CAPCON_SET; /* Capture Control set address */
ebrus 0:6bc4ac881c8e 1592 __O uint32_t CAPCON_CLR; /* Event Control clear address */
ebrus 0:6bc4ac881c8e 1593 __IO uint32_t TC[3]; /* Timer Counter register */
ebrus 0:6bc4ac881c8e 1594 __IO uint32_t LIM[3]; /* Limit register */
ebrus 0:6bc4ac881c8e 1595 __IO uint32_t MAT[3]; /* Match register */
ebrus 0:6bc4ac881c8e 1596 __IO uint32_t DT; /* Dead time register */
ebrus 0:6bc4ac881c8e 1597 __IO uint32_t CCP; /* Communication Pattern register */
ebrus 0:6bc4ac881c8e 1598 __I uint32_t CAP[3]; /* Capture register */
ebrus 0:6bc4ac881c8e 1599 __I uint32_t INTEN; /* Interrupt Enable read address */
ebrus 0:6bc4ac881c8e 1600 __O uint32_t INTEN_SET; /* Interrupt Enable set address */
ebrus 0:6bc4ac881c8e 1601 __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
ebrus 0:6bc4ac881c8e 1602 __I uint32_t CNTCON; /* Count Control read address */
ebrus 0:6bc4ac881c8e 1603 __O uint32_t CNTCON_SET; /* Count Control set address */
ebrus 0:6bc4ac881c8e 1604 __O uint32_t CNTCON_CLR; /* Count Control clear address */
ebrus 0:6bc4ac881c8e 1605 __I uint32_t INTF; /* Interrupt flags read address */
ebrus 0:6bc4ac881c8e 1606 __O uint32_t INTF_SET; /* Interrupt flags set address */
ebrus 0:6bc4ac881c8e 1607 __O uint32_t INTF_CLR; /* Interrupt flags clear address */
ebrus 0:6bc4ac881c8e 1608 __O uint32_t CAP_CLR; /* Capture clear address */
ebrus 0:6bc4ac881c8e 1609 } LPC_MCPWM_T;
ebrus 0:6bc4ac881c8e 1610
ebrus 0:6bc4ac881c8e 1611 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1612 * I2C register block structure
ebrus 0:6bc4ac881c8e 1613 */
ebrus 0:6bc4ac881c8e 1614 #define LPC_I2C0_BASE 0x400A1000
ebrus 0:6bc4ac881c8e 1615 #define LPC_I2C1_BASE 0x400E0000
ebrus 0:6bc4ac881c8e 1616
ebrus 0:6bc4ac881c8e 1617 typedef struct { /* I2C0 Structure */
ebrus 0:6bc4ac881c8e 1618 __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:6bc4ac881c8e 1619 __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
ebrus 0:6bc4ac881c8e 1620 __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
ebrus 0:6bc4ac881c8e 1621 __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:6bc4ac881c8e 1622 __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
ebrus 0:6bc4ac881c8e 1623 __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
ebrus 0:6bc4ac881c8e 1624 __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:6bc4ac881c8e 1625 __IO uint32_t MMCTRL; /* Monitor mode control register. */
ebrus 0:6bc4ac881c8e 1626 __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:6bc4ac881c8e 1627 __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:6bc4ac881c8e 1628 __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:6bc4ac881c8e 1629 __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
ebrus 0:6bc4ac881c8e 1630 __IO uint32_t MASK[4]; /* I2C Slave address mask register */
ebrus 0:6bc4ac881c8e 1631 } LPC_I2C_T;
ebrus 0:6bc4ac881c8e 1632
ebrus 0:6bc4ac881c8e 1633 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1634 * I2S register block structure
ebrus 0:6bc4ac881c8e 1635 */
ebrus 0:6bc4ac881c8e 1636 #define LPC_I2S0_BASE 0x400A2000
ebrus 0:6bc4ac881c8e 1637 #define LPC_I2S1_BASE 0x400A3000
ebrus 0:6bc4ac881c8e 1638
ebrus 0:6bc4ac881c8e 1639 typedef struct { /* I2S Structure */
ebrus 0:6bc4ac881c8e 1640 __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
ebrus 0:6bc4ac881c8e 1641 __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
ebrus 0:6bc4ac881c8e 1642 __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
ebrus 0:6bc4ac881c8e 1643 __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
ebrus 0:6bc4ac881c8e 1644 __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
ebrus 0:6bc4ac881c8e 1645 __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
ebrus 0:6bc4ac881c8e 1646 __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
ebrus 0:6bc4ac881c8e 1647 __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
ebrus 0:6bc4ac881c8e 1648 __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
ebrus 0:6bc4ac881c8e 1649 __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
ebrus 0:6bc4ac881c8e 1650 __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
ebrus 0:6bc4ac881c8e 1651 __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
ebrus 0:6bc4ac881c8e 1652 __IO uint32_t TXMODE; /* I2S Transmit mode control */
ebrus 0:6bc4ac881c8e 1653 __IO uint32_t RXMODE; /* I2S Receive mode control */
ebrus 0:6bc4ac881c8e 1654 } LPC_I2S_T;
ebrus 0:6bc4ac881c8e 1655
ebrus 0:6bc4ac881c8e 1656 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1657 * CCAN Controller Area Network register block structure
ebrus 0:6bc4ac881c8e 1658 */
ebrus 0:6bc4ac881c8e 1659 #define LPC_C_CAN1_BASE 0x400A4000
ebrus 0:6bc4ac881c8e 1660 #define LPC_C_CAN0_BASE 0x400E2000
ebrus 0:6bc4ac881c8e 1661
ebrus 0:6bc4ac881c8e 1662 typedef struct { /* C_CAN message interface Structure */
ebrus 0:6bc4ac881c8e 1663 __IO uint32_t IF_CMDREQ; /* Message interface command request */
ebrus 0:6bc4ac881c8e 1664 union {
ebrus 0:6bc4ac881c8e 1665 __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
ebrus 0:6bc4ac881c8e 1666 __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
ebrus 0:6bc4ac881c8e 1667 };
ebrus 0:6bc4ac881c8e 1668
ebrus 0:6bc4ac881c8e 1669 __IO uint32_t IF_MSK1; /* Message interface mask 1 */
ebrus 0:6bc4ac881c8e 1670 __IO uint32_t IF_MSK2; /* Message interface mask 2 */
ebrus 0:6bc4ac881c8e 1671 __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
ebrus 0:6bc4ac881c8e 1672 __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
ebrus 0:6bc4ac881c8e 1673 __IO uint32_t IF_MCTRL; /* Message interface message control */
ebrus 0:6bc4ac881c8e 1674 __IO uint32_t IF_DA1; /* Message interface data A1 */
ebrus 0:6bc4ac881c8e 1675 __IO uint32_t IF_DA2; /* Message interface data A2 */
ebrus 0:6bc4ac881c8e 1676 __IO uint32_t IF_DB1; /* Message interface data B1 */
ebrus 0:6bc4ac881c8e 1677 __IO uint32_t IF_DB2; /* Message interface data B2 */
ebrus 0:6bc4ac881c8e 1678 __I uint32_t RESERVED[13];
ebrus 0:6bc4ac881c8e 1679 } LPC_CCAN_IF_T;
ebrus 0:6bc4ac881c8e 1680
ebrus 0:6bc4ac881c8e 1681 typedef struct { /* C_CAN Structure */
ebrus 0:6bc4ac881c8e 1682 __IO uint32_t CNTL; /* CAN control */
ebrus 0:6bc4ac881c8e 1683 __IO uint32_t STAT; /* Status register */
ebrus 0:6bc4ac881c8e 1684 __I uint32_t EC; /* Error counter */
ebrus 0:6bc4ac881c8e 1685 __IO uint32_t BT; /* Bit timing register */
ebrus 0:6bc4ac881c8e 1686 __I uint32_t INT; /* Interrupt register */
ebrus 0:6bc4ac881c8e 1687 __IO uint32_t TEST; /* Test register */
ebrus 0:6bc4ac881c8e 1688 __IO uint32_t BRPE; /* Baud rate prescaler extension register */
ebrus 0:6bc4ac881c8e 1689 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 1690 LPC_CCAN_IF_T IF[2];
ebrus 0:6bc4ac881c8e 1691 __I uint32_t RESERVED2[8];
ebrus 0:6bc4ac881c8e 1692 __I uint32_t TXREQ1; /* Transmission request 1 */
ebrus 0:6bc4ac881c8e 1693 __I uint32_t TXREQ2; /* Transmission request 2 */
ebrus 0:6bc4ac881c8e 1694 __I uint32_t RESERVED3[6];
ebrus 0:6bc4ac881c8e 1695 __I uint32_t ND1; /* New data 1 */
ebrus 0:6bc4ac881c8e 1696 __I uint32_t ND2; /* New data 2 */
ebrus 0:6bc4ac881c8e 1697 __I uint32_t RESERVED4[6];
ebrus 0:6bc4ac881c8e 1698 __I uint32_t IR1; /* Interrupt pending 1 */
ebrus 0:6bc4ac881c8e 1699 __I uint32_t IR2; /* Interrupt pending 2 */
ebrus 0:6bc4ac881c8e 1700 __I uint32_t RESERVED5[6];
ebrus 0:6bc4ac881c8e 1701 __I uint32_t MSGV1; /* Message valid 1 */
ebrus 0:6bc4ac881c8e 1702 __I uint32_t MSGV2; /* Message valid 2 */
ebrus 0:6bc4ac881c8e 1703 __I uint32_t RESERVED6[6];
ebrus 0:6bc4ac881c8e 1704 __IO uint32_t CLKDIV; /* CAN clock divider register */
ebrus 0:6bc4ac881c8e 1705 } LPC_CCAN_T;
ebrus 0:6bc4ac881c8e 1706
ebrus 0:6bc4ac881c8e 1707 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1708 * Repetitive Interrupt Timer register block structure
ebrus 0:6bc4ac881c8e 1709 */
ebrus 0:6bc4ac881c8e 1710 #define LPC_RITIMER_BASE 0x400C0000
ebrus 0:6bc4ac881c8e 1711
ebrus 0:6bc4ac881c8e 1712 typedef struct { /* RITIMER Structure */
ebrus 0:6bc4ac881c8e 1713 __IO uint32_t COMPVAL; /* Compare register */
ebrus 0:6bc4ac881c8e 1714 __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
ebrus 0:6bc4ac881c8e 1715 __IO uint32_t CTRL; /* Control register. */
ebrus 0:6bc4ac881c8e 1716 __IO uint32_t COUNTER; /* 32-bit counter */
ebrus 0:6bc4ac881c8e 1717 } LPC_RITIMER_T;
ebrus 0:6bc4ac881c8e 1718
ebrus 0:6bc4ac881c8e 1719 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1720 * Quadrature Encoder Interface register block structure
ebrus 0:6bc4ac881c8e 1721 */
ebrus 0:6bc4ac881c8e 1722 #define LPC_QEI_BASE 0x400C6000
ebrus 0:6bc4ac881c8e 1723
ebrus 0:6bc4ac881c8e 1724 typedef struct { /* QEI Structure */
ebrus 0:6bc4ac881c8e 1725 __O uint32_t CON; /* Control register */
ebrus 0:6bc4ac881c8e 1726 __I uint32_t STAT; /* Encoder status register */
ebrus 0:6bc4ac881c8e 1727 __IO uint32_t CONF; /* Configuration register */
ebrus 0:6bc4ac881c8e 1728 __I uint32_t POS; /* Position register */
ebrus 0:6bc4ac881c8e 1729 __IO uint32_t MAXPOS; /* Maximum position register */
ebrus 0:6bc4ac881c8e 1730 __IO uint32_t CMPOS0; /* position compare register 0 */
ebrus 0:6bc4ac881c8e 1731 __IO uint32_t CMPOS1; /* position compare register 1 */
ebrus 0:6bc4ac881c8e 1732 __IO uint32_t CMPOS2; /* position compare register 2 */
ebrus 0:6bc4ac881c8e 1733 __I uint32_t INXCNT; /* Index count register */
ebrus 0:6bc4ac881c8e 1734 __IO uint32_t INXCMP0; /* Index compare register 0 */
ebrus 0:6bc4ac881c8e 1735 __IO uint32_t LOAD; /* Velocity timer reload register */
ebrus 0:6bc4ac881c8e 1736 __I uint32_t TIME; /* Velocity timer register */
ebrus 0:6bc4ac881c8e 1737 __I uint32_t VEL; /* Velocity counter register */
ebrus 0:6bc4ac881c8e 1738 __I uint32_t CAP; /* Velocity capture register */
ebrus 0:6bc4ac881c8e 1739 __IO uint32_t VELCOMP; /* Velocity compare register */
ebrus 0:6bc4ac881c8e 1740 __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
ebrus 0:6bc4ac881c8e 1741 __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
ebrus 0:6bc4ac881c8e 1742 __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
ebrus 0:6bc4ac881c8e 1743 __IO uint32_t WINDOW; /* Index acceptance window register */
ebrus 0:6bc4ac881c8e 1744 __IO uint32_t INXCMP1; /* Index compare register 1 */
ebrus 0:6bc4ac881c8e 1745 __IO uint32_t INXCMP2; /* Index compare register 2 */
ebrus 0:6bc4ac881c8e 1746 __I uint32_t RESERVED0[993];
ebrus 0:6bc4ac881c8e 1747 __O uint32_t IEC; /* Interrupt enable clear register */
ebrus 0:6bc4ac881c8e 1748 __O uint32_t IES; /* Interrupt enable set register */
ebrus 0:6bc4ac881c8e 1749 __I uint32_t INTSTAT; /* Interrupt status register */
ebrus 0:6bc4ac881c8e 1750 __I uint32_t IE; /* Interrupt enable register */
ebrus 0:6bc4ac881c8e 1751 __O uint32_t CLR; /* Interrupt status clear register */
ebrus 0:6bc4ac881c8e 1752 __O uint32_t SET; /* Interrupt status set register */
ebrus 0:6bc4ac881c8e 1753 } LPC_QEI_T;
ebrus 0:6bc4ac881c8e 1754
ebrus 0:6bc4ac881c8e 1755 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1756 * Global Input Multiplexer Array (GIMA) register block structure
ebrus 0:6bc4ac881c8e 1757 */
ebrus 0:6bc4ac881c8e 1758 #define LPC_GIMA_BASE 0x400C7000
ebrus 0:6bc4ac881c8e 1759
ebrus 0:6bc4ac881c8e 1760 typedef struct { /* GIMA Structure */
ebrus 0:6bc4ac881c8e 1761 __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
ebrus 0:6bc4ac881c8e 1762 __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
ebrus 0:6bc4ac881c8e 1763 __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
ebrus 0:6bc4ac881c8e 1764 __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
ebrus 0:6bc4ac881c8e 1765 __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
ebrus 0:6bc4ac881c8e 1766 __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
ebrus 0:6bc4ac881c8e 1767 __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
ebrus 0:6bc4ac881c8e 1768 __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
ebrus 0:6bc4ac881c8e 1769 } LPC_GIMA_T;
ebrus 0:6bc4ac881c8e 1770
ebrus 0:6bc4ac881c8e 1771 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1772 * DAC register block structure
ebrus 0:6bc4ac881c8e 1773 */
ebrus 0:6bc4ac881c8e 1774 #define LPC_DAC_BASE 0x400E1000
ebrus 0:6bc4ac881c8e 1775
ebrus 0:6bc4ac881c8e 1776 typedef struct { /* DAC Structure */
ebrus 0:6bc4ac881c8e 1777 __IO uint32_t CR; /* DAC register. Holds the conversion data. */
ebrus 0:6bc4ac881c8e 1778 __IO uint32_t CTRL; /* DAC control register. */
ebrus 0:6bc4ac881c8e 1779 __IO uint32_t CNTVAL; /* DAC counter value register. */
ebrus 0:6bc4ac881c8e 1780 } LPC_DAC_T;
ebrus 0:6bc4ac881c8e 1781
ebrus 0:6bc4ac881c8e 1782 /* After the selected settling time after this field is written with a
ebrus 0:6bc4ac881c8e 1783 * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
ebrus 0:6bc4ac881c8e 1784 * is VALUE/1024 ? VREF
ebrus 0:6bc4ac881c8e 1785 */
ebrus 0:6bc4ac881c8e 1786 #define DAC_RANGE 0x3FF
ebrus 0:6bc4ac881c8e 1787 #define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
ebrus 0:6bc4ac881c8e 1788 #define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
ebrus 0:6bc4ac881c8e 1789 #define DAC_VALUE(n) DAC_SET(n)
ebrus 0:6bc4ac881c8e 1790 /* If this bit = 0: The settling time of the DAC is 1 microsecond max,
ebrus 0:6bc4ac881c8e 1791 * and the maximum current is 700 microAmpere
ebrus 0:6bc4ac881c8e 1792 * If this bit = 1: The settling time of the DAC is 2.5 microsecond
ebrus 0:6bc4ac881c8e 1793 * and the maximum current is 350 microAmpere
ebrus 0:6bc4ac881c8e 1794 */
ebrus 0:6bc4ac881c8e 1795 #define DAC_BIAS_EN ((uint32_t) (1 << 16))
ebrus 0:6bc4ac881c8e 1796 /* Value to reload interrupt DMA counter */
ebrus 0:6bc4ac881c8e 1797 #define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
ebrus 0:6bc4ac881c8e 1798
ebrus 0:6bc4ac881c8e 1799 #define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
ebrus 0:6bc4ac881c8e 1800 #define DAC_CNT_ENA ((uint32_t) (1 << 2))
ebrus 0:6bc4ac881c8e 1801 #define DAC_DMA_ENA ((uint32_t) (1 << 3))
ebrus 0:6bc4ac881c8e 1802 #define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
ebrus 0:6bc4ac881c8e 1803
ebrus 0:6bc4ac881c8e 1804 /* Current option in DAC configuration option */
ebrus 0:6bc4ac881c8e 1805 typedef enum DAC_CURRENT_OPT {
ebrus 0:6bc4ac881c8e 1806 DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
ebrus 0:6bc4ac881c8e 1807 allows for a maximum update rate of 1 MHz */
ebrus 0:6bc4ac881c8e 1808 DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
ebrus 0:6bc4ac881c8e 1809 allows for a maximum update rate of 400 kHz */
ebrus 0:6bc4ac881c8e 1810 } DAC_CURRENT_OPT_T;
ebrus 0:6bc4ac881c8e 1811
ebrus 0:6bc4ac881c8e 1812 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1813 * ADC register block structure
ebrus 0:6bc4ac881c8e 1814 */
ebrus 0:6bc4ac881c8e 1815 #define LPC_ADC0_BASE 0x400E3000
ebrus 0:6bc4ac881c8e 1816 #define LPC_ADC1_BASE 0x400E4000
ebrus 0:6bc4ac881c8e 1817 #define ADC_ACC_10BITS
ebrus 0:6bc4ac881c8e 1818
ebrus 0:6bc4ac881c8e 1819 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1820 * 10 or 12-bit ADC register block structure
ebrus 0:6bc4ac881c8e 1821 */
ebrus 0:6bc4ac881c8e 1822 typedef struct { /* ADCn Structure */
ebrus 0:6bc4ac881c8e 1823 __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
ebrus 0:6bc4ac881c8e 1824 __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
ebrus 0:6bc4ac881c8e 1825 __I uint32_t RESERVED0;
ebrus 0:6bc4ac881c8e 1826 __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
ebrus 0:6bc4ac881c8e 1827 __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
ebrus 0:6bc4ac881c8e 1828 __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
ebrus 0:6bc4ac881c8e 1829 } LPC_ADC_T;
ebrus 0:6bc4ac881c8e 1830
ebrus 0:6bc4ac881c8e 1831 /* ADC register support bitfields and mask */
ebrus 0:6bc4ac881c8e 1832 #define ADC_RANGE 0x3FF
ebrus 0:6bc4ac881c8e 1833 #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
ebrus 0:6bc4ac881c8e 1834 #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
ebrus 0:6bc4ac881c8e 1835 #define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
ebrus 0:6bc4ac881c8e 1836 #define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
ebrus 0:6bc4ac881c8e 1837 #define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
ebrus 0:6bc4ac881c8e 1838 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
ebrus 0:6bc4ac881c8e 1839 #define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
ebrus 0:6bc4ac881c8e 1840 #define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
ebrus 0:6bc4ac881c8e 1841 #define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
ebrus 0:6bc4ac881c8e 1842 #define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
ebrus 0:6bc4ac881c8e 1843 #define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
ebrus 0:6bc4ac881c8e 1844 #define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ebrus 0:6bc4ac881c8e 1845 #define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ebrus 0:6bc4ac881c8e 1846 #define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ebrus 0:6bc4ac881c8e 1847 #define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ebrus 0:6bc4ac881c8e 1848 #define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
ebrus 0:6bc4ac881c8e 1849 #define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
ebrus 0:6bc4ac881c8e 1850 #define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
ebrus 0:6bc4ac881c8e 1851
ebrus 0:6bc4ac881c8e 1852 /* ADC status register used for IP drivers */
ebrus 0:6bc4ac881c8e 1853 typedef enum ADC_STATUS {
ebrus 0:6bc4ac881c8e 1854 ADC_DR_DONE_STAT, /* ADC data register staus */
ebrus 0:6bc4ac881c8e 1855 ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
ebrus 0:6bc4ac881c8e 1856 ADC_DR_ADINT_STAT /* ADC interrupt status */
ebrus 0:6bc4ac881c8e 1857 } ADC_STATUS_T;
ebrus 0:6bc4ac881c8e 1858
ebrus 0:6bc4ac881c8e 1859 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
ebrus 0:6bc4ac881c8e 1860 typedef enum ADC_START_MODE {
ebrus 0:6bc4ac881c8e 1861 ADC_NO_START = 0,
ebrus 0:6bc4ac881c8e 1862 ADC_START_NOW, /* Start conversion now */
ebrus 0:6bc4ac881c8e 1863 ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ebrus 0:6bc4ac881c8e 1864 ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ebrus 0:6bc4ac881c8e 1865 ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ebrus 0:6bc4ac881c8e 1866 ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ebrus 0:6bc4ac881c8e 1867 ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
ebrus 0:6bc4ac881c8e 1868 } ADC_START_MODE_T;
ebrus 0:6bc4ac881c8e 1869
ebrus 0:6bc4ac881c8e 1870 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1871 * GPIO port register block structure
ebrus 0:6bc4ac881c8e 1872 */
ebrus 0:6bc4ac881c8e 1873 #define LPC_GPIO_PORT_BASE 0x400F4000
ebrus 0:6bc4ac881c8e 1874 #define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
ebrus 0:6bc4ac881c8e 1875 #define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
ebrus 0:6bc4ac881c8e 1876 #define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
ebrus 0:6bc4ac881c8e 1877 #define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
ebrus 0:6bc4ac881c8e 1878 #define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
ebrus 0:6bc4ac881c8e 1879 #define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
ebrus 0:6bc4ac881c8e 1880 #define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
ebrus 0:6bc4ac881c8e 1881 #define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
ebrus 0:6bc4ac881c8e 1882
ebrus 0:6bc4ac881c8e 1883 typedef struct { /* GPIO_PORT Structure */
ebrus 0:6bc4ac881c8e 1884 __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
ebrus 0:6bc4ac881c8e 1885 __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
ebrus 0:6bc4ac881c8e 1886 __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
ebrus 0:6bc4ac881c8e 1887 __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
ebrus 0:6bc4ac881c8e 1888 __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
ebrus 0:6bc4ac881c8e 1889 __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
ebrus 0:6bc4ac881c8e 1890 __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
ebrus 0:6bc4ac881c8e 1891 __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
ebrus 0:6bc4ac881c8e 1892 __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
ebrus 0:6bc4ac881c8e 1893 } LPC_GPIO_T;
ebrus 0:6bc4ac881c8e 1894
ebrus 0:6bc4ac881c8e 1895 /* Calculate GPIO offset and port register address from group and pin number */
ebrus 0:6bc4ac881c8e 1896 #define GPIO_OFF(port, pin) ((port << 5) + pin)
ebrus 0:6bc4ac881c8e 1897 #define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
ebrus 0:6bc4ac881c8e 1898
ebrus 0:6bc4ac881c8e 1899 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1900 * SPI register block structure
ebrus 0:6bc4ac881c8e 1901 */
ebrus 0:6bc4ac881c8e 1902 #define LPC_SPI_BASE 0x40100000
ebrus 0:6bc4ac881c8e 1903
ebrus 0:6bc4ac881c8e 1904 typedef struct { /* SPI Structure */
ebrus 0:6bc4ac881c8e 1905 __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
ebrus 0:6bc4ac881c8e 1906 __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
ebrus 0:6bc4ac881c8e 1907 __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
ebrus 0:6bc4ac881c8e 1908 __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
ebrus 0:6bc4ac881c8e 1909 __I uint32_t RESERVED0[3];
ebrus 0:6bc4ac881c8e 1910 __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
ebrus 0:6bc4ac881c8e 1911 } LPC_SPI_T;
ebrus 0:6bc4ac881c8e 1912
ebrus 0:6bc4ac881c8e 1913 /* SPI CFG Register BitMask */
ebrus 0:6bc4ac881c8e 1914 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
ebrus 0:6bc4ac881c8e 1915 /* Enable of controlling the number of bits per transfer */
ebrus 0:6bc4ac881c8e 1916 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
ebrus 0:6bc4ac881c8e 1917 /* Mask of field of bit controlling */
ebrus 0:6bc4ac881c8e 1918 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
ebrus 0:6bc4ac881c8e 1919 /* Set the number of bits per a transfer */
ebrus 0:6bc4ac881c8e 1920 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
ebrus 0:6bc4ac881c8e 1921 /* SPI Clock Phase Select*/
ebrus 0:6bc4ac881c8e 1922 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
ebrus 0:6bc4ac881c8e 1923 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
ebrus 0:6bc4ac881c8e 1924 /* SPI Clock Polarity Select*/
ebrus 0:6bc4ac881c8e 1925 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
ebrus 0:6bc4ac881c8e 1926 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
ebrus 0:6bc4ac881c8e 1927 /* SPI Slave Mode Select */
ebrus 0:6bc4ac881c8e 1928 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
ebrus 0:6bc4ac881c8e 1929 /* SPI Master Mode Select */
ebrus 0:6bc4ac881c8e 1930 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
ebrus 0:6bc4ac881c8e 1931 /* SPI MSB First mode enable */
ebrus 0:6bc4ac881c8e 1932 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
ebrus 0:6bc4ac881c8e 1933 /* SPI LSB First mode enable */
ebrus 0:6bc4ac881c8e 1934 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
ebrus 0:6bc4ac881c8e 1935 /* SPI interrupt enable */
ebrus 0:6bc4ac881c8e 1936 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
ebrus 0:6bc4ac881c8e 1937 /* SPI STAT Register BitMask */
ebrus 0:6bc4ac881c8e 1938 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
ebrus 0:6bc4ac881c8e 1939 /* Slave abort Flag */
ebrus 0:6bc4ac881c8e 1940 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
ebrus 0:6bc4ac881c8e 1941 /* Mode fault Flag */
ebrus 0:6bc4ac881c8e 1942 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
ebrus 0:6bc4ac881c8e 1943 /* Read overrun flag*/
ebrus 0:6bc4ac881c8e 1944 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
ebrus 0:6bc4ac881c8e 1945 /* Write collision flag. */
ebrus 0:6bc4ac881c8e 1946 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
ebrus 0:6bc4ac881c8e 1947 /* SPI transfer complete flag. */
ebrus 0:6bc4ac881c8e 1948 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
ebrus 0:6bc4ac881c8e 1949 /* SPI error flag */
ebrus 0:6bc4ac881c8e 1950 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
ebrus 0:6bc4ac881c8e 1951 /* Enable SPI Test Mode */
ebrus 0:6bc4ac881c8e 1952 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
ebrus 0:6bc4ac881c8e 1953 /* SPI interrupt flag */
ebrus 0:6bc4ac881c8e 1954 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
ebrus 0:6bc4ac881c8e 1955 /* Receiver Data */
ebrus 0:6bc4ac881c8e 1956 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
ebrus 0:6bc4ac881c8e 1957
ebrus 0:6bc4ac881c8e 1958 /* SPI Mode*/
ebrus 0:6bc4ac881c8e 1959 typedef enum LPC_SPI_MODE {
ebrus 0:6bc4ac881c8e 1960 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
ebrus 0:6bc4ac881c8e 1961 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
ebrus 0:6bc4ac881c8e 1962 } LPC_SPI_MODE_T;
ebrus 0:6bc4ac881c8e 1963
ebrus 0:6bc4ac881c8e 1964 /* SPI Clock Mode*/
ebrus 0:6bc4ac881c8e 1965 typedef enum LPC_SPI_CLOCK_MODE {
ebrus 0:6bc4ac881c8e 1966 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
ebrus 0:6bc4ac881c8e 1967 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
ebrus 0:6bc4ac881c8e 1968 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
ebrus 0:6bc4ac881c8e 1969 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
ebrus 0:6bc4ac881c8e 1970 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
ebrus 0:6bc4ac881c8e 1971 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
ebrus 0:6bc4ac881c8e 1972 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
ebrus 0:6bc4ac881c8e 1973 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
ebrus 0:6bc4ac881c8e 1974 } LPC_SPI_CLOCK_MODE_T;
ebrus 0:6bc4ac881c8e 1975
ebrus 0:6bc4ac881c8e 1976 /* SPI Data Order Mode*/
ebrus 0:6bc4ac881c8e 1977 typedef enum LPC_SPI_DATA_ORDER {
ebrus 0:6bc4ac881c8e 1978 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
ebrus 0:6bc4ac881c8e 1979 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
ebrus 0:6bc4ac881c8e 1980 } LPC_SPI_DATA_ORDER_T;
ebrus 0:6bc4ac881c8e 1981
ebrus 0:6bc4ac881c8e 1982 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 1983 * Serial GPIO register block structure
ebrus 0:6bc4ac881c8e 1984 */
ebrus 0:6bc4ac881c8e 1985 #define LPC_SGPIO_BASE 0x40101000
ebrus 0:6bc4ac881c8e 1986
ebrus 0:6bc4ac881c8e 1987 typedef struct { /* SGPIO Structure */
ebrus 0:6bc4ac881c8e 1988 __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
ebrus 0:6bc4ac881c8e 1989 __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
ebrus 0:6bc4ac881c8e 1990 __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
ebrus 0:6bc4ac881c8e 1991 __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
ebrus 0:6bc4ac881c8e 1992 __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
ebrus 0:6bc4ac881c8e 1993 __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
ebrus 0:6bc4ac881c8e 1994 __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
ebrus 0:6bc4ac881c8e 1995 __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
ebrus 0:6bc4ac881c8e 1996 __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
ebrus 0:6bc4ac881c8e 1997 __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
ebrus 0:6bc4ac881c8e 1998 __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
ebrus 0:6bc4ac881c8e 1999 __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
ebrus 0:6bc4ac881c8e 2000 __I uint32_t GPIO_INREG; /* GPIO input status register */
ebrus 0:6bc4ac881c8e 2001 __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
ebrus 0:6bc4ac881c8e 2002 __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
ebrus 0:6bc4ac881c8e 2003 __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
ebrus 0:6bc4ac881c8e 2004 __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
ebrus 0:6bc4ac881c8e 2005 __I uint32_t RESERVED0[823];
ebrus 0:6bc4ac881c8e 2006 __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
ebrus 0:6bc4ac881c8e 2007 __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
ebrus 0:6bc4ac881c8e 2008 __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
ebrus 0:6bc4ac881c8e 2009 __I uint32_t STATUS_0; /* Shift clock interrupt status */
ebrus 0:6bc4ac881c8e 2010 __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
ebrus 0:6bc4ac881c8e 2011 __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
ebrus 0:6bc4ac881c8e 2012 __I uint32_t RESERVED1[2];
ebrus 0:6bc4ac881c8e 2013 __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
ebrus 0:6bc4ac881c8e 2014 __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
ebrus 0:6bc4ac881c8e 2015 __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
ebrus 0:6bc4ac881c8e 2016 __I uint32_t STATUS_1; /* Capture clock interrupt status */
ebrus 0:6bc4ac881c8e 2017 __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
ebrus 0:6bc4ac881c8e 2018 __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
ebrus 0:6bc4ac881c8e 2019 __I uint32_t RESERVED2[2];
ebrus 0:6bc4ac881c8e 2020 __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
ebrus 0:6bc4ac881c8e 2021 __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
ebrus 0:6bc4ac881c8e 2022 __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
ebrus 0:6bc4ac881c8e 2023 __I uint32_t STATUS_2; /* Pattern match interrupt status */
ebrus 0:6bc4ac881c8e 2024 __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
ebrus 0:6bc4ac881c8e 2025 __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
ebrus 0:6bc4ac881c8e 2026 __I uint32_t RESERVED3[2];
ebrus 0:6bc4ac881c8e 2027 __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
ebrus 0:6bc4ac881c8e 2028 __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
ebrus 0:6bc4ac881c8e 2029 __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
ebrus 0:6bc4ac881c8e 2030 __I uint32_t STATUS_3; /* Input bit match interrupt status */
ebrus 0:6bc4ac881c8e 2031 __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
ebrus 0:6bc4ac881c8e 2032 __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
ebrus 0:6bc4ac881c8e 2033 } LPC_SGPIO_T;
ebrus 0:6bc4ac881c8e 2034
ebrus 0:6bc4ac881c8e 2035 /* End of section using anonymous unions */
ebrus 0:6bc4ac881c8e 2036 #if defined(__ARMCC_VERSION)
ebrus 0:6bc4ac881c8e 2037 #pragma pop
ebrus 0:6bc4ac881c8e 2038 #elif defined(__CWCC__)
ebrus 0:6bc4ac881c8e 2039 #pragma pop
ebrus 0:6bc4ac881c8e 2040 #elif defined(__IAR_SYSTEMS_ICC__)
ebrus 0:6bc4ac881c8e 2041 //#pragma pop // FIXME not usable for IAR
ebrus 0:6bc4ac881c8e 2042 #else /* defined(__GNUC__) and others */
ebrus 0:6bc4ac881c8e 2043 /* Leave anonymous unions enabled */
ebrus 0:6bc4ac881c8e 2044 #endif
ebrus 0:6bc4ac881c8e 2045
ebrus 0:6bc4ac881c8e 2046 /* ---------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 2047 * LPC43xx Peripheral register set declarations
ebrus 0:6bc4ac881c8e 2048 */
ebrus 0:6bc4ac881c8e 2049 #define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
ebrus 0:6bc4ac881c8e 2050 #define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
ebrus 0:6bc4ac881c8e 2051 #define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
ebrus 0:6bc4ac881c8e 2052 #define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
ebrus 0:6bc4ac881c8e 2053 #define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
ebrus 0:6bc4ac881c8e 2054 #define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
ebrus 0:6bc4ac881c8e 2055 #define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
ebrus 0:6bc4ac881c8e 2056 #define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
ebrus 0:6bc4ac881c8e 2057 #define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
ebrus 0:6bc4ac881c8e 2058 #define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
ebrus 0:6bc4ac881c8e 2059 #define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
ebrus 0:6bc4ac881c8e 2060 #define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
ebrus 0:6bc4ac881c8e 2061 #define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
ebrus 0:6bc4ac881c8e 2062 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
ebrus 0:6bc4ac881c8e 2063 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
ebrus 0:6bc4ac881c8e 2064 #define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
ebrus 0:6bc4ac881c8e 2065 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
ebrus 0:6bc4ac881c8e 2066 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
ebrus 0:6bc4ac881c8e 2067 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
ebrus 0:6bc4ac881c8e 2068 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
ebrus 0:6bc4ac881c8e 2069 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
ebrus 0:6bc4ac881c8e 2070 #define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
ebrus 0:6bc4ac881c8e 2071 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
ebrus 0:6bc4ac881c8e 2072 #define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
ebrus 0:6bc4ac881c8e 2073 #define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
ebrus 0:6bc4ac881c8e 2074 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
ebrus 0:6bc4ac881c8e 2075 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
ebrus 0:6bc4ac881c8e 2076 #define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
ebrus 0:6bc4ac881c8e 2077 #define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
ebrus 0:6bc4ac881c8e 2078 #define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
ebrus 0:6bc4ac881c8e 2079 #define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
ebrus 0:6bc4ac881c8e 2080 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
ebrus 0:6bc4ac881c8e 2081 #define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
ebrus 0:6bc4ac881c8e 2082 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
ebrus 0:6bc4ac881c8e 2083 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
ebrus 0:6bc4ac881c8e 2084 #define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
ebrus 0:6bc4ac881c8e 2085 #define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
ebrus 0:6bc4ac881c8e 2086 #define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
ebrus 0:6bc4ac881c8e 2087 #define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
ebrus 0:6bc4ac881c8e 2088 #define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
ebrus 0:6bc4ac881c8e 2089 #define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
ebrus 0:6bc4ac881c8e 2090 #define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
ebrus 0:6bc4ac881c8e 2091 #define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
ebrus 0:6bc4ac881c8e 2092 #define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
ebrus 0:6bc4ac881c8e 2093 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
ebrus 0:6bc4ac881c8e 2094 #define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
ebrus 0:6bc4ac881c8e 2095 #define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
ebrus 0:6bc4ac881c8e 2096 #define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
ebrus 0:6bc4ac881c8e 2097 #define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
ebrus 0:6bc4ac881c8e 2098 #define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
ebrus 0:6bc4ac881c8e 2099 #define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
ebrus 0:6bc4ac881c8e 2100 #define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
ebrus 0:6bc4ac881c8e 2101 #define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
ebrus 0:6bc4ac881c8e 2102 #define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
ebrus 0:6bc4ac881c8e 2103 #define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
ebrus 0:6bc4ac881c8e 2104 #define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
ebrus 0:6bc4ac881c8e 2105 #define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
ebrus 0:6bc4ac881c8e 2106 #define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
ebrus 0:6bc4ac881c8e 2107 #define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
ebrus 0:6bc4ac881c8e 2108
ebrus 0:6bc4ac881c8e 2109 #ifdef __cplusplus
ebrus 0:6bc4ac881c8e 2110 }
ebrus 0:6bc4ac881c8e 2111 #endif
ebrus 0:6bc4ac881c8e 2112
ebrus 0:6bc4ac881c8e 2113 #endif /* __LPC43XX_H */